Apparatus, system, and method for system-on-chip replacement mode

Abstract

Devices, systems, and methods for system on chip (SoC) replacement mode. A memory device can be coupled to an SoC that can act as a controller for the memory. Commands and addresses can be sent to a first decoder of the memory along a command / address (CA) bus. The first decoder can determine a value of a signal along the CA bus using a first reference voltage. One pin in the CA bus can be coupled to a second decoder that can use a different second reference voltage. When a voltage on the pin exceeds the second reference voltage, the memory device can enter SoC replacement mode, where the memory can take various measures to maintain data integrity while a new SoC is online.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to apparatus, systems, and methods for system-on-chip mode switching. Background Technology

[0002] A semiconductor device may include a controller and a memory. The controller may operate the memory, for example, by providing commands to the memory and sending and receiving data from the memory. The memory may be volatile, storing information only when powered on. There may be situations where the controller needs to be replaced. However, if the device is powered off to replace the controller, the information in the memory may be lost. A method may be needed to replace the controller without losing the information stored in the memory. Summary of the Invention

[0003] Describe a device. The device includes: an input pin; a first decoder circuit coupled to the input pin, the first decoder circuit being configured to compare a voltage on the input pin with the first reference voltage; and a second decoder circuit coupled to the input pin, wherein the second input decoder circuit is configured to compare the voltage on the input pin with a second reference voltage different from the first input voltage.

[0004] A method is described. The method includes: receiving signals on a plurality of input pins of a memory device, wherein the signals are represented by voltages within a voltage range; entering a switching mode of the memory device in response to a switching mode entry signal, wherein the switching mode entry signal is represented by a voltage on one of the plurality of input pins that intersects with a reference voltage outside the voltage range; and ignoring the signals on the plurality of input pins while the memory device is in the switching mode.

[0005] A system is described. The system includes: a memory device configured to store information; a first system-on-chip (SoC) configured to act as a controller for the memory device; a second SoC; and a command address (CA) bus coupling the first SoC and the second SoC to the memory device, wherein the first SoC is configured to provide a switch mode entry signal along the CA bus to put the memory device into a switch mode, wherein the memory device is configured to retain the information in the memory device when in the switch mode, and wherein the second SoC is configured to take over the controller of the memory device. Attached Figure Description

[0006] Figure 1 This is a block diagram of a system including a memory according to some embodiments of the present disclosure.

[0007] Figure 2 This is a block diagram of an apparatus according to an embodiment of the present disclosure.

[0008] Figure 3 This is a graph showing the signal operation according to some embodiments of the present disclosure.

[0009] Figure 4 This is a graph showing the signal operation during mode switching according to some embodiments of the present disclosure.

[0010] Figure 5 This is a block diagram of a system including a memory according to some embodiments of the present disclosure.

[0011] Figure 6 This is a flowchart of a method for entering a System-on-Chip (SoC) replacement mode according to some embodiments of the present disclosure. Detailed Implementation

[0012] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form part of the invention, and are illustrated by means of specific embodiments in which the described systems and methods can be practiced. The descriptive details of these embodiments are sufficient to enable those skilled in the art to practice the systems and methods disclosed herein, and it should be understood that other embodiments can be used and structural and logical changes can be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, detailed descriptions of certain features will not be discussed where it is clearly apparent to those skilled in the art, so as not to obscure the description of the embodiments of this disclosure. Therefore, the following detailed description should not be construed as limiting, and the scope of this disclosure is defined only by the appended claims.

[0013] An apparatus may include a memory and a system-on-a-chip (SoC) that acts as a controller for the memory. The SoC may send various commands to the memory along a command address (CA) bus, which may include one or more parallel channels connected to input terminals (pins) of the memory. Each pin may continuously receive signals using a voltage on the pin to distinguish input levels. For example, a first voltage may represent a high logic signal, while a second voltage may represent a low logic level. The first and second voltages may represent the 'normal' voltage range of the input pin.

[0014] In some cases, it is useful and / or necessary to modify the SoC without powering down the memory, as power loss would result in the loss of information stored in the memory. For example, if the SoC runs a critical system, such as automotive AI, then a seamless transition to a new SoC is necessary if the old SoC fails. Putting the memory into a replacement mode to prepare it for SoC transition can be useful if it does not require increasing the number of CA pins.

[0015] This disclosure relates to devices, systems, and methods for using SoC changeover modes. The memory may include a second input circuitry and decoder coupled in parallel to a CA pin, as well as a primary input buffer and decoder. The primary input buffer and decoder are responsive to voltage levels within a voltage range. The second input circuitry and decoder are responsive when the voltage on the pin is higher than a threshold voltage (e.g., a reference voltage) outside the voltage range. The second decoder may provide one or more internal command signals that enable the memory to enter an SoC changeover mode. During the SoC changeover mode, the memory may perform self-refresh and / or other operations to maintain data integrity and may ignore inputs on the CA pin, except for a changeover mode exit command. In some embodiments, the same pin used to enter the changeover mode may be used to exit the changeover mode. In some embodiments, a first pin may be used to enter the changeover mode, while a second pin may be used to exit the changeover mode.

[0016] Figure 1 This is a block diagram of a memory-included system according to some embodiments of the present disclosure. System 100 includes a memory device 120 coupled to a first system-on-chip (SoC) 102 and a second SoC 104. The first SoC 102 acts as a controller for the memory 120 and is coupled to the memory 120 via a command / address (CA) bus 110 for carrying CA signals. It may be necessary to switch from using the first SoC 102 as the controller for the memory 120 to using the second SoC 104 as the controller for the memory 120 without losing data stored in the memory 120.

[0017] In some embodiments, memory may be co-coupled to both SoCs 102 and 104, with one SoC in operation and acting as a controller. For example, system 100 may be used to manage critical functions, such as managing autonomous driving, and it may be important that functionality is maintained even if one of the SoCs fails. Therefore, the first SoC 102 may be the primary SoC, and the second SoC 104 may be a backup SoC. When a fault is detected in the primary SoC, system 100 may switch to using the backup SoC.

[0018] In some embodiments, system 100 may typically include a single SoC (e.g., first SoC 102), and second SoC 104 may be coupled to CA bus 110, such that the second SoC can take over the controller of memory 120, which allows the first SoC 102 to be removed. For example, in some situations, system 100 may experience a functional failure, and the second SoC 104 may be swapped into system 100 to help diagnose and / or resolve the problem.

[0019] To switch from using the first SoC 102 as the controller to using the second SoC 104, the memory 120 can enter a 'switch mode'. The memory 120 enters switch mode via a switch mode entry signal, which is provided along the CA bus 110. Switch mode protects the data in the memory 120. While in switch mode, the memory 120 can automatically refresh itself to retain the information stored therein. In switch mode, the memory 120 can also ignore inputs along the CA bus 110 (except for signals exiting switch mode). This protects the memory 120 from erroneous signals that may occur during SoC switching.

[0020] Signals for entering and exiting the changeover mode of memory 120 can be provided along the CA bus 110. To reduce the number of physical connections (e.g., pins) along the CA bus 110, existing pins can be used for changeover mode entry and exit signals. Figure 1 In one embodiment, the same pin can be used to interchange both the mode entry and exit signals. Other embodiments (e.g., Figure 6 (As described in the embodiments) different pins can be used for the entry and exit signals.

[0021] The CA bus 110 can contain several different conductive elements CA <0> To CA <n>Each conductive element in the memory 120 can continuously carry a signal. The signal can be represented by the voltage of the conductive element. For example, a first voltage can represent a high logic level, and a second voltage can represent a low logic level. The input circuitry 122 of the memory 120 can receive voltages along different lines of the CA bus 110 and can filter and / or buffer voltages along the lines. For example, the input circuitry 122 can remove noise. The input circuitry 122 can provide input signals to the decoder 124, thereby determining which commands and / or addresses are represented by voltages along the lines. For example, if a first signal line contains a first voltage, then the decoder 124 can interpret it as a high logic level and provide one or more internal signals based on the meaning of the signal.

[0022] The memory 120 may also include a second input circuit 123 and a second decoder 125, which are coupled to a signal line (e.g., a pin) of the CA bus 110 and are used to receive a mode change command. Figure 1 In this embodiment, the second input circuit 123 is coupled to a specific pin CA of the CA bus 110. Therefore, both the main input circuit 122 and the second input circuit 123 can receive signals along pin CA. The signal. During normal operation, commands are sent along the command bus 110 (e.g., along pin CA). The voltage of the signal can be within a certain voltage range. This voltage range can represent the range between voltages used as high and low logic levels by the first decoder 124. The second decoder 125 can interpret voltages outside the range of the first decoder 124 as mode change entry signals.

[0023] For example, the first decoder 124 typically uses a first voltage V1 to represent a high logic level and a second voltage V0 to represent a low logic level. (Pin CA) The voltage on the circuit typically varies between V1 and V0 (and can also become slightly higher than V1 and slightly lower than V0). Therefore, the normal voltage range is between V1 and V0 (and / or between a voltage just above V1 and a voltage below V0). The first decoder 124 can use a reference voltage Vth as a threshold. The reference voltage Vth can be between V1 and V0, and the first decoder can determine any voltage above Vth as logic high and any voltage below Vth as logic low. To prevent [further issues] along CA... To prevent confusion between normal signals, the second decoder 125 can respond only to voltages outside the voltage range used by the first decoder 124. For example, the second decoder 125 can use a second reference voltage Vth2 outside the voltage range of the first decoder 124 (e.g., voltage Vth2 may be higher than voltage V1). The second decoder 125 can respond to pin CA voltages greater than the second reference voltage Vth2. A voltage on the CA pin (e.g., outside the normal voltage range) is interpreted as a mode change entry command. This is because such a high voltage is not normally present on the CA pin. Therefore, using reference Vth2 in the second decoder 125 helps prevent confusion between normal signals and mode change entry commands without requiring an additional pin. In this way, pin CA... It can carry three commands: normal high and low signals decoded by the first decoder 124 and a mode change entry command decoded by the second decoder 125.

[0024] exist Figure 1 In the embodiment, along pin CA The voltage can also be used as a mode change / exit command. For example, when pin CA... When the voltage on pin CA rises above the threshold reference voltage Vth2 of the second decoder 125, the decoder 125 can interpret it as a mode change entry command. When the voltage drops below the threshold reference voltage Vth2, the second decoder 125 can interpret it as a mode change and exit command.

[0025] System 100 may include switching logic 106, which can be used to manage the transition from a first SoC 102 to a second SoC 104. For example, during a switchover operation, the first SoC 102 may provide a switchover mode entry signal to the memory (e.g., by passing signal line CA). The voltage rises above the reference voltage threshold Vth2 of the second decoder 125. This allows the memory 120 to begin self-refreshing. Then, the switching logic 106 can instruct the second SoC 104 to activate it, allowing the second SoC 104 to power on or wake from sleep mode. In some embodiments, the second SoC 104 may begin providing a CA voltage above the reference voltage threshold Vth2. The voltage on the line. Once the second SoC is online, switching logic 106 signals that the first SoC 102 can be turned off. This is because the second SoC 104 still provides a voltage higher than Vth2 along the line CA. The voltage is such that memory 120 can remain in swap mode. Once the second SoC 104 is ready to take over operation, the second SoC 104 can provide an exit swap mode signal, for example, by sending a signal along pin CA. The voltage drops below the reference voltage threshold Vth2. Then, the second SoC 104 can begin providing normal communication along the CA bus 110. In some embodiments, the two SoCs 102 and 104 can communicate via switching logic, for example, allowing the second SoC 104 to resume operations previously performed by the first SoC.

[0026] In some embodiments, the first SoC 102 and the second SoC 104 are not co-coupled to the CA bus 110, but may be co-coupled to the switching logic 106. The switching logic 106 may provide mode change entry and exit signals in response to commands from the first SoC 102, and may additionally act as a pathway for the CA bus 110.

[0027] In some embodiments, instead of removing SoC 102 to replace it with another SoC 104, a replacement mode can be used to decouple memory 120 from SoC 102 for a period of time. For example, SoC 102 can put memory 120 into a replacement mode, which can then be removed and tested, replaced, and then a replacement mode exit signal can be sent to recouple SoC 102 to memory 120.

[0028] In some embodiments, a single connector may exist between memory 120 and SoC 102. Replacement logic 106 may be omitted. First SoC 102 may send a replacement mode enter signal, putting memory 120 into replacement mode. Then, first SoC 102 may be removed, and second SoC 104 may be inserted into the connector to CA bus 110. Second SoC 104 may then provide a replacement mode exit signal, which allows the memory to return to normal operation, with SoC 104 now acting as the memory controller. Memory 120 may maintain a replacement mode enable signal, which can be set to an active level by the replacement mode enter signal. When the replacement mode enable signal is active, the state of the replacement mode enable signal may be stored in memory 120 (e.g., a latch), and the memory may remain in replacement mode. The replacement mode exit signal may reset the replacement mode enable signal to an inactive level. Storing the enable signal in the latch of memory 120 can be used in any of the other embodiments described herein, but is particularly suitable for embodiments where the SoC is completely disconnected during replacement, since the voltage along the CA bus 110 may be uncontrolled without a controller connected.

[0029] Figure 2 This is a block diagram of a device according to an embodiment of the present disclosure. The device may be a semiconductor device 200, and will be referred to as such. Device 200 may be included in Figure 1 The memory 120 is used. In some embodiments, the semiconductor device 200 may include, but is not limited to, a DRAM device.

[0030] Semiconductor device 200 includes memory array 228. Memory array 228 is shown as comprising multiple memory groups. Figure 2 In one embodiment, memory array 228 is shown as comprising eight memory groups BANK0-BANK7. Each memory group includes multiple word lines WL, multiple bit lines BL and / BL, and multiple memory cells MC arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / BL. The selection of word lines WL is performed by row decoder 224, and the selection of bit lines BL and / BL is performed by column decoder 226. Figure 2 In this embodiment, row decoder 224 includes a corresponding row decoder for each memory bank, and column decoder 226 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL or / BL is amplified by the sense amplifier SAMP and transferred to read / write amplifier 230 via complementary local data line (LIOT / B), transfer gate (TG), and complementary main data line (MIOT / B). Conversely, write data output from read / write amplifier 230 is transferred to the sense amplifier SAMP via complementary main data line MIOT / B, transfer gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0031] Semiconductor device 200 may employ multiple external terminals, including those coupled to command and address buses (e.g., Figure 1 The device 200 includes a command and address (CA) terminal for receiving commands and addresses, a clock terminal for receiving clock signals CK_t and CK_c, data clock signals WCK_t and WCK_c and providing access data clock signals RDQS_t and RDQS_c, data terminals DQ and DM, and power supply terminals for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The various terminals of the device 200 can be collectively referred to as 'pins' and can be coupled to conductive elements that carry signals to the pins. For example, several CA pins may exist, each of which can receive a signal as a voltage. Each CA pin can receive signals in a serial format, where the voltage level changes over time to indicate different logic levels.

[0032] The clock terminal provides external clock signals CK_t and CK_c to the input buffer 218. These external clock signals can be complementary. The input buffer 218 generates an internal clock ICLK based on the CK_t and CK_c clock signals. The ICLK clock is provided to the command decoder 216 and the internal clock generator 220. The internal clock generator 220 provides individual internal clock signals LCLK based on the ICLK clock. The LCLK clock signals can be used for timing operations of various internal circuits. In some embodiments, a data clock (not shown) may also be provided for controlling data writing to / reading from the device 200.

[0033] The CA terminal can supply memory addresses. The memory addresses supplied to the CA terminal are transferred to the address decoder 214 via command / address input circuitry 212. Address decoder 214 receives the addresses and supplies the decoded row address XADD to row decoder 224 and the decoded column address YADD to column decoder 226. The CA terminal can also supply commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory (e.g., read commands for performing read operations and write commands for performing write operations), mode register write and read commands for performing mode register write and read operations, and other commands and operations.

[0034] Commands can be provided as internal command signals to command decoder 216 via command / address input circuitry 212. Command decoder 216 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 216 can provide a row command signal ACT for selecting word lines and a column command signal R / W for selecting bit lines.

[0035] The command address input circuit 212 may include a first set of input circuits 240 and a second set of input circuits 242. Input circuit 240 (e.g., Figure 1 Input circuit 122) can be coupled to the CA pin and can be used to process command signals along the CA bus, except for mode change entry and exit signals. Input circuit 242 (e.g., Figure 1 The input circuit 124 can process command signals along the CA bus related to changing modes (e.g., mode change in / out signals). In some embodiments, the number of CA pins coupled to the first input circuit 240 may be greater than the number coupled to the second input circuit 242. For example, only one CA pin may be coupled to the second input circuit 242. Pins coupled to the second input circuit 242 may also be coupled to the first input circuit 240.

[0036] Input circuits 240 and 242 can act as buffers for signals along the coupled CA pin. Input circuits 240 and 242 can pass the buffered signal to command decoder 216. The second input circuit 242 can handle different voltages than the first input circuit 240. In some embodiments, input circuit 242 can be coupled to a different system voltage than input circuit 240. For example, the second input circuit 242 can be coupled to a voltage higher than that of the first input circuit 240.

[0037] Command decoder 216 may include a first set of decoders 244 and a second decoder 246. The first set of decoders 244 (e.g., Figure 1 The decoder 244 can process commands other than those related to mode switching. For example, a first input circuit 240 may be coupled to the first decoder 244, and a second input circuit 242 may be coupled to the second decoder 246. The first decoder 244 can provide various commands, such as the read or write command R / W and the row activation command ACT. The second decoder 246 can provide internal signals that put the memory device 200 into a mode switching mode or that eject the memory 200 from a mode switching mode.

[0038] When a read command is received and the row and column addresses are supplied in a timely manner, read data is read from the memory cells corresponding to the row and column addresses in memory array 228. The read command is received by command decoder 244, which provides an internal command causing the read data from memory array 228 to be provided to read / write amplifier 230. The read data is output from data terminal DQ via input / output circuit 232.

[0039] When a write command is received and the row and column addresses are supplied in a timely manner, the write data supplied to the data terminal DQ is written to the memory cells in the memory array 228 corresponding to the row and column addresses. A data mask can be provided to the data terminal DM to mask part of the data when it is written to memory. The write command is received by the command decoder 244, which provides an internal command causing the write data to be received by the data receiver in the input / output circuit 232. The write data is supplied to the read / write amplifier 230 via the input / output circuit 232 and then to the memory array 228 for writing into the memory cell MC.

[0040] Upon receiving a switch mode entry signal, memory device 200 may enter a switch mode. During the switch mode, memory device 200 may take various measures to maintain data integrity in memory array 228. For example, memory 200 may instruct refresh control circuitry 222 to enter a self-refresh mode. Data in memory array 228 may decay over time. To prevent data decay, the values ​​in memory cells may be refreshed back to their initial values. In self-refresh mode, refresh control circuitry 222 may refresh memory cells at a certain rate, such that the information stored in each memory cell is refreshed before it is expected to decay. For example, refresh control circuitry 222 may refresh memory cells row by row and may cycle through rows of memory array 228. Self-refresh mode may also be activated during other non-switch mode periods.

[0041] Refresh control circuit 222 may receive a refresh signal AREF. The memory may enter self-refresh mode via an external signal (e.g., an external refresh signal or a command to put memory device 200 into a changeover mode). Once in self-refresh mode, memory 200 may generate an activation (e.g., a pulse) of the refresh signal AREF. In response to each activation of the refresh signal AREF, the memory may refresh one or more word lines. For example, in response to the activation of AREF, refresh control circuit 222 may provide several 'surges,' each of which may be associated with one or more refresh addresses. The refresh addresses may be provided to row decoder 224 of the refreshable word lines. The signal AREF may continue to be generated periodically until the memory exits self-refresh mode (e.g., in response to a changeover mode exit command). Refresh control circuit 222 may use internal logic to generate refresh addresses. For example, refresh control circuit 222 may have a sequence generator that provides one refresh address from a series of refresh addresses.

[0042] In some embodiments, refresh control circuitry 222 may additionally identify memory cells at risk of a faster rate of memory decay and refresh them out of order. For example, repeated accesses to a given row ('row hammering') can cause nearby rows to experience faster information decay. Refresh control circuitry 222 may identify these victim rows (e.g., based on access patterns) and refresh them as part of a targeted refresh. In some embodiments, refresh control circuitry 222 may combine sequential row refresh and targeted refresh.

[0043] During a mode change, command decoder 246 may provide a signal to input circuitry 212 and / or decoder 244 to cause memory device 200 to ignore signals on the CA bus (except for mode change exit commands). For example, in an embodiment where the mode change exit command is received by a second decoder 246, memory device 200 may disable input circuitry 240 and / or decoder 244 to prevent them from responding to voltages along the CA bus.

[0044] The power supply terminals provide power potentials VDD and VSS. These power potentials VDD and VSS are supplied to the internal voltage generator circuit 234. Based on the power potentials VDD and VSS supplied to the power supply terminals, the internal voltage generator circuit 234 generates various internal potentials VPP, VOD, VARY, VTARGET, VPERI, etc. The internal potential VPP is primarily used in the line decoder 224; the internal potentials VOD and VARY are primarily used in the sense amplifier SAMP contained in the memory array 228; VTARGET can be the target voltage of the internal potential VARY; and the internal potential VPERI is used in many peripheral circuit blocks.

[0045] The power supply terminals are also supplied with power potentials VDDQ and VSSQ. Power potentials VDDQ and VSSQ are supplied to the input / output circuit 232. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power potentials VDD and VSS supplied to the power supply terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power potentials VDD and VSS supplied to the power supply terminals. The power potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 232 to prevent power supply noise generated by the input / output circuit 232 from propagating to other circuit blocks.

[0046] Figure 3 This is a graph showing the signal operation according to some embodiments of the present disclosure. Graph 300 illustrates the signal operation along the CA bus (e.g., during normal operation) Figure 1 The voltage change of the signal lines of the CA bus 110 over time. Graph 300 can represent the voltage change along the signal lines coupled to both the main input circuit and the decoder, and the second input circuit and the decoder (e.g., ...). Figure 1 CA ) signal.

[0047] Curve 300 shows the operation of the signal along line CA and various example voltages for the input buffer and decoder. The main input circuit (e.g., Figure 1 122) and the main decoder (e.g., Figure 1 124) can use voltage levels based on system voltage VDD2 and ground voltage VSS. For example, the ground voltage VSS can be set to 0V, and the system voltage VDD2 can be 1.1V relative to the ground voltage VSS. Other voltages can be used in other examples. The input circuit and decoder can operate using voltage dividers to set various voltage levels between VDD2 and VSS. For example, the voltage V1 representing the high logic level along the signal line can be about 40% of VDD2. The voltage V0 representing the low logic level along the signal line can be about 10% of VDD2. The reference voltage threshold Vth can be between V1 and V0, e.g., about 27.2% of VDD2. Other ratios of the system voltage can be used in other example embodiments, e.g., V1 can be 50%, 30%, etc. of VDD2.

[0048] Since the signal changes over time, the threshold Vth is used to determine whether the signal is decoded as a high logic level or a low logic level. When the voltage on the pin coupled to the signal line is higher than Vth, the signal can be decoded as a high logic level. When the voltage on the pin is lower than Vth, the signal can be decoded as a low logic level. Thus, the voltage on the pin can remain within a voltage range that is typically between V1 and V0.

[0049] The second input circuit and decoder can use another threshold Vth2 to determine whether the signal is positive or negative. When the voltage on the pin is higher than the second threshold Vth2, the second decoder can decode it as a replacement mode incoming signal. As Figure 3 can be seen, during 'normal' operation, the voltage on the signal line can remain below the voltage Vth2 (e.g., because V1 < Vth2), and the second decoder can be inactive.

[0050] In some embodiments, the voltages can be selected such that the voltage on the signal line does not rise above Vth2 under normal circumstances. For example, Vth2 can be selected such that it is greater than the system voltage VDD2 for normal communication on the CA bus. Since the system voltage VDD2 is normally the maximum value that a signal on the CA bus can have, the second decoder is not activated. For example, the threshold Vth2 can be based on a second system voltage (e.g., VDD). The voltage VDD can be higher than VDD2. For example, if the voltage VDD2 is 1.1V and the voltage VDD is 2.5V, then the voltage Vth2 can be set to 50% of VDD. The second system voltage (e.g., VDD) can be used to generate a higher voltage for the replacement mode incoming command along the CA bus.

[0051] Figure 4 This is a graph showing signal operation during mode switching according to some embodiments of this disclosure. Graph 400 may be generally similar to... Figure 3 The curve 300 shows a signal, but graph 400 shows the signal used for changing modes, not 'normal' operation. For the sake of brevity, the previous information... Figure 3 The described features and operations will not be discussed again. Figure 4 repeat.

[0052] Figure 400 shows the relationship with Figure 3 The same signal lines (and pins) are shown, but in Figure 4 In this context, the pin is used to enter and exit memory switching modes. At the first moment, the voltage on the signal line rises above the second threshold voltage Vth2. This allows the second decoder (e.g., Figure 1 The 125) decodes the signal into a high logic level. Then, the second decoder can provide various signals indicating entry into a switching mode.

[0053] The memory can remain in the switching mode until a switching mode exit signal is received. For example, at a second time (e.g., after the first time), a second pulse along the signal line can rise above a second threshold voltage Vth2 (e.g., in a manner similar to the pulse received at the first time). A second decoder can interpret this second pulse as a switching mode exit signal, and the second decoder can provide various signals indicating exit from the switching mode. Normal communication along the pin can then be resumed (e.g., similar to...). Figure 3 (Those shown in the image).

[0054] For example, the second decoder may include a latch that holds a switching mode active signal. When the voltage on the pin rises above a second threshold, a pulse can be provided to the clock terminal of the latch, which can change the state of the switching mode active signal. Therefore, the latch can default to holding the switching mode active signal in an inactive state (e.g., low logic level). A voltage rise above Vth2 can switch the state of the switching mode active signal to active (e.g., high) level, which allows the memory to enter switching mode. Subsequent time after the voltage rises above Vth2 can return the state of the switching mode active signal to an inactive level, thereby returning the memory to normal operating mode.

[0055] Figure 5 This is a block diagram of a system including a memory according to some embodiments of the present disclosure. System 500 may be generally similar to Figure 1 In system 100, but in system 500, the first pin (e.g., CA) The second pin (e.g., CA) is used to send the mode change entry command. <j>This is used for the command to exit the mode change process. For the sake of brevity, it has already been explained... Figure 1 The described features and operations will not be discussed again. Figure 5 repeat.

[0056] System 500 includes memory 520 coupled along CA bus 510 to a first SoC 502 that acts as a controller. System 500 can switch from the first SoC 502 to using a second SoC 504 as the controller (e.g., using timing based on switching logic 506). To retain information in memory 520 and to protect memory 520 from erroneous signals along CA bus 510, memory 520 can enter a switching mode during the transition from the first SoC 502 to the second SoC 504, and then exit the switching mode to resume normal operation, where the second SoC 504 acts as the controller. For example, a switching mode entry signal can be sent along CA bus 510 to put memory 520 into switching mode, and then a switching mode exit signal can be sent along CA bus 510 to put memory 520 out of switching mode.

[0057] For example, the first conductive element / pin of the CA bus 510 (e.g., pin CA) This can be used to transmit mode change entry commands. Normally, the information can be transmitted along the CA bus 510 as a voltage within a certain voltage range (e.g., similar to...). Figure 3 The mode change command can be transmitted as a signal carrying a voltage outside the normal voltage range (e.g., similar to...). Figure 4 Pin CA This can be coupled to a main input circuit 522 and a decoder 524 that process signals within the normal voltage range, as well as a second input circuit 523 and a decoder 525. The second decoder 525 may have a voltage threshold outside the normal voltage range of the main decoder 524. When CA... When the voltage on the memory exceeds the threshold of the second decoder 525, the decoder 525 can interpret this as a switch mode entry signal and generate an internal signal that causes the memory 520 to enter switch mode. During the switch mode, the memory 520 can perform a self-refresh operation.

[0058] When the mode change is about to end, a mode change exit signal can be provided along the CA bus 510. In system 500, a different pin can be used to carry the mode change exit command instead of the same pin (e.g., as...). Figure 1 For example, when using pin CA When entering the load change mode, the CA pin can be used. <j>Load change mode exit command. Pin CA <j>These can be jointly coupled to the main input circuit 522 and the main decoder 524, as well as the third input circuit 526 and the third decoder 528. The third decoder 528 can respond to voltages outside the voltage threshold of the main decoder 524 in a manner similar to the second decoder 525. For example, the third decoder 528 can use a voltage threshold outside the voltage range of the main decoder 524. In some embodiments, the third decoder 528 may have the same threshold as the second decoder 525. A voltage greater than the threshold of the third decoder 528 is applied along pin CA. <j>The voltage, the third decoder 528 can provide various internal signals that allow the memory 520 to exit the switching mode.

[0059] In some embodiments, when in transition mode, memory 520 may also ignore commands along the CA bus 510. This helps protect memory 520 from erroneous voltages that may be generated along the CA bus 510 during transitions. In system 500, at pin CA... After receiving the mode change command, the memory can ignore the CA path. Other voltages, and can only be applied to voltages greater than the threshold voltage of the third decoder 528 along CA. <j>It responds to the voltage.

[0060] Similar to Figure 1 In different embodiments of system 100, system 500 may have different configurations. For example, in some embodiments, memory 520 may have a CA bus 510 with a single connector to a controller (e.g., one in a SoC), instead of being coupled in parallel. Thus, in instance operation, first SoC 502 may be coupled to CA bus 510 and a switch mode enter signal (e.g., along pin CA) may be provided to put memory 520 into a switch mode. Next, the first SoC 502 can be disconnected from the CA bus 510 and replaced by the second SoC 504. Once it is ready to begin operation, the second SoC can provide a switch-mode exit signal that returns the memory 520 to normal operation (e.g., along pin CA). <j>In this case, the second SoC 504 acts as the controller. In some embodiments, the switching logic 506 may be omitted.

[0061] Figure 6 This is a flowchart of a method for entering a System-on-Chip (SoC) replacement mode according to some embodiments of this disclosure. Method 600 may be... Figure 1-5 One or more executions in the device and system.

[0062] Method 600 may typically begin at block 610 and describes receiving signals on a plurality of input pins of a memory device. The signals may be represented by voltages within a certain voltage range. For example, a decoder of the memory may receive a first voltage (e.g., ... Figure 3 V1) is interpreted as a high logic level, and the second voltage (e.g., Figure 3 The voltage at the input pin (V0) is interpreted as a low logic level. The voltage on the input pin can generally fall within the range between V1 and V0 (and / or between voltages just above V1 and just below V0). The input pin can be coupled to a decoder that compares the received voltage to a threshold voltage to determine whether the received voltage at the input pin represents a high or low level. For example, if the voltage is above the threshold voltage, then the voltage represents a high logic level; if the voltage is below the threshold voltage, then the voltage represents a low logic level.

[0063] Input pins can be part of the command address (CA) input bus, and can receive commands, addresses, or combinations thereof. Commands instruct the memory device to perform an operation, while addresses indicate the location of the memory device within the memory array.

[0064] Method 600 may include block 620, which describes entering a changeover mode of the memory device in response to a changeover mode entry signal. The changeover mode entry signal may be represented by a voltage on one of the plurality of input pins that intersects a voltage threshold outside a voltage range. For example, one of the input pins may be coupled to a second decoder (and a first decoder). The second decoder may compare the voltage with a second threshold voltage that is different from the first threshold voltage used by the first decoder (e.g., ...). Figure 3-4 (Vth2). For example, the second threshold voltage may be outside the voltage range (e.g., greater than V1).

[0065] Box 620, typically followed by box 630, describes ignoring signals on the plurality of input pins when the device is in a switching mode. The memory device may take various measures during switching modes to protect the integrity of the information stored therein. For example, the memory device may ignore voltages on the input pins, except for a switching mode exit signal. In some embodiments, the memory device may ignore signals received by a decoder that processes commands and addresses. The memory may also perform other operations to maintain information integrity. For example, method 600 may include refreshing word lines of the memory array when the memory device is in a switching mode.

[0066] Method 600 may further include exiting a change mode in response to a change mode exit signal. The change mode exit signal may be represented by a voltage on one of the plurality of input pins for a change mode entry command that crosses a voltage threshold. For example, a rising edge may indicate change mode entry, and a falling edge may indicate change mode exit. The change mode exit signal may be represented by a voltage on another of the plurality of input pins that crosses a second voltage threshold. For example, a first pin may be used for the change mode entry signal, and a second pin may be used for the change mode exit signal.

[0067] The switching mode can be used when transitioning a memory device from a first SoC to a second SoC. For example, method 600 may include receiving a command from the first SoC before entering the switching mode, exiting the switching mode, and receiving a command from the second SoC after exiting the switching mode.

[0068] It should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate apparatus or apparatus portion of a system, apparatus, or method according to the present invention.

[0069] Finally, the foregoing discussion is intended only to illustrate the system of the present invention and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the system of the present invention has been described in particular detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broad and contemplated spirit and scope of the system of the present invention as set forth in the appended claims. Therefore, the specification and drawings should be regarded as illustrative and are not intended to limit the scope of the appended claims.< / j> < / j> < / j> < / j> < / j> < / j> < / n>

Claims

1. A device for switching on-chip system modes, comprising: Input pins and several other input pins; A first decoder circuit coupled to the input pin, the first decoder circuit being configured to compare the voltage on the input pin with a first reference voltage; as well as A second decoder circuit coupled to the input pin, wherein the second decoder circuit is configured to compare the voltage on the input pin with a second reference voltage different from the first reference voltage, wherein in response to the voltage on the input pin being greater than the second reference voltage, the device is configured to ignore signals along the plurality of other input pins.

2. The device according to claim 1, further comprising: Memory array; as well as A refresh control circuit, wherein in response to the voltage on the input pin being greater than the second reference voltage, the refresh control circuit is configured to begin refreshing the memory array.

3. The device according to claim 1, further comprising: A second input pin, wherein the first decoder circuit is coupled to the input pin and further configured to compare the voltage on the second input pin with the first reference voltage; as well as A third decoder circuit coupled to the second input pin, wherein the second decoder circuit is configured to compare the voltage on the second input pin with a third reference voltage.

4. The device according to claim 3, wherein the third reference voltage is the same as the second reference voltage.

5. The device of claim 1, wherein the input pin is coupled to a command address bus.

6. The device according to claim 1, further comprising: A first input circuit coupled between the input pin and the first decoder circuit, wherein the first input circuit is configured to buffer the voltage of the input pin; as well as A second input circuit is coupled between the input pin and the second decoder circuit, wherein the second input circuit is configured to buffer the voltage of the input pin.

7. A method for switching modes in an on-chip system, comprising: Receive signals from multiple input pins of the memory device, wherein the signals are represented by voltages within a certain voltage range; The memory device enters a switching mode in response to a switching mode entry signal, wherein the switching mode entry signal is represented by a voltage on one of the plurality of input pins that intersects with a reference voltage outside the voltage range; as well as When the memory device is in the switching mode, the signals on the plurality of input pins are ignored.

8. The method of claim 7, further comprising refreshing word lines of the memory array when the memory device is in the switching mode.

9. The method of claim 7, further comprising exiting the switching mode in response to a switching mode exit signal, wherein the switching mode exit signal is represented by the voltage on one of the plurality of input pins that crosses the reference voltage.

10. The method of claim 7, further comprising exiting the switching mode in response to a switching mode exit signal, wherein the switching mode exit signal is represented by the voltage on another of the plurality of input pins that crosses a second reference voltage.

11. The method of claim 7, further comprising: Receive commands from the first system-on-a-chip (SoC) before entering the switching mode; Exit the aforementioned change mode; as well as After exiting the change mode, a command is received from the second SoC.

12. The method of claim 7, wherein the signals on the plurality of input pins include commands, addresses, and combinations thereof.

13. The method of claim 7, further comprising: The voltage on one of the plurality of input pins is compared with the reference voltage using a first decoder circuit to determine whether the voltage indicates the change mode entry signal. as well as The state of the signal is determined by comparing the voltage on one of the plurality of input pins with different reference voltages using a second decoder circuit.

14. A system for switching on-chip systems, comprising: A memory device configured to store information; The first system-on-a-chip (SoC) is configured to act as a controller for the memory device; Second SoC; as well as The command address CA bus couples the first SoC and the second SoC to the memory device. The first SoC is configured to provide a switch mode entry signal along the CA bus to put the memory device into switch mode. The memory device is configured to retain the information in the memory device when in the switching mode, and The second SoC is configured to take over the controller of the memory device.

15. The system of claim 14, wherein when in the switching mode, the memory device is configured to refresh the memory array of the memory device and ignore signals along the CA bus, except for the switching mode exit signal.

16. The system of claim 14, wherein the second SoC is configured to provide a switch mode exit signal along the CA bus, and wherein the memory device exits the switch mode in response to the switch mode exit signal.

17. The system of claim 16, wherein the CA bus comprises a plurality of pins, and wherein the change mode entry signal and the change mode exit signal are carried by the same pin among the plurality of pins.

18. The system of claim 16, wherein the CA bus comprises a plurality of pins, and wherein the change mode entry signal and the change mode exit signal are carried by different pins of the plurality of pins.

19. The system of claim 14, wherein the change mode entry signal is a voltage outside the voltage range of other signals on the CA bus.

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