Display device and method of driving the same

Abstract

The present invention discloses a display device and a method for driving the display device. The display device includes a display panel, and the display panel includes multiple gate lines, multiple data lines, and multiple pixels connected to the multiple data lines and the multiple gate lines. A data driver provides data signals to the multiple data lines. The gate driver uses a clock signal to sequentially generate gate signals corresponding to a start pulse, and provides the gate signals to the multiple gate lines. A timing controller provides the clock signal and the start pulse to the gate driver. The gate driver compares the data signal provided to the first data line among the multiple data lines with at least one of the gate signals to generate a feedback signal. The timing controller sets a delay value of the clock signal based on the feedback signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2020-0064180, filed on May 28, 2020, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a display device and a method for driving the display device. More particularly, the present disclosure relates to a display device capable of improving signal processing of the display device and a method for driving the display device. Background Art

[0004] The display device includes data lines, gate lines, and pixels connected to the data lines and the gate lines. Each pixel writes or charges a data signal into a storage capacitor in response to a gate signal and emits light with a brightness corresponding to the charged data signal using a light emitting element.

[0005] When a data signal has a resistance-capacitance delay (hereinafter referred to as RC delay), the timing of supplying the data signal may not match the timing of supplying the gate signal. In this case, the data signal cannot fully charge the storage capacitor of the pixel, and the pixel may not emit light at the desired brightness. Therefore, there is a need to develop a new display device that can improve the brightness of the display device and a method for driving the display device. Summary of the Invention

[0006] An object of the present disclosure is to provide a display device capable of accurately determining a timing at which a gate signal is supplied corresponding to an RC delay of a data signal and a method of driving the display device.

[0007] To achieve the purpose of the present disclosure, a display device according to an embodiment of the present disclosure may include: a display panel including gate lines, data lines, and pixels connected to the data lines and the gate lines; a data driver that provides data signals to the data lines; a gate driver that sequentially generates gate signals corresponding to start pulses using a clock signal and provides the gate signals to the gate lines; and a timing controller that provides the clock signal and the start pulse to the gate driver. The gate driver may generate a feedback signal by comparing a data signal provided to a first data line among a plurality of data lines with at least one of the gate signals, and the timing controller may set a delay value of the clock signal based on the feedback signal.

[0008] According to an embodiment, a first data line among the data lines may be closest to the gate driver.

[0009] According to an embodiment, the display device may further include a first connection line adjacent to an nth gate line (where n is a positive integer) among the gate lines and connected to the first data line, and the gate driver may receive a data signal through the first connection line and compare the nth gate signal applied to the nth gate line with the data signal.

[0010] According to an embodiment, the data signal measured at the first connection line may have a resistance-capacitance delay with respect to the data signal measured at the output terminal of the data driver.

[0011] According to an embodiment, the gate driver may include a plurality of gate drive circuits. A first gate drive circuit among the gate drive circuits may include: a plurality of stages respectively connected to a first group of gate lines corresponding to the gate lines; and a comparator respectively connected to the nth gate line and the first connection line. Each of the stages may output a clock signal as a gate signal in response to a start pulse or a carry signal of a previous stage.

[0012] According to an embodiment, the nth gate line among the first group of gate lines may be farthest from the data driver.

[0013] According to an embodiment, the nth gate signal may vary within a first voltage range, the data signal may vary within a second voltage range, and the second voltage range may be a subset of the first voltage range.

[0014] According to an embodiment, the comparator may output a feedback signal having a first logic level when the voltage level of the nth gate signal is greater than or equal to the voltage level of the data signal, and output a feedback signal having a second logic level when the voltage level of the gate signal is lower than the voltage level of the data signal.

[0015] According to an embodiment, the feedback signal may include a pulse, and the pulse may have a first edge and a second edge that appear sequentially. The timing controller may determine the delay value of the clock signal based on a change in timing of the second edge of the pulse relative to the clock signal.

[0016] According to an embodiment, the timing controller may include: a clock generator that generates a reference clock signal and a delayed clock signal in which the reference clock signal is delayed; a delay time calculator that calculates the timing of the second edge of the feedback signal; and a delay value determination unit that controls the clock generator to output one of the reference clock signal and the delayed clock signal as a clock signal based on a change in timing.

[0017] According to an embodiment, when the second edge is maintained within the reference range and then outside the reference range according to the timing variation of the delayed clock signal, the delay value determination unit may determine the delay value of the clock signal based on the first timing among the timings maintained within the reference range.

[0018] According to an embodiment, the delay value determining unit may select a first delay value of the delayed clock signal corresponding to the first timing, and may respectively set sub-delay values ​​of pulses of the clock signal by interpolating the first delay value based on the nth gate line.

[0019] According to an embodiment, the clock generator may generate the clock signal by respectively delaying pulses of the external clock signal based on the sub-delay values.

[0020] According to an embodiment, the delay value determining unit may select a first delay value of the delayed clock signal corresponding to the first timing, and determine the period of the clock signal based on the first delay value.

[0021] According to an embodiment, the timing controller can determine a first delay value of the clock signal in a first interval corresponding to the first gate driving circuit, and determine a second delay value of the clock signal in a second interval corresponding to the second gate driving circuit among the gate driving circuits based on the first delay value.

[0022] According to an embodiment, the gate driving circuits may be connected to each other through one feedback line and connected to the timing controller through the feedback line.

[0023] According to an embodiment, the clock signal may include a plurality of sub-clock signals, each sub-clock signal being provided to a corresponding gate driving circuit among the gate driving circuits.

[0024] To achieve the purpose of the present disclosure, a method for driving a display device according to an embodiment of the present disclosure may include: providing a data signal to a data line through a data driver, and sequentially providing a clock signal as a gate signal to the gate lines through a gate driver; comparing a data signal provided to a first data line among the data lines with at least one of the gate signals through the gate driver to generate a feedback signal; calculating a delay time of the feedback signal based on the clock signal by a timing controller; and setting a delay value of the clock signal based on a change in the delay time of the feedback signal.

[0025] According to an embodiment, setting the delay value of the clock signal may include: determining whether a change in the delay time is outside a reference range; when the change in the delay time is within the reference range, increasing the delay value for delaying the clock signal; and repeatedly providing the clock signal as a gate signal to the gate line sequentially and generating a feedback signal.

[0026] According to an embodiment, setting the delay value of the clock signal may further include respectively setting sub-delay values ​​of pulses of the clock signal based on a previous delay value of the clock signal when a variation of the delay time is outside a reference range. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0028] Figure 1 is a diagram illustrating a display device according to an embodiment of the present disclosure.

[0029] Figure 2 It is an icon Figure 1 FIG. 1 is a diagram of an example of a display device.

[0030] Figure 3 The diagram is included in Figure 2 A waveform diagram of a data signal measured at a first data line in a display device.

[0031] Figure 4 The diagram is included in Figure 2 FIG. 1 is a diagram of an example of a first gate driver IC in a display device.

[0032] Figure 5 It is used to describe the Figure 4 FIG1 is a waveform diagram of the operation of the first gate driver IC stage.

[0033] Figure 6 It is used to describe the Figure 4 FIG1 is a waveform diagram of the operation of the comparator in the first gate driver IC.

[0034] Figure 7 The diagram is included in Figure 1 A block diagram of an example of a timing controller in a display device.

[0035] Figure 8 The diagram is provided by Figure 7 FIG1 is a waveform diagram of an example of a reference clock signal and a delayed clock signal generated by a timing controller.

[0036] Figure 9A and Figure 9B Is used to illustrate Figure 7 Waveform diagram of the process of setting the clock signal in the timing controller.

[0037] Figure 10A and Figure 10B The diagram is provided by Figure 7 FIG1 is a waveform diagram of an example of a clock signal set by a timing controller.

[0038] Figure 11 It is an icon Figure 1 FIG. 1 is a diagram of another example of a display device.

[0039] Figure 12 The diagram is included in Figure 11FIG. 1 is a waveform diagram of an example of a clock signal set by a timing controller in a display device.

[0040] Figure 13 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0041] Hereinafter, various embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that those skilled in the art can easily practice the present disclosure. The present disclosure can be implemented in various forms and is not limited to the embodiments described in this specification.

[0042] In order to clearly describe the present disclosure, parts that are not related to the description are omitted. Throughout the specification, the same or similar parts are represented by the same reference numerals. Therefore, the above reference numerals can be used in other drawings.

[0043] Figure 1 : is a diagram illustrating a display device according to an embodiment of the present disclosure. As one of the embodiments to which the present disclosure can be applied, Figure 1 The display device including multiple gate driver ICs and multiple data driver ICs is shown. However, the present disclosure is not limited thereto. For example, the present disclosure can also be applied to a display device including one gate driver IC and one data driver IC.

[0044] refer to Figure 1 and Figure 2 The display device 10 may include a display panel 100 (or a display unit), a gate driver 200, a data driver 300 (or a source driver), and a timing controller (TCON) 410. The gate driver 200 may include a gate driver integrated circuit 210 (hereinafter, the integrated circuit is referred to as "IC") (or a gate driving circuit), and the data driver 300 may include a data driver IC 310 (source driver IC, or a data driving circuit).

[0045] The display panel 100 may include a display area 110 for displaying an image and a non-display area 120 outside the display area 110. The display panel 100 may include gate lines, data lines, and pixels. Figure 2 A specific configuration of the display panel 100 is described.

[0046] The timing controller 410 can control the gate driver IC 210 and the data driver IC 310. The timing controller 410 can receive a control signal (e.g., a control signal including an external clock signal) from an external source (not shown) and generate a gate control signal and a data control signal based on the control signal. The timing controller 410 can provide the gate control signal to the gate driver IC 210 and the data control signal to the data driver IC 310.

[0047] In addition, the timing controller 410 may rearrange input data (or raw image data) provided from an external source (e.g., a graphics processor) to generate image data, and provide the image data to the data driver IC 310. The timing controller 410 may be mounted on the control board 400, or the timing controller 410 may be integrated with the control board 400.

[0048] The gate driver IC 210 and the data driver IC 310 may drive the display panel 100 .

[0049] The gate driver IC 210 may receive a gate control signal from the timing controller 410 and generate a gate signal based on the gate control signal. The gate driver IC 210 may provide the gate signal to the display panel 100.

[0050] The gate driver IC 210 may be mounted on the gate driver circuit film 220 and connected to the timing controller 410 mounted on the control board 400 via at least one data driver circuit film 320 (or source driver circuit film), a data printed circuit board 330 (or source printed circuit board), and / or a cable 500 (or flexible circuit board). However, the present disclosure is not limited thereto. For example, the gate driver IC 210 may be formed in the display panel 100 together with the pixels.

[0051] The data driver IC 310 may receive a data control signal and image data from the timing controller 410 and generate a data signal corresponding to the image data. The data driver IC 310 may provide the data signal to the display panel 100. The data driver IC 310 may be mounted on the data driving circuit film 320 and connected to the timing controller 410 via at least one data printed circuit board 330 and / or a cable 500.

[0052] The cable 500 may electrically connect the control board 400 and at least one data printed circuit board 330 through the upper connector 510 and the lower connector 520. Here, the cable 500 may refer to a device having wiring capable of electrically connecting the control board 400 and the data printed circuit board 330. For example, the cable 500 may be implemented as a flexible circuit board.

[0053] Figure 2 It is an icon Figure 1 FIG. 1 is a diagram showing an example of a display device. Figure 1 The simplified configuration of the display device 10 shown in FIG. Figure 2 Briefly shows Figure 1 , a first gate driver IC 210 - 1 and a second gate driver IC 210 - 2 are shown among the gate driver ICs.

[0054] refer to Figure 1 and Figure 2 , the display area 110 (or the display panel 100 ) may include gate lines GL1 to GLn and GLn+1 to GL2n, connection lines CL1 and CL2 , data lines DL1 , DL2 , . . . and DLm, and pixels PXL1 and PXL2 , where n and m are positive integers.

[0055] The gate lines GL1 to GLn and GLn+1 to GL2n may extend in the first direction DR1 and may be sequentially arranged along the second direction DR2.

[0056] The gate lines GL1 to GLn and GLn+1 to GL2n may be divided into a plurality of groups (or gate line groups) corresponding to the first gate driver IC 210-1 and the second gate driver IC 210-2, respectively. For example, the gate lines GL1 to GLn and GLn+1 to GL2n may include a first group of gate lines GL1 to GLn (or a first gate line group) and a second group of gate lines GLn+1 to GL2n (or a second gate line group). The first group of gate lines GL1 to GLn may include the first gate line GL1 to the nth gate line GLn and may be connected to the first gate driver IC 210-1. The second group of gate lines GLn+1 to GL2n may include the n+1th gate line GLn+1 to the 2nth gate line GL2n and may be connected to the second gate driver IC 210-2. For example, Figure 1 As shown in , when the display device 10 includes nine gate driver ICs, the gate lines GL1 to GLn and GLn+1 to GL2n may include nine gate line groups corresponding to the nine gate driver ICs, respectively. Each of the nine gate line groups may include n gate lines. The number of gate lines included in each gate line group in the gate line group may be different for each gate line group.

[0057] The data lines DL1 , DL2 , . . . , and DLm may extend in the second direction DR2 and may be sequentially arranged along the first direction DR1 .

[0058] In an embodiment, the first data line DL1 among the data lines DL1, DL2, ..., and DLm may be arranged closest to the first gate driver IC 210-1 and the second gate driver IC 210-2. As will be described later, although the display device 10 (or the timing controller 410) sets the clock signal CLK (or the delay value or period of the clock signal) for the first gate driver IC 210-1 and the second gate driver IC 210-2 in the clock setting interval, a test signal (e.g., a data signal corresponding to white) may be provided to the first data line DL1.

[0059] In an embodiment, the first data line DL1 may be a dummy line. In this case, when an image is displayed on the display area 110, for example, during a display interval, a valid data signal may not be provided to the first data line DL1, or a black data signal corresponding to black may be provided to the first data line DL1. Valid data signals may be provided to the second to mth data lines DL2 to DLm.

[0060] Connection lines CL1 and CL2 may be arranged between gate lines GL1 to GLn and GLn+1 to GL2n and extend in the first direction DR1. In addition, connection lines CL1 and CL2 may connect the first gate driver IC 210-1 and the second gate driver IC 210-2 with the first data line DL1, respectively.

[0061] For example, the first connection line CL1 may be arranged between the nth gate line GLn and the n+1th gate line GLn+1 or adjacent to the nth gate line GLn. In addition, the first connection line CL1 may extend in the first direction DR1 and connect the first gate driver IC 210-1 and the first data line DL1. In this case, the first gate driver IC 210-1 may receive a data signal (e.g., a data signal applied to the first data line DL1) through the first connection line CL1. Similarly, the second connection line CL2 may be arranged adjacent to the 2nth gate line GL2n and may connect the second gate driver IC 210-2 and the first data line DL1. In this case, the second gate driver IC 210-2 may receive a data signal (e.g., a data signal applied to the first data line DL1) through the second connection line CL2.

[0062] At the same time, Figure 2 , the first connection line CL1 is shown as being adjacent to the nth gate line GLn, which is the last gate line among the first gate line GL1 to the nth gate line GLn, but the position of the first connection line CL1 is not limited thereto. For example, the first connection line CL1 can be adjacent to any one of the first gate line GL1 to the nth gate line GLn (for example, a gate line in the middle order among the first gate line GL1 to the nth gate line GLn). However, as will be described later, since the position of the first connection line CL1 is far away from the data driver 300 (that is, the point where the data signal is supplied), the RC delay of the data signal can be measured more accurately. Therefore, a more optimized clock signal CLK can be set for the first gate driver IC 210-1.

[0063] Pixels PXL1 and PXL2 may be placed in an area where gate lines GL1 to GLn and GLn+1 to GL2n intersect data lines DL1, DL2, ..., and DLm, or in an area divided by gate lines GL1 to GLn and GLn+1 to GL2n and data lines DL1, DL2, ..., and DLm.

[0064] Each of the pixels PXL1 and PXL2 can be connected to a corresponding gate line among the gate lines GL1 to GLn and GLn+1 to GL2n and a corresponding data line among the data lines DL1, DL2, ... and DLm, and can emit light having a brightness corresponding to the data signal (i.e., the data signal provided by the corresponding data line) in response to a gate signal (i.e., the gate signal provided by the corresponding gate line). To this end, each of the pixels PXL1 and PXL2 may include at least one light-emitting element, a switching transistor that transmits the data signal in response to the gate signal, a storage capacitor that stores the data signal transmitted by the switching transistor, and a driving transistor that provides a driving current to the at least one light-emitting element in response to the stored data signal. Here, the light-emitting element may be an organic light-emitting element or an inorganic light-emitting element.

[0065] In an embodiment, when the first data line DL1 is a dummy line, the first pixels PXL1 connected to the first data line DL1 may be dummy pixels. For example, each of the first pixels PXL1 may include only pixel circuits such as a switching transistor and a driving transistor, and may not include a light-emitting element. Meanwhile, the second pixels PXL2 connected to the second data lines DL2 to the mth data line DLm may be effective pixels. Each of the second pixels PXL2 may include a switching transistor, a driving transistor, a storage capacitor, and a light-emitting element as described above, and emit light having a brightness corresponding to the data signal.

[0066] The first gate driver IC 210-1 may receive a clock signal CLK from the timing controller 410 via a clock line CLKL and receive a start pulse STV (or start signal) via a control line CL. The first gate driver IC 210-1 may sequentially generate gate signals corresponding to the start pulse STV using the clock signal CLK and sequentially provide the gate signals to the first to n-th gate lines GL1 to GLn. For example, the first gate driver IC 210-1 may be implemented as a shift register (or stage) for sequentially shifting and outputting the start pulse STV.

[0067] In an embodiment, the first gate driver IC 210-1 may compare the nth gate signal (i.e., the gate signal applied to the nth gate line GLn) with the data signal (i.e., the data signal provided through the first connection line CL1) to generate a feedback signal FB. The feedback signal FB may be provided to the timing controller 410 through the feedback line FBL.

[0068] Will refer to it later Figure 4 A detailed configuration and operation of the first gate driver IC 210 - 1 are described.

[0069] Similarly, the second gate driver IC 210-2 can receive a clock signal CLK from the timing controller 410 via the clock line CLKL and receive a carry signal (e.g., a carry signal corresponding to or identical to the gate signal provided to the nth gate line GLn) from the first gate driver IC 210-1. Furthermore, the second gate driver IC 210-2 can sequentially generate gate signals corresponding to the carry signal using the clock signal CLK and sequentially provide the gate signals to the n+1th gate line GLn+1 through the 2nth gate line GL2n. Furthermore, the second gate driver IC 210-2 can compare the 2nth gate signal (i.e., the gate signal applied to the 2nth gate line GL2n) with the data signal (i.e., the data signal provided via the second connection line CL2) to generate a feedback signal FB. The feedback signal FB of the second gate driver IC 210-2 can be provided to the timing controller 410 via the feedback line FBL, through which the feedback signal FB of the first gate driver IC 210-1 is transmitted.

[0070] The data driver 300 may generate data signals (or data voltages) based on the image data DATA and the data control signal DCS provided from the timing controller 410 and provide the data signals to the data lines DL1 , DL2 , . . . , and DLm.

[0071] In an embodiment, the data driver 300 may provide a test signal to the first data line DL1 in a setup interval of the display device 10. For example, the test signal may include a data signal for a pixel connected to the nth gate line GLn. For example, the test signal may include a data signal corresponding to white. As described above, since the first gate driver IC 210-1 compares the nth gate signal (i.e., the gate signal applied to the nth gate line GLn) with the data signal, the test signal may include a data signal corresponding to the time point of supplying the nth gate signal. Similarly, the test signal may include a data signal for a pixel connected to the 2nth gate line GL2n.

[0072] The timing controller 410 may generate a clock signal CLK, a start pulse STV, a data control signal DCS, and image data DATA.

[0073] In an embodiment, the timing controller 410 may generate the clock signal CLK based on an external clock signal provided from the outside, but adjust or change the delay value of the clock signal CLK (e.g., the time of delaying the external clock signal) based on the feedback signal FB. In other words, the timing controller 410 may change the period of the clock signal CLK.

[0074] For example, in the clock setting interval of the display device 10, the timing controller 410 can sequentially receive the feedback signal FB corresponding to the delayed clock signal while providing multiple delayed clock signals to the gate driver ICs 210-1 and 210-2, and determine the delay value (or period) of the clock signal CLK based on the change of the feedback signal FB. Here, the multiple delayed clock signals can have the same waveform as the external clock signal, but can have different phases. The feedback signal FB can be generated by comparing the gate signal and the data signal, and can include or reflect the delay information of the data signal based on the gate signal (for example, delay time information). This is because the data signal has a relatively large RC delay while overlapping with other components in the display area 110 (for example, transistors and power lines, etc.), while the gate signal applied to the gate line that does not overlap with other components (specifically the gate signal at the output terminal of the gate driver ICs 210-1 and 210-2) has a relatively small RC delay.

[0075] Therefore, the timing controller 410 can determine the delay value (or period) of the clock signal CLK based on the change of the feedback signal FB (for example, the interval in which the change of the feedback signal FB has a minimum value or is maintained at the minimum value (and the delayed clock signal corresponding to the interval)). For example, the timing controller 410 can compare the feedback signal FB with the reference clock signal (that is, the delayed clock signal generated based on the feedback signal FB) to extract the delay information of the data signal, select or determine the delayed clock signal that maintains the delay information at the minimum value, and set the clock signal CLK based on the delay value of the delayed clock signal.

[0076] Will refer to it later Figure 7 、 Figure 8 、 Figure 9A 、 Figure 9B 、 Figure 10A and Figure 10B A configuration in which the timing controller 410 sets a delay value (or period) of the clock signal CLK is described.

[0077] As reference Figure 2 As described, the first gate driver IC 210-1 (or Figure 1The gate driver 200 shown in the figure can receive the data signal (or test signal) of the first data line DL1 through the first connection line CL1, and compare the nth gate signal applied to the nth gate line GLn adjacent to the first connection line CL1 with the data signal to generate a feedback signal FB (i.e., a signal containing delay information of the data signal). The timing controller 410 can set the clock signal CLK based on the feedback signal FB (e.g., a clock signal that allows the gate signal to be provided to the gate line at a timing consistent with the data signal with RC delay). That is, the display device 10 can detect the RC delay of the data signal (or the interval in which the peak value of the data signal is supplied) and determine the timing of supplying the gate signal in response to the delay of the data signal. Therefore, the pixel (e.g., the second pixel PXL2) can charge the data signal in response to the gate signal to emit light with a desired brightness. Therefore, the quality of the image displayed on the display area 110 can be improved.

[0078] Figure 3 The diagram is included in Figure 2 A waveform diagram of a data signal measured at a first data line in a display device.

[0079] refer to Figure 2 and Figure 3 The first curve C_VDATA1 may represent a data signal measured at one end of the first data line DL1 (e.g., one end connected to the output terminal of the data driver 300) or a first point of the first data line DL1 overlapping the first gate line GL1. The second curve C_VDATA2 may represent a data signal measured at a second point of the first data line DL1 connected to the second connection line CL2 or the other end of the first data line DL1.

[0080] According to the first curve C_VDATA1, the data signal at the first point of the first data line DL1 can change from a first voltage level (e.g., a voltage level corresponding to black) to a second voltage level (e.g., a voltage level corresponding to white) at a first time point TP1, be maintained at the second voltage level in the interval between the first time point TP1 and the second time point TP2, and change from the second voltage level to the first voltage level at the second time point TP2.

[0081] At the same time, according to the second curve C_VDATA2, the data signal at the second point of the first data line DL1 can change from the first voltage level to the second voltage level starting at the first time point TP1', and can change from the second voltage level to the first voltage level (or a third voltage level that is close to the second voltage level but lower than the second voltage level) at the second time point TP2'. In this case, the data signal at the second point of the first data line DL1 can maintain a relatively gentle slope in the interval between the first time point TP1' and the second time point TP2'. Here, the first time point TP1' can be a time point delayed by a predetermined time from the first time point TP1. Similarly, the second time point TP2' can be a time point delayed by a predetermined time from the second time point TP2.

[0082] The first data line DL1 (or data lines DL1, DL2, ... and DLm) may overlap with the gate lines GL1 to GLn and GLn+1 to GL2n, the power lines and the light-emitting elements in the display area 110, and have a capacitance formed by these relationships. Due to the resistance and capacitance of the first data line DL1, an RC delay may occur in the data signal. Therefore, the data signal at a second point relatively spaced from the data driver 300 may have an RC delay based on the data signal at the first point. As the distance from the data driver 300 increases, the RC delay of the data signal may increase. In addition, as the display device 10 becomes larger and becomes higher resolution, the resistance and capacitance of the first data line DL1 (or data lines DL1, DL2, ... and DLm) may increase, and the RC delay of the data signal may further increase.

[0083] Meanwhile, the clock line CLKL may be arranged outside the display area 110 (ie, arranged between Figure 1 ), and the area of ​​the clock line CLKL that overlaps with other components (e.g., signal lines) can be small. Therefore, the clock signal CLK transmitted through the clock line CLKL and the gate signal output based on the clock signal (specifically, the gate signal at the point overlapping with the first data line DL1) can have a small RC delay. Therefore, the interval in which the data signal has a peak at the second point (i.e., the data signal has a relatively large RC delay) may not coincide with the time point (or interval) when the gate signal (or gate pulse) is supplied, and the data signal may not be fully charged into the pixel corresponding to the second point.

[0084] Therefore, the display device 10 can use the feedback signal FB to detect the interval in which the data signal (i.e., the data signal with RC delay) has a peak value, and adjust or set the delay value (or period) of the clock signal CLK so that the gate signal can be supplied in the interval.

[0085] Figure 4The diagram is included in Figure 2 FIG. 1 is a diagram of an example of a first gate driver IC in a display device. Figure 2 The first gate driver IC 210-1 and the second gate driver IC 210-2 (and Figure 1 2. The gate driver ICs shown in FIG. 21 are substantially the same except for the positions where they are arranged. Therefore, the first gate driver IC 210-1 that can cover the first gate driver IC 210-1 and the second gate driver IC 210-2 will be described. Figure 5 It is used to describe the Figure 4 FIG1 is a waveform diagram of the operation of the first gate driver IC stage.

[0086] First, refer to Figure 2 and Figure 4 , the first gate driver IC 210 - 1 (or a first gate driving circuit) may include stages ST1 , ST2 , . . . , and STn (or stage circuits) and a comparator COMP.

[0087] The stages ST1, ST2, ..., and STn may be connected to a first sub-clock line CLKL_S1, a second sub-clock line CLKL_S2, and a power supply line VL. The stages ST1, ST2, ..., and STn may receive a first sub-clock signal CLK_S1 provided through the first sub-clock line CLKL_S1, a second sub-clock signal CLK_S2 provided through the second sub-clock line CLKL_S2, and a logic low level VGL (or gate-off level) voltage provided through the power supply line VL as input signals. The first sub-clock line CLKL_S1 and the second sub-clock line CLKL_S2 may be included in a reference line. Figure 2 The second sub-clock signal CLK_S2 may have the same waveform as the first sub-clock signal CLK_S1 but may have a different phase from the first sub-clock signal CLK_S1.

[0088] In addition, stages ST1, ST2, ... and STn can be respectively connected to the first to nth gate lines GL1, GL2, ... and GLn (or a first group of gate lines), and sequentially provide or output first to nth gate signals GS1, GS2, ... and GSn to the first to nth gate lines GL1, GL2, ... and GLn.

[0089] Each of the stages ST1 , ST2 , . . . , and STn may output a clock signal as a gate signal in response to a start pulse STV or a carry signal of a previous stage.

[0090] For example, the first stage ST1 may include a node control circuit NCC and a buffer BUFF. The node control circuit NCC of the first stage ST1 may control the voltage of the first node Q and the voltage of the second node QB based on the start pulse STV. The buffer BUFF of the first stage ST1 may include a first transistor T1 and a second transistor T2. The first transistor T1 and the second transistor T2 may be N-type transistors, but the present disclosure is not limited thereto. In some cases, the first transistor T1 and the second transistor T2 may be implemented as P-type transistors.

[0091] In the first stage ST1, a first electrode of the first transistor T1 may be connected to the first sub clock line CLKL_S1, a second electrode of the first transistor T1 may be connected to the first gate line GL1, and a gate electrode of the first transistor T1 may be connected to a first node Q. A first electrode of the second transistor T2 may be connected to the first gate line GL1, a second electrode of the second transistor T2 may be connected to the power line VL, and a gate electrode of the second transistor T2 may be connected to a second node QB.

[0092] In the first stage ST1, when the node control circuit NCC adjusts the voltage of the first node Q to a logic high level in response to the start pulse STV, the first transistor T1 may be turned on, and the first sub-clock signal CLK_S1 may be provided to the first gate line GL1 as the first gate signal GS1. In the first stage ST1, when the start pulse STV is not applied, the node control circuit NCC may maintain the voltage of the second node QB at a logic high level. In this case, the second transistor T2 may be turned on, and the first gate signal GS1 may be maintained to have a logic low level VGL, or the logic low level VGL may be applied to the first gate line GL1.

[0093] Circuit configurations of the second to n-th stages ST2 to STn may be substantially the same as or similar to that of the first stage ST1 , and thus repeated descriptions will be omitted.

[0094] The second stage ST2 can control the voltage of the first node Q based on the first carry signal CR1, and output the second sub-clock signal CLK_S2 provided by the second sub-clock line CLKL_S2 to the second gate line GL2 as the second gate signal GS2. Here, the first carry signal CR1 can be provided from the first stage ST1 (i.e., the previous stage of the second stage ST2) and can have the same waveform and phase as the first gate signal GS1. For example, the first stage ST1 can mirror the first gate signal GS1 and output the first carry signal CR1.

[0095] Similarly, the nth stage STn may control the voltage of the first node Q based on the n-1th carry signal CRn-1 and output the second sub clock signal CLK_S2 provided through the second sub clock line CLKL_S2 to the nth gate line GLn as the nth gate signal GSn.

[0096] refer to Figure 5 , the first sub-clock signal CLK_S1 may have a first period PER1 and may have a logic high level and a logic low level that alternately repeat within the first period PER1. For example, an interval in which the first sub-clock signal CLK_S1 has a logic high level may have a first width PW1, and an interval in which the first sub-clock signal CLK_S1 has a logic low level may have a second width PW2. The first width PW1 and the second width PW2 may be the same and may have one horizontal time. However, the present disclosure is not limited thereto. For example, the second width PW2 may be greater than the first width PW1.

[0097] The start pulse STV may include a logic high level pulse.

[0098] In this case, the node control circuit NCC of the first stage ST1 may change the voltage of the first node Q to a logic high level and maintain the voltage of the first node Q at a logic high level during one horizontal time after the start pulse STV is applied. In this case, the first stage ST1 may output the first sub-clock signal CLK_S1 having a logic high level (i.e., one pulse of the first sub-clock signal CLK_S1) as the first gate signal GS1.

[0099] Similarly, the second stage ST2 can change the voltage of the first node Q to a logic high level in response to the first carry signal CR1 (i.e., the carry signal corresponding to the first gate signal GS1), maintain the voltage of the first node Q at a logic high level during one horizontal time after the first carry signal CR1 is applied, and output a second sub-clock signal CLK_S2 having a logic high level (i.e., one pulse of the second sub-clock signal CLK_S2) as the second gate signal GS2. In this way, the stages ST1, ST2, . . . and STn can sequentially output gate signals corresponding to the start pulse STV.

[0100] At the same time, Figure 5 , the start pulse STV and the gate signals GS1 and GS2 are shown to have a logic high level. However, this is an example, and the start pulse STV and the gate signals GS1 and GS2 are not limited thereto. For example, when the pixels PXL1 and PXL2 (refer to Figure 2) includes a P-type transistor instead of an N-type transistor, the start pulse STV and the gate signals GS1 and GS2 may have a logic low level. That is, the voltage levels (or waveforms) of the start pulse STV and the gate signals GS1 and GS2 may be determined according to the pixel PXL1 and PXL2 (reference Figure 2 ) varies depending on the type of transistor in the circuit.

[0101] Return Reference Figure 4 The comparator COMP may be connected to the nth gate line GLn and the first data line DL1 , respectively, and receive an nth gate signal GSn provided through the nth gate line GLn and a data signal provided through the first data line DL1 as input signals.

[0102] The comparator COMP can compare the nth gate signal GSn with the data signal and output the comparison result as the feedback signal FB. For example, the comparator COMP can be composed of a logic circuit including an amplifier. For example, when the voltage of the nth gate signal GSn is greater than or equal to the voltage of the data signal, the comparator COMP can output a first logic value (e.g., 1) (or a feedback signal FB having a first logic level). In addition, when the voltage of the nth gate signal GSn is less than the voltage of the data signal, the comparator COMP can output a second logic value (e.g., 0) (or a feedback signal FB having a second logic level).

[0103] You can refer to Figure 6 To describe the operation of the comparator COMP.

[0104] Figure 6 It is used to describe the Figure 4 FIG1 is a waveform diagram of the operation of the comparator in the first gate driver IC.

[0105] refer to Figure 4 、 Figure 5 and Figure 6 , the clock signal CLK (eg, the second sub-clock signal CLK_S2 ) may change from a logic low level to a logic high level at the first reference time point TP_REF1 , and change from a logic high level to a logic low level at the second reference time point TP_REF2 .

[0106] In this case, at least one of the stages ST1 to STn may output the gate signal GS using the clock signal CLK. For example, the nth stage STn may output the pulse of the second sub-clock signal CLK_S2 to the nth gate line GLn as the nth gate signal GSn.

[0107] The gate signal GS may change from a logic low level to a logic high level starting at a first reference time point TP_REF1, and may have a logic high level at a time point after a predetermined time has passed from the first reference time point TP_REF1. Furthermore, the gate signal GS may change from a logic high level to a logic low level starting at a second reference time point TP_REF2, and may have a logic low level after a predetermined time has passed from the second reference time point TP_REF2. The gate signal GS may have some response delay due to circuit elements of the stage, but the magnitude of the delay is relatively small and can be ignored.

[0108] The data signal VDATA may change from a first voltage level (e.g., a voltage level corresponding to black) to a second voltage level (e.g., a voltage level corresponding to white) corresponding to the gate signal GS. At the same time, the data signal VDATA (e.g., a test signal) may have a voltage level corresponding to the reference voltage. Figure 3 The first curve C_VDATA1 described above has substantially the same waveform, and therefore, repeated description will be omitted.

[0109] For example, the data signal VDATA may change from the first voltage level to the second voltage level before the first reference time point TP_REF1, and may have the second voltage level in the interval between the first reference time point TP_REF1 and the second reference time point TP_REF2. In addition, the data signal VDATA may change from the second voltage level to the first voltage level after the second reference time point TP_REF2.

[0110] For reference, the data signal VDATA may vary within a second voltage range VR2. For example, the size of the second voltage range VR2 (i.e., the difference between the second voltage level and the first voltage level) may be approximately 15V. The gate signal GS may vary within a first voltage range VR1. For example, the size of the first voltage range VR1 (i.e., the difference between a logic high level and a logic low level) may be approximately 30V. The second voltage range VR2 may be included in the first voltage range VR1 and may be a subset of the first voltage range VR1. That is, for switching (i.e., fully turning on and off) the pixels PXL1 and PXL2 (reference Figure 2 ) can have a voltage range greater than the data signal VDATA for controlling the amount of driving current flowing through the transistor. Figure 1 )(or Figure 2 The gate driver ICs 210 - 1 and 210 - 2 shown in FIG. 1 may receive a data signal VDATA within a first voltage range VR1 and generate a feedback signal FB including delay information of the data signal VDATA.

[0111] At the same time, the comparator COMP can compare the gate signal GS with the data signal VDATA to generate a feedback signal FB. That is, the feedback signal FB can represent the comparison result between the gate signal GS and the data signal VDATA.

[0112] like Figure 6 As shown in , when the voltage level of the gate signal GS is lower than the voltage level of the data signal VDATA, the feedback signal FB may have a logic low level. When the voltage level of the gate signal GS is greater than or equal to the voltage level of the data signal VDATA, the feedback signal FB may have a logic high level. Since the first voltage range VR1 of the gate signal GS is greater than the second voltage range VR2 of the data signal VDATA, the gate signal GS (or gate pulse) may have the same voltage as the data signal VDATA at two points (or time points), and the feedback signal FB may have a logic high level between the two points.

[0113] For example, the voltage level of the gate signal GS and the voltage level of the data signal VDATA may be the same at the start time point TP_START, and the voltage level of the gate signal GS and the voltage level of the data signal VDATA may be the same at the end time point TP_END. Therefore, the feedback signal FB may have a rising edge (or a first edge) at the start time point TP_START and a falling edge (or a second edge) at the end time point TP_END. The feedback signal FB may have a logic high level in the interval between the start time point TP_START and the end time point TP_END.

[0114] When the data signal VDATA has an RC delay, the waveform of the data signal VDATA may be changed. Therefore, the start time point TP_START and / or the end time point TP_END may be changed based on the first reference time point TP_REF1 and / or the second reference time point TP_REF2.

[0115] For example, the time difference D between the first reference time point TP_REF1 and the end time point TP_END may vary according to the RC delay of the data signal VDATA. Figure 2 ) can extract the delay information of the data signal VDATA based on the time difference D.

[0116] In addition, the interval G between the second reference time point TP_REF2 and the end time point TP_END can also be changed according to the RC delay of the data signal VDATA. In this case, the timing controller 410 (reference Figure 2 ) can extract the delay information of the data signal VDATA based on the interval G.

[0117] At the same time, the pulse width W of the feedback signal FB can also be changed according to the RC delay of the data signal VDATA. In this case, the timing controller 410 (refer to Figure 2 ) can extract the delay information of the data signal VDATA based on the pulse width W of the feedback signal FB.

[0118] As will be described later, since the gate signal GS must be supplied to the gate line at the same time as the data signal VDATA has a peak value, the falling edge of the feedback signal FB (i.e., the end time point TP_END) may be a main factor in determining the timing of supplying the gate signal GS (i.e., the delay value of the clock signal CLK). Therefore, the timing controller 410 (refer to Figure 2 ) can set the clock signal CLK (or the delay value of the clock signal CLK) based on the falling edge of the feedback signal FB (ie, the end time point TP_END).

[0119] As reference Figure 6 As described, the comparator COMP may compare the gate signal GS with the data signal VDATA to generate the feedback signal FB, and the falling edge of the feedback signal FB (ie, the end time point TP_END) may include delay information of the data signal VDATA.

[0120] Figure 7 The diagram is included in Figure 1 A block diagram of an example of a timing controller in a display device. Figure 8 The diagram is provided by Figure 7 FIG1 is a waveform diagram of an example of a reference clock signal and a delayed clock signal generated by a timing controller. Figure 9A and Figure 9B Is used to illustrate Figure 7 Waveform diagram of the process of setting the clock signal in the timing controller. Figure 10A and Figure 10B The diagram is provided by Figure 7 FIG1 is a waveform diagram of an example of a clock signal set by a timing controller.

[0121] refer to Figure 1 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9A 、 Figure 9B 、 Figure 10A and Figure 10B The timing controller 410 can set the clock signal CLK optimized for driving the display device 10 based on the change of the falling edge (i.e., the end time point TP_END) of the feedback signal FB while delaying the clock signal CLK. That is, the timing controller 410 can set the delay value (or period) of the clock signal CLK so that the gate signal GS is supplied corresponding to the data signal with the RC delay.

[0122] The timing controller 410 may include a clock generator 710 , a delay time calculator 720 , and a delay value determination unit 730 .

[0123] The clock generator 710 may generate a reference clock signal CLK_REF and delayed clock signals CLK_D1, CLK_D2, and CLK_D3. Here, the reference clock signal CLK_REF may be an external clock signal provided from an external source or a signal in which the external clock signal is delayed by a predetermined time. As will be described later, in setting the Figure 2 When the clock signal CLK of the first gate driver IC210-1 is shown in FIG, the reference clock signal CLK_REF may be an external clock signal. Figure 2 When the clock signal CLK of the second gate driver IC 210-2 is shown in FIG, the reference clock signal CLK_REF may be a clock signal set for the first gate driver IC 210-1. That is, the reference clock signal CLK_REF may be set differently for each gate driver IC.

[0124] The clock generator 710 may generate delayed clock signals CLK_D1 , CLK_D2 , and CLK_D3 by sequentially delaying the reference clock signal CLK_REF by a predetermined time.

[0125] like Figure 8 As shown in FIG, the reference clock signal CLK_REF and the delayed clock signals CLK_D1, CLK_D2 and CLK_D3 may have substantially the same waveform, but may have different phases. Figure 5 The described first sub-clock signal CLK_S1 (or second sub-clock signal CLK_S2 ) is substantially the same or similar, and thus repeated description will be omitted.

[0126] For example, the clock generator 710 can generate a first delayed clock signal CLK_D1 by delaying the reference clock signal CLK_REF by a first delay value DELAY1. Similarly, the clock generator 710 can generate a second delayed clock signal CLK_D2 by delaying the reference clock signal CLK_REF by a second delay value DELAY2. In addition, the clock generator 710 can generate a third delayed clock signal CLK_D3 by delaying the reference clock signal CLK_REF by a third delay value DELAY3. Figure 7, only the first delayed clock signal CLK_D1, the second delayed clock signal CLK_D2, and the third delayed clock signal CLK_D3 are shown. However, this is an example, and the clock generator 710 can generate four or more delayed clock signals using the same method for generating the first delayed clock signal CLK_D1, the second delayed clock signal CLK_D2, and the third delayed clock signal CLK_D3. In addition, the differences between the first delay value DELAY1, the second delay value DELAY2, and the third delay value DELAY3 can be equal to or different from each other, and the first delay value DELAY1, the second delay value DELAY2, and the third delay value DELAY3 can be variously set.

[0127] The clock generator 710 may sequentially output the reference clock signal CLK_REF and the delayed clock signals CLK_D1 , CLK_D2 , and CLK_D3 to the clock line CLKL in a process iteratively performed to set or find the optimal clock signal CLK (ie, in each of a plurality of setting intervals).

[0128] Meanwhile, the gate signal GS (reference clock signal CLK_REF) is outputted from the clock generator 710 and the delayed clock signals CLK_D1, CLK_D2 and CLK_D3. Figure 6 ) can have delay values ​​DELAY1, DELAY2 and DELAY3 respectively.

[0129] like Figure 9A As shown in FIG, the gate signal GS_1 in the first setting interval may be generated based on the reference clock signal CLK_REF and may not have a delay value or may have a delay value of 0. The waveform of the gate signal GS_1 in the first setting interval may be the same as that of the reference clock signal CLK_REF. Figure 6 The waveform of the gate signal GS described in FIG. 1 is substantially the same. In addition, the waveform of the data signal VDATA may be the same as that of the reference signal VDATA. Figure 6 The waveform of the data signal VDATA (or Figure 3 The first curve C_VDATA1 shown in FIG. 1 is substantially the same as that in FIG. Therefore, repeated description will be omitted.

[0130] The gate signal GS_2 in the second setup interval may be generated based on the first delayed clock signal CLK_D1 and may have a first delay value DELAY1. That is, based on the gate signal GS_1 in the first setup interval, the gate signal GS_2 in the second setup interval may have a phase delayed by the first delay value DELAY1.

[0131] The gate signal GS_3 in the third setup interval may be generated based on the second delayed clock signal CLK_D2 and may have a second delay value DELAY2. The gate signal GS_4 in the fourth setup interval may be generated based on the third delayed clock signal CLK_D3 and may have a third delay value DELAY3.

[0132] Return Reference Figure 7 The delay time calculator 720 may receive the feedback signal FB via the feedback line FBL and calculate the delay time of the data signal VDATA based on the feedback signal FB. For example, the delay time calculator 720 may calculate the timing of the falling edge of the feedback signal FB. For example, the delay time calculator 720 may calculate the timing of the falling edge of the feedback signal FB based on the clock signal CLK. For example, the delay time calculator 720 may calculate the timing of the falling edge of the feedback signal FB (i.e., the time difference D) based on the rising edge of the clock signal CLK (e.g., the first reference time point TP_REF1).

[0133] refer to Figure 9A The delay time calculator 720 may calculate a first time difference D1 based on the gate signal GS_1 in the first setting interval, and determine the first time difference D1 as the timing of the falling edge of the feedback signal FB. For example, in the first setting interval, the delay time calculator 720 may calculate the first time difference D1 from the rising edge of the reference clock signal CLK_REF to the falling edge of the feedback signal FB.

[0134] Similarly, according to the gate signal GS_2 in the second setting interval, the delay time calculator 720 can calculate the second time difference D2. For example, in the second setting interval, the delay time calculator 720 can calculate the second time difference D2 from the rising edge of the first delayed clock signal CLK_D1 to the falling edge of the feedback signal FB.

[0135] The delay time calculator 720 may calculate the third time difference D3 based on the gate signal GS_3 in the third setting interval. In addition, the delay time calculator 720 may calculate the fourth time difference D4 based on the gate signal GS_4 in the fourth setting interval.

[0136] However, the present disclosure is not limited thereto. The delay time calculator 720 may determine the timing of the falling edge of the feedback signal FB in various ways. For example, as shown in FIG. Figure 6As described, the delay time calculator 720 can calculate the pulse widths W1, W2, W3, and W4 of the feedback signal FB in the first setting interval, the second setting interval, the third setting interval, and the fourth setting interval, respectively, and determine the pulse widths W1, W2, W3, and W4 as the timing of the falling edge in each of the first setting interval, the second setting interval, the third setting interval, and the fourth setting interval. As another embodiment, the delay time calculator 720 can calculate the reference pulse widths W1, W2, W3, and W4 in the feedback signal FB in the first setting interval, the second setting interval, the third setting interval, and the fourth setting interval. Figure 6 The described interval G (ie, the difference between the second reference time point TP_REF and the end time point TP_END) is determined as the timing of the falling edge.

[0137] Return Reference Figure 7 The delay value determination unit 730 can control the clock generator 710 to output one of the reference clock signal CLK_REF and the delayed clock signals CLK_D1, CLK_D2, and CLK_D3 as the clock signal based on the timing variation of the falling edge of the feedback signal FB. For example, when the timing variation of the falling edge of the feedback signal FB in the corresponding setting interval does not meet a predetermined condition, the delay value determination unit 730 can control the clock generator 710 to output a clock signal with a larger delay value in the next setting interval.

[0138] In an embodiment, when the change in the timing of the falling edge of the feedback signal FB according to the reference clock signal CLK_REF and the delayed clock signals CLK_D1, CLK_D2 and CLK_D3 (i.e., the first, second, third and fourth time differences D1 to D4) is maintained within the reference range and then outside the reference range, the delay value determination unit 730 can finally set the clock signal CLK or finally determine the delay value of the clock signal CLK based on the clock signal (e.g., the second delayed clock signal CLK_D2) corresponding to the timing maintained within the reference range (e.g., the third time difference D3).

[0139] refer to Figure 9A For example, the second time difference D2 (i.e., the timing of the falling edge of the feedback signal FB) in the second setting interval may be close to the first time difference D1 in the first setting interval. That is, the difference between the second time difference D2 and the first time difference D1 may be substantially equal to 0.

[0140] Similarly, the third time difference D3 in the third setting interval may be close to the second time difference D2 in the second setting interval. That is, the difference between the third time difference D3 and the second time difference D2 may be substantially equal to zero.

[0141] Meanwhile, the fourth time difference D4 in the fourth setting interval may be greater than the third time difference D3 in the third setting interval. In the fourth setting interval, when the waveform of the gate signal GS_4 intersects the falling portion of the data signal VDATA (rather than the peak portion of the data signal VDATA), the timing of the falling edge of the feedback signal FB may be relatively delayed.

[0142] Therefore, the delay value determining unit 730 may finally set the clock signal CLK based on the second delayed clock signal CLK_D2 (or the second delay value DELAY2 of the second delayed clock signal CLK_D2 ) corresponding to the third setting interval.

[0143] In an embodiment, the delay value determination unit 730 may set a sub-delay value for each of the pulses of the clock signal CLK based on a position where the data signal VDATA is sensed and a delay value of the selected delayed clock signal.

[0144] For example, in the following, assuming Figure 9A The data signal VDATA is transmitted through the first connection line CL1 (reference Figure 4 ) is provided, and a second delay value DELAY2 of the second delayed clock signal CLK_D2 is selected.

[0145] In this case, the n-th gate signal GSn having the second delay value DELAY2 should be applied to the n-th gate line GLn (refer to Figure 4 ), and the first gate signal GS1 to the n-th gate signal GSn may have delay values ​​that sequentially increase to a maximum second delay value DELAY2. Therefore, each of the pulses of the clock signal CLK corresponding to the first gate signal GS1 to the n-th gate signal GSn may have a corresponding delay value. To this end, the delay value determining unit 730 may interpolate the second delay value DELAY2 based on the n-th gate line GLn (or n gate lines) to set a sub-delay value for each of the pulses of the clock signal CLK.

[0146] refer to Figure 10A , the first interval P1 may be where the clock signal CLK is provided to the first gate driver IC 210-1 (reference Figure 2 ) interval.

[0147] In the first interval P1, based on the reference clock signal CLK_REF (or an external clock signal), the first pulse PLS1 of the clock signal CLK may have a first sub-delay value DELAY_S1, the second pulse PLS2 may have a second sub-delay value DELAY_S2, and the k-th pulse PLSk may have a k-th sub-delay value DELAY_Sk. Here, k may be a positive integer less than n. For example, as shown in the reference clock signal Figure 4As described, when the stages ST1 , ST2 , . . . , and STn alternately output the two sub-clock signals CLK_S1 and CLK_S2 as gate signals, k may be n / 2.

[0148] For example, the first sub-delay value DELAY_S1 may be 0, the kth sub-delay value DELAY_Sk may be the same as the second delay value DELAY2, and the second sub-delay value DELAY_S2 may be equal to a value obtained by dividing the second delay value DELAY2 by k. For example, DELAY_Si=DELAY2 / k×(i-1), where i is an integer less than k.

[0149] The sub-delay values ​​DELAY_S1 to DELAY_Sk of the pulses PLS1 to PLSk of the clock signal CLK may be stored in a separate memory device. The timing controller 410 (or the clock generator 710) may generate the clock signal CLK by sequentially delaying the pulses of the external clock signal provided from the outside based on the sub-delay values ​​DELAY_S1 to DELAY_Sk.

[0150] In other words, the delay value determining unit 730 may adjust or increase the first period PERa of the clock signal CLK (or the clock signal CLK for the first gate driver IC 210 - 1 ) in the first section P1 by the first sub-delay value DELAY_S1 .

[0151] At the same time, Figure 10A In the embodiment of the present invention, the sub-delay values ​​DELAY_S1 to DELAY_Sk of the pulses PLS1 to PLSk of the clock signal CLK have been described as being different from each other. However, the sub-delay values ​​DELAY_S1 to DELAY_Sk of the pulses PLS1 to PLSk of the clock signal CLK are not limited thereto.

[0152] For example, when the n-th gate signal GSn having the second delay value DELAY2 is applied to the n-th gate line GLn (refer to Figure 4 ), the first to n-th gate signals GS1 to GSn may have a delay value equal to the second delay value DELAY2. Therefore, each of the pulses of the clock signal CLK corresponding to the first to n-th gate signals GS1 to GSn may have a corresponding delay value.

[0153] refer to Figure 10B , showing the Figure 10A The corresponding waveform.

[0154] In the first interval P1, based on the reference clock signal CLK_REF (or an external clock signal), the first pulse PLS1 of the clock signal CLK may have a first sub-delay value DELAY_S1′, the second pulse PLS2 may have a second sub-delay value DELAY_S2′, and the kth pulse PLSk may have a kth sub-delay value DELAY_Sk′.

[0155] For example, each of the first sub delay value DELAY_S1 ′, the second sub delay value DELAY_S2 ′, and the kth sub delay value DELAY_Sk′ may be the same as the second delay value DELAY2 .

[0156] That is, the clock signal CLK may have the same waveform (or the same period) as the reference clock signal CLK_REF, and may be delayed by a specific delay value (eg, the second delay value DELAY2 ) based on the reference clock signal CLK_REF.

[0157] The delay value of the clock signal CLK of the first section P1 may be stored in a separate memory device. The timing controller 410 (or the clock generator 710) may generate the clock signal CLK by delaying an external clock signal provided from the outside based on the delay value.

[0158] In the following, reference will be made to Figure 9B Another example is described. Figure 9B Shown with Figure 9A The waveform of the data signal VDATA_1 is the same as Figure 9A The waveform of the data signal VDATA is different and can be compared with the reference Figure 3 The second curve C_VDATA2 described is the same or similar.

[0159] For reference, you can refer to Figure 9A The waveform shown in the figure is used to describe the Figure 2 1 is used to set the clock signal CLK of the first gate driver IC 210-1 based on the data signal in the first connection line CL1 shown in FIG. Figure 9B The waveform shown in the figure is used to describe the Figure 2 2. The process of setting the clock signal CLK of the second gate driver IC 210-2 based on the data signal in the second connection line CL2 shown in FIG.

[0160] Return Reference Figure 8 and Figure 9B, the gate signal GS_5 in the fifth setting interval can be generated based on the reference clock signal CLK_REF. Here, the reference clock signal CLK_REF can be the clock signal CLK that is finally set for the first gate driver IC 210-1 (for example, the clock signal CLK in which the second delay value DELAY2 is reflected). The gate signal GS_6 in the sixth setting interval can have a first delay value DELAY1 based on the fifth gate signal GS_5. The gate signal GS_7 in the seventh setting interval can have a second delay value DELAY2 based on the fifth gate signal GS_5. The gate signal GS_8 in the eighth setting interval can have a third delay value DELAY3 based on the fifth gate signal GS_5.

[0161] The sixth time difference D6 (ie, the timing of the falling edge of the feedback signal FB) in the sixth setting interval may be similar to the fifth time difference D5 in the fifth setting interval.

[0162] Similarly, the seventh time difference D7 in the seventh setting interval may be close to the sixth time difference D6 in the sixth setting interval.

[0163] The eighth time difference D8 in the eighth setting interval may be greater than the seventh time difference D7 in the seventh setting interval.

[0164] In this case, the delay value determining unit 730 may finally set the clock signal CLK of the second gate driver IC 210 - 2 based on the delayed clock signal corresponding to the seventh setting interval.

[0165] Alternatively, when the eighth time difference D8 is greater than the seventh time difference D7, but it is determined that the difference between the eighth time difference D8 and the seventh time difference D7 is within the reference range (for example, less than the reference range), the delay value determination unit 730 can finally set the clock signal CLK of the second gate driver IC 210-2 based on the delayed clock signal corresponding to the eighth setting interval.

[0166] As described above, the delay value determination unit 730 may set a sub-delay value for each of the pulses of the clock signal CLK for the second gate driver IC 210 - 2 based on the position where the data signal VDATA is sensed and the delay value of the selected delayed clock signal.

[0167] For example, the delay value determining unit 730 may interpolate the delay value of the gate signal GS_7 based on the 2n-th gate line GL2n to set a sub-delay value for each of the pulses of the clock signal CLK for the second gate driver IC 210-2. Figure 2The n+1th gate line GLn+1 to the 2nth gate line GL2n shown in FIG. 2 are connected to the first gate driver IC 210-1 (reference Figure 2 ) and the delay value of the gate signal GS_7 to set a sub-delay value for each of the pulses of the clock signal CLK of the second gate driver IC 210-2.

[0168] Return Reference Figure 10A The second interval P2 may be where the clock signal CLK is provided to the second gate driver IC 210-2 (reference Figure 2 ) interval.

[0169] In the second interval P2, the k+1th pulse PLSk+1 of the clock signal CLK may have a k+1th sub-delay value DELAY_Sk+1, the k+2th pulse PLSk+2 may have a k+2th sub-delay value DELAY_Sk+2, and the 2kth pulse PLS2k may have a 2kth sub-delay value DELAY_S2k. The k+1th sub-delay value DELAY_Sk+1, the k+2th sub-delay value DELAY_Sk+2, and the 2kth sub-delay value DELAY_S2k may have different values, but the present disclosure is not limited thereto. For example, Figure 10B As shown in , the k+1th sub-delay value DELAY_Sk+1′, the k+2th sub-delay value DELAY_Sk+2′, and the 2kth sub-delay value DELAY_S2k′ may have the same value.

[0170] In an embodiment, a difference between the k+1th sub-delay value DELAY_Sk+1 and the kth sub-delay value DELAY_Sk may be different from a difference between the second sub-delay value DELAY_S2 and the first sub-delay value DELAY_S1 .

[0171] That is, the second period PERb of the clock signal CLK in the second section P2 for the second gate driver IC 210 - 2 may be different from the first period PERa of the clock signal CLK in the first section P1 .

[0172] The ninth interval P9 may be the period in which the clock signal CLK is supplied to the ninth gate driver IC (ie, the one farthest from the gate driver IC). Figure 2 The gate driver IC of the data driver 300 shown in FIG.

[0173] In the ninth interval P9, the 8k+1th pulse PLS8k+1 of the clock signal CLK may have an 8k+1th sub-delay value DELAY_S8k+1, and the 9kth pulse PLS9k may have a 9kth sub-delay value DELAY_S9k. The 8k+1th sub-delay value DELAY_S8k+1 and the 9kth sub-delay value DELAY_S9k may have different values. The 8k+1th sub-delay value DELAY_S8k+1′ and the 9kth sub-delay value DELAY_S9k′ may have different values.

[0174] The third period PERc of the clock signal CLK in the ninth section P9 for the ninth gate driver IC may be the same as or different from the first period PERa of the clock signal CLK in the first section P1 and the second period PERb of the clock signal CLK in the second section P2 , respectively.

[0175] As reference Figure 7 、 Figure 8 、 Figure 9A 、 Figure 9B 、 Figure 10A and Figure 10B As described, the timing controller 410 can monitor the timing variation of the falling edge of the feedback signal FB while increasing the delay value of the clock signal CLK. In addition, the timing controller 410 can select or determine the delay value of the clock signal CLK that keeps the timing variation of the falling edge of the feedback signal FB constant (e.g., kept to a minimum), and set the sub-delay value of each pulse of the clock signal CLK or determine the period of the clock signal CLK based on the delay value of the clock signal CLK.

[0176] In addition, when the display device 10 includes a plurality of gate driver ICs 210 - 1 and 210 - 2 , clock signals CLK for the gate driver ICs 210 - 1 and 210 - 2 may be set separately.

[0177] Therefore, in the interval where the data signal with RC delay has a peak value, the gate driver ICs 210-1 and 210-2 can output gate signals based on the clock signal CLK. Therefore, the charging rate of the data signal of the pixel can be improved, and the quality of the image displayed on the display device 10 can be improved.

[0178] Figure 11 It is an icon Figure 1 FIG. 1 is a diagram of another example of a display device. Figure 12 The diagram is included in Figure 11 FIG. 1 is a waveform diagram of an example of a clock signal set by a timing controller in a display device.

[0179] refer to Figure 1 、 Figure 2 and Figure 11 , Figure 11 The display device 10_1 and Figure 2 The difference between the display device 10 and the display device 10_1 is that the display device 10_1 includes a plurality of clock lines CLKL1, CLKL2, ... and CLKLp. In addition to the clock lines CLKL1, CLKL2, ... and CLKLp, the display device 10_1 can be connected to Figure 2 The display device 10 is substantially the same as or similar to that of FIG. 1 , and thus repeated description will be omitted.

[0180] The first clock line CLKL1 may be connected to the timing controller 410 and the first gate driver IC 210-1. The timing controller 410 may provide the first clock signal CLK1 to the first gate driver IC 210-1 through the first clock line CLKL1. The first gate driver IC 210-1 may generate a gate signal based on the first clock signal CLK1.

[0181] like Figure 12 As shown in FIG, the first clock signal CLK1 may have a first period PERa, and the first period PERa may be greater than the period of the reference clock signal CLK_REF by a first delay time DELAYa. Here, the first delay time DELAYa may be equal to the reference clock signal CLK_REF. Figure 10A The second sub-delay value DELAY_S2 described (or reference Figure 10B The second sub-delay value DELAY_S2') is described.

[0182] The second clock line CLKL2 may be connected to the timing controller 410 and the second gate driver IC 210-2. The timing controller 410 may provide the second clock signal CLK2 to the second gate driver IC 210-2 through the second clock line CLKL2. The second gate driver IC 210-2 may generate a gate signal based on the second clock signal CLK2.

[0183] like Figure 12 As shown in FIG, the second clock signal CLK2 may have a second period PERb, and the second period PERb may be greater than the period of the reference clock signal CLK_REF by a second delay time DELAYb. Here, the second delay time DELAYb may be equal to the reference clock signal CLK_REF. Figure 10A The difference between the k+2th sub-delay value DELAY_Sk+2 and the k+1th sub-delay value DELAY_Sk+1 is described.

[0184] The pth clock line CLKLp may be connected to the timing controller 410 and the pth gate driver IC. The timing controller 410 may provide the pth clock signal CLKp to the second gate driver IC through the pth clock line CLKLp. The pth gate driver IC may generate a gate signal based on the pth clock signal CLKp. Here, p is a positive integer. Figure 1 , for example, p can be 9.

[0185] like Figure 12 As shown in FIG, the pth clock signal CLKp may have a third period PERc, and the third period PERc may be greater than the period of the reference clock signal CLK_REF by a third delay time DELAYc. Here, the third delay time DELAYc may be the same as or different from the first delay time DELAYa and / or the second delay time DELAYb. However, since the RC delay of the data signal increases as the distance from the data driver 300 increases, the third delay time DELAYc may be greater than the first delay time DELAYa and the second delay time DELAYb.

[0186] and CLKp to the gate driver ICs 210-1, 210-2, . . . and the p-th gate driver IC through the plurality of clock lines CLKL1, CLKL2, . . . and CLKLp, the timing controller 410 may set the clock signals CLK1, CLK2, .

[0187] For example, Figure 2 The display device 10 may set a clock signal CLK (ie, Figure 10A The clock signal CLK in the first section P1 of the gate driver IC 210-1 is then set to the clock signal CLK of the second gate driver IC 210-2 on the premise of the clock signal CLK of the first gate driver IC 210-1 (ie, Figure 10A That is, since the clock signal CLK has partially different periods or delay values ​​in time division, the clock signal CLK must be set sequentially.

[0188] At the same time, since the clock signals CLK1, CLK2, ... and CLKp are Figure 11 . . and CLKp can be set independently (ie, individually) from each other.

[0189] Figure 13 is a flowchart illustrating a method of driving a display device according to an embodiment of the present disclosure.

[0190] refer to Figure 1 、 Figure 2 and Figure 13 , you can Figure 1 and Figure 2 Display device 10 (or Figure 11The method of driving the display device is executed in the display device 10_1). The method of driving the display device can be executed in a separate setting interval (or clock setting interval). Figure 13 method.

[0191] Figure 13 The method may provide data signals to data lines through the data driver 300, and sequentially output clock signals CLK to the gate lines GL1 to GLn and GLn+1 to GL2n through the gate driver 200 (or one of the gate driver ICs 210-1 and 210-2) (S1310).

[0192] As reference Figure 2 As described above, the data driver 300 may provide a data signal (or a test signal) to the first data line DL1. Figure 4 As described, the first gate driver IC 210 - 1 may output the clock signal CLK to the n-th gate line GLn as the n-th gate signal GSn.

[0193] Figure 13 The method may output a feedback signal by comparing the data signal with the gate signal through the x-th gate driver IC (S1320). Here, x may be a positive integer and may have a value of 1 for the first time.

[0194] As reference Figure 2 and Figure 4 As described, the first gate driver IC 210 - 1 may generate a feedback signal FB by comparing the data signal provided through the first connection line CL1 with the n-th gate signal GSn, and output the feedback signal FB to the feedback line FBL.

[0195] As reference Figure 6 As described, when the gate signal GS is greater than or equal to the data signal VDATA, the feedback signal FB may have a logic high level. In addition, when the gate signal GS is less than the data signal VDATA, the feedback signal FB may have a logic low level.

[0196] Figure 13 The method can calculate the delay time of the feedback signal FB based on the clock signal CLK (S1330).

[0197] As reference Figure 6 and Figure 7 As described above, the timing controller 410 (or the delay time calculator 720) can calculate the timing of the falling edge (or the second edge of the pulse) of the feedback signal FB based on the clock signal CLK. For example, the timing controller 410 can calculate the timing of the falling edge (or the second edge of the pulse) of the feedback signal FB based on the rising edge (i.e., Figure 6The timing of the falling edge of the feedback signal FB (ie, the time difference D) is calculated based on the first reference time point TP_REF1 shown in FIG.

[0198] Figure 13 The method can set the delay value of the clock signal based on the change of the delay time (or the timing of the falling edge) of the feedback signal FB.

[0199] In an embodiment, Figure 13 The method may determine whether the delay time of the feedback signal FB is outside the reference range, that is, whether the delay time of the feedback signal FB is changed (S1340).

[0200] For example, Figure 13 The method can determine the current delay time (i.e., within the current setting interval (e.g., reference Figure 9A The delay time of the feedback signal FB calculated in the second setting interval described in the present invention) is compared with the previous delay time (ie, the delay time of the feedback signal FB calculated in the previous setting interval (eg, the delay time of the feedback signal FB calculated in the second setting interval described in the present invention) Figure 9A Whether the difference between the delay time of the feedback signal FB calculated in the first setting interval described above is greater than the reference value. Figure 13 The method can determine whether the current delay time is greater than the previous delay time.

[0201] As reference Figure 9A As described above, when the peak interval of the data signal VDATA overlaps with the gate signal GS, the delay time of the feedback signal FB can be kept at a minimum. Alternatively, when the peak interval of the data signal VDATA partially overlaps with the gate signal GS, the delay time of the feedback signal FB can be relatively increased. Therefore, Figure 13 The method can find the time points at which the variation of the delay time decreases and remains constant (for example, the time points at which the peak interval of the data signal VDATA begins to overlap with the gate signal GS) and the time points at which the variation of the delay time remains constant and increases (for example, the time points at which the gate signal GS begins to deviate from the peak interval of the data signal VDATA).

[0202] When the delay time of the feedback signal FB does not change, Figure 13 The method can increase the delay value of the clock signal (S1350). In addition, Figure 13 The method may perform a step of outputting a clock signal CLK as a gate signal (S1310), a step of outputting a feedback signal (S1320), a step of calculating a delay time of the feedback signal (S1330), and a step of determining whether the delay time changes again (S1340).

[0203] As reference Figure 7 、 Figure 8 and Figure 9AAs described, the timing controller 410 may sequentially generate the delayed clock signals CLK_D1 , CLK_D2 , and CLK_D3 , and determine whether the delay time of the feedback signal FB is changed according to the delayed clock signals CLK_D1 , CLK_D2 , and CLK_D3 in a plurality of setting intervals.

[0204] When the delay time of the feedback signal FB changes (or when the delay time increases), the clock signal for the x-th gate driver IC may be set based on the previous delay value of the clock signal CLK ( S1360 ).

[0205] As reference Figure 9A As described, when the delay time is changed in the fourth setting interval, Figure 13 The method can set the clock signal CLK of the first gate driver IC 210-1 based on the second delay value DELAY2 of the second delayed clock signal CLK_D2 in the third setting interval. Figure 10A As described, the second delay value DELAY2 may be interpolated based on the nth gate line GLn to set a sub-delay value of each of the pulses PLS1 to PLSk of the clock signal CLK in the first interval P1. As another embodiment, as shown in FIG. Figure 12 As described above, the period of the first clock signal CLK1 can be set based on the second delay value DELAY2. As another embodiment, as shown in FIG. Figure 10B As described, the delay value of the clock signal CLK in the first section P1 may be set based on the second delay value DELAY2 according to the n-th gate line GLn.

[0206] Afterwards, Figure 13 The method may set the clock signal CLK for the gate driver IC located after the x-th gate driver IC (ie, spaced farther from the data driver 300 than the x-th gate driver IC).

[0207] Figure 13 The method can determine whether the clock signal CLK is completely set for all gate driver ICs in the gate driver 200. For example, when the gate driver 200 includes p gate driver ICs, Figure 13 The method can determine whether the constant x is equal to the constant p (S1370).

[0208] When the constant x is not equal to the constant p, Figure 13 The method may increase the constant x by 1 (S1380) and set the clock signal CLK for the corresponding gate driver IC.

[0209] For example, when the clock signal CLK for the first gate driver IC 210-1 is fully set, Figure 13The clock signal CLK for the second gate driver IC 210 - 2 may be set by the method of FIG.

[0210] refer to Figure 1 , for example, when the gate driver 200 includes nine gate driver ICs, Figure 13 The method may sequentially set the clock signal CLK for each of the nine gate driver ICs.

[0211] As reference Figure 13 As described, the method for driving a display device can generate a feedback signal FB containing delay information of the data signal by comparing the data signal of the first data line DL1 with a specific gate signal passing through the gate driver 200. In addition, the method for driving a display device can monitor the timing change of the second edge of the feedback signal FB while increasing the delay value of the clock signal CLK, and ultimately determine the delay value of the clock signal CLK that keeps the change constant (for example, kept to a minimum), and set the sub-delay value of each of the pulses of the clock signal CLK or determine the period of the clock signal CLK based on the determined delay value. The clock signal CLK can be a gate signal and can be supplied to the pixel at the same time as the data signal with RC delay. That is, the timing of supplying the data signal and the gate signal can coincide with each other. Therefore, the charging rate of the data signal of the pixel can be improved, and the quality of the image displayed on the display device can be improved.

[0212] According to an embodiment of the present disclosure, a display device and a method for driving the display device can generate a feedback signal containing delay information of the data signal by comparing the data signal of the data line with a specific gate signal passing through a gate driver, monitor the change of the second edge of the feedback signal (e.g., the falling edge of the pulse) while increasing the delay value of the clock signal, and determine the delay value of the clock signal that keeps the change constant (e.g., kept to a minimum). The gate signal generated based on the clock signal reflecting the delay value can be supplied to the pixel at the same time point (or time) as the data signal with RC delay. That is, the timing of supplying the data signal and the gate signal can coincide with each other. Therefore, the charging rate of the data signal of the pixel can be improved, and the quality of the image displayed on the display device can be improved.

[0213] The detailed description of the present disclosure described with reference to the accompanying drawings is merely illustrative of the present disclosure and is only used for the purpose of illustrating the present disclosure, and is not intended to limit the meaning of the present disclosure or the scope of the present disclosure described in the claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims

1. A display device comprising: A display panel comprising a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines; a data driver providing data signals to the plurality of data lines; a gate driver that sequentially generates gate signals corresponding to a start pulse using a clock signal and supplies the gate signals to the plurality of gate lines; a timing controller, providing the clock signal and the start pulse to the gate driver; as well as a first connecting line adjacent to an nth gate line among the plurality of gate lines and connected to a first data line among the plurality of data lines, wherein n is a positive integer; wherein the gate driver receives a data signal supplied to the first data line through the first connection line, and generates a feedback signal by comparing an nth gate signal applied to the nth gate line with the data signal supplied to the first data line, and The timing controller sets a delay value of the clock signal based on the feedback signal.

2. The display device according to claim 1, wherein The first data line among the plurality of data lines is positioned closest to the gate driver.

3. The display device according to claim 1, wherein The data signal measured at the first connection line includes a resistance-capacitance delay relative to the data signal measured at the output terminal of the data driver.

4. The display device according to claim 1, wherein The gate driver includes a plurality of gate driving circuits, The first gate driving circuit among the gate driving circuits includes: a plurality of stages respectively connected to respective gate lines in a corresponding first group of gate lines among the plurality of gate lines; and a comparator connected to each of the nth gate line and the first connection line, respectively; The first group of gate lines includes the first gate line to the nth gate line, and Each of the stages outputs the clock signal as a gate signal in response to the start pulse or a carry signal of a previous stage.

5. The display device according to claim 4, wherein The n-th gate line among the first group of gate lines is located farthest from the data driver. The display device according to claim 4 , wherein: The nth gate signal varies within a first voltage range, wherein the data signal provided to the first data line varies within a second voltage range, and The second voltage range is a subset of the first voltage range.

7. The display device according to claim 4, wherein The comparator outputs the feedback signal having a first logic level when the voltage level of the nth gate signal is greater than or equal to the voltage level of the data signal supplied to the first data line, and outputs the feedback signal having a second logic level when the voltage level of the nth gate signal is lower than the voltage level of the data signal supplied to the first data line.

8. The display device according to claim 4, wherein The feedback signal includes a pulse, and the pulse includes a first edge and a second edge that appear sequentially, and The timing controller determines the delay value of the clock signal based on a change in timing of the second edge of the pulse relative to the clock signal.

9. A method for driving a display device, the display device comprising a plurality of data lines, a plurality of gate lines, and a plurality of pixels connected to the plurality of data lines and the plurality of gate lines, the method comprising: supplying a data signal to the plurality of data lines through a data driver and sequentially supplying a clock signal as a gate signal to the plurality of gate lines through a gate driver; generating a feedback signal by comparing, by the gate driver, a data signal provided to a first data line among the plurality of data lines with at least one of the gate signals; Calculating the delay time of the feedback signal based on the clock signal by a timing controller; as well as setting a delay value of the clock signal based on a change in the delay time of the feedback signal, The display device further includes a first connecting line, the first connecting line is adjacent to the nth gate line among the plurality of gate lines and is connected to the first data line, wherein n is a positive integer, and The gate driver receives the data signal supplied to the first data line through the first connection line, and compares the nth gate signal applied to the nth gate line with the data signal supplied to the first data line.

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