Apparatus and method for controlling refresh operation

Abstract

The present disclosure relates to devices and methods for control of refresh operations. In some examples, a memory device can perform refresh operations in response to internal and / or external commands. Internal refresh commands can include an auto-refresh command and a row hammer (e.g., targeted) refresh command. External commands can include a refresh management command. In some examples, the external command can cause a refresh operation to occur after a number of activate commands. The memory device can monitor row addresses associated with the activate commands. In some examples, if none of the row addresses associated with the activate commands are generated at a high frequency, the memory device can skip a refresh operation indicated by a refresh management command. In some examples, a row address can be determined to be an aggressor row address if a received row address matches a previously received row address.

Description

Technical Field

[0001] This disclosure generally relates to semiconductor devices, and more particularly to semiconductor memory devices. Specifically, this disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Background Technology

[0002] Information can be stored as physical signals (e.g., the charge on a capacitor element) in individual memory cells of a memory device. The memory device may contain volatile memory, and the physical signals can decay over time (which may degrade or destroy the information stored in the memory cells). It may be necessary to periodically refresh the information in the memory cells by restoring the physical signals to their initial values, for example, by rewriting the information.

[0003] As memory component size decreases, memory cell density increases dramatically. Repeated access to specific memory cells or groups of memory cells (often referred to as 'row hammer') can lead to an increased rate of data degradation in nearby memory cells. As part of targeted refresh operations performed by the memory device, memory cells affected by the row hammer effect can be identified and refreshed. These targeted refresh operations can replace (e.g., steal) time slots originally intended for background refresh operations (e.g., automatic refresh). Some memory devices allow external commands to cause the memory device to perform refresh operations. In some applications, refresh operations performed in response to external commands can be added to both background and targeted refresh operations. It may be necessary to balance multiple refresh operations performed by the memory device. Summary of the Invention

[0004] In one aspect, this disclosure relates to an apparatus comprising: a burst detector circuit configured to determine whether a current row address received by a memory is an intruder row address when the current row address is received at a frequency equal to or greater than a cutoff frequency; and skip logic circuitry configured to deliver an active refresh management refresh signal at least in part in response to determining the intruder row address, wherein the active refresh management refresh signal causes the memory to perform a refresh operation outside of a refresh mode.

[0005] In another aspect, this disclosure relates to a system comprising: a memory controller configured to count the number of activation commands received by the memory and provide an action refresh signal when the number of activation commands equals a threshold; and a memory comprising: a burst detector configured to determine whether a row address received by the memory is an intruder row address and provide an action burst flag in response to the intruder row address; and skip logic circuitry configured to pass the action refresh signal in response to the action burst flag and to mask the action refresh signal when the burst flag is inactive.

[0006] In another aspect, this disclosure relates to a method comprising: receiving a plurality of access requests and corresponding plurality of row addresses via a memory; determining whether a row address is an intruder row address based at least in part on the frequency at which the memory receives the row addresses among the plurality of row addresses, wherein the row address is determined to be the intruder row when the frequency is equal to or greater than the cutoff frequency of a high-pass filter; and performing a refresh management refresh operation in response to an external refresh management signal and the determination that the row address among the plurality of row addresses is the intruder row address. Attached Figure Description

[0007] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0008] Figure 2 This is a block diagram of a refresh control circuit according to an embodiment of the present disclosure.

[0009] Figure 3 This is a block diagram of a refresh management circuitry system according to an embodiment of the present disclosure.

[0010] Figure 4 This is a block diagram of an access counter circuit according to an embodiment of the present disclosure.

[0011] Figure 5 This is a block diagram of a burst detector circuit according to an embodiment of the present disclosure.

[0012] Figure 6 This is a block diagram of a refresh management address storage circuit according to an embodiment of the present disclosure.

[0013] Figure 7 This is a block diagram of a skip logic circuit according to an embodiment of the present disclosure.

[0014] Figure 8 This is a timing diagram of a distributed refresh management technique according to embodiments of the present disclosure.

[0015] Figure 9 This is a block diagram of an example of a simplified RFM circuit system according to embodiments of the present disclosure.

[0016] Figure 10 This is a timing diagram of a delayed distributed refresh management technique according to embodiments of the present disclosure.

[0017] Figure 11 This is a flowchart of a method according to an embodiment of the present disclosure. Detailed Implementation

[0018] The following description of certain embodiments is exemplary in nature and is in no way intended to limit the scope of this disclosure or its application or use. In the following detailed description of embodiments of the systems and methods of the invention, reference is made to the accompanying drawings, which form a part of this document, and to specific embodiments in which the described systems and methods can be practiced, illustrated by means of the illustrations. These embodiments are described in sufficient detail to enable those skilled in the art to practice the systems and methods disclosed in this invention, and it should be understood that other embodiments can be utilized and structural and logical changes can be made without departing from the spirit and scope of this disclosure. Furthermore, for clarity, certain features will not be discussed in detail when they are obvious to those skilled in the art, so as not to obscure the description of embodiments of this disclosure. Therefore, the following detailed description should not be construed in a limiting sense, and the scope of this disclosure is defined only by the appended claims.

[0019] Information in volatile memory devices can be stored in memory cells (e.g., as charge on capacitive elements) and can decay over time. Memory cells can be organized into rows (word lines) and columns (bit lines), and memory cells can be refreshed row by row. To prevent information from being lost or corrupted due to this decay, the memory can implement a refresh process, such as a refresh operation as part of a refresh mode. During a refresh operation, information can be rewritten to word lines to restore its initial state. Automatic refresh operations can be performed sequentially on the word lines of the memory, such that over time, each word line in the memory is refreshed at a rate faster than the expected data degradation rate.

[0020] Repeated access to specific rows of memory (e.g., attacker rows) can increase the decay rate in rows adjacent to the attacker row (e.g., victim rows). These repeated accesses may be part of an intentional attack on the memory and / or may be due to the memory's 'natural' access patterns. The increased decay rate in victim rows may require them to be refreshed as part of a targeted refresh operation. As part of a refresh mode, the memory device may periodically perform targeted refresh operations. For example, when the memory device is in refresh mode, it may perform a set of refresh operations comprising several auto-refresh operations and several targeted refresh operations, and then repeat this cycle. In some embodiments, the targeted refresh operation may 'steal' time slots that would otherwise be used for auto-refresh operations. Typically, the memory device may cycle between performing access operations for a period of time, entering refresh mode for a period of time, performing access operations, and so on.

[0021] If the memory begins receiving access requests at an extremely high rate (e.g., activation commands), it may indicate that an attack on the memory is occurring and a refresh operation may be necessary, even when the device is not in refresh mode (e.g., performing an automatic refresh or targeted refresh). Based on several access commands (e.g., grouped), additional refresh request commands may be issued, potentially leading to additional refresh operations even when the memory is not in refresh mode. These additional refresh requests may be initiated and / or configured based on external commands provided to the memory. For example, the memory controller may count the number of access commands provided to the memory and provide commands / signals indicating that additional refresh operations should be performed. In another instance, an external command, referred to as a refresh management (RFM) command, may indicate the number of access requests prior to the additional refresh operation (e.g., performing a refresh operation once every 120 access requests). The additional refresh operation may be referred to as an RFM refresh operation. The row selected for refresh during an RFM refresh operation (e.g., the victim row) may be determined in the same manner or in a different manner than the row selected for refresh during a targeted refresh operation.

[0022] However, a high rate of access requests does not always correspond to an attack on the memory. For example, if no word lines are accessed at a high frequency (e.g., many different word lines are accessed during a high rate of access requests), then data in adjacent word lines may not require additional refreshes to prevent degradation. In these cases, some or all of the RFM refresh operations may not be necessary to retain data in the memory cell. In some cases, unnecessary RFM refresh operations can degrade the performance of the memory device. In some cases, unnecessary RFM refresh operations can cause refresh word lines to become auxiliary aggressor word lines. That is, RFM refresh operations can act as auxiliary row hammer attacks on refresh word lines. Therefore, it may be necessary to manage RFM refresh operations to reduce unnecessary refresh operations.

[0023] According to embodiments of this disclosure, the memory can skip some RFM refresh operations, at least in part, based on the frequency of receiving row addresses. In some embodiments, row addresses with associated access requests can be monitored to determine whether one or more row addresses are accessed at a sufficiently high frequency, and the word line associated with the row address is an aggressor row (e.g., there is an increased risk of data degradation in adjacent word lines). In some embodiments, a high-pass filter can be used to determine whether a row address is associated with an aggressor row. The cutoff frequency of the high-pass filter can determine whether a row address is determined to be an aggressor row address. For example, a row address received at a frequency below the cutoff frequency can be determined not to be an aggressor row address, while a row address received at a frequency equal to or greater than the cutoff frequency can be determined to be an aggressor row address. In some embodiments, if a row address is received at a rate more than once within multiple consecutive access requests, then the row address can be determined to be received at a frequency at or above the cutoff frequency.

[0024] If no row address associated with the access request is identified as the intruder row, the RFM refresh operation can be skipped. In other words, the memory can ignore RFM signals (received from outside the memory or generated internally based on external RFM commands) that indicate an RFM refresh operation should be performed.

[0025] If one or more row addresses associated with the access request are determined to be intruder rows, an RFM refresh operation can be performed. In some embodiments, the row address identified as an intruder row by the high-pass filter can be used to generate the refresh address for the word line refreshed during the RFM refresh operation.

[0026] Figure 1 This is a block diagram of a semiconductor device according to an embodiment of the present disclosure. Semiconductor device 100 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip.

[0027] Semiconductor device 100 includes memory array 118. Memory array 118 is shown as containing multiple memory groups. Figure 1 In one embodiment, memory array 118 is shown as comprising eight memory groups BANK0 to BANK7. Other embodiments of memory array 118 may contain more or fewer groups. Each memory group comprises multiple word lines WL, multiple bit lines BL and / or BL, and multiple memory cells MC, the memory cells MC being arranged at the intersections of the multiple word lines WL and the multiple bit lines BL and / or BL. The selection of word lines WL is performed by row decoder 108, and the selection of bit lines BL and / or BL is performed by column decoder 110. Figure 1In this embodiment, row decoder 108 includes a corresponding row decoder for each memory bank, and column decoder 110 includes a corresponding column decoder for each memory bank. Bit lines BL and / BL are coupled to corresponding sense amplifiers (SAMPs). Read data from bit lines BL or / BL is amplified by the sense amplifier SAMP and transferred to read / write amplifier 120 via complementary local data line (LIOT / B), transfer gate (TG), and complementary main data line (MIOT / B). Conversely, write data output from read / write amplifier 120 is transferred to the sense amplifier SAMP via complementary main data line MIOT / B, transfer gate TG, and complementary local data line LIOT / B, and written to the memory cell MC coupled to bit line BL or / BL.

[0028] The semiconductor device 100 may employ multiple external terminals, including: a command and address (C / A) terminal coupled to the command and address bus to receive commands and addresses; a CS signal clock terminal for receiving clock CK and / or CK; a data terminal DQ for providing data; and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ.

[0029] The clock terminal supplies external clocks CK and / CK to input circuit 112. These external clocks can be complementary. Input circuit 112 generates an internal clock ICLK based on CK and / CK. The ICLK clock is provided to command decoder circuit 110 and internal clock generator 114. Internal clock generator 114 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used for timing operations of various internal circuits. The internal data clock LCLK is provided to input / output circuit 122 to time the operation of circuits included in input / output circuit 122, for example, to a data receiver to time the reception of written data.

[0030] The C / A terminal may supply a memory address. The memory address supplied to the C / A terminal is transferred to the address decoder 104 via command / address input circuitry 102. Address decoder 104 receives the address and supplies the decoded row address XADD to row decoder 108 and the decoded column address YADD to column decoder circuitry 110. Address decoder 104 may also supply a decoded group address BADD, which indicates a group in memory array 118 containing the decoded row address XADD and column address YADD. The C / A terminal may supply commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as read commands for performing read operations and write commands for performing write operations, and other commands and operations. Access commands may be associated with one or more row addresses XADD, column addresses YADD, and group addresses BADD to indicate the memory cell to be accessed. In some embodiments, commands and / or addresses may be provided by components external to device 100, such as... Figure 1 The memory controller 101 shown communicates with device 100.

[0031] Commands can be provided as internal command signals to command decoder 106 via command / address input circuitry 102. Command decoder 106 includes circuitry for decoding internal command signals to generate various internal signals and commands for performing operations. For example, command decoder 106 can provide row command signals for selecting word lines and column command signals for selecting bit lines.

[0032] Device 100 can receive access commands, which are read commands. When a read command is received and the group address, row address, and column address are supplied in a timely manner, read data is read from the memory cells corresponding to the row and column addresses in memory array 118. The read command is received by command decoder circuit 106, which provides an internal command causing the read data from memory array 118 to be provided to read / write amplifier 120. The read data is output to the data terminal DQ via input / output circuit 122.

[0033] Device 100 can receive access commands, which are write commands. When a write command is received and the group address, row address, and column address are supplied in a timely manner, write data supplied to the data terminal DQ is written to the memory cells in the memory array 118 corresponding to the row and column addresses. The write command is received by command decoder circuit 106, which provides an internal command causing the write data to be received by the data receiver in input / output circuit 122. A write clock can also be provided to an external clock terminal for timing the data receiver in input / output circuit 122 to receive the write data. The write data is supplied to read / write amplifier 120 via input / output circuit 122 and then to memory array 118 for writing into memory cell MC.

[0034] The device 100 may also receive commands that cause it to perform one or more refresh operations as part of a self-refresh mode. The device 100 may periodically be in refresh mode. Therefore, refresh operations may be performed periodically whenever the memory device is in refresh mode. In some embodiments, the refresh mode command may be issued to the memory device 100 externally. In some embodiments, the refresh mode command may be generated periodically by components of the device. In some embodiments, the refresh signal AREF may also be activated when an external signal indicates a refresh mode entry command. The refresh signal AREF may be a pulse signal activated when the command decoder circuit 106 receives a signal indicating entry into self-refresh mode. The refresh signal AREF may be activated immediately after the command input and may subsequently be activated cyclically at desired internal timings. The refresh signal AREF can be used to control the timing of refresh operations during refresh mode. A self-refresh exit command may stop the automatic activation of the refresh signal AREF and may return the device 100 to an idle state and / or resume other operations.

[0035] A refresh signal AREF is supplied to refresh control circuitry 116. Refresh control circuitry 116 supplies a refresh row address RXADD to row decoder 108, which refreshes one or more word lines WL indicated by the refresh row address RXADD. In some embodiments, refresh address RXADD may represent a single word line. In some embodiments, refresh address RXADD may represent multiple word lines that can be refreshed sequentially or simultaneously by row decoder 108. In some embodiments, the number of word lines represented by refresh address RXADD may be different for different refresh addresses. Refresh control circuitry 116 can control the timing of the refresh operation and can generate and provide refresh address RXADD. Refresh control circuitry 116 may be controlled to change details of refresh address RXADD (e.g., how the refresh address is calculated, the timing of the refresh address, the number of word lines represented by the address), or may operate based on internal logic.

[0036] The refresh control circuit 116 can selectively output a target refresh address (e.g., one or more victim addresses specified by an aggressor) or an auto-refresh address (e.g., from a series of auto-refresh addresses) as the refresh address RXADD. Based on the type of the refresh address RXADD, the line decoder 108 can perform a target refresh or auto-refresh operation. The auto-refresh address can be from a series of addresses provided based on the activation of the refresh signal AREF. The refresh control circuit 116 can cycle through a series of auto-refresh addresses at a rate determined by AREF. In some embodiments, the auto-refresh operation can be performed generally at a certain timing such that the series of auto-refresh addresses cycle through, so that no information degradation is expected between auto-refresh operations on a given word line. In other words, the auto-refresh operation can be performed such that each word line is refreshed at a rate faster than the expected information decay rate.

[0037] As used herein, signal activation can refer to any part of the signal waveform in which the circuit responds. For example, if the circuit responds to a rising edge, then a signal switching from low to high can be considered activated. One type of activation is a pulse, where the signal switches from low to high for a period of time and then returns to low. This can trigger circuitry that responds to rising edges, falling edges, and / or signals at high logic levels.

[0038] The refresh control circuit 116 can also determine a target refresh address, which is an address that needs to be updated based on the access pattern of nearby addresses in the memory array 118 (e.g., the attacker address corresponding to the attacker row), i.e., the victim address corresponding to the victim row. The refresh control circuit 116 can calculate the target refresh address using one or more signals from the device 100. For example, the refresh address RXADD can be calculated based on the row address XADD provided by the address decoder.

[0039] In some embodiments, the refresh control circuit 116 may sample the current value of the row address XADD provided by the address decoder 104 along the row address bus and determine a target refresh address based on one or more of the sampled addresses. The sampled addresses may be stored in a data storage unit of the refresh control circuit. When the row address XADD is sampled, it may be compared with the address stored in the data storage unit. In some embodiments, the intruder address may be determined based on the sampled and / or stored addresses. For example, a comparison between the sampled address and the stored address may be used to update a count value associated with the stored address (e.g., an access count), and the intruder address may be calculated based on the count value. The refresh address RXADD may then be used based on the intruder address.

[0040] Although this disclosure generally pertains to identifying aggressor and victim word lines and addresses, it should be understood that, as used herein, an aggressor word line does not necessarily need to degrade data in adjacent word lines, and a victim word line does not necessarily need to undergo such degradation. The refresh control circuit 116 can use criteria to determine whether an address is an aggressor address, which can capture potential aggressor addresses rather than definitively determining which addresses are causing data degradation in nearby victims. For example, the refresh control circuit 116 can determine potential aggressor addresses based on address access patterns, and this criterion may include some addresses that are not aggressors and miss some addresses that are aggressors. Similarly, victim addresses can be determined based on which word lines are expected to be implemented by an aggressor, rather than definitively determining which word lines are experiencing an increased rate of data decay.

[0041] A refresh address RXADD can be provided based on the timing of the refresh signal AREF. During the periodic refresh operation in refresh mode, the refresh control circuit 116 may have time slots corresponding to the timing of AREF, and may provide one or more refresh addresses RXADD during each time slot. In some embodiments, the target refresh address may be published in a time slot that was originally assigned to an auto-refresh address (e.g., "stolen"). In some embodiments, a specific time slot may be reserved for the target refresh address, and the refresh control circuit 116 may determine whether to provide the target refresh address, not provide an address during the time slot, or actually provide an auto-refresh address during the time slot.

[0042] The refresh control circuit 116 can use various methods to determine the timing of the target refresh operation. During refresh mode, the refresh control circuit 116 can have periodic target refresh operations, wherein the refresh control circuit 116 performs automatic refresh operations and target refresh operations based on a periodic schedule (e.g., by providing the target refresh address as the refresh address RXADD). For example, after entering refresh mode, the refresh control circuit 116 can perform a specific number of automatic refresh operations, and then perform (e.g., steal) a specific number of target refresh operations.

[0043] In addition to automatic refresh and targeted refresh operations, refresh control circuitry 116 may also perform refresh management (RFM) refresh operations, which in some applications may be based on access modes of a group associated with refresh control circuitry 116. Examples of access modes include, but are not limited to, the number of received access requests (e.g., activation commands) and the access request rate. Device 100 may receive commands, for example, from memory controller 101, which are refresh management commands (e.g., a request management command may be received at the command / address terminal C / A). Command decoder circuitry 106 may provide a refresh management command signal RFMC based on the refresh management command. In some embodiments, the refresh management command may be the RFMC signal, which may be directly passed to refresh control circuitry 116. In some embodiments, the RFMC signal may configure the refresh management circuitry system included in refresh control circuitry 116. For example, the RFMC signal may indicate the number of access requests received before performing an RFM refresh operation (e.g., a threshold for the number of access requests before initiating an RFM refresh operation, the RFM refresh mode type). In some embodiments, in response to the RFMC signal, refresh control circuitry 116 may indicate that an RFM refresh operation should be performed.

[0044] In some embodiments, as referenced Figure 2-4 In more detail, at least some of the refresh management circuitry may be included in the memory controller 101. For example, the memory controller 101 may count the number of access requests provided to the device 100. In this example, the device 100 may receive the RFM signal RFM from the memory controller 101 as an alternative to or supplement to the RFM command signal RFMC.

[0045] In some embodiments, these RFM refresh operations may occur outside of refresh modes. For example, high-rate access to a group may indicate an attack is in progress. In some embodiments, refresh control circuitry 116 may monitor row addresses with access commands. Monitoring row addresses may include storing received row addresses and counting the number of times row addresses are received. Once the access command count exceeds a threshold, an RFM refresh operation may be performed if one or more of the row addresses are determined to be received at a frequency higher than or equal to the cutoff frequency (i.e., one or more of the row addresses are determined to be associated with an attacker row). If no row address is determined to be received at a frequency higher than or equal to the cutoff frequency, the RFM refresh operation may be skipped. In some instances, after an RFM refresh operation or after skipping an RFM refresh operation, the counts of access commands and row addresses may be adjusted (e.g., reset to initial values, or reduced). It should be understood that the process of refreshing word lines during periodic and targeted RFM refresh operations may be substantially the same, the difference generally being the timing of when the refresh is performed.

[0046] The power supply terminals are supplied with power potentials VDD and VSS. These power potentials VDD and VSS are supplied to the internal voltage generator circuit 124. The internal voltage generator circuit 124 generates various internal potentials VPP, VOD, VARY, VPERI, etc., based on the power potentials VDD and VSS supplied to the power supply terminals. Internal potential VPP is primarily used in the line decoder 108, internal potentials VOD and VARY are primarily used in the sense amplifier SAMP included in the memory array 118, and internal potential VPERI is used in many peripheral circuit blocks.

[0047] The power supply terminals are also supplied with power potentials VDDQ and VSSQ. Power potentials VDDQ and VSSQ are supplied to the input / output circuit 122. In embodiments of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be the same potentials as the power potentials VDD and VSS supplied to the power supply terminals. In another embodiment of this disclosure, the power potentials VDDQ and VSSQ supplied to the power supply terminals may be different potentials from the power potentials VDD and VSS supplied to the power supply terminals. The power potentials VDDQ and VSSQ supplied to the power supply terminals are used in the input / output circuit 122 so that power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0048] Figure 2 This is a block diagram of a refresh control circuit according to an embodiment of the present disclosure. In some embodiments, the refresh control circuit 216 may be included in... Figure 1 The refresh control circuit 116 is shown. Specific internal components and signals of the refresh control circuit 216 are illustrated to illustrate its operation. Dashed line 218 is shown to indicate that in some embodiments, each component (e.g., refresh control circuit 216 and row decoder 208) may correspond to a specific memory group, and these components may be repeated for each memory group. Therefore, multiple refresh control circuits 216 and row decoders 208 may exist. For simplicity, only components of a single group will be described.

[0049] DRAM interface 226 can provide one or more signals to address refresh control circuitry 216 and row decoder 208. Refresh control circuitry 216 may include refresh state control circuitry 228, target refresh circuitry system 230, refresh management circuitry system 232, and refresh address generator circuitry 234. DRAM interface 226 can provide one or more control signals, such as refresh signal AREF, refresh management command signal RFMC, activation and precharge signals ACT / Pre, and row address XADD. When the group associated with refresh control circuitry 216 is in refresh mode, refresh control circuitry 216 provides timing to refresh address XADD based on refresh signal AREF. Refresh control circuitry can also provide refresh address XADD (and other signals) for RFM refresh operations.

[0050] DRAM interface 226 may represent one or more components that provide signals to components of a group. In some embodiments, DRAM interface 226 may represent a device coupled to a semiconductor memory device (e.g., Figure 1 The memory controller (e.g., memory controller 101) of the device 100. In some embodiments, the DRAM interface 226 may represent a component, such as Figure 1 The command address input circuit 102, address decoder 104, and / or command decoder circuit 106 are included. The DRAM interface 226 provides row address XADD, refresh signal AREF, and access signals such as activation signal ACT and precharge signal Pre. Although Figure 2 Not shown, but the DRAM interface 226 can also provide a group address BADD, which indicates which group the accessed row address XADD belongs to. The group address BADD can activate a specific refresh control circuit 216 associated with the group indicated by the group address BADD. The DRAM interface can also put the refresh control circuit into refresh mode by providing the refresh signal AREF for activation. The refresh signal AREF can be a periodic signal provided during refresh mode, which indicates the timing of the refresh operation. As part of the access operation, access signals ACT and Pre, as well as the row address XADD, can be provided. An activation signal ACT can be provided to activate a given group of memory. A precharge signal Pre can be provided to precharge a given group of memory. The row address XADD can be a signal containing multiple bits (which can be transmitted sequentially or in parallel) and can correspond to a specific row of the activated memory group.

[0051] The target refresh circuitry system 230 may include one or more circuits for detecting one or more aggressor rows, such as aggressor rows in a row hammer attack. The target refresh circuitry system 230 may receive row address XADD and ACT / Pre signals from DRAM interface 226. In some instances, the received row address (sampled address or all addresses) may be stored and / or compared with previously stored addresses. The target refresh circuitry system 230 may provide a matching address RHR_ADD based on the current row address XADD and / or previously stored row addresses. In some embodiments, the matching address RHR_ADD may correspond at least a few times to the row address most frequently received over a period of time. The matching address RHR_ADD may be provided to refresh address generator circuitry 234 for calculating the victim word line of the aggressor word line associated with the matching address RHR_ADD. Examples of suitable circuitry for implementing the target refresh circuitry system 230 can be found in U.S. Patent Nos. 9,805,783, 10,685,696, and 16 / 268,818. However, the target refresh circuit system 230 is not limited to these examples.

[0052] The refresh management (RFM) circuitry 232 may include one or more circuits for determining when an RFM refresh operation should be performed. The RFM circuitry 232 may receive an RFM command signal RFMC, which may indicate one or more conditions for determining when an RFM refresh operation should be performed. The RFM circuitry 232 may receive an ACT / Pre signal and count the number of access requests based at least in part on the number of times an activation signal ACT is activated. When the count reaches a threshold (which may be set by the RFMC signal in some embodiments), the refresh management circuitry 232 may activate an RFM refresh (RFMR) signal provided to the refresh state control circuitry 228 indicating that an RFM refresh operation should be performed. Once the threshold is reached, the count value of the access requests may be adjusted (e.g., decremented, reset, set to zero), and the counting of access requests may continue. In some embodiments, the RFM circuitry 232 may receive a row address XADD. Similar to the target refresh circuitry 230, the RFM circuitry 232 may store and / or compare the received row address (sampled address or all addresses) with a previously stored address. In some embodiments, comparing a row address with a previously stored row address can be used to at least partially determine whether one or more row addresses are intruder rows.

[0053] If it is determined that none of the received row addresses are intruder row addresses (e.g., received at or above the cutoff frequency), then the refresh management circuitry 232 may not activate the RFMR signal when the access request count reaches a threshold. In some embodiments, the count of access requests can be adjusted even when the RFMR signal is not activated. If it is determined that one or more of the received row addresses are associated with an intruder row, then said one or more addresses can be provided to the refresh address generator circuitry 234 as the RFM address RFM_ADD and the RFMR signal can be activated. In some embodiments, the row addresses stored in the refresh management circuitry 232 may also be adjusted (e.g., erased, shifted, overwritten) when the access request threshold is reached and / or the RFMR signal is activated.

[0054] For reference Figure 1 As discussed, in some embodiments, access requests can be counted by a memory controller, such as memory controller 101, rather than by refresh control circuitry 216. In these embodiments, refresh management circuitry 232 can receive RFM signals via DRAM interface 226. When refresh management circuitry 232 determines that the received row address is an intruder row, refresh management circuitry 232 can provide an active RFMR signal in response to the received RFM signal.

[0055] The refresh status control circuit 228 can provide a refresh operation type signal ROT, indicating what type of refresh operation should be performed (e.g., automatic refresh, target refresh, RFM refresh). In some embodiments, ROT can be a multi-bit signal. The state of the ROT signal can be based at least in part on the states of the refresh signal AREF and the RFM refresh signal RFMR.

[0056] As part of the refresh mode, the memory device can perform a series of refresh operations to periodically refresh rows of the memory device. Refresh state control circuitry 228 can determine whether a given refresh operation is an automatic refresh operation or a targeted refresh operation. A ROT signal can be generated to indicate that the device should refresh a specific target row (e.g., the victim row) instead of an address in the series of automatic refresh addresses. Refresh state control circuitry 228 can adjust the state of the ROT signal such that a series of automatic refresh operations and targeted refresh operations are performed in response to the activation of one or more refresh signals AREF.

[0057] In some embodiments, the refresh control circuit 216 may perform multiple refresh operations in response to each activation of the refresh signal AREF. For example, whenever the refresh signal AREF is received, the refresh control circuit 216 may perform K different refresh operations by providing K different refresh addresses RXADD. Each refresh operation may be referred to as a 'pump'. Each of the K different refresh operations may be an automatic refresh operation or a target refresh operation. In some embodiments, the number of target and automatic refresh operations in each group of pumps may be constant in response to the activation of the refresh signal AREF. In some embodiments, it may vary.

[0058] Based on the state of the ROT signal, the refresh address generator circuit 234 can provide a refresh address RXADD that can be an auto-refresh address, one or more victim addresses corresponding to the victim row of the aggressor row corresponding to the matching address RHR_ADD, or one or more victim addresses corresponding to the victim row of the aggressor row (e.g., a high-frequency row) corresponding to RFM_ADD. The line decoder 208 can perform a refresh operation in response to the refresh address RXADD and the refresh operation type signal ROT.

[0059] The refresh address generator circuit 234 may receive a matching address RHR_ADD from the target refresh circuitry system 230. The matching address RHR_ADD may represent an aggressor row. The refresh address generator circuit 234 may determine the location of one or more victim rows based on the matching address RHR_ADD and provide them as refresh addresses RXADD when the ROT signal indicates a target refresh operation. In some embodiments, victim rows may include rows that are physically adjacent to the aggressor rows (e.g., RHR_ADD+1 and RHR_ADD-1). In some embodiments, victim rows may also include rows that are physically adjacent to the aggressor rows (e.g., RHR_ADD+2 and RHR_ADD-2). Other relationships between victim rows and identified aggressor rows may be used in other instances. For example, + / -3, + / -4, and / or other rows may also be refreshed.

[0060] The refresh address generator circuit 234 can receive the RFM address RFM_ADD from the RFM circuit system 232. The RFM address RFM_ADD can represent the row address received at a frequency at or above the cutoff frequency, and it can correspond to an aggressor row. The refresh address generator circuit 234 can determine the location of one or more victim rows based on the RFM address RFM_ADD and provide them as refresh address RXADD when the ROT signal indicates an RFM refresh operation. Similar to the target refresh operation, the victim rows can include rows that are physically adjacent to the aggressor rows and / or rows that are physically adjacent to the aggressor rows. Other relationships between victim rows and identified aggressor rows can be used in other instances.

[0061] The refresh address generator circuit 234 can determine the value of the refresh address RXADD based on the ROT signal. In some embodiments, when the ROT signal indicates an automatic refresh operation, the refresh address generator circuit 234 can provide one of a series of automatic refresh addresses. When the ROT signal indicates a target refresh operation, the refresh address generator circuit 234 can provide a target refresh address as the refresh address RXADD, for example, providing a victim address. In some embodiments, the refresh address generator circuit 234 can count the number of times the ROT signal indicates a target refresh operation and can provide a closer victim line (e.g., RHR_ADD+ / -1) more frequently than a victim line further away from the aggressor address (e.g., RHR_ADD+ / -2). When the ROT signal indicates an RFM refresh operation, the refresh address generator circuit 234 can provide an address corresponding to a victim address (e.g., RFM_ADD+ / -1) generated at least partially based on the RFM address RFM_ADD as the refresh address RXADD.

[0062] Alternatively, in some embodiments, the refresh management circuitry 232 may not provide the RFM address RFM_ADD. Instead, the refresh address generator circuitry 234 may receive the matching address RHR_ADD to generate the refresh address RXADD during the RFM refresh operation.

[0063] In some embodiments, an RFM refresh operation may be performed at least in part in response to the refresh management circuitry 232 providing the RFMR signal, even if the refresh operation would not otherwise be performed. For example, after providing the RFMR signal, the refresh control circuitry 216 may issue the ROT signal, indicating that an RFM refresh operation should be performed, even if the memory device is not currently in refresh mode. In some embodiments, access operations may be in a 'suspended' state when the memory performs an RFM refresh, and subsequently, access operations may resume. In some embodiments, the refresh operation type ROT signal may indicate that multiple RFM refresh operations should be performed (e.g., by indicating multiple RFM refresh operations). For example, in response to each activation of the RFM state of the ROT signal, the refresh state control circuitry 228 may indicate that two RFM refresh operations should be performed. In other instances, a different number of RFM refresh operations may be performed in response to each activation.

[0064] The row decoder 208 can perform one or more operations on the memory array (not shown) based on received signals and addresses. For example, in response to the activation signal ACT, the row address XADD, and the ROT signal, the row decoder 208 can direct one or more access operations (e.g., read operations) on the specified row address XADD. In response to the ROT signal indicating a refresh operation, the row decoder 208 can refresh the refresh address RXADD. It should be understood that the actual methods for performing the target refresh operation and the RFM refresh operation can be substantially the same (e.g., refreshing the victim word line based on the seed address RHR_ADD or RFM_ADD), and the different terms are intended to distinguish the cause of a particular refresh operation.

[0065] Figure 3 This is a block diagram of a refresh management circuitry system according to an embodiment of the present disclosure. In some embodiments, refresh management circuitry system 332 may be included in refresh management circuitry system 232. Refresh management circuitry system 300 may include access counter circuitry 336, burst detector circuitry 338, RFM address storage circuitry 340, and skip logic circuitry 342.

[0066] Access counter circuit 336 may receive an activation signal ACT. The activation signal ACT may be provided by command decoder circuitry, such as command decoder circuitry 106. Access counter circuit 336 may count the number of access requests based at least in part on the number of times the activation signal ACT is activated. When the number of access requests reaches a threshold, access counter circuit 336 may activate refresh management signal RFM. In some embodiments, the RFM signal may be a pulse signal (e.g., a square wave) that transitions from one logic state (e.g., low) to another logic state (e.g., high) and then back to the initial logic state over a period of time (e.g., half a clock cycle or one or more clock cycles). In some embodiments, access counter circuit 336 may be included in memory controller 301 communicatively coupled to memory containing other components of refresh management circuitry system 300. In some embodiments, memory controller 301 may be included in memory controller 101.

[0067] Burst detector circuit 338 may receive an activation signal ACT and a row address XADD. Burst detector circuit 338 may store and / or compare the received row address XADD with a previously received row address XADD to determine whether a row address XADD (e.g., an aggressor row address) has been received at a frequency at or above a cutoff frequency. In some embodiments, burst detector circuit 338 may store and / or compare all row address XADDs. In some embodiments, burst detector circuit 338 may store and / or compare several row address XADDs. In some embodiments, these several may be based at least in part on the activation signal ACT. When burst detector circuit 338 determines that a row address XADD has been received at a frequency at or above a cutoff frequency, burst detector circuit 338 may activate a burst flag clock signal Burst_Flag_Clk. In some embodiments, the Burst_Flag_Clk signal may be a pulse signal. Burst detector circuit 338 may receive an RFM signal from access counter circuit 336. In some embodiments, at least in part in response to the activation of the RFM signal, one or more components of burst detector circuit 338 may be adjusted (e.g., reset).

[0068] The RFM address storage circuit 340 can receive a row address XADD and a Burst_Flag_Clk signal from the burst detector circuit 338. In response to the activation of the Burst_Flag_Clk signal, if the current row address is not already stored in the RFM address storage circuit 340, then the RFM address storage circuit 340 can store the current row address XADD. The current row address may correspond to an intruder row identified by the burst detector circuit 338. When storing a new address, the RFM address storage circuit 340 can activate an incrementing signal Incr provided to the skip logic circuit 342. In some embodiments, the incrementing signal Incr may be a pulse signal. The RFM address storage circuit 340 can receive an RFM signal. In response to the activation of the RFM signal, the RFM address storage circuit 340 can provide an RFM address RFM_ADD. In some embodiments, the RFM address RFM_ADD may be provided to a refresh address generator circuit, such as refresh address generator circuit 234.

[0069] Skip logic circuit 342 may receive an RFM signal from access counter circuit 336 and an increment signal Incr from RFM address storage circuit 340. Skip logic circuit 342 may count the number of times the RFM signal and Incr signal are received. If the number of times the RFM signal is received is equal to or less than the number of times the Incr signal is received, it may indicate that an intruder row address that has not yet been provided as an RFM refresh address RFM_ADD is stored in RFM address storage circuit 340. Therefore, in response to the RFM signal, skip logic circuit 342 may activate the RFM refresh signal RFMR. In some embodiments, the RFMR signal may be provided to refresh state control circuitry, such as refresh state control circuit 228. If the number of times the RFM signal is received is greater than the Incr signal, it may indicate that an intruder row has not been identified since the start of a previous RFM refresh operation. Therefore, in response to the RFM signal, skip logic circuit 342 may not activate the RFM refresh signal RFMR. This may cause an RFM refresh operation based on the number of access requests to be skipped.

[0070] Although the RFM signal provided by the access counter circuit 336 and the RFM refresh signal RFMR provided by the skip logic circuit 342 are described as separate signals, in some embodiments, the two can be regarded as the same signal, and the skip logic circuit 342 selectively masks or blocks the RFM signal at least in part based on the Incr signal.

[0071] Figure 4 This is a block diagram of an access counter circuit according to an embodiment of the present disclosure. Access counter circuit 436 can be used to implement access counter circuit 336. In some embodiments, access counter circuit 436 may include counter 444 and pulse generator 446. In some embodiments, access counter circuit 436 may be included in memory controller 401. In some embodiments, memory controller 401 may be included in memory controller 301 and / or memory controller 101.

[0072] In some embodiments, counter 444 may be a multi-bit counter that increments its count value each time an activation signal ACT is received. When the multi-bit counter reaches its maximum value, counter 444 may be reset. Resetting counter 444 may activate the refresh management signal RFM.

[0073] In some embodiments, for example Figure 4In the embodiment shown, counter 444 may have a programmable threshold, for example, programmed via the RFM command signal RFMC. Each time an activation signal ACT is received, the count value may increment and be compared with the threshold. When the count value is found to equal the threshold, counter 444 may activate the threshold signal Thresh provided to pulse generator 446. Pulse generator 446 may generate pulses for applying the RFM signal. The RFM signal may be provided to counter 444. In response to applying the RFM signal, counter 444 may adjust the count value. In some embodiments, adjusting the count value may include resetting to an initial value (e.g., zero).

[0074] After resetting and / or adjusting the count value in response to the applied RFM signal, counter 444 may continue to increment in response to the applied activation signal ACT. Although counter 444 is described as incrementing the count value in response to the activation signal ACT, in some embodiments, counter 444 may decrement the count value in response to the activation signal ACT. For example, counter 444 may count down from a threshold to zero.

[0075] Figure 5 This is a block diagram of a burst detector circuit according to an embodiment of the present disclosure. In some embodiments, burst detector circuit 538 may be used to implement burst detector circuit 338. Burst detector circuit 538 may include first-in-first-out (FIFO) circuit 548, comparator circuit 552, and pulse generator 554.

[0076] FIFO circuit 548 may include multiple registers 550, labeled R0-R3. Each of registers 550 may be configured to store a row address XADD. FIFO circuit 548 may receive an activation signal ACT. The activation signal ACT may be received from a command decoder circuit, such as command decoder circuit 106. The activation signal ACT may act as a clock signal to control the contents of FIFO circuit 548. In response to the activation signal ACT, FIFO circuit 548 may latch the current row address XADD (XA0) in register R0. The previously stored row address (XA1) may be shifted from register R0 to register R1. The previously stored row address (XA2) may be shifted from register R1 to register R2, and so on. The previously stored matching address in the last register R4 may be discarded.

[0077] When a new row address XA0 is received, comparator circuit 552 compares row address XA0 with row addresses XA1-XA4 in registers 550 and R0-R3. If row address XA0 matches one or more of row addresses XA1-XA4 in FIFO circuit 548 (e.g., the same as them), it indicates that row address XA0 is being received at a high frequency (e.g., at or above the cutoff frequency). That is, the word line associated with row address XA0 can be accessed at a high frequency / rate via access requests. Therefore, the word line associated with row address XA0 can be an intruder row. If the current row address XA0 matches one of row addresses XA1-XA4 in FIFO circuit 548 (e.g., the same as them), comparator circuit 552 activates the burst flag signal Burst_Flag. The Burst_Flag signal can be received by pulse generator 554, which can activate the burst flag clock signal Burst_Flag_Clk in response to the Burst_Flag signal. Burst_Flag_Clk can indicate that the burst detector circuit 538 has identified an intruder row. In some embodiments, the Burst_Flag_Clk signal can be provided to RFM address storage circuitry, such as RFM address storage circuitry 340. As disclosed herein, the Burst_Flag_Clk signal can cause the RFM address storage circuitry to store the current row address XA0.

[0078] The FIFO circuit 548 may further receive a refresh management signal RFM from access counter circuitry, such as access counter circuitry 436 and / or access counter circuitry 336. In some embodiments, the RFM signal may act as a reset signal and clear register 550 of the FIFO circuit 548.

[0079] Although the FIFO circuit 548 is shown with four registers 550, it may contain more or fewer registers in other embodiments. The burst detector circuit 538 can act as a digital high-pass filter. Row addresses received at low frequencies can be "filtered out," while row addresses received at high frequencies can be "passed through" by activating the Burst_Flag signal. In other words, row addresses received at frequencies below the cutoff frequency can be determined to be non-aggressor rows, while row addresses received at frequencies at or above the cutoff frequency can be determined to be aggressor rows.

[0080] The cutoff frequency can be at least partially defined by the row address received more than once in N consecutive access requests, where N is the number of registers 550 in the FIFO circuit 548. By increasing the number of registers 550 in the FIFO circuit 548, the cutoff frequency decreases, and lower-frequency row addresses can be passed in part because earlier row addresses are stored in the FIFO circuit 548. Therefore, the probability that the row address in register 550 matches the current row address XA0 increases. By decreasing the number of registers 550 in the FIFO circuit 548, the cutoff frequency increases, and the burst detector circuit 538 only passes higher-frequency row addresses. The value of the cutoff frequency of the FIFO circuit 548 in Hertz can be at least partially determined by the frequency of access requests (e.g., activation signals) received by the burst detector circuit 538. Therefore, in some embodiments, if the frequency of access requests changes, the frequency in Hertz also changes. However, in some embodiments, the cutoff frequency based on receiving a row address more than once in several access requests can remain constant.

[0081] exist Figure 5 In the embodiment shown, FIFO circuit 548 latches row address XADD in response to each activation signal ACT. However, in other embodiments, burst detector circuit 538 may include sampling circuitry that generates a sampled signal that triggers FIFO circuit 548, instead of the activation signal ACT. In some embodiments, the sampled signal may be at least partially based on the activation signal ACT. The sampled signal may be non-random (e.g., periodic), random, or pseudo-random.

[0082] Figure 6 This is a block diagram of a refresh management address storage circuit according to embodiments of the present disclosure. In some embodiments, RFM address storage circuit 640 may be included in RFM address storage circuit 340. RFM address storage circuit 640 may include multiple address registers 656 and a comparison logic circuit 658. Although Figure 6 The diagram shows four address registers 656ADD_Reg0-3, but in other embodiments, the address storage circuitry 640 may contain more or fewer address registers 656.

[0083] RFM address storage circuit 640 can receive row address XADD and burst flag clock signal Burst_Flag_Clk. The Burst_Flag_Clk signal can be received from burst detector circuitry, such as burst detector circuitry 538 and / or 338. In response to the Burst_Flag_Clk signal, comparison logic circuitry 658 can compare the current row address XADD with the row address already stored in address register 656. If the current row address XADD does not match any address stored in address register 656, then comparison logic circuitry 658 can activate a new address flag New_adr_flag signal provided to one of the address registers 656. In response to the New_adr_flag signal, the corresponding address register 656 can store the current row address XADD. In some embodiments, comparison logic 658 allows the order in which row addresses are stored in address register 656 to be consecutive. For example, in response to the first Burst_Flag_Clk pulse, the row address can be stored in Add_Reg0. In response to the second Burst_Flag_Clk pulse, the row address can be stored in Add_Reg1, and so on. In other embodiments, the order in which the row addresses are stored in address register 656 can be random or pseudo-random. In some embodiments, each time a new address is stored in one of the registers 656, the RFM address storage circuit 640 can provide an incrementing signal Incr to the skip logic circuit (e.g., skip logic circuit 342).

[0084] If the current row address XADD matches one of the row addresses already stored in register 656, then the RFM address storage circuit 640 may not store (e.g., ignore) the current row address, and the Incr signal may not be activated (e.g., remain inactive). In some embodiments, if all registers 656 are currently storing row addresses, then the new address may be ignored, even if the new address does not match any address stored in address register 656. In this case, the Incr signal may not be activated.

[0085] RFM address storage circuit 640 can receive a refresh management signal RFM. The RFM signal can be provided by an access counter circuit, such as access counter circuits 436 and / or 336. In response to the applied RFM signal, RFM address storage circuit 640 can use an output address from address register 656 as the RFM address RFM_ADD. In some embodiments, the RFM address RFM_ADD can be provided to a refresh address generator circuit, such as refresh address generator circuit 234. In some embodiments, the order in which addresses are provided from address register 656 can be sequential. For example, in response to a first RFM pulse, an address stored in Add_Reg0 can be provided. In response to a second RFM pulse, an address stored in ADD_Reg1 can be provided, and so on. In some embodiments, the order in which addresses are provided from address register 656 can be random or pseudo-random.

[0086] Figure 7 This is a block diagram of a skip logic circuit according to an embodiment of the present disclosure. In some embodiments, skip logic circuit 742 may be included in skip logic circuit 342. Skip logic circuit 742 may include bit counter 760 and control logic circuit 762.

[0087] Bit counter 760 may receive an increment signal Incr from RFM address storage circuitry, such as RFM address storage circuitry 640 and / or 340. When bit counter 760 receives the Incr signal, bit counter 760 may increment the count value. Bit counter 760 may receive a refresh management signal RFM. When bit counter 760 receives the RFM signal, bit counter 760 may decrement the count value. In some embodiments, the count value will not fall below a minimum value (e.g., zero).

[0088] For reference Figure 6 As mentioned, the incrementing signal Incr is activated in response to a new row address stored in the RFM address storage circuit. This indicates that an RFM refresh operation may be needed to refresh the victim row associated with the row address stored in the RFM address storage circuit. When the RFM signal is activated, it indicates that an RFM refresh operation will be performed, and the row address will be provided from the RFM address storage circuit to generate the refresh address. Therefore, the RFM signal can indicate that one less aggressor row address stored in the RFM address storage circuit requires an RFM refresh operation.

[0089] Therefore, when bit counter 760 has a value greater than the minimum value (e.g., zero), it indicates the presence of an intruder line stored in the RFM address memory circuit to be processed by the RFM refresh operation. When bit counter 760 has a value equal to the minimum value, it indicates that all intruder lines stored in the RFM address memory circuit have been provided to the refresh address generator circuit during one or more RFM refresh operations.

[0090] In some embodiments, when the bit counter 760 has a value greater than the minimum value, it can provide an inactive Skip signal. When the bit counter 760 has a value equal to the minimum value, it can provide an active Skip signal. The Skip signal and the RFM signal can be provided to the control logic circuit 762 as inputs. The control logic circuit 762 can also receive the RFM signal as an input. Based on the state of the Skip signal, the control logic circuit 762 can provide an active RFM refresh signal RFMR in response to the active RFM signal.

[0091] exist Figure 7 In the example shown, control logic 762 includes an AND gate. In this example, the Skip signal can be active low (e.g., a low logic state). Therefore, when the count value of bit counter 760 is greater than a minimum value, the Skip signal can be high, and control logic 762 can provide an active RFM refresh signal RFMR in response to an active RFM signal. When the count value of bit counter 760 is equal to the minimum value, the Skip signal can be low, and control logic 762 can keep the RFM refresh signal RFMR inactive, even if an active RFM signal is received. Keeping the RFMR signal inactive can be referred to as masking and / or blocking the active RFM signal. The logic gates and signal states are provided only as examples. In other embodiments, other suitable logic circuitry may be included in control logic 762, and / or the Skip signal may be an active high signal.

[0092] Therefore, by suppressing the RFM signal when there is no new intruder row address stored in the RFM address storage circuit, unnecessary RFM refresh operations can be reduced.

[0093] As disclosed herein, RFM refresh operations performed by a memory device (e.g., device 100) can be controlled at least in part based on external commands. In some embodiments, external commands (e.g., RFM commands) can be provided by a memory controller and / or processor communicating with the memory device. In some applications, RFM commands may allow for greater control over refresh operations, since automatic and targeted refresh operations are typically controlled by commands within the memory device. For example, in addition to being able to indicate that an RFM refresh operation should be performed for a number of access requests, an RFM command may also indicate the number of RFM refresh operations to be performed once the number of access requests reaches a threshold.

[0094] In some embodiments, a single RFM refresh operation may be performed when the number of access requests reaches a threshold. This may be referred to as a "distributed" RFM refresh operation. In other embodiments, multiple RFM refresh operations may be performed. In some embodiments, if multiple RFM refresh operations are performed as soon as the number of access requests is reached, the threshold may be larger than when performing a single RFM refresh operation. This may be referred to as a "deferred" RFM refresh operation.

[0095] Figure 8 This is a timing diagram of a distributed refresh management technique according to embodiments of the present disclosure. Timing diagram 800 may show the state of signals of a memory device (e.g., memory device 100). The first row of timing diagram 800 shows the relative timing of activation commands ACT corresponding to access requests and the individual refresh operations. Activation commands ACT are shown as shorter, thinner lines. However, densely spaced activation commands (e.g., high frequency) are shown as boxes filled with diagonal lines. Periods of sparse activation commands (e.g., several or none) are shown as boxes filled with dots. Automatic refresh operations are shown as taller dashed lines. Target refresh operations are shown as taller, thicker dashed lines. RFM refresh operations are shown as taller lines, but when an RFM operation is skipped, it is shown as a dashed line.

[0096] During periodic refresh mode, automatic refresh and / or target refresh operations can be performed (e.g., based on a periodic signal, such as AREF). In some embodiments, for example... Figure 8 In the embodiment shown, the memory device can perform a "dual-pump" refresh operation during refresh mode. Figure 8 In the example shown, the first pump can perform an automatic refresh operation, and the second pump can perform a target refresh operation. In some embodiments, the two pumps can perform the target refresh operation periodically.

[0097] Unlike automatic refresh and target refresh operations, the RFM refresh operation can be performed in response to the number of activation commands (ACTs), rather than periodically based on time. In some embodiments, the activation commands can be counted by access counter circuitry, such as access counter circuitry 336 and / or 436, and the access counter circuitry can provide signals (in...) Figure 8 (Not shown in the image), indicating that an RFM refresh operation should be performed once the count value reaches the threshold. Therefore, as... Figure 8 As shown, the timing of the RFM refresh operation is more closely spaced during the periods of the high-rate activation command ACT (e.g., period 802) compared to the period of the low-rate activation command ACT (e.g., period 804).

[0098] The second row of timing diagram 800 shows the state of the Burst_Flag signal. The Burst_Flag signal can be provided by a portion of the burst detector, such as comparator circuit 552 of burst detector circuit 538. (See reference...) Figure 5 As described, Burst_Flag can transition to an active state (e.g., in response to determining that the current row address matches a previously received row address stored in the burst detector (e.g., FIFO circuit 548)). Figure 8 (High state in the example shown). This indicates that the row address is being received at or above the cutoff frequency and corresponds to the aggressor row. The Burst_Flag can transition to an inactive state at least in part in response to performing an RFM refresh operation (e.g., in...). Figure 8 (The low state in the example shown).

[0099] like Figure 8 As shown, at or near time T0, the burst detector determines that the row address corresponds to the aggressor row and the Burst_Flag transitions to the active state. Once the number of activated commands (ACT) reaches a threshold, an RFM refresh operation is performed at or near time T1. The RFM refresh operation may be performed in response to a skip logic circuit (e.g., skip logic circuits 342 and / or 742) at least in part in response to the active RFM refresh signal RFMR provided by the Burst_Flag provided by the burst detector, for example, as referenced Figure 5-7 As described. At least in part in response to an RFM refresh operation, Burst_Flag may transition to an inactive state at or near time T1.

[0100] The access counter circuit can continue to count the number of activation commands (ACTs) received after an RFM refresh operation is performed at or near time T1. The threshold may be reached again at or near time T2. However, during the time between the RFM refresh operation and the re-reaching of the threshold, the burst detector will not detect intruder rows. That is, all row addresses associated with activation commands (ACTs) may have already been received at a low frequency, thus posing a lower risk of becoming intruder rows. Therefore, the Burst_Flag signal can remain low, and the skip logic circuit can keep the RFMR signal in an inactive state. As shown by the dashed line at or near time T2, an RFM refresh operation may not be performed (e.g., skipped), even if the access counter circuit reaches the threshold. The same situation occurs at or near time T3, and yet another RFM refresh operation is skipped.

[0101] like Figure 8As shown, the Burst_Flag signal can remain active for a variable amount of time. The pulse width of the Burst_Flag signal can be based on the rate at which the aggressor line is detected after a previous RFM refresh operation (or a scheduled RFM refresh operation).

[0102] Although reference Figure 3-7 The described RFM circuit system can be used for implementation Figure 8 The distributed refresh management technology is shown in the figure, but in some embodiments, alternative embodiments of the RFM circuit system may be used.

[0103] Figure 9 This is a block diagram of an example of an RFM circuit system according to embodiments of the present disclosure. In some embodiments, a simplified RFM circuit system 932 may be included in RFM circuit system 232. The simplified RFM circuit system 932 may include an access counter circuit 936 (in some embodiments, it may be included in a memory controller 901), a burst detector circuit 938, and a skip logic circuit 942. In some embodiments, the access counter circuit 436 may be used to implement the access counter circuit 932.

[0104] In some embodiments, the burst detector circuitry 938 may be equivalent to the burst detector 538, but the pulse generator 554 may be omitted, and the burst detector 938 may provide a burst flag signal Burst_Flag instead of a burst flag clock signal Burst_Flag_Clk. Skip logic circuitry 942 may receive the RFM signal from the access counter circuitry 936 and the Burst_Flag from the burst detector 938. Skip logic circuitry 942 may include appropriate logic gates (e.g., AND gates) such that when the Burst_Flag signal and the RFM signal are applied, skip logic circuitry 942 provides an applied RFM refresh signal RFMR. In some embodiments, refresh address generator circuitry (e.g., refresh address generator circuitry 234) may be configured to use the current row address XADD as the RFM address RFM_ADD during the RFM refresh operation. In other embodiments, the RFM circuitry system 932 may optionally further include an RFM address register 940 configured to latch the row address XADD in response to the applied Burst_Flag signal.

[0105] Figure 10 This is a timing diagram of a delayed distributed refresh management technique according to embodiments of the present disclosure. Timing diagram 1000 may show the state of signals of a memory device, such as memory device 100. In some embodiments, the memory device may include an RFM circuit system, such as RFM circuit system 332, which in some embodiments may be referenced... Figure 4-7 The circuit implementation described.

[0106] The first row of timing diagram 1000 shows the relative timing of activation commands (ACTs) corresponding to access requests and the individual refresh operations. Activation commands (ACTs) are shown as shorter, thinner lines. However, densely spaced activation commands (e.g., high frequency) are shown as boxes filled with diagonal lines. Periods of sparse activation commands (e.g., a few or none) are shown as boxes filled with dots. Automatic refresh operations are shown as taller dashed lines. Target refresh operations are shown as taller, thicker dashed lines. RFM refresh operations are shown as taller lines, but when an RFM operation is skipped, it is shown as a dashed line. In some embodiments, Figure 10 The refresh operation shown can be performed by referring to... Figure 8 The process is performed in a largely the same manner as described. However, for RFM refresh operations, four RFM refresh operations are performed instead of a single RFM refresh operation when the count value reaches a threshold. The four RFM refresh operations are provided for illustrative purposes only, and in some embodiments, any number of RFM refresh operations may be performed.

[0107] The second row of timing diagram 1000 shows the burst flag clock signal Burst_Flag_Clk, which can be provided by a burst detector circuit, such as burst detector circuit 538. The third row of timing diagram 1000 shows the value of the bit counter of the skip logic circuit, such as bit counter 760 of skip logic circuit 7422. The remaining rows of timing diagram 1000 show the state of the address register ADD_Reg0-3 of the RFM address storage circuit (e.g., address storage circuit 640). In some embodiments, for example... Figure 10 The embodiment shown allows selection of the number of address registers for the RFM address storage circuitry to match the response to the RFM refresh signal RFMR (in Figure 10 The number of RFM refresh operations performed (not shown in the figure).

[0108] At or near time T0, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that the row address corresponds to the aggressor row. In response to the Burst_Flag_Clk pulse, an address register ADD_Reg0 stores the current row address Add_0. The RFM address storage circuitry can provide an action increment signal to the skip logic circuitry (in... Figure 10 (Not shown in the diagram). In response to an increment signal, the bit counter increments the value stored within it. In the example shown, the value increments from zero to one.

[0109] At or near time T1, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that another row address corresponds to the intruder row. In response to the Burst_Flag_Clk pulse, an address register ADD_Reg1 stores the current row address Add_1. The RFM address storage circuitry can provide an action increment signal to the skip logic circuitry, which in turn increments the bit counter value from 1 to 2 in response.

[0110] At or near time T2, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that another row address corresponds to the intruder row. In response to the Burst_Flag_Clk pulse, an address register ADD_Reg2 stores the current row address Add_2. The RFM address storage circuitry can provide an action increment signal to the skip logic circuitry, which in turn increments the bit counter value from 2 to 3 in response.

[0111] At or near time T3, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that another row address corresponds to the intruder row. In response to the Burst_Flag_Clk pulse, an address register ADD_Reg3 stores the current row address Add_3. The RFM address storage circuitry can provide an action increment signal to the skip logic circuitry, which in turn increments the bit counter value from 3 to 4 in response.

[0112] At or before time T4, the threshold number of activation commands (ACT) can be reached. Because the bit counter has a value greater than zero (e.g., four), the RFM refresh signal RFMR (at...) is activated. Figure 10 (Not shown) can be provided to refresh state controller circuit, such as refresh state controller circuit 228, and the RFM refresh operation can be performed by the memory device starting at or near time T4.

[0113] In response to the first RFM refresh operation, the address stored in ADD_Reg0 can be provided to the refresh address generator circuit, such as refresh address generator circuit 234, and the bit counter value can be decreased from 4 to 3. Because the bit counter value is still greater than zero, the active RFM refresh signal RFMR can be provided. In response to the second RFM refresh operation, the address stored in ADD_Reg1 can be provided to the refresh address generator circuit, and the bit counter value can be decreased from 3 to 2. The same process is performed for the third and fourth RFM refresh operations. After the fourth RFM refresh operation is completed, the bit counter value returns to zero, and all registers ADD_Reg0-3 are empty (e.g., do not contain valid data). In some embodiments, the access counter value can be reset, and counting can continue from the reset value (e.g., zero or a threshold in the case of access counter countdown).

[0114] At or near time T5, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that another row address corresponds to the intruder row. In response to the Burst_Flag_Clk pulse, an address register ADD_Reg0 stores the current row address Add_4. The RFM address storage circuitry can provide an action increment signal to the skip logic circuitry, which in turn increments the bit counter value from 0 to 1 in response.

[0115] At or near time T6, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that another row address corresponds to the intruder row. In response to the Burst_Flag_Clk pulse, an address register ADD_Reg1 stores the current row address Add_5. The RFM address storage circuitry can provide an action increment signal to the skip logic circuitry, which in turn increments the bit counter value from 1 to 2 in response.

[0116] At or before time T7, the threshold number of activation commands (ACT) can be reached. Because the bit counter has a value greater than zero (e.g., 2), the active RFM refresh signal RFMR can be provided to the refresh status controller circuit, and the RFM refresh operation can begin to be performed by the memory device at or near time T7.

[0117] In response to the first RFM refresh operation, the address stored in ADD_Reg0 can be provided to the refresh address generator circuit, and the bit counter value can be decreased from 2 to 1. Because the bit counter value is still greater than zero, the active RFM refresh signal RFMR can be provided. In response to the second RFM refresh operation, the address stored in ADD_Reg1 can be provided to the refresh address generator circuit, and the bit counter value can be decreased from 1 to 0. However, because the bit counter now has a value of zero, unlike the previous set of RFM refresh operations at time T4, the active RFM refresh signal RFMR is not provided by the skip logic circuit. Therefore, two of these four RFM refresh operations are not executed (e.g., skipped).

[0118] At or near time T8, while three of the four address registers (ADD_Reg0-2) are storing the previously detected aggressor row address, the burst detector issues the Burst_Flag_Clk signal. However, in this case, the RFM address storage circuitry determines that the current row address at or near time T8 is already stored in one of the registers (ADD_Reg0-2). Therefore, that address is not stored (e.g., ignored), and the bit counter value is not incremented (e.g., remains at three).

[0119] At or near time T9, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that another row address corresponds to the intruder row. At this time, the current row address is not stored in one of the address registers ADD_Reg0-2, and ADD_Reg3 stores the current row address Add_9.

[0120] At or near time T10, the Burst_Flag_Clk signal transitions to provide an action pulse in response to the burst detector determining that another row address corresponds to an aggressor row. However, all address registers ADD_Reg0-3 are currently storing the previously detected aggressor row address, and the address is not stored. The bit counter value is not incremented. Therefore, in some embodiments, and in some applications, not all identified aggressor rows can be addressed via the RFM refresh operation. In some embodiments, the access counter threshold can be selected to reduce the risk of missing aggressor row addresses identified by the burst detector.

[0121] Figure 11 This is a flowchart of a method according to an embodiment of the present disclosure. In some embodiments, method 1100 may be executed by a memory device, such as memory device 100.

[0122] At block 1102, the action "receiving multiple access requests and corresponding multiple row addresses" can be performed. The access requests and row addresses can be received by the memory device via command address input circuitry, such as command address input circuitry 102. At block 1104, the action "counting the number of the multiple access requests" can be performed. In some embodiments, the counting can be performed by access counter circuitry, such as access counter circuitry 336, 436, and / or 936. In some embodiments, the counting can be performed by a memory controller, such as memory controllers 101, 301, 401, and / or 901.

[0123] At box 1106, “Determine whether a row address among the plurality of row addresses is an aggressor row address.” In some embodiments, determining whether a row address is an aggressor row address may be based at least in part on the frequency at which the memory receives the row address. For example, a row address may be determined to be an aggressor row when the frequency is equal to or greater than the cutoff frequency of a high-pass filter. In some embodiments, the cutoff frequency may be selected based on the frequency of accessing the word line associated with the row address at which data in word lines physically adjacent to the word line is at risk of data degradation. In some embodiments, the determination may be performed by burst detector circuitry, such as burst detector circuitry 338, 538, and / or 938. In some embodiments, a row address is determined to be an aggressor row when the row address matches at least one previously received row address stored in a register of a burst detector in memory.

[0124] At block 1108, an "Execute Refresh Management Refresh Operation" can be performed. The RFM refresh operation can be performed in response to a refresh management refresh signal, which can be provided in response to the number of the plurality of access requests equaling a threshold and the row address being determined to be an intruder row address. In some embodiments, the refresh management refresh signal can be an external command / signal provided by the memory controller. In some embodiments, the refresh management refresh operation can be performed by refresh control circuitry (e.g., refresh control circuitry 116 and / or 216) or at least caused by refresh control circuitry. In some embodiments, the RFM refresh operation is skipped when row addresses received by the memory are each received at a low frequency—below the cutoff frequency. That is, the row address is received at a frequency that does not increase the risk of data degradation in the word line stored in the physically adjacent word line corresponding to the row address. In some embodiments, the RFM refresh operation is skipped in response to the masking effect of skip logic circuitry (e.g., skip logic circuitry 342, 742, and / or 942) on the RFM refresh signal.

[0125] The systems, methods, and apparatuses disclosed herein allow monitoring of row addresses with associated access requests to determine whether one or more row addresses are accessed at a high frequency (e.g., at or above the high-pass cutoff frequency), which may indicate that the row addresses are associated with an aggressor row. If none of the row addresses associated with the access request are determined to be provided at a high frequency (e.g., not determined to be an aggressor row), then the RFM refresh operation can be skipped. In some applications, this can reduce unnecessary refresh operations.

[0126] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with or separated from one or more other examples, embodiments, and / or processes and / or performed in a separate device or device portion of a system, apparatus, or method according to the present invention.

[0127] Finally, the foregoing discussion is intended to illustrate the system of the invention only and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the system of the invention has been described in detail with reference to exemplary embodiments, it should be understood that many modifications and alternative embodiments can be devised by those skilled in the art without departing from the broader and established spirit and scope of the system of the invention as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A semiconductor device comprising: A burst detector circuit is configured to determine whether a current row address is an intruder row address when it is received from a memory at a frequency equal to or greater than a cutoff frequency, wherein the burst detector circuit is configured to compare the current row address with one or more previously received row addresses, wherein the burst detector circuit is configured to provide an activation flag when the current row address matches one or more of the previously received row addresses, wherein the burst detector circuit includes: A pulse generator configured to provide the activation flag as a pulse signal; A first-in, first-out (FIFO) circuit, comprising a plurality of registers each configured to store one of the previously received row addresses; and A comparator circuit configured to compare the current row address with the previously received row address, and to provide an action burst flag to the pulse generator when the current row address matches one of the previously received row addresses, wherein the pulse generator is configured to provide the action flag as the pulse signal in response to the action burst flag; and Skip logic circuitry configured to deliver an active refresh management refresh signal at least in part in response to determining the intruder row address, wherein the active refresh management refresh signal causes the memory to perform a refresh operation outside of refresh mode.

2. The semiconductor device of claim 1, further comprising an access counter circuit configured to count the number of access commands and provide the action refresh management refresh signal when the number of access commands reaches a threshold.

3. The semiconductor device according to claim 2, wherein the access counter circuit comprises: A counter circuit configured to adjust the count value in response to the access command; as well as A pulse generator circuit, wherein the pulse generator circuit is configured to provide the action refresh management refresh signal as a pulse signal when the count value reaches the threshold.

4. A semiconductor device comprising: A burst detector circuit is configured to determine whether a current row address is an aggressor row address when a current row address received by a memory is received at a frequency equal to or greater than a cutoff frequency, wherein the burst detector circuit is configured to compare the current row address with one or more previously received row addresses, wherein the burst detector circuit is configured to provide an action flag when the current row address matches one or more of the previously received row addresses. Skip logic circuitry configured to deliver an active refresh management refresh signal at least in part in response to determining the intruder row address, wherein the active refresh management refresh signal causes the memory to perform a refresh operation outside of refresh mode; as well as An address storage circuit configured to store the current row address and provide an increment signal in response to the action flag, wherein the address storage circuit includes: Multiple address registers; as well as A comparator circuit configured to compare the current row address with a row address stored in one of the plurality of address registers in response to the activation flag, wherein the comparator circuit is configured to store the current row address in one of the plurality of address registers when the current row address does not match the row address stored in the plurality of address registers and at least one of the plurality of address registers is not storing a row address.

5. The semiconductor device of claim 4, wherein the skip logic circuitry includes a bit counter, wherein the value of the bit counterry increases in response to the action increment signal, and the value of the bit counterry decreases in response to the refresh management refresh signal, wherein the skip logic circuitry is configured to transmit the refresh management refresh signal when the value of the bit counterry is greater than a minimum value.

6. A semiconductor system comprising: A memory controller configured to count the number of activation commands received from the memory and provide an action refresh signal when the number of activation commands equals a threshold. as well as The memory includes: A burst detector configured to determine whether a row address received by the memory is an intruder row address and to provide an active burst flag in response to the intruder row address; Skip logic circuitry, which is configured to transmit the action refresh signal in response to the action burst flag, and to mask the action refresh signal when the burst flag is not active; An address register configured to store the row address in response to the action burst flag, wherein the address register is configured to provide the row address when the skip logic circuitry passes the action refresh signal; A refresh state controller circuit configured to provide a refresh operation type signal, such that a refresh management refresh operation is performed upon receiving the active refresh signal from the skip logic circuit; and A refresh address generator circuit configured to generate a refresh address at least in part based on the row address provided from the address register, in response to a refresh operation type signal indicating a refresh management refresh operation.

7. The semiconductor system of claim 6, wherein the refresh address corresponds to a word line that is physically adjacent to the row address provided from the address register.

8. A semiconductor system comprising: A memory controller configured to count the number of activation commands received from the memory and provide an action refresh signal when the number of activation commands equals a threshold. as well as The memory includes: A burst detector configured to determine whether a row address received from memory is an intruder row address and to provide an active burst flag in response to the intruder row address, wherein the burst detector includes: A first-in, first-out (FIFO) circuit, comprising a plurality of registers configured to store row addresses received by the memory; and A comparator circuit configured to provide the active burst flag when the row address matches at least one of the row addresses stored in the plurality of registers; and A skip logic circuit is configured to transmit the action refresh signal in response to the action burst flag and to mask the action refresh signal when the burst flag is not active.

9. The semiconductor system of claim 8, wherein the FIFO circuit is configured to be reset by the action refresh signal provided by the memory controller.

10. The semiconductor system of claim 8, wherein the FIFO circuit is a high-pass filter, wherein the cutoff frequency of the high-pass filter is at least partially based on the number of the plurality of registers.

11. A method for performing memory operations, comprising: The memory receives multiple access requests and corresponding row addresses from the memory controller. The multiple row addresses are stored in multiple registers of the first-in-first-out (FIFO) circuit of the burst detector circuit; Using a comparator circuit, it is determined, at least in part, whether the row address is an aggressor row address based on whether the row address matches at least one of the row addresses stored in the plurality of registers; When the row address matches at least one of the plurality of row addresses stored in the plurality of registers, an action burst flag is provided from the comparator circuit; The refresh management refresh operation is performed in response to an external refresh management signal and the action burst flag. as well as Skip the refresh management refresh operation when the burst flag is not active.

12. The method of claim 11, wherein the FIFO circuit includes a high-pass filter having a cutoff frequency, wherein the refresh management refresh operation is skipped when the plurality of row addresses are each received at a frequency lower than the cutoff frequency.

13. The method of claim 12, wherein the frequency is equal to or greater than the cutoff frequency when the row address of the plurality of row addresses matches at least one of a plurality of previously received row addresses stored in the plurality of registers.

14. The method of claim 11, wherein the external refresh management signal is provided at least in part in response to receiving a plurality of access requests at the memory.

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