Layer error rate difference-aware intra-block page wear leveling control method and system
By analyzing the chip characteristics in a 3D NAND Flash storage device and setting an intermediate threshold k, pages with high error rates are released, which solves the problem of unbalanced wear of pages within the block and extends the service life of the block and the device.
CN114168492BActive Publication Date: 2025-03-18WUHAN UNIV OF TECH
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Patent Information
- Application Number
- CN202111510344.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-12-10
- Publication Date
- 2025-03-18
- Estimated Expiration
- 2041-12-10
AI Technical Summary
Technical Problem
In 3D NAND Flash storage devices, due to the difference in bit error rates between layers, the page wear in the block is uneven, thus shortening the service life of the block.
Method used
By analyzing the characteristics of the 3D NAND Flash chip, the parameters are adjusted to determine an intermediate threshold k, which is used to determine whether the error rate of the page exceeds the threshold. If it exceeds the current page, it will release it, thereby achieving balance of page wear within the block.
Benefits of technology
Extend block life, reduce the chance of block damage, and enable the device to provide its full capacity for longer periods of time, thus extending the device's service life.
✦ Generated by Eureka AI based on patent content.
Abstract
A layer error rate difference-aware intra-block page wear leveling control method includes the following steps: S1, analyzing the characteristics of a 3D NAND Flash chip to obtain a first parameter; S2, adjusting the first parameter to obtain a second parameter k with the goal of achieving the optimal effect of intra-block page wear leveling control, wherein the second parameter k is an intermediate threshold value less than the maximum page error amount K that can be processed per page; S3, when it is necessary to program a page in a flash memory block, judging whether to program the current page according to the second parameter k, and releasing the current page if the error rate of the current page is greater than k. That is, the second parameter k is used to periodically release weak pages, so that the intra-block page wear is leveled.
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