Systems and methods involving hardware-based memory reset to avoid unresponsive memory

Abstract

Systems and methods of exposing memory operations provide for hardware-based reset of unresponsive memory devices. In one embodiment, an exemplary system can include a semiconductor memory device having a memory array, a controller that can include firmware components for controlling memory operations, and a reset circuit that includes power-on circuitry and timeout circuitry. The reset circuit can be configured to detect when the memory device is in an unresponsive state, and to reset the memory device without using any internal controller components that can be impacted by the unresponsive state.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application Serial No. 16 / 543,271, filed August 16, 2019, entitled “Systems and methods relating to hardware-based reset of unresponse memory devices,” the entire disclosure of which is hereby incorporated by reference. Technical Field

[0003] This disclosure generally relates to semiconductor memories, and more specifically, to systems and methods for implementing hardware-based resets of memory devices that have become unresponsive. Background Technology

[0004] Integrated circuit devices are found throughout a wide range of electronic devices, including memory devices, which are often simply referred to as memory. Memory devices are typically provided as internal semiconductor integrated circuit devices in computers or other electronic devices. There are many different types of memory, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has evolved into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. The data state (e.g., data value) of each memory cell is determined by changes in the threshold voltage (Vt) of the memory cell, programmed through charge storage structures (e.g., floating gates or charge traps) or other physical phenomena (e.g., phase transitions or polarization). Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory, so named because of the logical arrangement of its basic memory cell configuration. Typically, the memory cell arrays used for NAND flash memory are arranged such that the control gates of each memory cell in a row of the array are connected together to form an access line, such as a word line. Columns in the array contain strings of memory cells (often called NAND strings) connected in series between a pair of select gates, such as between a source select transistor and a drain select transistor.

[0007] Furthermore, current NAND memory devices offer various methods to reset the memory if it becomes unresponsive. For example, certain commands can be used to reset the entire memory device, but these commands are typically handled by the memory control circuitry and / or firmware controller, which is also used in memory operation. In contrast to the entire memory device, other techniques are provided to reset erase or program operations, but these techniques usually require internal control circuitry and / or firmware. These techniques are unavailable if the control circuitry and / or firmware controller that handles the reset command also becomes unresponsive, which may be accompanied by low voltage, illegal sequences, etc. Therefore, when a memory device becomes unresponsive in this way, the user may have no recourse, as powering off is not an option in actual system and operation. Updating memory designs to avoid such defects is also a challenge, as adding another dedicated pin to perform this reset independently of the control circuitry and firmware is not feasible due to the cost and complexity of adding extra pins to the package.

[0008] The disclosed embodiments provide technical solutions to improve upon the above-mentioned deficiencies and / or otherwise compensate for or overcome the above and other shortcomings of existing semiconductor memories. Summary of the Invention

[0009] On one hand, this disclosure provides a reset circuit for a memory device, the reset circuit comprising: a controller having a first output configured to remain in a first logic state in response to the memory device being in an unresponsive state; a write protection (WP) pin external to the memory device and set to a second logic state when the memory device is controlled to not perform a write operation; and a timeout circuit coupled to the first output and the WP pin and configured to generate a reset signal to reset the memory device when the first output and the WP pin are respectively held in the first logic state and the second logic state for a predetermined duration.

[0010] On the other hand, this disclosure provides a method for resetting a memory device, the method comprising: setting a first output of a controller to a first logic state in response to the memory device being in an unresponsive state; setting a write protection (WP) pin external to the memory device to a second logic state when the memory device is controlled to not perform a write operation; and generating a reset signal to reset the memory device by means of a timeout circuit coupled to the first output and the WP pin when the first output and the WP pin are respectively held continuously in the first logic state and the second logic state for a predetermined duration. Attached Figure Description

[0011] The foregoing and other objects, features, and advantages of this disclosure will become apparent from the following description of the embodiments illustrated in the accompanying drawings, wherein reference numerals refer to the same parts throughout the various views. The drawings are not necessarily drawn to scale and are intended to illustrate the principles of this disclosure.

[0012] Figure 1 This is a simplified block diagram of a memory device communicating with a processor according to some embodiments of the present disclosure.

[0013] Figure 2 This is a simplified diagram illustrating an exemplary memory device package and associated pin assignments according to some embodiments of the present disclosure.

[0014] Figure 3 This is a block diagram illustrating an exemplary reset and memory control circuitry system according to some embodiments of the present disclosure.

[0015] Figure 4 It is a general waveform that illustrates the behavior of a timeout reset circuit system and associated delays according to some embodiments of the present disclosure. Detailed Implementation

[0016] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention and illustrate specific embodiments. Throughout the drawings, similar reference numerals describe substantially similar components. Other embodiments may be utilized without departing from the scope of this disclosure, and structural, logical, and electrical changes may be made. Therefore, the following detailed description should not be considered limiting.

[0017] For example, as used herein, the term "semiconductor" may refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior processing steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0018] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0019] Various embodiments will be discussed using examples of NAND memory devices. However, it should be understood that the concepts disclosed herein can also be applied to other forms of semiconductor memory.

[0020] As explained in more detail below, systems and methods for memory operation provide hardware-based reset of unresponsive memory devices. In one embodiment, an exemplary system may include: a semiconductor memory device having a memory array; a controller that may include firmware components for controlling memory operation; and a reset circuitry system that includes a specific timeout circuit. The reset circuitry system may be configured to detect when the memory device is in an unresponsive state and reset the memory device without using any internal controller components that may be impacted / affected by the unresponsive state. The timeout circuitry may be configured with a timeout delay value based on parameters and conditions specific to the memory device. Once enabled, the timeout circuitry can reset the entire memory device without requiring either the internal memory control circuitry system or the memory's firmware controller—i.e., components that may or could become unresponsive—to process the associated reset command.

[0021] Figure 1This is a simplified block diagram illustrating communication between a first device in the form of a memory (e.g., a memory device) 100, as described in an embodiment, and a second device in the form of a processor 130, which is part of a third device in the form of an electronic system. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, cellular phones, etc. For example, the processor 130 of a controller external to the memory device 100 may be a memory controller or other external host device.

[0022] Memory device 100 includes an array 104 of memory cells logically arranged in rows and columns. Memory cells in a logical row are typically connected to the same access line (collectively referred to as a word line), while memory cells in a logical column are typically selectively connected to the same data line (collectively referred to as a bit line). A single access line may be associated with memory cells in more than one logical row, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed as one of at least two data states.

[0023] Row decoding circuitry 108 and column decoding circuitry 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 to manage command, address, and data inputs to and outputs data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands. Count register 126 may communicate with control logic 116 to store count data, such as data representing the corresponding read cycle number for different portions of memory cell array 104. Although depicted as a separate storage register, count register 126 may represent a portion of memory cell array 104.

[0024] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to commands and generates status information for external processor 130. Specifically, control logic 116 is configured to perform access operations (e.g., read operations, programming operations, and / or erase operations) according to the embodiments described herein. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control them in response to addresses.

[0025] Control logic 116 also communicates with cache register 118. Cache register 118, guided by control logic 116, latches incoming or outgoing data to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data is transferred from cache register 118 to data register 120 for transfer to memory cell array 104; subsequently, new data from I / O control circuitry 112 is latched in cache register 118. During read operations, data is transferred from cache register 118 to I / O control circuitry 112 for output to external processor 130; subsequently, new data is transferred from data register 120 to cache register 118. Status register 122 communicates with I / O control circuitry 112 and control logic 116 to latch status information for output to processor 130.

[0026] Memory device 100 receives control signals from processor 130 at control logic 116 via control link 132. These control signals may include Chip Enable (CE#), Command Latch Enable (CLE), Address Latch Enable (ALE), Write Enable (WE#), Read Enable (RE#), and Write Protection (WP#) 133. Memory device 100 may also generate output signals, such as Ready / Busy (R / B#) 135. The control signals and output signals may be applied to or presented on designated pins of the memory package, as further described below. Figure 2 As shown. Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via multiplexed input / output (I / O) bus 134, and outputs data to the processor 130 via I / O bus 134.

[0027] For example, commands are received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and written to the command register 124. Addresses are received via the input / output (I / O) pins [7:0] of the I / O bus 134 at I / O control circuitry system 112, and written to the address register 114. Data is received via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices at I / O control circuitry system 112, and written to the cache register 118. The data is then written to the data register 120 to program the memory cell array 104. In another embodiment, the cache register 118 may be omitted, and data may be written directly to the data register 120. Data is also output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices.

[0028] Those skilled in the art will understand that additional circuitry and signals can be provided and the process has been simplified. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0029] In addition, although specific I / O pins are described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations, numbers, and / or specific I / O pins may be used in various embodiments.

[0030] Figure 2 This is a simplified diagram illustrating an exemplary memory device package and associated pin assignments according to some embodiments of the present disclosure. Reference Figure 2 This is a top view showing an exemplary pin assignment for a memory device package, illustrating some of the input and output pins of the memory device. For example, Figure 2The pin assignments shown are for Vcc, Vss, CLE (Command Latch Enable), ALE (Address Latch Enable), WE# (Write Enable), WP# (Write Protection) 133, R / B# (Ready / Busy) 135, and various NC (Not Involved), DNU (Not Used) pins, as well as other pins. As described in more detail below, the embodiments described herein may reuse the write protection WP# pin to provide a mechanism for resetting the entire memory device, i.e., if the entire device becomes unresponsive. Furthermore, some embodiments may utilize the duration of a low signal on the Ready / Busy output or pin to calculate a timeout delay value used by timeout circuitry to reset the memory device.

[0031] Figure 3 This is a block diagram illustrating an exemplary reset and memory control circuitry system according to some embodiments of the present disclosure. The embodiments of the disclosed technology involve... Figure 3 The illustrative circuit system may include a first logic circuit 310, a timeout circuit 315, a power-on circuit, a second logic circuit, and a controller 335, wherein the controller may be a control circuit system, control logic 116, firmware controller, etc. (See reference) Figure 3 The signals being processed may include a write protection signal 305 from write protection pin 133, a (reset) input from timeout circuit 310, an output 317 from timeout circuit 315, an output 322 from power-on circuit 320, an output (global reset signal 330) from second logic circuit 325 (which may be low (e.g., Lowvcc) or high (e.g., Vcc), and an output from controller 335, which may be a busy signal 340 from controller 335, such as a ready / busy signal RB#.

[0032] refer to Figure 3In the example embodiment shown, the busy signal 340, provided as an output of controller 335, is fed back in the loop to be provided, along with the write protection signal 305, as part of a control signal for enabling a timeout circuit via its reset input 310. Here, when write protection is held low and busy signal 340 is also high, timeout circuit 315 can be enabled, for example, via first logic circuit 310, thereby indicating that the memory device is unresponsive. As shown, this logic can be implanted using an OR gate, but various other logics can be utilized. A further advantage of this example embodiment is that it allows the write protection WP# pin and function to continue to be used for their original purpose without triggering the hardware reset disclosed herein. Here, for example, a normal abort of programming and erasing operations will cause busy signal 340 to switch back to a low state and reset timeout circuit 315. Conversely, the special hardware reset described herein occurs only if the memory device remains unresponsive (i.e., the busy signal 340 is high) after the write protection 305 has been kept low and the busy signal 340 has been kept high for a duration exceeding the full timeout delay value or "fixed delay" calculated for the use of the timeout circuit 315.

[0033] In some embodiments, the timeout delay value may be calculated based on the greater of: (i) the time required to keep the write protection signal low to reset the erase / program operation, i.e., when the memory becomes unresponsive during erase or program; and (ii) the worst-case time required for the busy signal to be high, i.e., the worst-case time for the memory device to be busy, indicating that it is in an unresponsive state. Regarding the first time (i), the embodiments herein may determine for the memory device the first time to keep the write protection signal low during an erase or program operation to perform this reset. The time required to perform this reset operation (often referred to as tRST) may be provided in the datasheet of a given memory device, for example, as a tRST specification. Here, for example, if the memory device becomes unresponsive during erase or program, a reset is performed by keeping the write protection signal active (e.g., low) for a period longer than this reset time tRST to see if the memory device's busy signal transitions from a busy or unresponsive state to a ready state. Regarding the second time (ii), the embodiments described herein may also set the timeout delay value to be equal to or just higher than the second time during which the busy signal remains high, if this second time is greater than the first time (i). Here, for example, this second time may be established by determining the worst-case busy high time for any memory operation of the memory device. Furthermore, the reset circuitry may consider adding a margin to the second time. Thus, by comparing these two times and using the larger of the two, the timeout circuitry is not triggered until after the worst-case time period has elapsed. Therefore, subsequently, if the write protection signal remains low throughout the entire worst-case time delay value, the reset circuitry is configured to provide a reset signal to transition the control circuitry and / or the memory device from an unresponsive state. The following is in conjunction with... Figure 4 This document further demonstrates and describes the operations involving this timeout delay value or fixed delay. Additional conditions related to hardware reset can also be added as part of triggering the timeout delay. For example, a hardware reset could depend on things such as NAND initialization failure, a certain number of failed NAND programming / erase operations, etc.

[0034] Figure 4 This is a general waveform illustrating the behavior of a timeout reset circuit system and associated delays according to some embodiments of this disclosure. (Reference) Figure 4 The above text is combined with Figure 3 The example waveforms corresponding to the busy signal 340, write protection signal 305, and global reset signal 330 are illustrated. For example... Figure 4As shown, when the busy signal 340 goes high when the memory device enters an unresponsive state, the memory can initially operate normally with the global reset signal 330 high (Vcc) and write protection 305 off (high). Subsequently, the write protection signal 305 can be switched to active (low), which can be applied for a customary period of time tRST sufficient to reset an unresponsive erase or programming operation. However, once the write protection signal 305 is held for both the initial reset attempt period tRST and the full duration of the fixed delay 405 ('timeout delay value'), a reset consistent with the disclosed technique can then be provided, for example, by activating the global reset signal 330 provided to reset the memory. This resets the memory circuitry and memory device at 410, resulting in a hardware-based timeout reset. At 415, after power-off and associated reset of the memory circuitry are complete, the global reset signal 330 to the memory circuitry is returned to high (Vcc) and the busy signal returns to low (ready) state. Therefore, the hardware reset described herein can be configured to occur only if the memory device remains unresponsive after the write protection has been held low and the ready / busy signal has been held low for a duration exceeding the timeout delay 405. Thus, the embodiments described herein can reuse existing circuitry and pins, such as existing write protection pins, and combine this use with the disclosed reset and timeout circuitry to provide the ability to reset an unresponsive memory device without requiring access to or processing of circuit components that may be inactive (unresponsive) due to the memory device's unresponsive state.

[0035] Furthermore, the subject matter disclosed above can be implemented in many different forms, and therefore the covered or claimed subject matter is intended to be understood as not being limited to any of the exemplary embodiments set forth herein; exemplary embodiments are provided merely for illustration. Likewise, a reasonably broad scope is intended for the claimed or covered subject matter. Among other things, the subject matter may be embodied as a method, apparatus, component, or system, for example. Therefore, embodiments may take the form of, for example, hardware, software, firmware, or any combination thereof (other than software itself). Thus, the following detailed description is not intended to be restrictive.

[0036] Throughout the specification and claims, terms may have nuanced meanings as presented or implied in the context, in addition to their expressly stated meanings. Similarly, the phrase "in one embodiment" as used herein does not necessarily refer to the same embodiment, and the phrase "in another embodiment" as used herein does not necessarily refer to different embodiments. For example, the claimed subject matter is intended to encompass combinations of all or part of exemplary embodiments.

[0037] Generally, terms can be understood at least partially based on their use in context. For example, terms such as “and,” “or,” or “and / or” as used herein can have a variety of meanings, which can depend at least in part on the context in which such terms are used. Typically, “or,” when used with an associative list (e.g., A, B, or C), is intended to mean A, B, and C, used here in an inclusive sense, and A, B, or C, used here in an exclusive sense. Additionally, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least in part on the context, terms such as “a (a / an)” or “described” can also be understood to convey either singular or plural usage. Furthermore, the term “based on” can be understood to not necessarily be intended to convey a set of exclusive factors, and conversely, can depend at least in part on the context allowing for the presence of other factors that are not necessarily explicitly described.

[0038] Those skilled in the art will recognize that the methods and apparatus of this disclosure can be implemented in many ways and are therefore not limited to the exemplary embodiments and examples described above. In other words, aspects / elements can be implemented by single or multiple components in various combinations and / or sub-combinations, and aspects can be distributed among components and / or sub-components. In this regard, any number of features of the different embodiments described herein can be combined into single or multiple embodiments, and alternative embodiments having fewer or more features than all those described herein are possible.

[0039] While various embodiments have been described for the purposes of this disclosure, such embodiments should not be construed as limiting the teachings of this disclosure to those embodiments. Various changes and modifications may be made to the above elements and features to obtain results that remain within the scope of the systems and processes described in this disclosure.

Claims

1. A reset circuit for a memory device, the reset circuit comprising: A controller having a first output configured to remain in a first logic state in response to the memory device being in an unresponsive state; The write-protect WP pin is external to the memory device and is set to a second logic state when the memory device is controlled to not perform write operations. and A timeout circuit, coupled to the first output and the WP pin, is configured to generate a reset signal to reset the memory device when the first output and the WP pin are held continuously for a period longer than a predetermined duration in both the first logic state and the second logic state.

2. The reset circuit of claim 1, wherein the timeout circuit is coupled to the first output and the WP pin via an OR gate, wherein the first output and the WP pin provide inputs to the OR gate, and the input of the timeout circuit receives the output from the OR gate.

3. The reset circuit according to claim 2, wherein the first logic state is logic "1" and the second logic state is logic "0".

4. The reset circuit of claim 1, wherein the reset signal is provided to the controller to switch the first output to a third logic state that is logically opposite to the first logic state, the third logic state indicating that the memory device has exited the unresponsive state.

5. The reset circuit of claim 1, wherein the predetermined duration is longer than the erase or program reset time of the memory device.

6. The reset circuit of claim 1, wherein the predetermined duration is longer than the worst-case no-response time of any memory operation of the memory device.

7. The reset circuit of claim 1, further comprising a power-on circuit configured to provide a power-on signal in response to a power-on operation, the power-on signal preventing the generation of the reset signal.

8. The reset circuit of claim 7, further comprising an OR gate configured to receive the energizing signal and the output of the timeout circuit as inputs, and to output the reset signal.

9. A method for resetting a memory device, the method comprising: In response to the memory device being in an unresponsive state, the first output of the controller is set to a first logic state; When the memory device is controlled to not perform a write operation, the write protection WP pin outside the memory device is set to the second logic state; and When the first output and the WP pin are held continuously in the first logic state and the second logic state for a period of time longer than a predetermined duration, a reset signal is generated by a timeout circuit coupled to the first output and the WP pin to reset the memory device.

10. The method of claim 9, further comprising: The reset signal is used to switch the first output of the controller to a third logical state that is logically opposite to the first logical state, the third logical state indicating that the memory device has exited the unresponsive state.

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