A method for accelerating processing of a video compression card based on a RISC-V processor

Abstract

The present invention relates to an acceleration processing method for a video compression card based on a RISC-V processor, and belongs to the technical field of video compression card software compression research. The method performs the following steps: 1) collected image information; 2) completing AVS format encoding of the image information; 3) using the RISC-V processor and the coprocessor to interact to complete the zig-zag scanning and run-length encoding of the image information in step 2); 4) completing AVS format entropy encoding of the image information that has completed the zig-zag scanning and run-length encoding in step 3); 5) completing AVS video compression; the coprocessor participates in completing the execution, memory access and write-back functions of the RISC-V processor through coprocessor instructions. The present invention utilizes the characteristic of RISC-V itself that it has easy-to-expand instructions, generates specific coprocessor instructions for zig-zag scanning and run-length encoding at the compiler level, and adds them to traditional CPU instructions.

Description

Technical Field

[0001] The invention relates to an acceleration processing method of a video compression card based on a RISC-V processor, and belongs to the technical field of research on software compression of video compression cards. Background Art

[0002] Traditional processors mainly refer to the two major camps of Intel and ARM. In traditional fields such as PCs and servers, Intel processors have an absolute monopoly position. In mobile platforms and embedded fields, ARM is in a core position and has a very high market share.

[0003] As international competition becomes increasingly fierce, various industries are increasingly demanding domestic processors. RISC-V is pronounced RISC Five, which means the fifth generation of reduced instruction set processors. It is a new instruction set architecture, and it is open source and can be freely used by any academic institution or commercial organization, with the advantage of being self-controlled.

[0004] Most of the standards currently used in the market are MPEG and H.264. More and more products are restricted by patents and have become bombs in the field of video surveillance. The AVS-s standard is a video compression standard with completely independent intellectual property rights in my country. Therefore, the video compression method using the RISC-V+AVS-s combination has the characteristics of complete autonomy and controllability, and is becoming more and more popular, especially in areas with high security requirements, such as national defense, aerospace and other fields.

[0005] Now RISC-V processors are increasingly used as dedicated processors in the field of video surveillance, and software-based video compression cards are now the mainstream application because they are cheap and do not require additional video compression chip overhead (compared to hardware compression cards). However, the use of RISC-V software compression depends entirely on the performance of the CPU and the algorithm optimization of the compression software. The 8x8 quantized residual coefficients are zig-zag scanned, and then the scanned data is run-length encoded to obtain a (run, level) array, where run represents the number of zeros before the non-zero coefficients, and level represents the value of the non-zero coefficients. Because this part will calculate the position of 64 data (8*8 matrix), and then determine the scanning direction, and perform non-zero counting at the same time, it consumes more CPU resources and clock cycles. In the field of surveillance with increasingly higher requirements for clarity, the demand for accelerated software compression is also increasing. Summary of the invention

[0006] The technical problem to be solved by the present invention is to provide an acceleration processing method for a video compression card based on a RISC-V processor.

[0007] In order to solve the above technical problems, the technical solution proposed by the present invention is: an acceleration processing method of a video compression card based on a RISC-V processor, performing the following steps:

[0008] 1) The collected image information;

[0009] 2) Complete AVS format encoding of the image information;

[0010] 3) Use the RISC-V processor and coprocessor to interact and complete the zig-zag scanning and run-length encoding of the image information in step 2);

[0011] 4) Perform AVS format entropy coding on the image information that has completed zig-zag scanning and run-length coding in step 3);

[0012] 5) Complete AVS video compression;

[0013] The coprocessor participates in completing the execution, memory access and write-back functions of the RISC-V processor through coprocessor instructions.

[0014] A further improvement of the above scheme is that: the coprocessor instructions include a SETUP instruction, a DATA_PRC instruction, a RDFLAG instruction and a RDDATA instruction;

[0015] The SETUP instruction is used to obtain the first address of the data to be processed in the memory and set the target register 1 to 0;

[0016] The DATA_PRC instruction is used to process the data to be processed and indicate whether the processing is completed through the target register 1;

[0017] The RDFLAG instruction is used to read the value of the target register 1 to determine whether the zig-zag scan and run-length encoding are completed;

[0018] The RDDATA instruction is used to read the value of target register 2 or target register 3, obtain the first address and number of processing results in the memory, and set the value of target register 1 to 0.

[0019] A further improvement of the above solution is that the coprocessor reads N2 filtered data to the coprocessor according to the filter size N and the first address of the N2 data to be filtered in the LSU storage unit.

[0020] The beneficial effect of the present invention is: utilizing the characteristic of RISC-V itself that it has easily expandable instructions, generating specific instructions for the coprocessor for zig-zag scanning and run-length encoding at the compiler level, and adding them to traditional CPU instructions.

[0021] At the same time, the coprocessor has a non-zero detection function, which can greatly speed up the video compression processing speed and meet the requirements of real-time compression processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a flow chart of an acceleration processing method of a video compression card based on a RISC-V processor according to an embodiment of the present invention.

[0023] Figure 2 It is an example diagram of zig-zag scanning and run-length encoding according to an embodiment of the present invention. DETAILED DESCRIPTION Example

[0024] The present embodiment is a method for accelerating the processing of a video compression card based on a RISC-V processor, such as Figure 1 As shown, perform the following steps:

[0025] 1) The collected image information;

[0026] 2) Complete AVS format encoding of image information;

[0027] 3) Use the RISC-V processor and coprocessor to interact and complete the zig-zag scanning and run-length encoding of the image information in step 2);

[0028] 4) Perform AVS format entropy coding on the image information that has completed zig-zag scanning and run-length coding in step 3);

[0029] 5) Complete AVS video compression;

[0030] The coprocessor participates in the execution, memory access, and write-back functions of the RISC-V processor through coprocessor instructions.

[0031] The coprocessor reads N2 filtered data to the coprocessor according to the filter size N and the first address of the N2 data to be filtered in the LSU storage unit.

[0032] Coprocessor instructions include SETUP instruction, DATA_PRC instruction, RDFLAG instruction and RDDATA instruction;

[0033] The SETUP instruction is used to obtain the first address of the data to be processed in the memory and set the target register 1 to 0;

[0034] DATA_PRC instruction, used to process the data to be processed and indicate whether the processing is completed through the destination register 1;

[0035] RDFLAG instruction is used to read the value of destination register 1 to determine whether zig-zag scanning and run-length encoding are completed;

[0036] The RDDATA instruction is used to read the value of target register 2 or target register 3, obtain the first address and number of processing results in the memory, and set the value of target register 1 to 0.

[0037] The interface between the coprocessor and the EXU, LSU, and WB units in this embodiment is a ROCC (Rocket Custom Coprocessor) interface (taking the Rocket RISC-V core as an example). Among them, EXU is the execution unit inside the CPU (RISC-V processor), WB is the write-back unit, and LSU is the storage unit.

[0038] 1. After the software program is compiled, a SETUP instruction is generated, which stores the 8x8 residual data at the first address of the LSU storage unit and sets the value of the target register 1 to 0.

[0039] 2. The coprocessor reads N^2 filtered data to the coprocessor according to the filter size N and the first address of the N^2 data to be filtered in the LSU storage unit.

[0040] 3. Then run the DATA_PRC instruction to perform zig-zag scanning and run-length encoding on the 8x8 data read from the coprocessor. Figure 2 For example ( Figure 2 The numbers in the brackets indicate the order in which 8x8 data is input from the memory to the coprocessor, and the arrows in the figure represent the zig-zag scanning order) as follows:

[0041] 3.1 The data first passes through the non-zero data detection module, whose function is to detect each 8x8 data and obtain the total number of non-zero data NO_ZERO_CNT in the current 8x8 group.

[0042] 3.2 The data passes through the position calculation module, which outputs the value of the non-zero data and the position in the 8x8 matrix, where the position refers to the count when input by row, that is, Figure 2 The value in the brackets. The output format is (data, pos). Figure 2 For example, the output is (3, 0) (2, 1) (1, 2) (11, 4) (11, 8) (5, 9) (7, 10) (12, 12)

[0043] (4, 15)(2, 17)(4, 18)(12, 21)(9, 22)(6, 25)(8, 26)

[0044] (5, 27) (7, 29) (5, 33) (11, 34) (11, 35) (5, 36) (12, 41) (11, 48) (12, 50) (6, 51) (2, 57) (13, 58)

[0045] 3.3: The position analysis module outputs the final run-length encoding array based on the output results of the position calculation module.

[0046] The process is as follows: the module follows the zig-zag scanning order, that is, according to Figure 2 Analyze the output of POS_CUL according to the direction of the arrow in

[0047] 0,1,8,16,9,2,3,10,17,24,32,25,18,11,4,5,

[0048] 12, 19, 26, 33, 40, 48, 41, 34, 27, 20, 13, 6, 7, 14, 21, 28,

[0049] 35, 42, 49, 56, 57, 50, 43, 36, 29, 22, 15, 23, 30, 37, 44, 51,

[0050] 58, 59, 52, 45, 38, 31, 39, 46, 53, 60, 61, 54, 47, 55, 62, 63

[0051] The output results of the position calculation module are traversed in the order of (the pos position of the result),

[0052] The process is,

[0053] Counter mid_zero_cnt=0, first find out if there is non-zero data at pos=0,

[0054] If pos=0 in the output result of the position calculation module and there is a non-zero value, then (mid_zero_cnt, non-zero value) is directly output, and mid_zero_cnt is set to 0.

[0055] If pos=0 in the output result of the position calculation module and there is no non-zero value, no output will be given and mid_zero_cnt=mid_zero_cnt+1.

[0056] Continue to look for non-zero data at pos=1

[0057] If the output result of the position calculation module contains pos=1 and there is a non-zero value, then the output is

[0058] (mid_zero_cnt, non-zero value), and mid_zero_cnt is set to 0.

[0059] If pos=1 in the output result of the position calculation module and there is no non-zero value, no output will be given and mid_zero_cnt=mid_zero_cnt+1.

[0060] Continue to look for non-zero data at pos=8

[0061] If the output result of the position calculation module contains pos=1 and there is a non-zero value, then the output is

[0062] (mid_zero_cnt, non-zero value), and mid_zero_cnt is set to 0.

[0063] If pos=1 in the output result of the position calculation module and there is no non-zero value, no output will be given and mid_zero_cnt=mid_zero_cnt+1.

[0064] And so on, until the scan is completed. Also note that during the scan process of this step, the number of non-zero values ​​that have been scanned will be counted, NO_ZERO_END_SCAN_CNT. When NO_ZERO_END_SCAN_CN=NO_ZERO_CNT (the output value of the ZERO_DET module), the current scan is stopped to speed up the processing. After the scan is completed, the target register 1 is set to 1. At the same time, after obtaining the non-zero value, the obtained (mid_zero_cnt, non-zero value) is directly written to the storage space of the storage start address specified by the target register 2. In this way, when the scan is completed, the write-back of (mid_zero_cnt, non-zero value) is completed, and the value of NO_ZERO_CNT is written to the target register 3.

[0065] 4: Then run the RDFLAG instruction to read the value of the target register 1.

[0066] 4.1 If the value is 1, it means that during the execution of DATA_PRC, the zig-zag scan and run-length encoding of the 8x8 residual data have been completed. Then execute the MIDRD instruction and execute step 5.

[0067] 4.2 If the value is 0, it means that DATA_PRC has not completed the zig-zag scanning and run-length encoding of the 8x8 residual data. Next, continue to execute the RDFLAG instruction and return to step 4.

[0068] 5: Run the RDDATA instruction, which sets the value of the target register to 0 and reads the values ​​of target registers 2 and 3 at the same time. In this way, the software obtains the results of zig-zag scanning and run-length encoding of the current 8x8 residual data. The software can continue with the next process, and the coprocessor waits for the input of the next set of 8x8 residual data.

[0069] The image information acquisition of this embodiment is completed by a camera, which can be a conventional field requiring video surveillance, or a field such as aviation and national defense. For the parts before entropy coding specified in the AVS protocol, such as intra-frame prediction, inter-frame prediction, quantization, motion compensation, loop filtering, etc., they are all implemented by software (the software runs on a RISC-V processor). The zig-zag code scanning and run-length coding in the AVS entropy coding are designed into the format of an instruction set using the method of this proposal and implemented by a coprocessor. The entropy coding after the zig-zag code scanning is still implemented by software running on a RISC-V processor.

[0070] The present invention is not limited to the specific technical solutions described in the above embodiments. In addition to the above embodiments, the present invention may also have other implementation modes. For those skilled in the art, any technical solutions formed by any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for accelerating processing of a video compression card based on a RISC-V processor, characterized in that: Follow these steps: 1) The collected image information; 2) Complete AVS format encoding of the image information; 3) Use the RISC-V processor and coprocessor to interact and complete the zig-zag scanning and run-length encoding of the image information in step 2); 4) Perform AVS format entropy coding on the image information that has completed zig-zag scanning and run-length coding in step 3); 5) Complete AVS video compression; The coprocessor participates in completing the execution, memory access and write-back functions of the RISC-V processor through coprocessor instructions; The coprocessor instructions include a SETUP instruction, a DATA_PRC instruction, an RDFLAG instruction and an RDDATA instruction; the SETUP instruction is used to obtain the first address of the data to be processed in the memory and set the target register 1 to 0; The DATA_PRC instruction is used to perform zig-zag scanning and run-length encoding processing on the 8x8 data read from the coprocessor and indicate whether the processing is completed through the target register 1; Specifically: The data first passes through the non-zero data detection module, which detects each 8x8 data and obtains the total number of non-zero data in the current 8x8 group, NO_ZERO_CNT; The data passes through the position calculation module, which outputs the value of the non-zero data and the position in the 8x8 matrix, where the position refers to the count when input in rows; as well as The position analysis module outputs the final run-length encoding array according to the output result of the position calculation module; The RDFLAG instruction is used to read the value of the target register 1 to determine whether the zig-zag scan and run-length encoding are completed; The RDDATA instruction is used to read the values ​​of target register 2 and target register 3, obtain the first address and number of the processing result memory, and set the value of target register 1 to 0; The target register 2 stores (mid_zero_cnt, non-zero value), and the target register 3 stores the value of NO_ZERO_CNT, wherein mid_zero_cnt is a counter.

2. The accelerated processing method of the video compression card based on the RISC-V processor according to claim 1, characterized in that: The coprocessor reads N^2 filtered data to the coprocessor according to the filter size N and the first address of the N^2 data to be filtered in the LSU storage unit.

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