Display substrate and display device

Abstract

The present disclosure provides a display substrate and a display device, belonging to the field of display technology. The display substrate includes a plurality of test circuit groups, each test circuit group includes a plurality of test circuits, and each test circuit is coupled to a data signal line and a data line lead, the data line lead is coupled to the data line, and the data line is further coupled to the pixel. Each test circuit can transmit the data signal provided by the data signal line to the data line through the data line lead to light up the pixel. Since the resistance value of the conductive film layer coupled to the data line lead in each test circuit is negatively correlated with the length of the data line lead, it is possible to effectively compensate for the resistance values ​​of data line leads of different lengths, so that the resistance values ​​on each data line lead are close. Furthermore, the uniformity of the data signal transmitted to each data line can be improved, and the uniformity of the luminous brightness of multiple pixels can be improved. In this way, the accuracy of the lighting test can be ensured to be better.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0002] Organic light-emitting diode (OLED) display substrates are widely used in various display devices due to their advantages such as low power consumption, fast response speed and wide viewing angle.

[0003] Currently, to ensure a good factory yield rate for OLED display substrates, multiple pixels in the OLED display substrate are subjected to a lighting test before the OLED display substrates are shipped to verify that the multiple pixels can emit light normally. Based on this, a panel test (CT) circuit is generally provided in the OLED display substrate. The CT circuit is coupled to multiple data lines via multiple data line leads, and the multiple data lines are coupled to multiple pixels. The CT circuit is used to transmit data signals to the multiple data lines via the multiple data line leads. The multiple data lines are used to further transmit the received data signals to the multiple pixels to illuminate the multiple pixels.

[0004] However, due to the arrangement, the lengths of the data lines vary, which means that the resistance values ​​of the data lines vary. This results in poor uniformity of the data signals transmitted to each data line, which in turn leads to poor uniformity of the luminance of multiple pixels, affecting the test accuracy of the lighting test. Summary of the Invention

[0005] The embodiments of the present disclosure provide a display substrate and a display device, which can solve the problem in the related art that the test accuracy of a lighting test is affected by the difference in resistance values ​​on the leads of each data line.

[0006] The technical solution is as follows:

[0007] In one aspect, a display substrate is provided, comprising:

[0008] a substrate having a display area and a non-display area at least partially surrounding the display area;

[0009] a plurality of pixels located in the display area;

[0010] a plurality of data lines, located in the display area and coupled to the plurality of pixels, and configured to provide data signals to the plurality of pixels;

[0011] a plurality of data line leads, located in the non-display area and coupled to the plurality of data lines;

[0012] At least one switch control line, a plurality of data signal lines, and a plurality of test circuit groups are located in the non-display area, each of the test circuit groups includes a plurality of test circuits, each of the test circuits has a multi-layer conductive film layer, and is coupled to one of the switch control line, one of the data signal line, and one of the data line lead lines through the multi-layer conductive film layers, and is used to transmit a data signal from the data signal line to the data line via the data line lead line in response to a switch control signal provided by the switch control line;

[0013] Among the multiple conductive film layers included in each of the test circuits, the resistance value of the target conductive film layer coupled to the data line lead is negatively correlated with the length of the data line lead.

[0014] Optionally, the length of the orthographic projection of the target conductive film layer on the substrate is negatively correlated with the length of the data line lead.

[0015] Optionally, the width of the orthographic projection of the target conductive film layer on the substrate is positively correlated with the length of the data line lead.

[0016] Optionally, the maximum width of the orthographic projection of the target conductive film layer on the substrate is positively correlated with the length of the data line lead.

[0017] Optionally, the multilayer conductive film layer includes: an active layer, a first gate metal layer and a first source / drain metal layer located on one side of the substrate;

[0018] The active layer is coupled to the first source-drain metal layer, the first source-drain metal layer is also coupled to the data signal line and the data line lead respectively, and the first gate metal layer is coupled to the switch control line;

[0019] The target conductive film layer includes: the active layer coupled to the data line lead through the first source / drain metal layer.

[0020] Optionally, the display substrate further includes: a second gate metal layer and a second source / drain metal layer;

[0021] The switch control line is located in the same layer as the first source-drain metal layer, the data signal line is located in the same layer as the first source-drain metal layer and the second source-drain metal layer, and the data line lead is located in the same layer as the first gate metal layer or the second gate metal layer.

[0022] Optionally, each pixel includes a plurality of sub-pixels of different colors, and each sub-pixel is coupled to a corresponding data line; and the number of test circuits included in each test circuit group, and the number of switch control lines and the number of data signal lines included in the display substrate are all the same as the number of sub-pixels included in each pixel;

[0023] Wherein, each test circuit included in each test circuit group is coupled to a different switch control line and to a different data signal line;

[0024] Furthermore, in each of the test circuit groups, the test circuits coupled to the data lines corresponding to sub-pixels of the same color share the same data signal line and are coupled to the same switch control line.

[0025] Optionally, each of the pixels includes: a red sub-pixel, a green sub-pixel, and a blue sub-pixel;

[0026] In each of the test circuit groups, the test circuit coupled to the data line corresponding to the red sub-pixel and the test circuit coupled to the data line corresponding to the blue sub-pixel share the same data line lead.

[0027] Optionally, each of the test circuits includes: a switching transistor;

[0028] The gate of the switch transistor is coupled to the switch control line, the first electrode of the switch transistor is coupled to the data signal line, and the second electrode of the switch transistor is coupled to the data line lead.

[0029] On the other hand, a display device is provided, comprising: a power supply component, and the display substrate according to the above aspect;

[0030] The power supply component is coupled to the display substrate and is used to supply power to the display substrate.

[0031] In summary, the technical solutions provided by the embodiments of the present disclosure have at least the following beneficial effects:

[0032] A display substrate and a display device are provided. The display substrate includes a plurality of test circuit groups, each test circuit group includes a plurality of test circuits, and each test circuit is respectively coupled to a data signal line and a data line lead, the data line lead is coupled to the data line, and the data line is further coupled to the pixel. Each test circuit can transmit the data signal provided by the data signal line to the data line through the data line lead to light up the pixel. Since the resistance value of the conductive film layer coupled to the data signal line in each test circuit is negatively correlated with the length of the data line lead, effective compensation for the resistance values ​​of data line leads of different lengths can be achieved, so that the resistance values ​​on each data line lead are close. Furthermore, the uniformity of the data signal transmitted to each data line can be improved, and the uniformity of the luminous brightness of multiple pixels can be improved. In this way, the accuracy of the lighting test can be ensured to be good. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0034] Figure 1 is a schematic structural diagram of a display substrate provided by an embodiment of the present disclosure;

[0035] Figure 2 This is a schematic diagram of the resistance distribution of each data line lead provided by an embodiment of the present disclosure;

[0036] Figure 3 is a schematic structural diagram of another display substrate provided by an embodiment of the present disclosure;

[0037] Figure 4 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0038] Figure 5 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0039] Figure 6 is a structural schematic diagram of another display substrate provided by an embodiment of the present disclosure;

[0040] Figure 7 This is a structural layout of a test circuit in a display substrate provided by an embodiment of the present disclosure;

[0041] Figure 8 This is another structural layout of a test circuit in a display substrate provided by an embodiment of the present disclosure;

[0042] Figure 9 This is another structural layout of a test circuit in a display substrate provided by an embodiment of the present disclosure;

[0043] Figure 10 This is a structural layout of a test circuit in another display substrate provided by an embodiment of the present disclosure;

[0044] Figure 11 is a schematic diagram of a display substrate including a test circuit structure layout provided by an embodiment of the present disclosure;

[0045] Figure 12 It is a structural schematic diagram of a display device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0046] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0047] The terms used in the embodiments of the present disclosure are intended only to explain the embodiments of the present disclosure and are not intended to limit the present disclosure. Unless otherwise defined, the technical or scientific terms used in the embodiments of the present disclosure should have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure belongs. For example, the terms "first," "second," or "third," and similar terms used in the embodiments of the present disclosure do not indicate any order, quantity, or importance, but are simply used to distinguish different components. Similarly, terms such as "one" or "a" do not indicate a quantitative limitation, but rather indicate the presence of at least one. Terms such as "include" or "comprising" mean that the elements or objects appearing before "include" or "comprising" include the elements or objects listed after "include" or "comprising" and their equivalents, and do not exclude other elements or objects. Terms such as "upper," "lower," "left," or "right" are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly. "Connected" or "coupled" refers to an electrical connection. "And / or" indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0048] Display devices using OLED display substrates have become a mainstream trend. The manufacturing of such display devices generally involves the sequential steps of substrate (panel, PNL) and module. The PNL stage primarily manufactures the display substrate, while the module stage primarily involves packaging the driver circuit and display substrate. The driver circuit refers to the circuit used to drive the display substrate for display.

[0049] Furthermore, in order to verify the production of the PNL segment, intercept defective display substrates manufactured by the PNL segment in advance, save module materials for the subsequent module segment, and clarify the material relationship between the PNL segment and the module segment, a CT circuit is usually used in the PNL segment to perform a lighting test on the pixels in the display substrate. In addition, in order to improve the utilization rate of the display substrate, the CT circuit is usually set at the fan-out position. That is, combined with Figure 1 The CT circuit is typically located in the lower center of the display substrate. The CT circuit couples to the data lines connected to the pixels on the display substrate via multiple data line leads to illuminate the pixels. For example, the pixels on the display substrate are typically arranged in an array, with multiple columns of pixels correspondingly coupled to multiple data lines, and multiple data line leads are then coupled to these multiple data lines in a one-to-one correspondence. During the lighting test, the CT circuit transmits consistent data signals to each data line lead, and theoretically, each pixel should emit the same brightness.

[0050] However, due to this arrangement, the lengths of the data line leads are different. Figure 1 When the CT circuit is located directly below the display substrate, the length of each data line gradually decreases as it approaches the center of the display substrate on both sides. The formula for calculating the resistance value R of a resistor is: "R = ρL / S; where ρ represents the resistivity, which is determined by the properties of the structure that constitutes the resistor (e.g., the data line lead); L represents the length of the structure that constitutes the resistor; and S represents the cross-sectional area of ​​the resistor." This shows that the length of the data line lead is positively correlated with the resistance value R. That is, the longer the data line lead, the greater the resistance; conversely, the shorter the data line lead, the smaller the resistance. Figure 2 The figure shows the resistance distribution of each data line lead to which each data line is coupled from the left side to the right side of the display substrate. The horizontal axis refers to the position of the data line lead, and the vertical axis refers to the size of the resistance value R, which can be in ohms (Ω). Figure 2 It can be seen that the resistance value of the data line lead coupled to the shortest data line in the middle of the display substrate is the smallest, and the resistance value of the data line lead coupled to the longest data line on both sides of the display substrate is the largest. The different resistance values ​​on the data line leads lead to different loading on each data line lead, which in turn leads to poor uniformity of the data signal transmitted to each data line, different luminance of each column of pixels, and uneven display brightness of the display substrate, resulting in Figure 1 The vertical defect (block mura) shown.

[0051] The embodiment of the present disclosure provides a display substrate, which does not have any resistance difference when performing a lighting test on the display substrate. Figure 1 The block mura shown has a high lighting test accuracy.

[0052] Figure 3 Schematic diagram of the structure of a display substrate provided by an embodiment of the present disclosure. Figure 3 As shown, the display substrate includes: a substrate 01 having a display area A1 and a non-display area B1 at least partially surrounding the display area A1. Figure 3 The non-display area B1 is shown as being located below the display area A1, adjacent to the display area A1, and partially surrounding the display area A1. Of course, the non-display area B1 is not limited to being located below the display area A1. For example, the non-display area B1 may also be located above the display area A1.

[0053] Continue to refer Figure 3The display substrate further includes: a plurality of pixels O2 and a plurality of data lines D0 located in the display area A1, and a plurality of data line leads D1, at least one switch control line SW1, a plurality of data signal lines D2, and a plurality of test circuit groups O3 located in the non-display area B1.

[0054] The plurality of data lines D0 are coupled to the plurality of pixels 02 and are used to provide data signals to the plurality of pixels 02. The plurality of data line leads D1 are coupled to the plurality of data lines D0. For example, referring to Figure 3 , multiple pixels 02 can be arranged in an array. Pixels 02 in the same column can be coupled to the same data line D0, and each data line lead D1 can be coupled to a corresponding data line D0. It should be noted that each pixel 02 can include multiple sub-pixels of different colors. Each sub-pixel can be coupled to a data line D0, and different sub-pixels can be coupled to different data lines D0. In other words, each pixel 02 is actually coupled to multiple data lines D0.

[0055] Each test circuit group 03 includes multiple test circuits 031. Each test circuit 031 has multiple conductive film layers (not shown) and is coupled to a switch control line SW1, a data signal line D2, and a data line lead D1 through the multiple conductive film layers. Each test circuit 031 is configured to transmit a data signal provided by a data signal line D2 to a data line D0 via a data line lead D1 in response to a switch control signal provided by the switch control line SW1. In other words, the data signals provided by the multiple data lines D0 to the multiple pixels 02 can originate from the data signal lines D2. Driven by these data signals, the multiple pixels 02 can emit light, thereby achieving a lighting test for the multiple pixels 02. The multiple test circuit groups 03 herein correspond to the CT circuits described in the above embodiment.

[0056] In each test circuit 031, the resistance R of the target conductive film layer coupled to the data line lead D1 is negatively correlated with the length of the data line lead D1. That is, the longer the data line lead D1, the lower the resistance R of the target conductive film layer; conversely, the shorter the data line lead D1, the higher the resistance R of the target conductive film layer. Thus, for a data line lead D1 with a longer length and a higher resistance R, the resistance R of the data line lead D1 can be compensated by reducing the resistance of the target conductive film layer in the test circuit 031 to which it is coupled. For a data line lead D1 with a shorter length and a lower resistance R, the resistance R of the data line lead D1 can be compensated by increasing the resistance of the target conductive film layer in the test circuit 031 to which it is coupled. This ultimately improves loading uniformity across data line leads D1 of varying lengths, ensuring more consistent data signals transmitted from each test circuit 031 to each data line D0 and more uniform luminance across each pixel 02. Furthermore, the test accuracy of the lighting test can be improved, so that the test precision is better.

[0057] In summary, an embodiment of the present disclosure provides a display substrate. The display substrate includes a plurality of test circuit groups, each test circuit group includes a plurality of test circuits, and each test circuit is respectively coupled to a data signal line and a data line lead, the data line lead is coupled to the data line, and the data line is further coupled to the pixel. Each test circuit can transmit the data signal provided by the data signal line to the data line through the data line lead to light up the pixel. Since the resistance value of the conductive film layer coupled to the data signal line in each test circuit is negatively correlated with the length of the data line lead, it is possible to effectively compensate for the resistance values ​​of data line leads of different lengths, so that the resistance values ​​on each data line lead are close. Furthermore, the uniformity of the data signals transmitted to each data line can be improved, and the uniformity of the luminous brightness of multiple pixels can be improved. In this way, the accuracy of the lighting test can be ensured to be better.

[0058] In combination with the above resistance formula, it can be seen that in the embodiment of the present disclosure, the resistance value of the target conductive film layer can be flexibly set by adjusting the length or width of the orthographic projection of the target conductive film layer on the substrate 01.

[0059] As an optional implementation, the length of the orthographic projection of the target conductive film layer of each test circuit 031 on the substrate 01 can be set to be negatively correlated with the length of the data line lead D1. That is, the longer the data line lead D1 is, the shorter the orthographic projection of the target conductive film layer on the substrate 01 is set; conversely, the shorter the data line lead D1 is, the longer the orthographic projection of the target conductive film layer on the substrate 01 is set.

[0060] Alternatively, as another optional implementation, the width of the orthographic projection of the target conductive film layer of each test circuit 031 on the substrate 01 can be set to be positively correlated with the length of the data line lead D1. That is, the longer the data line lead D1 is, the wider the orthographic projection of the target conductive film layer on the substrate 01 is set; conversely, the shorter the data line lead D1 is, the narrower the orthographic projection of the target conductive film layer on the substrate 01 is set.

[0061] Of course, in some other embodiments, the length and width of the orthographic projection of the target conductive film layer on the substrate 01 may also be adjusted simultaneously to achieve reliable compensation for the resistance value on the data line lead D1.

[0062] Optionally, in the disclosed embodiment, the maximum width of the orthographic projection of the target conductive film layer on substrate 01 may be positively correlated with the length of the data line lead D1. For example, the orthographic projections of the various segments of the target conductive film layer on substrate 01 may have uneven widths, with the width of the widest segment positively correlated with the length of the data line lead D1. Of course, in other embodiments, the average width of the orthographic projection of the target conductive film layer on substrate 01 may be positively correlated with the length of the data line lead D1. Alternatively, the orthographic projections of the various segments of the target conductive film layer on substrate 01 may have uniform widths.

[0063] Optionally, in the disclosed embodiment, as described in the above embodiment, each pixel O2 may include multiple sub-pixels of different colors. On this basis, each sub-pixel may be coupled to a corresponding data line D0. Multiple sub-pixels in the display substrate may be arranged in an array, and sub-pixels in the same column may share the same data line D0. That is, they are coupled to the same data line D0.

[0064] The number of test circuits 031 included in each test circuit group 03, as well as the number of switch control lines SW1 and data signal lines D2 included in the display substrate, can be the same as the number of sub-pixels included in each pixel 02. Furthermore, each test circuit 031 included in each test circuit group 03 is coupled to a different switch control line SW1 and a different data signal line D2. Furthermore, within each test circuit group 03, the test circuits 031 coupled to the data line D0 corresponding to sub-pixels of the same color share the same data signal line D2 (i.e., are coupled to the same data signal line D2) and share the same switch control line SW1 (i.e., are coupled to the same switch control line SW1).

[0065] For example, reference Figure 4, each pixel 02 shown includes: a red (Red, R) sub-pixel R1, a blue (Blue, B) sub-pixel B1, and a green (Green, G) sub-pixel G1. The red sub-pixels R1 in the same column are coupled to the same data line D0, the green sub-pixels G1 in the same column are coupled to the same data line D0, and the blue sub-pixels B1 in the same column are coupled to the same data line D0. Accordingly, each test circuit group 03 includes three test circuits 031, namely a first test circuit 031-1, a second test circuit 031-2, and a third test circuit 031-3. The display substrate includes three switch control lines SW1-R1, SW1-G1, and SW1-B1, and three data signal lines D2-R1, D2-G1, and D2-B1. That is, the CT circuit described in the embodiment of the present disclosure is a CT circuit with a 3D3S structure (i.e., including three data signal lines and three switch control lines). Of course, in some embodiments, the CT circuit may also have other structures, such as 3D1S (ie, including 3 data signal lines and 1 switch control line).

[0066] The first test circuit 031-1 can be coupled to the switch control line SW1-R1, the data signal line D2-R1, and a data line lead D1, respectively. The data line lead D1 can be coupled to the data line D0 coupled to the red sub-pixel R1. In response to a switch control signal provided by the switch control line SW1-R1, the first test circuit 031-1 can transmit a data signal provided by the data signal line D2-R1 via the data line lead D1 to the data line D0 coupled to the red sub-pixel R1, thereby illuminating the red sub-pixel R1. Furthermore, the first test circuits 031-1 in different test circuit groups 03 are all coupled to the switch control line SW1-R1 and the data signal line D2-R1.

[0067] Second test circuit 031-2 can be coupled to switch control line SW1-B1, data signal line D2-B1, and a data line lead D1, respectively. Data line lead D1 can be coupled to data line D0 coupled to blue sub-pixel B1. In response to a switch control signal provided by switch control line SW1-B1, second test circuit 031-2 can transmit a data signal provided by data signal line D2-B1 via data line lead D1 to data line D0 coupled to blue sub-pixel B1, thereby illuminating blue sub-pixel B1. Furthermore, each second test circuit 031-2 in different test circuit groups 03 is coupled to switch control line SW1-B1 and data signal line D2-B1.

[0068] The third test circuit 031-3 can be coupled to the switch control line SW1-G1, the data signal line D2-G1, and a data line lead D1, respectively. The data line lead D1 can be coupled to the data line D0 coupled to the green sub-pixel G1. In response to a switch control signal provided by the switch control line SW1-G1, the third test circuit 031-3 can transmit the data signal provided by the data signal line D2-G1 via the data line lead D1 to the data line D0 coupled to the green sub-pixel G1, thereby illuminating the green sub-pixel G1. Furthermore, the third test circuits 031-3 in different test circuit groups 03 are all coupled to the switch control line SW1-G1 and the data signal line D2-G1.

[0069] Optional, reference Figure 4 , sub-pixels of different colors are coupled to different data lines D0, and different test circuits 031 are coupled to different data lines D0 through different data line leads D1. Or, referring to Figure 5 In each test circuit group 03, the test circuit 031 coupled to the data line D0 corresponding to the red sub-pixel R1 and the test circuit 031 coupled to the data line D0 corresponding to the blue sub-pixel B1 can share the same data line lead D1. That is, the first test circuit 031-1 and the third test circuit 031-3 are coupled to the same data line lead D1. On this basis, Figure 5 As shown, the red sub-pixel R1 and the blue sub-pixel B1 can be coupled to the same data line D0 and coupled to the same data line lead D1 through the same data line D0. Of course, in some embodiments, the red sub-pixel R1 and the blue sub-pixel B1 can be coupled to different data lines D0, and then the different data lines D0 are coupled to the same data line lead D1.

[0070] Testing has shown that the data signal required to drive red sub-pixel R1 and blue sub-pixel B1 are similar. Therefore, by providing a single data line lead D1 to couple data line D0 corresponding to red sub-pixel R1 and data line D0 corresponding to blue sub-pixel B1, or by coupling red sub-pixel R1 and blue sub-pixel B1 to the same data line D0, wiring can be simplified and costs can be reduced.

[0071] by Figure 5 Take the structure shown as an example, Figure 6 FIG1 shows a schematic diagram of another structure of a display substrate. Figure 6 It can be seen that each test circuit 031 (ie, the first test circuit 031 - 1 , the second test circuit 031 - 2 and the third test circuit 031 - 3 ) may include: a switching transistor T1 .

[0072] The gate of the switch transistor T1 may be coupled to the switch control line SW1 , the first electrode of the switch transistor T1 may be coupled to the data signal line D2 , and the second electrode of the switch transistor T1 may be coupled to the data line lead D1 .

[0073] For example, the gate of the switching transistor T1 included in the first test circuit 031-1 can be coupled to the switch control line SW1-R1, the first electrode can be coupled to the data signal line D2-R1, and the second electrode can be coupled to the data line lead D1. The gate of the switching transistor T1 included in the second test circuit 031-2 can be coupled to the switch control line SW1-B1, the first electrode can be coupled to the data signal line D2-B1, and the second electrode can be coupled to the data line lead D1. The gate of the switching transistor T1 included in the third test circuit 031-2 can be coupled to the switch control line SW1-G1, the first electrode can be coupled to the data signal line D2-G1, and the second electrode can be coupled to the data line lead D1.

[0074] and, Figure 6 The second electrode of the switch transistor T1 included in the second test circuit 031-2 and the second electrode of the switch transistor T1 included in the third test circuit 031-2 are coupled to the same data line lead D1. Figure 6 It can also be seen that each pixel O2 in the display substrate can include one red sub-pixel R1, one blue sub-pixel B1, and two green sub-pixels G1. The two green sub-pixels G1 are symmetrically arranged and coupled to the same data line lead D1. The red sub-pixel R1 and the blue sub-pixel B1 can both be polygonal in shape, and the size of the red sub-pixel R1 can be smaller than the size of the blue sub-pixel B1. The shape of the green sub-pixel G1 can be semicircular. Of course, in some embodiments, the sub-pixels can also have other shapes, and the size of the red sub-pixel R1 can also be larger than the size of the blue sub-pixel B1.

[0075] For example, taking the example of setting the length of the positive projection of the target conductive film layer of each test circuit 031 on the substrate 01 to be negatively correlated with the length of the data line lead D1, Figure 7 A structural layout of a first test circuit 031 - 1 and a second test circuit 031 - 2 is shown. Figure 8 A structural layout of a third test circuit 031-3 is shown. And, taking the example of setting the maximum width of the positive projection of the target conductive film layer of each test circuit 031 on the substrate 01 to be positively correlated with the length of the data line lead D1, Figure 9 A structural layout of a first test circuit 031 - 1 and a second test circuit 031 - 2 is shown.

[0076] refer to Figures 7 to 9As can be seen, the multi-layer conductive film layers of each test circuit 031 may include: an active layer (poly) P1 located on one side of the substrate 01, a first gate metal layer GATE1, and a first source and drain (SD) metal layer SD1. The active layer P1 may be coupled to the first source and drain metal layer SD1, which may also be coupled to the data signal line D2 and the data line lead D1, respectively. The first gate metal layer GATE1 may be coupled to the switch control line SW1. Based on this, the target conductive film layers described in the above embodiment may include: an active layer P1 coupled to the data line lead D1 via the first source and drain metal layer SD1. That is, the resistance value of the data line lead D1 can be compensated by adjusting the length and / or width of the active layer P1.

[0077] For example, reference Figure 7 and Figure 8 , and the corresponding partial enlarged diagram, it can be seen that the longer the data line lead D1 is, the shorter the length L0 of the active layer P1 is. Figure 9 As can be seen from the partial enlarged view, the longer the data line lead D1 is, the wider the width d0 of the active layer P1 is.

[0078] It should be noted that when adjusting the width d0, the target conductive film layer may also include the first source / drain metal layer SD1 coupled to the data signal line D2. That is, the width of the first source / drain metal layer SD1 may be adjusted simultaneously. Of course, in some embodiments, when adjusting the length L0, the length of the first source / drain metal layer SD1 may also be adjusted simultaneously.

[0079] Optional, reference Figures 7 to 9 It can be seen that the display substrate may further include: a second gate metal layer GATE2 and a second source / drain metal layer SD2.

[0080] Specifically, the switch control line SW1 can be located on the same layer as the first source-drain metal layer SD1, and the data signal line D2 can be located on the same layer as the first source-drain metal layer SD1 and the second source-drain metal layer SD2. That is, the data signal line D2 can include two source-drain metal layers, the source-drain metal layer SD1 and the source-drain metal layer SD2. This ensures the stability of the data signal provided by the data signal line D2. The data line lead D1 can be located on the same layer as the first gate metal layer GATE1 or the second gate metal layer GATE2. For example, of every two adjacent data line leads D1, one data line lead D1 can be located on the same layer as the first gate metal layer GATE1, and the other data line lead D1 can be located on the same layer as the second gate metal layer GATE2.

[0081] Among them, being located in the same layer may refer to: using the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to pattern the film layer through a single patterning process to form a layer structure. Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous. That is, multiple elements, components, structures and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. In this way, manufacturing processes and manufacturing costs can be saved, and manufacturing efficiency can be accelerated.

[0082] Optional, combined Figures 7 to 9 In a direction away from the substrate 01, the active layer P1, the first gate metal layer GATE1, the second gate metal layer GATE2, the first source / drain metal layer SD1, and the second source / drain metal layer SD2 can be stacked sequentially. One or more insulating layers can be provided between each adjacent layer. The first source / drain metal layer SD1 and the active layer P1 can be coupled via a via extending through the insulating layer therebetween, and the first source / drain metal layer SD1 and the first gate metal layer GATE1 can be coupled via a via extending through the insulating layer therebetween.

[0083] It should be noted that Figure 7 and Figure 9 Furthermore, the stacking arrangement of the active layer P1, the first gate metal layer GATE1, the second gate metal layer GATE2, the first source / drain metal layer SD1, and the second source / drain metal layer SD2 is not limited to the stacking arrangement described in the embodiment of the present disclosure.

[0084] Optional, reference Figure 3 It can be seen that in the embodiment of the present disclosure, the display area A1 and the non-display area B1 can be arranged along the first direction X1, the switch control line SW1 and the data signal line D2 in the display substrate can both extend along the second direction X2, the data line D0 can extend along the first direction X1, and the first direction X1 intersects the second direction X2. Figure 3 The first direction X1 and the second direction X2 are perpendicular to each other.

[0085] Recombination Figures 7 to 10 As can be seen, in each test circuit group 03 described in the embodiments of the present disclosure, the first test circuit 031-1, the second test circuit 031-2, and the third test circuit 031-3 can be arranged sequentially along the first direction X1. Furthermore, with each pair of adjacent third test circuits 031-3 forming a group, the two third test circuits 031-3 can be arranged in an alternating pattern along the first direction X1. Furthermore, the first test circuit 031-1 and the second test circuit 031-2 can share the active layer P1 and be coupled to the same data line lead D1.

[0086] by Figure 7 Take the structure shown as an example, Figure 11 FIG. 1 shows a schematic diagram of the structure of another display substrate. Figure 11 It can be further seen that each test circuit group 03 can be located at the Fanout and coupled to the data line D0 coupled to the pixel 02 through the data line lead D1. Moreover, the data line lead D1 becomes shorter and shorter as it approaches the center of the display substrate. Accordingly, as described in the above embodiment, Figure 11 , the active layer P1 included in the test circuit 031 can be longer and longer.

[0087] In summary, an embodiment of the present disclosure provides a display substrate. The display substrate includes a plurality of test circuit groups, each test circuit group includes a plurality of test circuits, and each test circuit is respectively coupled to a data signal line and a data line lead, the data line lead is coupled to the data line, and the data line is further coupled to the pixel. Each test circuit can transmit the data signal provided by the data signal line to the data line through the data line lead to light up the pixel. Since the resistance value of the conductive film layer coupled to the data signal line in each test circuit is negatively correlated with the length of the data line lead, it is possible to effectively compensate for the resistance values ​​of data line leads of different lengths, so that the resistance values ​​on each data line lead are close. Furthermore, the uniformity of the data signals transmitted to each data line can be improved, and the uniformity of the luminous brightness of multiple pixels can be improved. In this way, the accuracy of the lighting test can be ensured to be better.

[0088] Figure 12 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 12 As shown, the display device includes: a power supply component J1, and a display substrate 00 as shown in the above drawings.

[0089] The power supply component J1 is coupled to the display substrate 00 and is used to supply power to the display substrate 00 .

[0090] Optionally, the display device can be: an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, a liquid crystal display (LCD) device, a mobile phone, a tablet computer, a television, a monitor, or any other product or component with a display function.

[0091] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display substrate, characterized in that: The display substrate comprises: a substrate having a display area and a non-display area at least partially surrounding the display area; a plurality of pixels located in the display area; a plurality of data lines, located in the display area and coupled to the plurality of pixels, and configured to provide data signals to the plurality of pixels; a plurality of data line leads, located in the non-display area and coupled to the plurality of data lines; At least one switch control line, a plurality of data signal lines, and a plurality of test circuit groups are located in the non-display area, each of the test circuit groups includes a plurality of test circuits, each of the test circuits has a multi-layer conductive film layer, and is coupled to one of the switch control line, one of the data signal line, and one of the data line lead lines through the multi-layer conductive film layers, and is used to transmit a data signal from the data signal line to the data line via the data line lead line in response to a switch control signal provided by the switch control line; Wherein, in the multi-layer conductive film layers included in each of the test circuits, the resistance value of the target conductive film layer coupled to the data line lead is negatively correlated with the length of the data line lead; The multi-layer conductive film layer includes: an active layer, a first gate metal layer, and a first source / drain metal layer located on one side of the substrate; the active layer is coupled to the first source / drain metal layer, the first source / drain metal layer is also coupled to the data signal line and the data line lead, respectively, and the first gate metal layer is coupled to the switch control line; The target conductive film layer includes: the active layer coupled to the data line lead through the first source / drain metal layer.

2. The display substrate according to claim 1, wherein: The length of the orthographic projection of the target conductive film layer on the substrate is negatively correlated with the length of the data line lead.

3. The display substrate according to claim 1, wherein The width of the orthographic projection of the target conductive film layer on the substrate is positively correlated with the length of the data line lead.

4. The display substrate according to claim 3, wherein: The maximum width of the orthographic projection of the target conductive film layer on the substrate is positively correlated with the length of the data line lead.

5. The display substrate according to claim 1, wherein The display substrate further includes: a second gate metal layer and a second source / drain metal layer; The switch control line is located in the same layer as the first source-drain metal layer, the data signal line is located in the same layer as the first source-drain metal layer and the second source-drain metal layer, and the data line lead is located in the same layer as the first gate metal layer or the second gate metal layer.

6. The display substrate according to any one of claims 1 to 4, characterized in that: Each pixel includes a plurality of sub-pixels of different colors, each of the sub-pixels being coupled to a corresponding data line; and the number of test circuits included in each test circuit group, and the number of switch control lines and the number of data signal lines included in the display substrate are all the same as the number of sub-pixels included in each pixel; Wherein, each test circuit included in each test circuit group is coupled to a different switch control line and to a different data signal line; Furthermore, in each of the test circuit groups, the test circuits coupled to the data lines corresponding to sub-pixels of the same color share the same data signal line and are coupled to the same switch control line.

7. The display substrate according to claim 6, wherein: Each of the pixels includes: a red sub-pixel, a green sub-pixel and a blue sub-pixel; In each of the test circuit groups, the test circuit coupled to the data line corresponding to the red sub-pixel and the test circuit coupled to the data line corresponding to the blue sub-pixel share the same data line lead.

8. The display substrate according to any one of claims 1 to 4, characterized in that: Each of the test circuits includes: a switching transistor; The gate of the switch transistor is coupled to the switch control line, the first electrode of the switch transistor is coupled to the data signal line, and the second electrode of the switch transistor is coupled to the data line lead.

9. A display device, characterized in that: The display device comprises: a power supply component, and a display substrate according to any one of claims 1 to 8; The power supply component is coupled to the display substrate and is used to supply power to the display substrate.

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