Method, device, storage medium and electronic equipment for debugging multimedia processing chip

Abstract

Embodiments of the present application disclose a method and device for debugging a multimedia processing chip, a storage medium and an electronic device. An application processing chip is connected to a peripheral interface of the multimedia processing chip. The application processing chip receives an interrupt signal from the multimedia processing chip, and the interrupt signal indicates that a communication bus of the multimedia processing chip is suspended. A debugging signal of a debugging interface of the multimedia processing chip is simulated through the peripheral interface. An IP core that has an abnormality in the multimedia processing chip is determined based on the debugging signal. In this way, when the communication bus of the multimedia processing chip cannot normally operate, the application processing chip connected to the multimedia processing chip can simulate the debugging signal through the connected peripheral interface, and timely locate the IP core that has the abnormality based on the debugging signal.

Description

Technical Field

[0001] This application relates to the field of electronic equipment technology, and specifically to a method, apparatus, storage medium, and electronic equipment for debugging a multimedia processing chip. Background Technology

[0002] As electronic devices become increasingly feature-rich, some incorporate multiple chips to enhance processing power. When one of these chips experiences a communication bus hang during operation, it can cause the chip to malfunction. In such cases, it's necessary to locate the faulty IP core to restore normal operation of the electronic device. However, due to the communication bus hang, it's impossible to pinpoint the faulty IP core via the communication bus itself. Summary of the Invention

[0003] This application provides a method, apparatus, storage medium, and electronic device for debugging a multimedia processing chip, which can promptly locate abnormal IP cores when the communication bus of the multimedia processing chip is suspended.

[0004] In a first aspect, embodiments of this application provide a method for debugging a multimedia processing chip within an application processing chip, wherein the application processing chip is connected to a peripheral interface of the multimedia processing chip, and the method includes:

[0005] An interrupt signal is received from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended;

[0006] The debugging signals of the debugging interface of the multimedia processing chip are simulated through the peripheral interface; and

[0007] Based on the debugging signal, the IP core in the multimedia processing chip that is malfunctioning is identified.

[0008] Secondly, embodiments of this application also provide a method for debugging a multimedia processing chip, wherein the peripheral interface of the multimedia processing chip is connected to an application processing chip, and the method includes:

[0009] When a communication bus suspension is detected, an interrupt signal is sent to the application processing chip.

[0010] Thirdly, embodiments of this application also provide a method for debugging a multimedia processing chip, wherein the peripheral interface of the multimedia processing chip is connected to an application processing chip, including:

[0011] When the multimedia processing chip detects that the communication bus is suspended, the multimedia processing chip sends an interrupt signal to the application processing chip.

[0012] After receiving the interrupt signal, the application processing chip simulates the debugging signal of the multimedia processing chip's debugging interface through the peripheral interface; and

[0013] Based on the debugging signal, the application processing chip determines the IP core in the multimedia processing chip that is malfunctioning.

[0014] Fourthly, embodiments of this application also provide an apparatus for debugging a multimedia processing chip within an application processing chip, wherein the application processing chip is connected to a peripheral interface of the multimedia processing chip, and the apparatus includes:

[0015] A signal receiving module is configured to receive an interrupt signal from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended;

[0016] A signal simulation module is used to simulate the debugging signals of the debugging interface of the multimedia processing chip through the peripheral interface; and

[0017] An anomaly localization module is used to determine the IP core in the multimedia processing chip that has an anomaly based on the debugging signal.

[0018] Fifthly, embodiments of this application also provide an apparatus for debugging a multimedia processing chip, wherein the peripheral interface of the multimedia processing chip is connected to an application processing chip, and the apparatus includes:

[0019] The signal sending module is used to send an interrupt signal to the application processing chip when a communication bus suspension is detected.

[0020] Sixthly, embodiments of this application also provide an apparatus for debugging a multimedia processing chip, wherein the peripheral interface of the multimedia processing chip is connected to an application processing chip, and the apparatus includes:

[0021] A signal sending module is used to send an interrupt signal to the application processing chip when a communication bus suspension is detected.

[0022] A signal simulation module is used to simulate the debugging signal of the multimedia processing chip's debugging interface through the peripheral interface after receiving the interrupt signal; and

[0023] An anomaly localization module is used to determine the IP core in the multimedia processing chip that has an anomaly based on the debugging signal.

[0024] In a seventh aspect, embodiments of this application also provide a computer-readable storage medium having a computer program stored thereon, which, when run on a computer, causes the computer to perform a method for debugging a multimedia processing chip in an application processing chip as provided in any embodiment of this application; or, when run on a computer, causes the computer to perform a method for debugging a multimedia processing chip in a multimedia processing chip as provided in any embodiment of this application.

[0025] Eighthly, embodiments of this application also provide an electronic device, which includes the apparatus for debugging a multimedia processing chip provided in any embodiment of this application.

[0026] The technical solution provided in this application embodiment connects the application processing chip and the multimedia processing chip via a peripheral interface. When the communication bus of the multimedia processing chip fails to operate normally, an interrupt signal is sent to the application processing chip connected to it. The application processing chip can simulate a debugging signal through the connected peripheral interface and locate the IP core of the multimedia processing chip that is malfunctioning based on the debugging signal. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 A schematic diagram illustrating a scenario for debugging a multimedia processing chip using an external device.

[0029] Figure 2 This is a flowchart illustrating a method for debugging a multimedia processing chip in an application processing chip, as provided in an embodiment of this application.

[0030] Figure 3 This is an interactive schematic diagram illustrating the method for debugging a multimedia processing chip provided in an embodiment of this application.

[0031] Figure 4 This is a schematic diagram of the structure of an apparatus for debugging a multimedia processing chip in an application processing chip, provided in an embodiment of this application.

[0032] Figure 5 This is a schematic diagram of a first structure of an electronic device provided in an embodiment of this application.

[0033] Figure 6 This is a schematic diagram of a second structure of an electronic device provided in an embodiment of this application.

[0034] Figure 7This is a schematic diagram of a third structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the protection scope of this application.

[0036] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0037] Please see Figure 1 , Figure 1 This diagram illustrates a scenario where an external device is used to debug a multimedia processing chip. The electronic device includes an application processing chip and a multimedia processing chip, with the application processing chip connected to the multimedia processing chip via a peripheral interface. The multimedia processing chip also has a debug interface, which can be used to debug the electronic device during the testing phase. For example, an external debugging device can be connected through the debug interface to debug the multimedia processing chip. Typically, the debug interface is disabled during mass production. This means that if the communication bus of the multimedia processing chip is suspended when the user uses the electronic device, the device must be returned to the factory for disassembly, the debug interface resoldered, and then an external debugging device connected to the debug interface to debug the communication bus. This is inefficient and inconvenient for users.

[0038] To address this issue, embodiments of this application provide a method for debugging a multimedia processing chip within an application processing chip. The method can be executed by the apparatus provided in this application for debugging a multimedia processing chip within an application processing chip, wherein the apparatus for debugging the multimedia processing chip can be implemented in hardware or software. Please refer to... Figure 2 , Figure 2 This is a flowchart illustrating a method for debugging a multimedia processing chip within an application processing chip, as provided in an embodiment of this application. The specific flow of this method for debugging a multimedia processing chip within an application processing chip, as provided in an embodiment of this application, is as follows:

[0039] In step 101, an interrupt signal is received from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended.

[0040] In this embodiment of the application, the multimedia processing chip may be a Pre-ISP (Pre-Image Signal Processor), which can be used to perform some image processing, such as performing bad pixel calibration, linearization and other processing on the raw image data output by the camera, or performing backlight photography in the RAW (unprocessed and uncompressed format) domain, high dynamic range photography, etc.

[0041] The multimedia processing chip may include a processor, memory, NPU (Neural-network Processing Unit), image signal processing, DDR (Double Data Rate Synchronous Dynamic Random Access Memory), and other IP cores (Intellectual Property cores, also known as intellectual property cores or intellectual property modules). These IP cores are connected to each other via a communication bus for communication.

[0042] Normally, if a multimedia processing chip malfunctions during operation, the faulty IP core can be located by obtaining log information through the communication bus. However, in some cases, malfunctions in certain IP cores can cause the communication bus to hang. In this situation, the communication bus cannot function properly, and log information cannot be obtained. For example, when a user takes a photo using a camera application, the multimedia processing chip performs image processing operations. If a malfunction in one IP core causes the communication bus to hang, the screen may freeze or go black.

[0043] In addition, the multimedia processing chip also includes a debug bus and debug interfaces connected to the debug bus. Each IP core in the multimedia processing chip is also connected to the debug bus. For example, the debug interface may be a JTAG (Joint TestAction Group) interface, SWD (Serial Wire Debug), etc. Generally, these interfaces are used to debug the multimedia processing chip during the testing phase. However, during the mass production phase, the physical interfaces used for debugging are disabled. Therefore, users cannot use these debug interfaces to debug faults in the multimedia processing chip during the usage phase.

[0044] In addition, peripheral interfaces can be SDIO (Secure Digital Input and Output) interfaces, SPI (Serial Peripheral Interface), etc.

[0045] Please see Figure 3 , Figure 3 This is an interactive schematic diagram illustrating a method for debugging a multimedia processing chip within an application processing chip, as provided in an embodiment of this application. When the multimedia processing chip suspends the communication bus due to an IP core malfunction, it sends an interrupt signal to the application processing chip.

[0046] In 102, the debugging signal of the debugging interface of the multimedia processing chip is simulated through the peripheral interface.

[0047] In step 103, based on the debugging signal, the IP core in the multimedia processing chip that is malfunctioning is identified.

[0048] When the application processing chip receives an interrupt signal from the multimedia processing chip, it simulates the debug signal of the debug interface through the peripheral interface of the multimedia processing chip.

[0049] Taking the SDIO interface as an example and the JTAG interface as a debugging interface, the solution of this application embodiment will be described. The application processing chip simulates the JTAG debugging signal through the SDIO interface according to the JTAG protocol. That is, the application processing chip simulates the JTAG read and write operation timing through the SDIO interface to debug the multimedia processing chip and determine the IP core that is abnormal.

[0050] For example, in some embodiments, simulating the debugging signal of the debugging interface of the multimedia processing chip through the peripheral interface includes: simulating the debugging signal of the modulation interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debugging interface.

[0051] The JTAG interface includes four pins: TCK: Test Clock Input; TDI: Test Data Input (data is input to the JTAG interface via TDI); TDO: Test Data Output (data is output from the JTAG interface via TDO); and TMS: Test Mode Selection (used to set the JTAG interface to a specific test mode). In this embodiment, an SDIO register, denoted as the first preset register, is added. A preset debugging protocol is also added to the SDIO controller. This preset debugging protocol matches the debugging interface; for example, if the debugging interface is a JTAG interface, then the preset debugging protocol is the JTAG protocol. The added first preset register is associated with the JTAG interface. For example, the lowest four bits of the first preset register correspond one-to-one with the four pins of the JTAG. By writing to these four bits of the first preset register, the levels of the four JTAG pins (TMS / TDI / TCK / TDO) are changed, thereby simulating the JTAG read / write timing. The signal input through the TDI pin can trigger a debugging command, which instructs the JTAG interface to locate the abnormal IP core through the JTAG bus and output the debugging result data to the application processing chip through the TDO pin.

[0052] For example, in one embodiment, determining the IP core that has malfunctioned in the multimedia processing chip based on the debug signal includes: reading debug data from the debug register corresponding to the IP core of the multimedia processing chip based on the debug signal; and determining the IP core that has malfunctioned based on the debug data.

[0053] In this embodiment, each IP core corresponds to a debug register. When a fault occurs during the operation of an IP core, data is written to the corresponding debug register to record the fault information. After a debug command is triggered through the debug interface, the debug data of the debug register of each IP core is read through the debug bus and transmitted to the application processing chip through the peripheral interface. The application processing chip determines the IP core that has malfunctioned based on all the debug data. For example, it checks whether a field in the debug register has a preset value; if the preset value exists, it determines that the IP core corresponding to that debug register has malfunctioned.

[0054] In one embodiment, the application processing chip can analyze the debugging data locally to identify the IP core that has malfunctioned.

[0055] Alternatively, in another embodiment, the application processing chip sends an anomaly location request to the server based on the debugging data; and receives a location result from the server, the location result indicating the IP core where the anomaly occurred.

[0056] In this embodiment, the application processing chip sends all the acquired debugging data to the server, which analyzes the data to identify the abnormal IP cores and returns the results to the application processing chip.

[0057] In some embodiments, after identifying an abnormal IP core, the abnormal IP core can be reset via a peripheral interface to restore the normal operation of the communication bus of the multimedia processing chip. For example, in one embodiment, the method further includes: simulating a reset signal by writing to a second preset register of the peripheral interface and sending the reset signal to the multimedia processing chip, which indicates the abnormal IP core that needs to be reset.

[0058] In this embodiment, in addition to the first preset register mentioned above, another register, denoted as the second preset register, is added to the peripheral interface. The application processing chip triggers a reset signal for the abnormal IP core by writing data to the second preset register. The second preset register can be configured with multiple bits, one bit corresponding to one IP core. After identifying the abnormal IP core, the application processing chip writes a specific value to the bit corresponding to the abnormal IP core in the second preset register to trigger a reset signal for the abnormal IP core. This reset signal is transmitted to the abnormal IP core via the debug bus, causing the abnormal IP core to restart and thus restoring the operation of the communication bus.

[0059] In practice, this application is not limited by the execution order of the described steps. Without causing conflicts, some steps may be performed in other orders or simultaneously.

[0060] As can be seen from the above, the method for debugging a multimedia processing chip in an application processing chip provided in this application embodiment involves connecting the application processing chip to the peripheral interface of the multimedia processing chip. When the communication bus of the multimedia processing chip cannot operate normally, an interrupt signal is sent to the application processing chip connected to it. The application processing chip can simulate the debugging signal through the connected peripheral interface and locate the IP core of the multimedia processing chip that is malfunctioning based on the debugging signal.

[0061] This application embodiment also provides a method for debugging a multimedia processing chip, wherein the peripheral interface of the multimedia processing chip is connected to an application processing chip, and the method includes:

[0062] When a communication bus suspension is detected, an interrupt signal is sent to the application processing chip.

[0063] In this embodiment, if the multimedia processing chip detects a communication bus suspension, it sends an interrupt signal to the application processing chip. Upon receiving this interrupt signal, the application processing chip simulates the debugging signal of the multimedia processing chip's debugging interface through the connected peripheral interface. Based on this debugging signal, it locates the IP core of the multimedia processing chip that is malfunctioning. The process of generating the debugging signal is detailed in the method for debugging the multimedia processing chip within the application processing chip described above, and will not be repeated here.

[0064] In some embodiments, the method further includes resetting the malfunctioning IP core in response to a reset signal received from the multimedia processing chip. The process for generating the reset signal is detailed in the method for debugging the multimedia processing chip in the application processing chip described above, and will not be repeated here.

[0065] This application also provides a method for debugging a multimedia processing chip, including:

[0066] When the multimedia processing chip detects that the communication bus is suspended, the multimedia processing chip sends an interrupt signal to the application processing chip.

[0067] After receiving the interrupt signal, the application processing chip simulates the debugging signal of the multimedia processing chip's debugging interface through the peripheral interface; and

[0068] Based on the debugging signal, the multimedia processing chip identifies the IP core in the multimedia processing chip that has malfunctioned.

[0069] The specific implementation process is detailed in the above-described method embodiment for debugging the multimedia processing chip in the application processing chip, and will not be repeated here.

[0070] In one embodiment, an apparatus for debugging a multimedia processing chip within an application processing chip is also provided. Please refer to [link to previous document]. Figure 4 , Figure 4 This is a schematic diagram of the structure of the apparatus 300 for debugging a multimedia processing chip in an application processing chip, provided in an embodiment of this application. The application processing chip and the multimedia processing chip are connected via peripheral interfaces. The apparatus 300 for debugging the multimedia processing chip includes a signal receiving module 301, a signal simulation module 302, and an anomaly location module 303, as follows:

[0071] The signal receiving module 301 is used to receive an interrupt signal from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended;

[0072] The signal simulation module 302 is used to simulate the debugging signal of the debugging interface of the multimedia processing chip through the peripheral interface;

[0073] The anomaly location module 303 is used to determine the IP core in the multimedia processing chip that has an anomaly based on the debugging signal.

[0074] In some embodiments, the signal simulation module 302 is further configured to: simulate the debugging signal of the modulation interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debugging interface.

[0075] In some embodiments, the anomaly location module 303 is further configured to: read debugging data from the debugging register corresponding to the IP core of the multimedia processing chip based on the debugging signal; and determine the IP core that has an anomaly based on the debugging data.

[0076] In some embodiments, the anomaly location module 303 is further configured to: send an anomaly location request to the server based on the debugging data; and receive a location result from the server, wherein the location result indicates the IP core where the anomaly occurred.

[0077] In some embodiments, the apparatus 300 for debugging the multimedia processing chip further includes an anomaly repair module, which is configured to: simulate a reset signal by writing to a second preset register of the peripheral interface and send the reset signal to the multimedia processing chip, indicating an abnormal IP core that needs to be reset.

[0078] In some embodiments, the peripheral interface is a Secure Digital Input / Output Interface or a Serial Peripheral Interface; and / or the debug interface is a Joint Test Working Group Interface or a Serial Debug Interface.

[0079] It should be noted that the apparatus for debugging a multimedia processing chip in an application processing chip provided in this application embodiment belongs to the same concept as the method for debugging a multimedia processing chip in an application processing chip in the above embodiment. Any of the methods provided in the method embodiment for debugging a multimedia processing chip in an application processing chip can be implemented by this apparatus. For details of the specific implementation process, please refer to the method embodiment for debugging a multimedia processing chip, which will not be repeated here.

[0080] As can be seen from the above, the apparatus 300 for debugging a multimedia processing chip in an application processing chip proposed in this application embodiment connects the application processing chip and the multimedia processing chip through the peripheral interface. The apparatus 300 includes a signal receiving module 301, a signal simulation module 302, and an anomaly location module 303. When the bus of the multimedia processing chip is suspended, an interrupt signal is triggered. The signal receiving module 301 of the application processing chip receives the interrupt signal sent by the multimedia processing chip, and the signal simulation module 302 simulates the debugging signal of the debugging interface through the peripheral interface of the multimedia processing chip. Based on the debugging signal, the anomaly location module 303 determines the abnormal IP core from among the multiple IP cores of the multimedia processing chip.

[0081] In one embodiment, an apparatus for debugging a multimedia processing chip is also provided. The peripheral interface of the multimedia processing chip is connected to an application processing chip. The apparatus for debugging the multimedia processing chip includes:

[0082] The signal sending module is used to send an interrupt signal to the application processing chip when a communication bus suspension is detected.

[0083] In one embodiment, an apparatus for debugging a multimedia processing chip is also provided. The peripheral interface of the multimedia processing chip is connected to an application processing chip, and the apparatus includes:

[0084] A signal sending module is used to send an interrupt signal to the application processing chip when a communication bus suspension is detected.

[0085] A signal simulation module is used to simulate the debugging signal of the multimedia processing chip's debugging interface through the peripheral interface after receiving the interrupt signal; and

[0086] An anomaly localization module is used to determine the IP core in the multimedia processing chip that has an anomaly based on the debugging signal.

[0087] The specific implementation process is detailed in the above-described method embodiment for debugging the multimedia processing chip in the application processing chip, and will not be repeated here.

[0088] This application also provides an electronic device. The electronic device includes the aforementioned apparatus for debugging a multimedia processing chip within an application processing chip.

[0089] This application also provides an electronic device. The electronic device may be a smartphone, tablet computer, or similar device. Please refer to... Figure 5 , Figure 5 This is a schematic diagram of a first structure of an electronic device provided in an embodiment of this application. The electronic device 400 includes an application processing chip 401 and a multimedia processing chip 402. The multimedia processing chip includes a peripheral interface 4021. The application processing chip 401 and the multimedia processing chip 402 are connected through the peripheral interface 4021. The multimedia processing chip 402 is used to: send an interrupt signal to the application processing chip when a communication bus suspension is detected; the application processing chip 401 is used to: upon receiving the interrupt signal, simulate a debugging signal from the debugging interface of the multimedia processing chip through the peripheral interface; and, based on the debugging signal, determine the IP core in the multimedia processing chip that has malfunctioned.

[0090] Please see Figure 6 , Figure 6This is a second structural schematic diagram of the electronic device provided in an embodiment of this application. The application processing chip 401 includes a processor 4011 and a memory 4012. The processor 4011 and the memory 4012 are electrically connected.

[0091] The processor 4011 is the control center of the electronic device 400. It connects various parts of the electronic device through various interfaces and lines. By running or calling computer programs stored in the memory 4012 and calling data stored in the memory 4012, it performs various functions of the electronic device and processes data, thereby monitoring the electronic device as a whole.

[0092] Memory 4012 can be used to store computer programs and data. The computer programs stored in memory 4012 contain instructions that can be executed in the processor. The computer programs can be composed of various functional modules. The processor 4011 executes various functional applications and data processing by calling the computer programs stored in memory 4012.

[0093] In this embodiment, the processor 4011 in the electronic device 4010 loads the instructions corresponding to the processes of one or more computer programs into the memory 4012 according to the following steps, and the processor 4011 runs the computer programs stored in the memory 4012 to realize various functions:

[0094] An interrupt signal is received from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended;

[0095] The debugging signals of the debugging interface of the multimedia processing chip are simulated through the peripheral interface; and

[0096] Based on the debugging signal, the IP core in the multimedia processing chip that is malfunctioning is identified.

[0097] In some embodiments, please refer to Figure 7 , Figure 7 This is a third structural diagram of the electronic device provided in the embodiments of this application. The electronic device 400 further includes: a radio frequency circuit 403, a display screen 404, a control circuit 405, an input unit 406, an audio circuit 407, a sensor 408, and a power supply 409. The processor 401 is electrically connected to the radio frequency circuit 403, the display screen 404, the control circuit 405, the input unit 406, the audio circuit 407, the sensor 408, and the power supply 409.

[0098] The radio frequency circuit 403 is used to transmit and receive radio frequency signals to communicate with network devices or other electronic devices via wireless communication.

[0099] The display screen 404 can be used to display information input by the user or information provided to the user, as well as various graphical user interfaces of electronic devices, which can be composed of images, text, icons, videos, and any combination thereof.

[0100] The control circuit 405 is electrically connected to the display screen 404 and is used to control the display screen 404 to display information.

[0101] The input unit 406 can be used to receive input numeric or character information or user characteristic information (such as fingerprints), and to generate keyboard, mouse, joystick, optical, or trackball signal inputs related to user settings and function control. The input unit 406 may include a fingerprint recognition module.

[0102] The audio circuit 407 provides an audio interface between the user and the electronic device via a speaker and a microphone. The audio circuit 407 includes a microphone. The microphone is electrically connected to the processor 4011. The microphone is used to receive voice information input by the user.

[0103] Sensor 408 is used to collect information about the external environment. Sensor 408 may include one or more sensors such as an ambient light sensor, an accelerometer, and a gyroscope.

[0104] The power supply 409 is used to supply power to the various components of the electronic device 400. In some embodiments, the power supply 409 can be logically connected to the processor 4011 through a power management system, thereby enabling functions such as charging, discharging, and power consumption management through the power management system.

[0105] Although not shown in the figure, electronic device 400 may also include a camera, Bluetooth module, etc., which will not be described in detail here.

[0106] In this embodiment, the processor 4011 in the electronic device 400 loads the instructions corresponding to the processes of one or more computer programs into the memory 402 according to the following steps, and the processor 4011 runs the computer programs stored in the memory 402 to realize various functions:

[0107] An interrupt signal is received from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended;

[0108] The debugging signals of the debugging interface of the multimedia processing chip are simulated through the peripheral interface; and

[0109] Based on the debugging signal, the IP core in the multimedia processing chip that is malfunctioning is identified.

[0110] As described above, this application provides an electronic device including an application processing chip and a multimedia processing chip, which are connected via a peripheral interface. When the bus of the multimedia processing chip is suspended, an interrupt signal is triggered. The application processing chip receives the interrupt signal sent by the multimedia processing chip and simulates a debug signal from the debug interface through the peripheral interface of the multimedia processing chip. Based on this debug signal, the abnormal IP core is identified from among the multiple IP cores of the multimedia processing chip. In this way, when the communication bus of the multimedia processing chip cannot operate normally, the application processing chip connected to it can simulate a debug signal through the connected peripheral interface and locate the abnormal IP core based on the debug signal.

[0111] This application also provides a computer-readable storage medium storing a computer program. When the computer program is run on a computer, the computer executes the method for debugging a multimedia processing chip in an application processing chip as provided in any of the above embodiments; or, when the computer program is run on a computer, the computer executes the method for debugging a multimedia processing chip in a multimedia processing chip as provided in any of the embodiments of this application.

[0112] It should be noted that those skilled in the art will understand that all or part of the steps in the various methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, which may include, but is not limited to, read-only memory (ROM), random access memory (RAM), magnetic disk or optical disk, etc.

[0113] Furthermore, the terms "first," "second," and "third," etc., used in this application are used to distinguish different objects, not to describe a specific order. Additionally, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or modules is not limited to the listed steps or modules, but some embodiments may also include steps or modules not listed, or some embodiments may include other steps or modules inherent to these processes, methods, products, or devices.

[0114] The methods, apparatus, storage media, and electronic devices for debugging multimedia processing chips provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application; at the same time, those skilled in the art will recognize that, based on the ideas of this application, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for debugging a multimedia processing chip in an application processing chip, wherein, The application processing chip is connected to the peripheral interface of the multimedia processing chip, characterized in that it includes: An interrupt signal is received from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended; Simulating the debugging signals of the multimedia processing chip's debugging interface through the peripheral interface includes: simulating the debugging signals of the debugging interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debugging interface; and Based on the debug signal, the IP cores that have malfunctioned in the multimedia processing chip are identified, including: each IP core corresponds to a debug register; when a fault occurs in an IP core during operation, data is written to the corresponding debug register to record the fault information; after a debug instruction is triggered through the debug interface, the debug data of the debug register of each IP core is read through the debug bus and transmitted to the application processing chip through the peripheral interface; the application processing chip identifies the IP core that has malfunctioned based on all the debug data.

2. The method as described in claim 1, characterized in that, The step of determining the IP core in the multimedia processing chip that has malfunctioned based on the debugging signal includes: Based on the debug signal, debug data is read from the debug register corresponding to the IP core of the multimedia processing chip; and The IP core that malfunctioned was identified based on the debugging data.

3. The method as described in claim 2, characterized in that, The step of determining the IP core that malfunctioned based on the debugging data includes: Based on the debug data, an anomaly location request is sent to the server; and The server receives a location result indicating the IP core where the anomaly occurred.

4. The method as described in claim 1, characterized in that, The method further includes: A reset signal is simulated by writing to a second preset register of the peripheral interface and then sending the reset signal to the multimedia processing chip, indicating an abnormal IP core that needs to be reset.

5. The method according to any one of claims 1 to 4, characterized in that, The peripheral interface is a secure digital input / output interface or a serial peripheral interface; and / or the debugging interface is a joint test working group interface or a serial debugging interface.

6. A method for debugging a multimedia processing chip, wherein, The peripheral interface of the multimedia processing chip is connected to the application processing chip, characterized in that it includes: When the multimedia processing chip detects that the communication bus is suspended, the multimedia processing chip sends an interrupt signal to the application processing chip. After receiving the interrupt signal, the application processing chip simulates the debugging signal of the multimedia processing chip's debugging interface through the peripheral interface, including: simulating the debugging signal of the debugging interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debugging interface; and The application processing chip determines the IP core that has malfunctioned in the multimedia processing chip based on the debugging signal, including: each IP core corresponds to a debugging register; when a fault occurs in an IP core during operation, data is written to the corresponding debugging register to record the fault information; after the debugging instruction is triggered through the debugging interface, the debugging data of the debugging register of each IP core is read through the debugging bus and transmitted to the application processing chip through the peripheral interface; the application processing chip determines the IP core that has malfunctioned based on all the debugging data.

7. An apparatus for debugging a multimedia processing chip within an application processing chip, wherein, The application processing chip is connected to the peripheral interface of the multimedia processing chip, characterized in that the device includes: A signal receiving module is configured to receive an interrupt signal from the multimedia processing chip, the interrupt signal indicating that the communication bus of the multimedia processing chip is suspended; A signal simulation module is used to simulate the debugging signals of the debugging interface of the multimedia processing chip through the peripheral interface, including: simulating the debugging signals of the debugging interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debugging interface; and An anomaly localization module is used to determine the IP core that has malfunctioned in the multimedia processing chip based on the debugging signal. The module includes: each IP core has a corresponding debugging register; when a fault occurs in an IP core during operation, data is written to the corresponding debugging register to record the fault information; after a debugging instruction is triggered through the debugging interface, the debugging data of the debugging register of each IP core is read through the debugging bus and transmitted to the application processing chip through the peripheral interface; the application processing chip determines the IP core that has malfunctioned based on all the debugging data.

8. An apparatus for debugging a multimedia processing chip, wherein, The peripheral interface of the multimedia processing chip is connected to the application processing chip, characterized in that the device includes: A signal sending module is used to send an interrupt signal to the application processing chip when a communication bus suspension is detected. A signal simulation module, upon receiving the interrupt signal, simulates the debugging signal of the multimedia processing chip's debugging interface through the peripheral interface, including: simulating the debugging signal of the debugging interface by writing to a first preset register of the peripheral interface, wherein the first preset register is associated with the debugging interface; and An anomaly localization module is used to determine the IP core that has malfunctioned in the multimedia processing chip based on the debugging signal. The module includes: each IP core has a corresponding debugging register; when a fault occurs in an IP core during operation, data is written to the corresponding debugging register to record the fault information; after a debugging instruction is triggered through the debugging interface, the debugging data of the debugging register of each IP core is read through the debugging bus and transmitted to the application processing chip through the peripheral interface; the application processing chip determines the IP core that has malfunctioned based on all the debugging data.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is run on the computer, the computer performs the method of debugging a multimedia processing chip in an application processing chip as described in any one of claims 1 to 5. Alternatively, when the computer program is run on a computer, it causes the computer to perform the method for debugging a multimedia processing chip as described in claim 6.

10. An electronic device, characterized in that, The electronic device includes the apparatus of claim 7 or 8.

11. A computer program product, characterized in that, The computer program product includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the method of any one of claims 1 to 5, or to perform the method of claim 6.

Images