Core plate pressure measurement method, system, device, equipment, medium and program product

Abstract

The core board stress testing method, system, device, equipment, medium and program product provided by the present disclosure are related to the field of computers, in particular to the field of cloud computing, and can be applied to scenarios such as cloud servers. The specific implementation scheme is: sending a network connection request to at least two core boards in a server to be tested; and sending a stress testing command to the core boards in the case where a feedback message of the core boards is received in response to the network connection request. The technical scheme of the present disclosure can implement batch stress testing on the core boards in the server.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and more particularly to the field of cloud computing, specifically to a core board stress testing method, system, apparatus, equipment, medium, and program product. Background Technology

[0002] To reduce the failure rate of the core board in the server, stress testing needs to be performed on the core board before the server is put into production and delivered, thereby reducing the failure rate during user use and improving the user experience.

[0003] Servers typically contain a large number of core boards, and manually testing each one is a very labor-intensive task. Therefore, improving the efficiency of core board stress testing is crucial for ensuring the yield rate of servers. Summary of the Invention

[0004] This disclosure provides a core board voltage testing method, system, apparatus, equipment, medium, and program product.

[0005] According to one aspect of this disclosure, a core board stress testing method is provided, comprising:

[0006] Send network connection requests to at least two core boards in the server under test;

[0007] Upon receiving a feedback message from the core board regarding the network connection request, a stress test command is sent to the core board.

[0008] According to another aspect of this disclosure, a core board stress testing system is provided, including a stress testing server and a server under test; the server under test includes at least two core boards; the stress testing server and the core boards in the server under test are communicatively connected.

[0009] The stress testing server is used to execute the core board stress testing method of any embodiment of this disclosure;

[0010] The core board is used to execute the load testing commands sent by the load testing server.

[0011] According to another aspect of this disclosure, an electronic device is provided, comprising:

[0012] At least one processor; and

[0013] A memory that is communicatively connected to at least one processor; wherein,

[0014] The memory stores instructions that can be executed by at least one processor, which enables the at least one processor to perform the core board stress testing method of any embodiment of this disclosure.

[0015] According to another aspect of this disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to cause a computer to execute the core board stress testing method of any embodiment of this disclosure.

[0016] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the core board stress testing method of any embodiment of this disclosure.

[0017] The embodiments disclosed herein can enable batch stress testing of multiple core boards within a server.

[0018] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0019] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0020] Figure 1 This is a schematic diagram of a core board pressure testing method provided according to an embodiment of the present disclosure;

[0021] Figure 2 This is a schematic diagram of a core board pressure testing method provided according to an embodiment of the present disclosure;

[0022] Figure 3 This is a schematic diagram of a core board voltage testing system provided according to an embodiment of the present disclosure;

[0023] Figure 4 This is a schematic diagram of a core board voltage testing system provided according to an embodiment of the present disclosure;

[0024] Figure 5 This is a schematic diagram of a core board pressure testing device according to an embodiment of the present disclosure.

[0025] Figure 6 This is a block diagram of an electronic device used to implement the core board voltage testing method of the embodiments of this disclosure. Detailed Implementation

[0026] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0027] Figure 1 This is a schematic diagram of a core board stress testing method disclosed in an embodiment of this disclosure. This embodiment can be applied to batch stress testing of multiple core boards in a server. The method of this embodiment can be executed by a core board stress testing device, which can be implemented in software and / or hardware and specifically configured in an electronic device with a certain data processing capability. The electronic device can be a client device or a server device. Client devices include mobile phones, tablet computers, vehicle terminals, and desktop computers.

[0028] S110: Send network connection requests to at least two core boards in the server under test.

[0029] The server under test includes at least two core boards, each of which is a separate processing unit and can be considered a server node. Stacking multiple core boards to form the server under test can increase computing density and improve data processing efficiency. For example, the server under test is an ARM (Advanced RISC Machine) server, and the core boards in the server under test are ARM core boards.

[0030] To reduce the failure rate of the core boards in the server under test during operation, stress testing of the core boards is necessary. Typically, the number of core boards in a server under test is large, and manually performing stress testing on them is extremely labor-intensive. Generally, only a portion of the core boards in the server under test can be sampled, making it impossible to determine the yield rate or failure rate of the core boards in the server chassis.

[0031] In this embodiment of the disclosure, after the core board in the server under test is powered on, the load testing server can send network connection requests in batches to the core board in the server under test to determine whether a communication connection can be established with each core board through the network, thereby determining whether a fault has occurred in the core board in the server under test based on the network connection status. For example, the load testing server can establish a communication connection with each core board in the server under test through TCP (Transmission Control Protocol).

[0032] S120. Upon receiving a feedback message from the core board regarding a network connection request, send a stress test command to the core board.

[0033] A stress test command is a command used to perform stress tests on the core board. For example, a stress test command is a reboot command or a command to simulate a core board kernel crash.

[0034] In this embodiment of the disclosure, when the load testing server receives a feedback message from the core board regarding a network connection request, it indicates that the load testing server has established a network connection with the core board. At this time, it can send a load testing command to the core board to instruct the core board to execute the load testing command.

[0035] If the load testing server does not receive a response message from the core board regarding the network connection request within the set time, it indicates that the core board cannot establish a network connection with the load testing server, thus confirming a fault in the core board. In this case, the time when the network connection request was sent can be recorded as the time the core board failed.

[0036] In a specific example, the load testing server starts timing after sending a network connection request. If it receives a response message from the core board within 5 seconds, it sends a restart command to the core board, instructing it to restart. If no response message is received from the core board after 5 seconds, a fault is confirmed in the core board, and the time when the network connection request was sent is recorded as the time when the core board failed.

[0037] Furthermore, if a fault is confirmed in the core board, a probe packet can be sent to the network address corresponding to the core board using the Ping command to test the network status of the core board. For example, if a response to the Ping command is received from the network address corresponding to the core board, it can be determined that the core board network is normal and available, meaning the fault is not the network card. If no response to the Ping command is received after a set time, the fault can be located in the network card.

[0038] The technical solution of this disclosure embodiment allows the load testing server to perform batch load testing on the core boards in the server under test by sending network connection requests to at least two core boards in the server under test, and sending load testing commands to the core boards after receiving feedback messages from the core boards regarding the network connection requests. This allows the failure rate of the core boards in the server under test to be obtained.

[0039] Figure 2 This is a schematic diagram of a core board stress testing method according to an embodiment of this disclosure. Based on the above embodiment, it further refines the method by providing specific steps before sending network connection requests to at least two core boards in the server under test. The following is a combination of... Figure 2 The present disclosure provides a core board voltage testing method, which includes the following:

[0040] S210. Deploy boot scripts to at least two core boards in the server under test; the boot scripts include at least one software repair program.

[0041] The boot script is a script that runs during the core board's boot process to repair at least one software fault on the core board. Specifically, the boot script is built based on software faults that have occurred on the core board in the past, and includes fixes for at least one known software fault. For example, the boot script may include a software fix for a network card boot failure, and / or a fix for a GPU (Graphics Processing Unit) error.

[0042] In this embodiment of the present disclosure, the stress testing server can pre-distribute startup scripts to at least two core boards in the server under test, so that the core boards run the startup scripts during the startup process, thereby eliminating some known software faults, ensuring that the core boards start in a normal state, avoiding the impact of abnormal situations during the startup process on the stress test results, and ensuring the accuracy of the stress test results.

[0043] For example, the load testing server pre-deploys a startup script on the core board of the server under test. The startup script includes a software repair program for network card startup failures. This startup script can control the network card to restart during the core board startup process, thereby eliminating network card startup abnormalities.

[0044] For another example, the load testing server pre-deploys a startup script on the core board of the server under test. This startup script includes a fix for GPU errors. This startup script can control the core board to restart during its startup process, thereby eliminating GPU error faults.

[0045] S220: Send network connection requests to at least two core boards in the server under test.

[0046] S230. Upon receiving a feedback message from the core board regarding a network connection request, send a stress test command to the core board.

[0047] Optionally, the load testing command may include at least one of the following: core board restart or simulated core board kernel crash.

[0048] In this optional embodiment, the load testing command can be at least one of core board restart or simulated core board kernel crash. By sending pre-packaged load testing commands to the core boards in batches, the load testing server can perform batch testing on the core boards in the server under test, improving load testing efficiency while also obtaining the failure rate of the core boards inside the server chassis.

[0049] S240. If no feedback message for the network connection request is received from the core board within the set time period, a network probe command is sent to the core board, and the network status of the core board is determined based on the response time of the core board to the network probe command.

[0050] In this embodiment, if the load testing server does not receive a feedback message from the core board regarding a network connection request within a set time period, it can be determined that the core board is faulty. To further pinpoint the fault, a network probe command can be sent to the core board, and the network status of the core board can be determined based on its response time. Specifically, a timer is started when the network probe command is sent to the core board. If a response message from the core board is received within the set time period, the network card of the core board is determined to be normal; that is, network card failure can be ruled out as a reason why the load testing server and the core board cannot establish a network connection. If no response message is received from the core board within the set time period, the network card of the core board is identified as faulty. By sending a network probe command to the core board that has not successfully connected, the load testing server can initially determine the fault of the core board, which is helpful for subsequent fault location and repair.

[0051] In a specific example, the load testing server sends probe packets to the network address corresponding to the core board via the Ping command. If a response to the Ping command is received from the network address corresponding to the core board within 5 seconds, it is determined that the core board network is normal, and the fault point of the core board is not the network card; if no response to the Ping command is received after 5 seconds, the fault point of the core board is the network card.

[0052] It is worth noting that S230 and S240 are executed selectively based on the actual situation. S230 is executed when the load testing server receives a feedback message from the core board regarding the network connection request, and S240 is executed when no feedback message from the core board regarding the network connection request is received.

[0053] The technical solution of this disclosure embodiment involves a load testing server deploying boot scripts to at least two core boards in the server under test. After the core boards in the server under test are powered on, the server sends network connection requests to at least two core boards. Upon receiving feedback messages from the core boards regarding the network connection requests, the server sends a load testing command to the core boards. If no feedback messages are received from the core boards regarding the network connection requests within a set time, the server sends a network probe command to the core boards. Based on the response time of the core boards to the network probe command, the network status of the core boards is determined. This allows for batch load testing of core boards in the server, and even when the network connection is unavailable, the network status of the core boards can be obtained, which helps in subsequent core board problem localization and repair.

[0054] Figure 3 This is a schematic diagram of a core board stress testing system according to an embodiment of the present disclosure. This embodiment of the present disclosure can be applied to the situation of performing batch stress testing on multiple core boards in a server.

[0055] like Figure 3 As shown, the core board stress testing system includes a stress testing server 1 and a server under test 2; the server under test 2 includes at least two core boards 21; the core boards 21 in the stress testing server 1 and the server under test 2 are communicatively connected.

[0056] The load testing server 1 is used to send network connection requests to at least two core boards 21 in the server under test 2, and to send load testing commands to the core board 21 upon receiving feedback messages from the core board 21 regarding the network connection requests.

[0057] In this scenario, after the core board 21 in the server under test 2 is powered on, the load testing server 1 can send a batch of network connection requests to the core board 21 in the server under test 2 to determine whether a communication connection can be established with each core board 21 through the network. Based on the network connection status, the load testing server 1 can determine whether the core board 21 in the server under test 2 is currently malfunctioning. For example, the load testing server 1 can establish a communication connection with each core board 21 in the server under test 2 via TCP (Transmission Control Protocol).

[0058] When the load testing server 1 receives a feedback message from the core board 21 regarding a network connection request, it indicates that the load testing server 1 has established a network connection with the core board 21. At this point, it can send a load testing command to the core board 21 to instruct the core board 21 to execute the load testing command. The load testing command includes at least one of the following: core board restart or simulating a core board kernel crash.

[0059] If the load testing server 1 does not receive a feedback message from the core board 21 regarding the network connection request within the set time, it indicates that the core board 21 cannot establish a network connection with the load testing server 1, thus confirming a fault in the core board 21. In this case, the time when the network connection request was sent can be recorded as the time when the core board 21 failed.

[0060] Optionally, the load testing server 1 is also used to: deploy boot scripts to at least two core boards 21 in the server under test 2 before sending network connection requests to them. The boot scripts include at least one software repair program to cause the core boards 21 to run the boot scripts during the boot process and repair known software faults, such as network card startup failures or GPU errors.

[0061] Optionally, the load testing server 1 is also used to: send a network probe command to the core board 21 if no feedback message for the network connection request is received from the core board 21 within a set time period; and determine the network status of the core board 21 based on the response time of the core board 21 to the network probe command.

[0062] In this optional embodiment, if the load testing server 1 does not receive a feedback message from the core board 21 regarding the network connection request within a set time period, it can be determined that the core board 21 is faulty. To locate the fault in the core board 21, a network probe command can be further sent to the core board 21. If a response message is received from the core board 21 within the set time period, it is determined that the network card of the core board 21 is normal; if no response message is received from the core board 21 within the set time period, the fault in the core board 21 is located as a network card fault.

[0063] The core board 21 is used to execute the load testing commands sent by the load testing server 1.

[0064] The core board 21 is used to execute the stress test command after receiving the stress test command sent by the stress test server 1, and complete the stress test of the core board 21.

[0065] The technical solution of this disclosure embodiment allows the stress testing server to perform batch stress testing on the core boards of the server under test by sending network connection requests to at least two core boards in the server under test, and sending stress testing commands to the core boards upon receiving feedback messages from the core boards regarding the network connection requests. This enables the failure rate of the server under test to be obtained. Furthermore, by pre-issuing boot scripts to the core boards, startup anomalies during the core board startup process can be eliminated, avoiding the impact of startup anomalies on the stress test results and ensuring the accuracy of the stress test results.

[0066] Figure 4 This is a schematic diagram of a core board stress testing system according to an embodiment of the present disclosure. The embodiments of the present disclosure are applicable to the situation of batch stress testing of multiple core boards in a server. Based on the above embodiments, the core board stress testing system also includes a log capture device and provides specific execution operations for the core board and the specific execution operations for the log capture device.

[0067] like Figure 4 As shown, the core board stress testing system includes a stress testing server 1 and a server under test 2; the server under test 2 includes at least two core boards 21; the core boards 21 in the stress testing server 1 and the server under test 2 are communicatively connected.

[0068] The load testing server 1 is used to send network connection requests to at least two core boards 21 in the server under test 2, and to send load testing commands to the core board 21 upon receiving feedback messages from the core board 21 regarding the network connection requests.

[0069] The core board 21 is used to execute the load testing commands sent by the load testing server 1.

[0070] The core board stress testing system also includes a log capture device 3, which is communicatively connected to at least two core boards 21 in the server under test 2.

[0071] Log capture device 3 is used to capture the core board operation log of at least one core board 21 during the execution of stress test commands.

[0072] The core board stress testing system also includes a log capture device 3, which is communicatively connected to at least two core boards 21 in the server under test 2. Specifically, the log capture device 3 can be connected to the core boards 21 in the server under test 2 via a serial cable.

[0073] Log capture device 3 is used to establish a connection with the core board 21 in the server under test 2 via a serial port, and to capture the core board operation logs in real time during the execution of load test commands. Specifically, the core board operation logs can include logs before and after the core board 21's operating system starts. For example, the core board's power-on / off signal flags, U-boot stage logs, Boot stage logs, and file system loading stage logs, etc.

[0074] Log capture device 3 can simultaneously capture the core board operation logs of multiple core boards 21 in the server under test 2 during the execution of load test commands. Users can obtain the hardware logs of the core board 21 in various operating states in log capture device 3, which improves the efficiency of fault location when the core board 21 fails and helps to repair the core board 21 in a timely manner.

[0075] The core board 21 is specifically used to execute the load testing commands sent by the load testing server 1 and record the command execution log during the execution of the load testing commands.

[0076] The core board 21 records command execution logs during the execution of load testing commands. Specifically, it can record a start timestamp when the load testing command begins execution, an end timestamp when the load testing command completes execution, and a dmesg log when an exception occurs during the execution of the load testing command.

[0077] In addition, the core board 21 can also record self-test information during the execution of the boot script, the core board 21 boot time, and network card information, SSHD process information, and device routing information during the core board 21's operation. This allows users to understand the operating status of the core board 21 and the execution status of stress test commands.

[0078] The core board 21 is also used to: repair at least one software fault by running a pre-deployed startup script; the startup script includes at least one software repair program.

[0079] The core board 21 pre-obtains the startup script issued by the stress test server 1, which includes one or more software repair programs. Running the startup script during the startup process can eliminate some known software faults, ensure that the core board 21 starts in a normal state, avoid abnormalities during the startup process from affecting the stress test results, and ensure the accuracy of the stress test results.

[0080] For example, the startup script may include a software repair program for network card startup failures. During the startup process, the core board 21 can control the network card to restart by running the startup script, thereby eliminating network card startup abnormalities.

[0081] For example, the boot script may include a fix for GPU errors. During the boot process, the core board 21 runs this boot script, which can control the core board 21 to restart, thereby eliminating the GPU error.

[0082] The technical solution of this disclosure embodiment allows the load testing server to perform batch load testing on the core boards of the server under test by sending network connection requests to at least two core boards in the server under test, and sending load testing commands to the core boards upon receiving feedback messages from the core boards regarding the network connection requests, thereby obtaining the failure rate of the server under test.

[0083] According to embodiments of this disclosure, Figure 5 This is a structural diagram of the core board stress testing device in this embodiment of the disclosure. This embodiment is applicable to the situation of batch stress testing multiple core boards in a server. The device is implemented in software and / or hardware and is specifically configured in an electronic device with a certain data processing capability.

[0084] like Figure 5 A core board stress testing device 500, as shown, includes: a network connection request sending module 510 and a stress testing command sending module 520; wherein,

[0085] The network connection request sending module 510 is used to send network connection requests to at least two core boards in the server under test.

[0086] The load test command sending module 520 is used to send a load test command to the core board when it receives a feedback message from the core board regarding the network connection request.

[0087] The technical solution of this disclosure embodiment allows the load testing server to perform batch load testing on the core boards of the server under test by sending network connection requests to at least two core boards in the server under test, and sending load testing commands to the core boards upon receiving feedback messages from the core boards regarding the network connection requests, thereby obtaining the failure rate of the server under test.

[0088] Furthermore, the core board voltage testing device 500 also includes:

[0089] The script deployment module is used to deploy a startup script to at least two core boards of the server under test before sending a network connection request to at least two core boards of the server under test; the startup script includes at least one software repair program.

[0090] Furthermore, the core board voltage testing device 500 also includes:

[0091] The network detection command sending module is used to send a network detection command to the core board if no feedback message for the network connection request is received from the core board within a set time period.

[0092] The network status determination module is used to determine the network status of the core board based on the response time of the core board to the network probe command.

[0093] Furthermore, the stress test commands include at least one of core board restart or simulating a core board kernel crash.

[0094] The core board stress testing device provided in this disclosure can execute the core board stress testing method provided in any embodiment of this disclosure, and has the corresponding functional modules and beneficial effects of the method execution.

[0095] The collection, storage, use, processing, transmission, provision, and disclosure of user personal information involved in the technical solution disclosed herein comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0096] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0097] Figure 6 A schematic block diagram of an example electronic device 600 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0098] like Figure 6As shown, device 600 includes a computing unit 601, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 602 or a computer program loaded from storage unit 608 into random access memory (RAM) 603. RAM 603 may also store various programs and data required for the operation of device 600. The computing unit 601, ROM 602, and RAM 603 are interconnected via bus 604. Input / output (I / O) interface 605 is also connected to bus 604.

[0099] Multiple components in device 600 are connected to I / O interface 605, including: input unit 606, such as keyboard, mouse, etc.; output unit 607, such as various types of monitors, speakers, etc.; storage unit 608, such as disk, optical disk, etc.; and communication unit 609, such as network card, modem, wireless transceiver, etc. Communication unit 609 allows device 600 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0100] The computing unit 601 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 601 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 601 performs the various methods and processes described above, such as the core board stress testing method. For example, in some embodiments, the core board stress testing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on device 600 via ROM 602 and / or communication unit 609. When the computer program is loaded into RAM 603 and executed by the computing unit 601, one or more steps of the core board stress testing method described above may be performed. Alternatively, in other embodiments, the computing unit 601 may be configured to perform the core board stress testing method by any other suitable means (e.g., by means of firmware).

[0101] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0102] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0103] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0104] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0105] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with embodiments of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.

[0106] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, servers in distributed systems, or servers incorporating blockchain technology.

[0107] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0108] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A core board stress testing method, comprising: Deploy startup scripts to at least two core boards in the server under test so that the core boards run the startup scripts during the startup process to ensure that the core boards start in a normal state; the startup scripts are built based on software faults that have occurred in the history of the core boards and include at least one software repair program to fix known software faults of the core boards; Send network connection requests to at least two core boards in the server under test; each core board is a separate processing unit in the server under test. Upon receiving a feedback message from the core board regarding the network connection request, a stress test command is sent to the core board; the stress test command includes at least one of core board restart or simulating a core board kernel crash; If no feedback message regarding the network connection request is received from the core board within the set time period, a network probe command is sent to the core board. The network status of the core board is determined based on its response time to network probe commands. The core board operation log is captured by a log capture device during the execution of the stress test command; the log capture device is connected to at least two core boards in the server under test via a serial port.

2. A core board stress testing system, comprising a stress testing server, a log capture device, and a server under test; the server under test includes at least two core boards; the stress testing server and the core boards in the server under test are communicatively connected; the log capture device is communicatively connected to at least two core boards in the server under test via a serial port; wherein The stress testing server is used to execute the core board stress testing method described in claim 1; The core board is used to repair at least one software fault by running a pre-deployed startup script, and to execute load test commands sent by the load test server; the startup script includes at least one software repair program. The log capture device is used to capture the core board operation logs of the at least two core boards during the execution of stress test commands.

3. The system of claim 2, wherein, The core board is specifically used for: Execute the load testing commands sent by the load testing server and record the command execution log during the load testing command execution process.

4. A core board pressure testing device, comprising: The script deployment module is used to deploy startup scripts to at least two core boards in the server under test, so that the core boards run the startup scripts during the startup process to ensure that the core boards start in a normal state; the startup scripts are built based on software faults that have occurred in the history of the core boards, and include at least one software repair program to repair known software faults of the core boards; A network connection request sending module is used to send network connection requests to at least two core boards in the server under test; each core board is a separate processing unit in the server under test. The load test command sending module is used to send a load test command to the core board upon receiving a feedback message from the core board regarding the network connection request; the load test command includes at least one of core board restart or simulating core board kernel crash; The network detection command sending module is used to send a network detection command to the core board if no feedback message for the network connection request is received from the core board within a set time period. The network status determination module is used to determine the network status of the core board based on the response time of the core board to the network probe command. The log capture module is used to capture the core board's operation log during the execution of stress test commands by the core board through a log capture device; the log capture device is connected to at least two core boards in the server under test via a serial port.

5. An electronic device, comprising: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, which, when executed by the at least one processor, enables the at least one processor to perform the core board stress testing method of claim 1.

6. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions are used to cause the computer to execute the core board stress testing method according to claim 1.

7. A computer program product comprising a computer program / instructions that, when executed by a processor, implement the core board stress testing method according to claim 1.

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