Digital-to-analog converter

Abstract

A digital-to-analog converter (DAC) includes: a plurality of DAC transistor devices having an input side and an output side, the input side being configured to be selectively coupled to a system voltage based on a digital input signal and the output side being configured to provide an analog output signal; a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices being configured as variable resistors; and control circuitry configured to adjust the bias of the non-DAC transistor devices.

Description

[0001] Priority requirements

[0002] This application claims priority to non-provisional application No. 16 / 577,074, filed on September 20, 2019, entitled “DIGITAL-TO-ANALOG CONVERTER,” which has been assigned to the assignee of this application and is expressly incorporated herein by reference. Technical Field

[0003] This disclosure relates generally to electronic devices, and more specifically to digital-to-analog converters. Background Technology

[0004] Wireless communication devices and technologies are becoming increasingly prevalent. Wireless communication devices typically transmit and receive communication signals. These signals are usually processed by a variety of different components and circuits. One type of circuit that processes communication signals is a phase-locked loop (PLL). A PLL is a device that compares the phase and / or frequency of two different signals and generates an error signal representing the phase and / or frequency difference between the two compared signals. When two signals have different phases and / or frequencies, the phase and / or frequency difference between them is constantly changing. The error signal is then used to control the phase and / or frequency of the loop so that when the phase and / or frequency difference between the two signals is fixed, the two signals are at the same phase and / or frequency. Digital PLLs (DPLLs) typically include phase detectors and / or frequency comparators or detectors, digitally controlled oscillators (DCOs) whose frequency can be adjusted based on control voltage or current signals, filter circuits, feedback circuits, and may include other circuits such as buffer circuits. A DCO may include a digital-to-analog converter (DAC) and an oscillator.

[0005] The term "5G" refers to an evolving wireless communication technology. This evolving technology enables communication at higher frequencies than LTE, such as millimeter-wave (mmW) frequencies. For example, millimeter-wave signals are those that operate at extremely high frequencies, such as 20-30 GHz and higher. A PLL designed to operate at millimeter-wave frequencies may need to meet stringent design and / or performance specifications. The DCO included in the PLL may also have stringent design and / or performance specifications. A high-performance DAC is expected to be provided. Summary of the Invention

[0006] Various implementations of the systems, methods, and apparatus within the scope of the appended claims each have several aspects, none of which alone is responsible for the desired properties described herein. Without limiting the scope of the appended claims, some prominent features are described herein.

[0007] Details of one or more implementations of the subject matter described in this specification are set forth in the accompanying drawings and the following description. Other features, aspects, and advantages will become apparent from the description, drawings, and claims. Note that the relative dimensions in the following drawings may not be drawn to scale.

[0008] One aspect of this disclosure provides a digital-to-analog converter (DAC) comprising: a plurality of DAC transistor devices having an input side and an output side, the input side being configured to be selectively coupled to a system voltage based on a digital input signal, and the output side being configured to provide an analog output signal; a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices being configured as variable resistors; and control circuitry configured to adjust the bias of the non-DAC transistor devices.

[0009] Another aspect of this disclosure provides a method for operating a digital-to-analog converter (DAC), the method comprising: providing a variable resistor at the input side of the DAC; providing a signal indicating a voltage margin to a control circuit; and adjusting the variable resistor using the control circuit.

[0010] Another aspect of this disclosure provides an apparatus comprising: means for providing a variable resistor at the input side of a digital-to-analog converter (DAC); means for providing a signal indicating a voltage margin; and means for adjusting the variable resistor based on the signal indicating the voltage margin.

[0011] Another aspect of this disclosure provides a phase-locked loop (PLL) circuit, comprising: a phase detector configured to provide a control signal; a filter configured to receive the control signal and provide a filtered voltage signal; and a digitally controlled oscillator (DCO) configured to receive the filtered voltage signal, the DCO having a digital-to-analog converter (DAC) circuit and a ring oscillator. The DAC circuit includes: a plurality of DAC transistor devices, the input side of which is coupled to the output of the filter and the output side of which is coupled to the ring oscillator; and a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices being configured as variable resistors. Attached Figure Description

[0012] In the accompanying drawings, unless otherwise specified, the same reference numerals refer to the same parts in various views. For reference numerals designated with letter characters such as "102a" or "102b", the letter character designation can distinguish two similar parts or elements present in the same drawing. When the reference numerals are intended to cover all parts with the same reference numerals in all drawings, the letter character designation of the reference numerals may be omitted.

[0013] Figure 1This is a diagram showing a wireless device communicating with a wireless communication system.

[0014] Figure 2 This is a block diagram illustrating a wireless device that can implement exemplary technologies of this disclosure.

[0015] Figure 3 This is a simplified block diagram of a PLL circuit.

[0016] Figure 4 To show in more detail Figure 3 A schematic diagram of an exemplary embodiment of the DCO.

[0017] Figure 5 yes Figure 3 or Figure 4 Detailed schematic diagram of an exemplary embodiment of the DCO.

[0018] Figure 6 yes Figure 5 A detailed schematic diagram of an exemplary embodiment of a digitally controlled oscillator (DCO), the DCO including... Figure 5 An exemplary embodiment of the operating condition circuit.

[0019] Figure 7 This is a schematic diagram of an exemplary embodiment of DCO, showing in more detail... Figure 6 An exemplary embodiment of the operating condition circuit.

[0020] Figure 8 This is a detailed schematic diagram of an exemplary embodiment of a digitally controlled oscillator (DCO), which is similar to... Figure 5 DCO, including Figure 5 An exemplary embodiment of the operating condition circuit.

[0021] Figure 9 This is a schematic diagram of an exemplary embodiment of DCO, showing in more detail... Figure 8 An exemplary embodiment of the operating condition circuit.

[0022] Figure 10 This is a detailed schematic diagram of an exemplary embodiment of a digitally controlled oscillator (DCO), which is similar to... Figure 5 DCO, including Figure 5 An exemplary embodiment of the operating condition circuit.

[0023] Figure 11 This is a schematic diagram of an exemplary embodiment of DCO, showing in more detail... Figure 9 An exemplary embodiment of the operating condition circuit.

[0024] Figure 12 This is a flowchart illustrating an operational example of a DAC circuit according to an exemplary embodiment of the present disclosure.

[0025] Figure 13 This is a functional block diagram of a device for a DAC circuit according to exemplary embodiments of the present disclosure. Detailed Implementation

[0026] This document uses the term "exemplary" to mean "used as an example, instance, or illustration." Any aspect described as "exemplary" in this document should not be construed as preferred or superior to other aspects.

[0027] A PLL designed to operate at mmW frequencies should meet very stringent integrated phase noise (IPN) specifications, which may include strict 1 / f noise specifications for a DCO and the ability to have a wide frequency tuning range. A wide-tuning-range PLL can have a tuning range, for example, from 600MHz to 4.5GHz, so a DAC with a wide current output range is also beneficial for supporting the wide frequency tuning range of the PLL.

[0028] DACs can be implemented using, for example, metal-oxide-semiconductor (MOS) technology, and can be P-type (PMOS), N-type (NMOS), or a combination of PMOS and NMOS. When implemented using PMOS technology, the DAC may generate significant phase noise at the PLL output, with the dominant noise type from the low offset frequencies of a PMOS DAC being referred to as "flicker noise" or "1 / f noise." Low offset frequencies refer to frequencies with a small frequency shift from the DAC's carrier or operating frequency. Flicker noise is electronic noise with a power spectral density of "1 / f." The term "1 / f noise" can be defined as a signal or process with a spectrum such that the power spectral density (energy or power per frequency interval) is inversely proportional to the frequency of the signal. This noise is typically high at lower offset frequencies and difficult to filter out. Therefore, a DAC with a wide current range and low flicker noise can be advantageous. Flicker noise can be reduced by increasing the width and length of the transistors that include the DAC to make it larger. However, increasing the overall width and length of the DAC may require costly trade-offs in a wide-tuning-range PLL, as the DAC typically occupies a large area to provide a wide range of output currents. Furthermore, adding such an already large DAC could result in an undesirable increase in required area and power consumption.

[0029] Exemplary embodiments of this disclosure pertain to a DAC circuit. The DAC circuit can implement active negative feedback (degeneration), for example, reducing low-frequency 1 / f noise in the DAC. In an exemplary embodiment, a non-DAC transistor device can be implemented at the input side of the DAC transistor device. The non-DAC transistor device can be implemented to create a variable resistance at the input side of the DAC transistor device. The non-DAC transistor device can be configured to provide an adjustable negative feedback resistance to the DAC transistor device. The resistance of the non-DAC transistor device can be controlled by control circuitry that can receive feedback signals from operating condition circuitry. The operating condition circuitry can respond to one or more of the DAC's current output and the DAC's system voltage level.

[0030] This document describes embodiments of a DAC implemented in a PLL and / or DCO, such as in a wireless device. Furthermore, DACs for certain frequency ranges are described in some aspects. However, those skilled in the art will understand that the teachings herein can be used with DACs that can be implemented in combination with any number of devices or applications, including applications outside of PLLs and DCOs and in devices other than wireless devices and / or having any number of different frequency ranges.

[0031] Figure 1 This diagram illustrates communication between wireless device 110 and wireless communication system 120. Wireless communication system 120 can be a Long Term Evolution (LTE) system, a Code Division Multiple Access (CDMA) system, a Global System for Mobile Communications (GSM) system, a Wireless Local Area Network (WLAN) system, a 5G system, or some other wireless system. The CDMA system can implement Wideband CDMA (WCDMA), CDMA 1X, Evolved Data Optimized (EVDO), Time Division Synchronous CDMA (TD-SCDMA), or some other version of CDMA. For simplicity, Figure 1 A wireless communication system 120 is shown, comprising two base stations 130 and 132 and a system controller 140. Typically, a wireless communication system may include any number of base stations and any set of network entities.

[0032] Wireless device 110 may also be referred to as user equipment (UE), mobile station, terminal, access terminal, subscriber unit, station, etc. Wireless device 110 may be a cellular phone, smartphone, tablet computer, wireless modem, personal digital assistant (PDA), handheld device, laptop computer, smart notebook computer, internet-enabled notebook computer, tablet computer, cordless phone, medical device, device configured to connect to one or more other devices (e.g., via the Internet of Things), wireless local loop (WLL) station, Bluetooth device, etc. Wireless device 110 can communicate with wireless communication system 120. Wireless device 110 can also receive signals from broadcast stations (e.g., broadcast station 134), signals from one or more satellites in a Global Navigation Satellite System (GNSS) (e.g., satellite 150), etc. Wireless device 110 may support one or more radio technologies for wireless communication, such as LTE, WCDMA, CDMA 1X, EVDO, TD-SCDMA, GSM, 802.11, 5G, etc.

[0033] Wireless device 110 may support carrier aggregation, for example, as described in one or more LTE or 5G standards. In some embodiments, a single data stream is transmitted over multiple carriers using carrier aggregation, for example, relative to a separate carrier for the respective data stream.

[0034] Wireless device 110 can operate in a low-frequency band (LB) covering frequencies below 1000 MHz, a mid-frequency band (MB) covering frequencies from 1000 MHz to 2300 MHz, and / or a high-frequency band (HB) covering frequencies above 2300 MHz. For example, the low-frequency band can cover 698 to 960 MHz, the mid-frequency band can cover 1475 to 2170 MHz, and the high-frequency band can cover 2300 to 2690 MHz and 3400 to 3800 MHz. The low-frequency, mid-frequency, and high-frequency bands refer to three groups of frequency bands (or band sets), each group comprising several frequency bands (or simply "bands"). Each band can cover up to 200 MHz and may include one or more carriers. In LTE, each carrier can cover up to 20 MHz. LTE Release 11 supports 35 bands, referred to as LTE / UMTS bands and listed in 3GPP TS 36.101. In LTE Release 11, the wireless device 110 can be configured with up to five carriers in one or two frequency bands. The wireless device 110 can also operate at frequencies higher than 3800MHz, such as frequencies up to 6GHz and / or millimeter wave frequencies.

[0035] Wireless device 110 can also communicate with wireless device 160. In an exemplary embodiment, wireless device 160 may be a wireless access point or another wireless communication device that includes part of a wireless local area network (WLAN). An exemplary embodiment of the WLAN signal may include WiFi or other communication signals using, for example, unlicensed communication spectrum in the 5 GHz to 6 GHz range.

[0036] Carrier aggregation (CA) can generally be divided into two types—intra-band CA and inter-band CA. Intra-band CA refers to operation on multiple carriers within the same frequency band. Inter-band CA refers to operation on multiple carriers in different frequency bands.

[0037] Figure 2 This is a block diagram illustrating a wireless device 200 that can implement the exemplary techniques of this disclosure. Figure 2 An example of transceiver 220 is shown. Generally, signal conditioning in transmitter 230 and receiver 250 can be performed by one or more stages such as amplifiers, filters, up-converters, down-converters, etc. These circuit blocks may differ from... Figure 2 Arranged as shown in the diagram. Furthermore, Figure 2 Other circuit blocks, not shown, can also be used to regulate the signals in transmitter 230 and receiver 250. Unless otherwise stated, Figure 2 Any signal in any of the other diagrams in the attached figures can be single-ended or differential. Figure 2 Some circuit blocks can also be omitted.

[0038] exist Figure 2 In the example shown, wireless device 200 typically includes a transceiver 220 and a data processor 210. Data processor 210 may include memory (not shown) for storing data and program code and may typically include both analog and digital processing elements, or may include only digital processing elements. Transceiver 220 includes a transmitter 230 and a receiver 250 supporting bidirectional communication. Typically, wireless device 200 may include any number of transmitters and / or receivers for any number of communication systems and frequency bands. All or part of transceiver 220 may be implemented on one or more analog integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc.

[0039] Transmitters or receivers can be implemented using either superheterodyne or direct conversion architectures. In a superheterodyne architecture, the signal undergoes frequency conversion in multiple stages between radio frequency (RF) and baseband; for example, from RF to intermediate frequency (IF) in one stage, and then from IF to baseband in another stage at the receiver. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband or near-baseband in a single stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. Figure 2 In the example shown, transmitter 230 and receiver 250 are implemented using a direct conversion architecture.

[0040] In the transmission path, data processor 210 processes the data to be transmitted and provides in-phase (I) and quadrature (Q) analog output signals to transmitter 230. In an exemplary embodiment, data processor 210 includes digital-to-analog converters (DACs) 214a and 214b for converting the digital signals generated by data processor 210 into I and Q analog output signals, such as I and Q output currents, for further processing. In other embodiments, DACs 214a and 214b are included in transceiver 220 and data processor 210 provides data (e.g., for I and Q) digitally to transceiver 220.

[0041] Within transmitter 230, low-pass filters 232a and 232b filter the I and Q analog transmit signals, respectively, to remove unwanted images caused by the previous digital-to-analog conversion. Amplifiers (Amp) 234a and 234b amplify the signals from low-pass filters 232a and 232b, respectively, and provide I and Q baseband signals. Upconverter 240 upconverts the I and Q baseband signals using the I and Q transmit (TX) local oscillator (LO) signals from TX LO signal generator 290, and provides upconverted signals. Filter 242 filters the upconverted signals to remove unwanted images caused by upconversion and noise in the receive band. Power amplifier (PA) 244 amplifies the signal from filter 242 to obtain the desired output power level and provide the transmit RF signal. The transmit RF signal is routed via duplexer or switch 246 and transmitted via antenna 248.

[0042] The power amplifier 244 may include one or more stages, such as driver stages, power amplifier stages, or other components. These stages may be configured to amplify communication signals in one or more frequency bands and at one or more power levels. Depending on various factors, the power amplifier 244 may be configured to operate using one or more bias signals and may be configured in various topologies or architectures.

[0043] In the receiving path, antenna 248 receives communication signals and provides the received RF signals, which are routed via a duplexer or switch 346 and provided to a low-noise amplifier (LNA) 252. Duplexer 246 is designed to operate under a specific RX-TX duplexer frequency separation, isolating the RX and TX signals. The received RF signals are amplified by LNA 252 and filtered by filter 254 to obtain the desired RF input signals. Down-conversion mixers 261a and 261b mix the output of filter 254 with the I and Q received (RX) LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 280 to generate I and Q baseband signals. The I and Q baseband signals are amplified by amplifiers 262a and 262b and further filtered by low-pass filters 264a and 264b to obtain the I and Q analog input signals provided to data processor 210. In the exemplary embodiment shown, the data processor 210 includes analog-to-digital converters (ADCs) 216a and 216b for converting analog input signals into digital signals for further processing by the data processor 210. In some embodiments, ADCs 216a and 216b are included in a transceiver 220 and provide data digitally to the data processor 210.

[0044] exist Figure 2 In this configuration, TX LO signal generator 290 generates I and Q TX LO signals for up-conversion, while RX LO signal generator 280 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. Phase-locked loop (PLL) 292 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the TX LO signals from LO signal generator 290. Similarly, PLL 282 receives timing information from data processor 210 and generates control signals for adjusting the frequency and / or phase of the RX LO signals from LO signal generator 280.

[0045] Wireless device 200 may support carrier aggregation (CA) and may (i) receive multiple downlink signals transmitted by one or more cells on multiple downlink carriers at different frequencies and / or (ii) transmit multiple uplink signals to one or more cells on multiple uplink carriers. However, those skilled in the art will understand that the aspects described herein can be implemented in systems, devices, and / or architectures that do not support carrier aggregation.

[0046] Some components of transceiver 220 Figure 2The configurations shown herein may or may not represent the physical device configuration in some implementations. For example, as described above, transceiver 220 can be implemented in various integrated circuits (ICs), RF ICs (RFICs), mixed-signal ICs, etc. In some embodiments, transceiver 220 is implemented on a substrate or board, such as a printed circuit board (PCB) with various modules. For example, PA 244, filter 242, and duplexer 246 can be implemented in separate modules or as discrete components, while the remaining components shown in transceiver 220 can be implemented in a single transceiver chip. Furthermore, although Figure 2 The I and Q signals are illustrated, but those skilled in the art will understand that transceiver 220 may alternatively use a polar architecture, or may include elements for implementing a polar architecture in addition to an orthogonal architecture.

[0047] Exemplary embodiments of this disclosure relate to a DAC, which may include active negative feedback and may be implemented in a digitally controlled oscillator (DCO), which may be part of, or implemented in, an RX PLL 282 and / or a TX PLL 292 or other components.

[0048] Figure 3 This is a simplified block diagram of PLL circuit 300. PLL circuit 300 may be an example of the RX PLL 282 or TXPLL 292 described herein. In an exemplary embodiment, PLL circuit 300 is an example of a digital PLL (DPLL). However, it should be understood that the embodiments described herein can also be applied to analog PLLs, and other types of PLLs. Figure 2 This refers to a PLL circuit other than the PLL circuit itself. For simplicity, this document uses the term PLL throughout to refer to either an analog PLL or a digital PLL. In an exemplary embodiment, the PLL circuit 300 includes a phase detector (PD) 304, a filter 306, a digitally controlled oscillator (DCO) 308, and a feedback circuit, which may include a programmable 1 / N divider (NDIV) 309. In an exemplary embodiment, the filter 306 may be a digital low-pass filter (LPF) and may also be referred to as a loop filter.

[0049] Reference frequency fref and input phase φ ref The input signal is provided to the phase detector 304 via connection 302. In an exemplary embodiment, the phase detector 304 may include a phase comparator or other circuitry that, after processing by the programmable divider 309, is based on a frequency fout and an output phase φ. out The output signal will connect the phase of the input signal on 302 and the feedback signal (φ) on 319.div The phase detector 304 compares the signal phases at connections 302 and 319 and generates a digitized output `dout` at connection 313 based on the phase difference between the signal phase at connection 302 and the feedback signal phase at connection 319. The output `dout` of the phase detector at connection 313 is then low-pass filtered by a digital low-pass filter 306. In an exemplary embodiment, filter 306 removes high-frequency noise from the signal `dout` at connection 313 and provides one or more DAC codes contained in a frequency codeword (FCW) at connection 314.

[0050] The DAC code in the FCW on connection 314 is then provided to DCO 308, which provides a frequency fout and an output phase φ. out The output signals of the DCO 308. The output signals of the DCO 308 (fout and φ) out The frequency and phase of the input signal (fref and φ) are related to the frequency and phase of the input signal. ref It is proportional to the input phase φ of fref. ref and the output phase φ of fout out The comparison and adjustment are performed using feedback path 318 until the output phase φ is reached. out Equal to the input phase φ ref Up to this point. The programmable frequency divider 309 can be, for example, Figure 2 The data processor 210 is programmed to provide n-division multiplexing (NDIV) functionality. The PLL circuit 300 operates in three stages: free-running, capture, and phase-locked.

[0051] In an exemplary embodiment, the phase detector 304 may be a phase comparator circuit that compares the input phase φref with the phase (φ) of the frequency-divided DCO clock at connection 319. div ), and generate a digital output dou, which is related to the input phase φ. ref Phase φ of the frequency divider DCO clock div The phase difference between them is proportional.

[0052] In an exemplary embodiment, filter 306 attenuates high-frequency noise in the output of phase detector 304, thereby helping to control the dynamic characteristics of PLL circuit 300. Dynamic characteristics include capture and lock-in range, bandwidth, and transient response. Lock-in range is the frequency range of PLL circuit 300 that tracks changes in the input frequency and phase. Capture range is the range within which PLL circuit 300 achieves phase lock. When locked via the feedback loop of programmable divider 309, DCO 308 generates an output frequency fout such that fout = NDIV * fref.

[0053] Figure 4 To show in more detail Figure 3 A schematic diagram of an exemplary embodiment 408 of a DCO. In the exemplary embodiment, the DCO 408 includes a digital-to-analog converter (DAC) 402 and a ring oscillator 406. A digital low-pass filter 306 ( Figure 3 The output of ) is connected to 314 ( Figure 3 ) and provided to DAC 402 ( Figure 3 DAC 402 generates a current called Idco, which is supplied to ring oscillator 406 through connection 407. The output fout of ring oscillator 406 on connection 316 responds to the current signal Idco on connection 407.

[0054] Ring oscillator 406 includes an odd number of inverters configured in a ring, whose outputs oscillate between two voltage levels representing logic values ​​of true and false. The inverters are configured in a chain, and the output of the last inverter is fed back to the first inverter. In an exemplary embodiment, ring oscillator 406 includes inverters 412, 414, and 416 and capacitors 413, 415, and 417. Capacitors 413, 415, and 417 may be referred to as load capacitors and represent the effective capacitive load C at the output of each respective inverter stage 412, 414, and 416. load Current Idco is supplied to each inverter via bus 409. Output fout (φ) out ) via connection 316 ( Figure 3 () is taken from inverter 416 and controlled by the current Idco connected to 407. Although Figure 4 The diagram shows three inverter stages 412, 414, and 416 and three capacitors 413, 415, and 417, but the ring oscillator 406 may include more inverter stages and capacitors.

[0055] Figure 5 yes Figure 3 or Figure 4 A detailed schematic diagram of an exemplary embodiment 500 of a digitally controlled oscillator (DCO). In the exemplary embodiment, the DCO 500 includes a digital-to-analog converter (DAC) circuit 510 and a ring oscillator 406 ( Figure 4 In an exemplary embodiment, the DAC circuit 510 includes a plurality of DAC transistor devices 512, 514, and 516. In an exemplary embodiment, the DAC transistor devices 512, 514, and 516 may be implemented using P-type metal-oxide-semiconductor (PMOS) transistor devices and may be configured to generate a current (Idco) on connection 518, which may be used to control the frequency of the ring oscillator 406. The DAC transistor devices 512, 514, and 516 may also be referred to as DAC PMOS transistor devices.

[0056] The value of the current Idco on connection 518 is proportional to and controls the output frequency of the ring oscillator 406, and when implemented in a phase-locked loop (PLL) circuit, it can be controlled at connection 316 of the PLL circuit. Figure 3 and Figure 4 The frequency output fout of the ring oscillator 406 is formed on the connection (node) 518. As the current Idco on connection 518 increases, the frequency fout on connection 316 increases proportionally to the current Idco on connection 518, and decreases proportionally to the current Idco on connection 316. Connection 518 represents the output of the DAC circuit 510 and the input of the ring oscillator 406. In some applications, a wide tuning range is desired for the PLL, provided that the maximum jitter requirement (1 / f noise) is met so that the PLL can cover a wide range of output frequencies. Since the frequency output fout increases with the current Idco, it is generally beneficial for the PLL to provide a wide range of currents for the DAC output to achieve a wide tuning range.

[0057] DAC circuit 510 also includes an operational amplifier (OpAmp) 522, which is configured to equalize the voltage input Vres at the non-inverting input 552 and the voltage input Vdco at the inverting input 554. OpAmp 522 is configured to linearize the frequency response fout of the ring oscillator 406 output by controlling the voltage supplied to the gate terminals of DAC transistor devices 512, 514, and 516 at node 524, such that, as will be described below, the linear response of the output frequency fout enables the frequency codeword (FCW) of the DAC transistor devices 512, 514, and 516. In other embodiments, components for linearizing the output frequency response fout are omitted.

[0058] According to an exemplary embodiment, the DAC circuit 510 further includes a plurality of additional non-DAC transistor devices 542, 544, 546, and 548. In an exemplary embodiment, the non-DAC transistor devices 542, 544, 546, and 548 may be implemented as PMOS devices and may be configured to operate in the transistor region such that the on-resistance Ron of each of the non-DAC transistor devices 542, 544, 546, and 548 is controlled by its respective gate voltage and also scaled inversely to its overdrive voltage. As used herein, the term “overdrive voltage” (Vov) for an NMOS transistor device is equal to the gate-source voltage (Vgs) of the device minus the NMOS threshold voltage (Vthn); and for a PMOS transistor device, the overdrive voltage Vov is equal to the source-gate voltage (Vsg) minus the absolute PMOS threshold voltage (abs(Vthp)) (i.e., for NMOS, Vov = Vgs - Vthn, and for PMOS, Vov = Vsg - abs(Vthp)). In the configuration shown in DAC circuit 510, non-DAC transistor devices 544, 546, and 548 are used as negative feedback transistors 512, 514, and 516, respectively, and in such an exemplary embodiment, may also be referred to as MOS negative feedback transistor devices. Non-DAC transistor devices 544, 546, and 548 may include an active MOS negative feedback circuit 540. Although not considered a MOS negative feedback transistor device, non-DAC transistor device 542 also serves as a voltage-dependent resistor and as a reference non-DAC transistor device for non-DAC transistor devices 544, 546, and 548. The gate of each of the non-DAC transistor devices 542, 544, 546, and 548 is coupled to control circuitry 530 via connection 566. In an exemplary embodiment, control circuitry 530 may also be interchangeably referred to as a bias circuit, a MOS adjustment circuit, or a negative feedback MOS bias circuit.

[0059] In applications requiring a wide-range PLL, the DAC circuit 510 can be configured to provide a wide range of output currents Idco to cover the desired frequency range of the DCO 500 to support the wide tuning range of the PLL. In such applications, multiple MOS tuning units can be used in the DAC to provide the desired range of output current Idco. For example, each selectively enabled MOS tuning unit can provide a certain amount of current, where the total current provided by the selectively enabled MOS tuning units includes the output current Idco.

[0060] exist Figure 5In an exemplary embodiment, for example, to selectively contribute a portion of the current to the output current Idco, large ctune (LCT) units 572, 574, and 576 can be configured as MOS tuning units in the DAC circuit 510. Figure 5 In the configuration shown, the large ctune (LCT) unit 572 includes transistors 544 and 512; and the large ctune (LCT) unit 574 includes transistors 546 and 514. Similarly, the ctune (CT) unit 576 includes transistors 548 and 516. Figure 5 In the exemplary embodiment shown, the difference between CT unit 576 and LCT units 572 and 574 is that transistors 544, 512, 546, and 514 in LCT units 572 and 574 are larger than transistors 548 and 516 in CT unit 576. Similarly, the switching transistors (not shown) in LCT units 572 and 574 are larger than the switching transistors (not shown) in CT unit 576. In the exemplary embodiment, the transistors in LCT units 572 and 574 can be 48 times (48x) larger than the transistors in CT unit 576. Generally, the larger the transistor device, the lower the resistance. In the exemplary embodiment, each unit in LCT unit 572, LCT unit 574, and CT unit 576 represents one of a plurality of LCT units and CT units. Figure 5 In the exemplary embodiment shown, there are N+1 LCT units 572 (LCTs) <n:0>The system comprises 15 LCT units 574 (LCT<14:0>) and 256 CT units 576 (CT<255:0>). In an exemplary embodiment, N+1 LCT units 572 are always on. In an exemplary embodiment, the state of each LCT unit in the 15 LCT units 574 is controlled by information contained in the DCO code (FCW) provided to the 15 LCT units 574. Similarly, the state of each CT unit in the 256 CT units 576 is controlled by information contained in the DCO code represented by the FCW provided to the 256 CT units 576. For example, if the FCW is provided by a 12-bit wide bus, the FCW can be written as FCW<11:0>. The lower eight (8) bits of the FCW (FCW<7:0>) can be used to control the state of the 256 CT units 576; and the higher four (4) bits of the FCW (FCW<11:8>) can be used to control the state of the 15 LCT units 574. When CT unit 576 or LCT unit 574 is turned on, it provides a certain amount of current, which is limited by the size of the transistors in CT unit 576 and LCT unit 574. To support higher output frequencies (e.g., higher frequency fout on connection 316), more LCT units 574 and CT units 576 are turned on by DCO FCW, resulting in a higher current Idco at node 518 and a higher output frequency fout on connection 316. Similarly, at lower output frequencies, fewer LCT units 574 and CT units 576 are turned on, resulting in a lower current Idco and a lower output frequency fout.

[0061] An exemplary MOS tuning unit is shown using reference numeral 580. In an exemplary embodiment, the MOS tuning unit 580 may be as follows: Figure 5 The general representation of any tuning unit shown is for the large ctune (LCT) unit 572 or 574 or the ctune (CT) unit 576. However, as Figure 5 As shown, large cune (LCT) units 572 and 574 and cune (CT) unit 576 are illustrated in a simplified form, where the switching transistor device 586 is not shown. However, each tuning unit in the large cune (LCT) units 572 and 574 and the cune (CT) unit 576 can be implemented with an architecture similar to that of tuning unit 580. MOS tuning unit 580 may include switching transistor device 586, non-DAC transistor device 584 (e.g., a negative feedback transistor device), and DAC transistor device 582. Switching transistor device 586 can be configured to receive a frequency codeword (FCW) at its gate via connection 314 as an enable signal, and its source can be coupled to the system voltage Vdd via connection 541. Therefore, tuning unit 580 is configured to be selectively enabled based on FCW; the value of FCW will determine whether switch 586 is open or closed, and thus determine whether current is supplied by tuning unit 580. The drain of the switching transistor device 586 can be coupled to the source of the non-DAC transistor device 584; and the drain of the non-DAC transistor device 584 can be coupled to the source of the DAC transistor device 582. The drain of the DAC transistor device 582 can be coupled to node 518. The gate of the non-DAC transistor device 584 can be coupled to connection 566 and the gate of the DAC transistor device 582 can be coupled to connection 524. In an exemplary embodiment for a given MOS tuning unit 580, the relative dimensions of the switching transistor device 586, the non-DAC transistor device 584, and the DAC transistor device 582 can be the same. Furthermore, the non-DAC transistor device 584 and the DAC transistor device 582 can be configured to flow a defined amount of current based on their dimensions and the bias signal at the respective gate connections 566 and 524 when the switching transistor device 586 is closed / enabled.

[0062] Capacitor 543 is coupled between the system voltage Vdd at connection 541 and the gates of DAC transistor devices 512, 514, and 516. Resistor 556 is coupled between the drain of DAC transistor device 512 and system ground. Capacitor 558 is coupled between the inverting input of OpAmp 522 at connection 554 and system ground. As described above, OpAmp 522 makes the voltage Vres at connection 552 equal to the voltage Vdco at connection 554, and linearizes the frequency response of ring oscillator 406. The output frequency of ring oscillator 406 at connection 316 is linearly proportional to the DAC code represented by FCW, such that the output frequency fout = C / (R*C) load )*FCW. In this example, C load is the effective capacitive load at the output of each inverter stage in the ring oscillator 406, R is the value of resistor 556, and C is a constant determined by the size ratio of LCT unit 574 and CT unit 576 and the number of LCT units 572.

[0063] In an exemplary embodiment, non-DAC transistor devices 544, 546, and 548 are coupled at the input side of the DAC circuit 510, i.e., the drain terminals of non-DAC transistor devices 544, 546, and 548 are coupled to the source terminals of DAC transistor devices 512, 514, and 516, respectively. In an exemplary embodiment, non-DAC transistor devices 544, 546, and 548 may include a MOS negative feedback circuit 540. In an exemplary embodiment, DAC transistor devices 512, 514, and 516 may be collectively referred to as DAC transistor device 525. Although three DAC transistor devices 512, 514, and 516 and three corresponding non-DAC transistor devices 544, 546, and 548 are shown at the input, i.e., the drain terminals of non-DAC transistor devices 544, 546, and 548 are coupled to the source terminals of DAC transistor devices 512, 514, and 516, other numbers of DAC transistor devices and non-DAC transistor devices are possible depending on the implementation.

[0064] In some implementations, at lower offset frequencies, the noise contributed by the DAC transistors 512, 514, and 516 (i.e., PMOS transistors) to the current Idco on connection 518 is difficult to eliminate. Adding negative feedback resistors to the source terminals of the DAC transistors 512, 514, and 516 can significantly reduce the low-frequency noise generated by the DAC transistors 512, 514, and 516. Conventional resistors may be difficult to implement in circuit layout and may not scale well with the dimensions of the DAC transistors 512, 514, and 516. For example, using conventional resistors in each of these DAC tuning units (LCT units 572 and 574, CT unit 576) could result in a very large DAC area, which is undesirable.

[0065] According to an exemplary embodiment, the negative feedback resistor added to the source (i.e., input) of each of the DAC transistor devices 512, 514, and 516 can be implemented using non-DAC transistor devices 544, 546, and 548 as the negative feedback resistors for the respective DAC transistor devices 512, 514, and 516, respectively. The resistance value provided by each of the non-DAC transistor devices 544, 546, and 548 can be controlled by the voltage at the gate of the non-DAC transistor devices 542, 544, 546, and 548 when the non-DAC transistor devices 542, 544, 546, and 548 are operated in the transistor region.

[0066] According to an exemplary embodiment, the non-DAC transistor device 542 can be configured as a reference negative feedback MOS transistor device or an adjustment transistor device to help limit the bias voltage based on the reference current Iref, and can also be configured to operate in the transistor region as described below. In the exemplary embodiment, the non-DAC transistor device 542 is interchangeably referred to herein as a reference negative feedback MOS transistor device or an adjustment transistor device.

[0067] The source of non-DAC transistor device 544 is coupled to the system voltage Vdd at connection 541, and the drain of non-DAC transistor device 544 is coupled to the source of DAC transistor device 512. The source of non-DAC transistor device 546 is coupled to the system voltage Vdd at connection 541, and the drain of non-DAC transistor device 546 is coupled to the source of DAC transistor device 514. The source of non-DAC transistor device 548 is coupled to the system voltage Vdd at connection 541, and the drain of non-DAC transistor device 548 is coupled to the source of DAC transistor device 516. The drain of DAC transistor device 512 is coupled to system ground via resistor 556. The drain of DAC transistor device 514 is coupled to the drain of DAC transistor device 516, and provides the current output Idco of DAC circuit 510 at node 518.

[0068] In an exemplary embodiment, the control circuit 530 includes a bias OpAmp 532, a resistor 533, a reference negative feedback MOS transistor device 542, a current source 534, N-type MOS (NMOS) transistor devices 535 and 536, and an NMOS transistor device 537. The NMOS transistor device 536 is connected as a diode. The inverting input of the bias OpAmp 532 is configured to receive a reference voltage Vref at connection 561, and the non-inverting input of the bias OpAmp 532 at connection 562 is configured to receive the output of the reference negative feedback MOS transistor device 542 at node 564, which is also coupled to the drain of the reference negative feedback MOS transistor device 542.

[0069] Current source 534 generates a reference current Iref, which flows into the drain of the diode-connected NMOS transistor device 536 at connection 539. NMOS transistor devices 535, 536, and 537 form a current mirror, and therefore, the reference current Iref also flows into the drain of NMOS transistor device 535 at connection 568 and into the drain of NMOS transistor device 537 at connection 538.

[0070] The reference current Iref appearing on connection 538 is coupled to node 564 and the drain of the reference negative feedback MOS transistor device 542. The output of bias OpAmp 532 is provided to the gate of each of the non-DAC transistor devices 542, 544, 546, and 548 through connection 566, thereby using the bias voltage generated by control circuitry 530 to control the gate voltage and resistance value of each of the non-DAC transistor devices 542, 544, 546, and 548.

[0071] Resistor 533 is coupled between the system voltage Vdd at connection 541 and the drain of NMOS transistor device 535. A value ΔV appears across resistor 533 such that the value of Vref, the inverting input of bias OpAmp 532 applied to connection 561, is lower than the system voltage Vdd at connection 541 by an amount ΔV.

[0072] OpAmp 532 ensures that the input voltages at connections 561 and 562 will be substantially equal, such that the voltage at node 564 is driven to be equal to the reference voltage Vref at connection 561. Since the reference voltage Vref is ΔV lower than the system voltage Vdd, the voltage at node 564 will also be ΔV lower than the system voltage Vdd. In this way, the drain-source voltage Vds of the reference negative feedback MOS transistor device 542 is also ΔV.

[0073] When ΔV is sufficiently low and sufficient current flows in the reference negative feedback MOS transistor 542, OpAmp 532 will drive the gate of the reference negative feedback MOS transistor 542, keeping it in the transistor region. In this case, the on-resistance Ron of the reference negative feedback MOS transistor 542 is the same as the resistance of resistor 533, because the on-resistance Ron of the reference negative feedback MOS transistor 542 is defined by dividing the voltage across the source-drain terminals of the reference negative feedback MOS transistor 542 (i.e., Vsd = ΔV = Iref * (resistance of resistor 533)) by the current flowing in the reference negative feedback MOS transistor 542. As a result, the on-resistance Ron of the reference negative feedback MOS transistor 542 is ΔV divided by Iref, which is equal to the resistance of resistor 533.

[0074] When the reference negative feedback MOS transistor device 542 is in the transistor region, it behaves as a resistor, and its resistance is controlled by the gate voltage across connection 566. Because the non-DAC transistor devices 544, 546, and 548 are electrically similar to the reference negative feedback MOS transistor device 542, their behavior will be similar, even though they may offer different resistances based on their relative dimensions. As stated above, given equivalent dimensions, the on-resistance Ron of the non-DAC transistor devices 542, 544, 546, and 548 can be configured to be substantially equal to the resistance of resistor 533. Since the gate voltages of non-DAC transistor devices 544, 546, and 548 are equal to the gate voltage of the reference negative feedback MOS transistor device 542, if the non-DAC transistor devices 544, 546, and 548 have the same dimensions as the reference negative feedback MOS transistor device 542, the on-resistance Ron of the non-DAC transistor devices 544, 546, and 548 will be approximately equal to the on-resistance Ron of the reference negative feedback MOS transistor device 542. However, in Figure 5 In the exemplary embodiment shown, the relative size of the reference negative feedback MOS transistor device 542 can be m=10, the relative size of the non-DAC transistor devices 544 and 546 can be m=48, and the relative size of the non-DAC transistor device 548 can be m=1, such that their corresponding on-resistance is proportional to their relative size. Figure 5 In the example shown, due to the size difference between non-DAC transistor devices 542, 544, 546, and 548, the corresponding resistance will be inversely proportional to the corresponding relative size difference. Thus, all other things being equal, the larger transistor device will generally provide a smaller resistance. For example, when the size of non-DAC transistor devices 544 and 546 is 48 times the size of non-DAC transistor device 548, the on-resistance Ron of transistor devices 544 and 546 will be 1 / 48 of the on-resistance Ron of non-DAC transistor device 548, because the on-resistance Ron is inversely proportional to the size of the transistor device. Given the relative sizes of the aforementioned non-DAC transistor devices 544, 546, and 548, non-DAC transistor device 548 will provide a larger resistance than non-DAC transistor devices 546 and 544.

[0075] The value of resistor 533 is selected based on the desired negative feedback resistance of non-DAC transistor devices 544, 546, and 548. Depending on the implementation, non-DAC transistor devices 542, 544, 546, and 548 may also be scaled differently to obtain the desired on-resistance Ron of non-DAC transistor devices 544, 546, and 548 suitable for LCT units 572 and 574 and CT unit 576.

[0076] The DAC circuit 510 also includes an operating condition circuit 570 coupled to node 564 via connection 567. The operating condition circuit 570 is configured to determine one or more operating conditions, aspects, or parameters of the DAC circuit 510, and may also be configured to provide a feedback signal to control circuit 530, which can be used to additionally control the current flowing through node 564, thereby controlling the current flowing through reference negative feedback MOS transistor device 542. The operating condition circuit 570 may also be referred to as a sensing circuit.

[0077] In an exemplary embodiment, the operating condition circuit 570 may be configured to sense the current supplied to the ring oscillator 406 at node 518 and provide a feedback signal to the control circuit 530 based on the current Idco to optimize the voltage margin of the DAC circuit 510 over a wide frequency range, where Idco is related to the frequency fout at connection 316.

[0078] In another exemplary embodiment, the operating condition circuit 570 may be configured to sense the voltage between connection 541, Vdd, and system ground, and provide a feedback signal to the control circuit 530 at node 564 based on the system voltage Vdd, so as to optimize the voltage margin of the DAC circuit 510 over a wide voltage range and improve the 1 / f noise performance of the DAC circuit 510.

[0079] In another exemplary embodiment, the operating condition circuit 570 may be configured to sense the current supplied to the ring oscillator 406 at node 518 and the voltage between connection 541, Vdd and system ground, and provide a feedback signal to the control circuit 530 at node 564 based on the current Idco and the system voltage Vdd to optimize the voltage margin of the DAC circuit 510 over a wide voltage range and improve the 1 / f noise performance of the DAC circuit 510.

[0080] Figure 6 This is a detailed schematic diagram of an exemplary embodiment of a digitally controlled oscillator (DCO) 600, which is similar to... Figure 5 DCO, including Figure 5 An exemplary embodiment of the operating condition circuit. Figure 6 Zhongyu Figure 5 Components that correspond to each other in the diagram are numbered the same and are not described in detail again. Figure 6 In an exemplary embodiment, the operating condition circuit 610 is represented by a current source 611, which is configured to respond to the output current Idco on connection 518. The output current Idco of the DAC circuit 515 increases with the output frequency of the ring oscillator 406, such that in addition to responding to the output current Idco on connection 518, the operating condition circuit 610 also responds to the output frequency fout of the ring oscillator 406, because the output current Idco on connection 518 increases with the output frequency fout on connection 316. In an exemplary embodiment, the current source 611 generates a sense current Isense, wherein, in an exemplary embodiment, the sense current Isense is equal to the absorb current Isink generated by the current source 611. As used herein, the term "absorb current" refers to the current absorbed or received from an NMOS transistor device, and the term "source current" refers to the current sourced or supplied from a PMOS transistor device. In an exemplary embodiment, the current Isink is equal to the current Idco on connection 518 multiplied by a scaling factor k. In other words, the current Idco on connection 518 is scaled by the scaling factor k to generate the current Isink.

[0081] In an exemplary embodiment, the current Isink (which is the same as Isense in this example) can be added to node 564, resulting in a total current flowing through the reference negative feedback MOS transistor device 542 in addition to the current Iref, such that in this example, the total current flowing through the reference negative feedback MOS transistor device 542 includes Iref and Isense.

[0082] Regardless of the amount of current flowing through the reference negative feedback MOS transistor device 542, OpAmp 532 maintains the voltage at connection 564 at the same voltage level as the voltage Vref at connection 561, so that the drain-source voltage Vds across the reference negative feedback MOS transistor device 542 remains constant regardless of the amount of current flowing through it.

[0083] As described above, when the operating condition circuit is turned on, the current flowing through the reference negative feedback MOS transistor device 542 is (Iref + Isense). Furthermore, since Isense increases with the output frequency fout of the ring oscillator 406, the current flowing through the reference negative feedback MOS transistor device 542 also increases with the output frequency fout of the ring oscillator 406. As a result, the on-resistance Ron decreases with the output frequency fout of the ring oscillator 406. In this way, the voltage margin of the DAC circuit 515 is tuned (e.g., it can be optimized) because the on-resistance Ron of the reference negative feedback MOS transistor device 542 decreases as the output frequency fout of the ring oscillator 406 increases. In this exemplary embodiment, the current Isense generated by the current source 611 is proportional to the current Idco at node 518 and increases with the output frequency fout at connection 316, allowing the operating condition circuit 610 to improve the voltage margin response of the DAC circuit 515 in response to the current Idco and the output frequency fout.

[0084] In an exemplary embodiment, the reference voltage Vref provided to the inverting input of Opamp 532 on connection 561 can be defined by the voltage drop ΔV across resistor 533. The voltage drop ΔV across resistor 533 is also related to the reference current Iref flowing through NMOS transistor device 535 on connection 568 and NMOS transistor device 537 on connection 538. Typically, increasing Iref and / or increasing Isense increases the current flowing in the reference negative feedback MOS transistor. To accommodate the increased current in the reference negative feedback MOS transistor device 542, Opamp 532 reduces the voltage on connection 566 while maintaining the voltage on the non-inverting input 562 (which is the same as the voltage at node 564) equal to the voltage on the inverting input 561, resulting in an increase in the on-resistance Ron of the reference negative feedback MOS transistor device 542 when current flows through it. In an exemplary embodiment, the reduced voltage at the output of OpAmp 532 also reduces the on-resistance Ron of the non-DAC transistor devices 544, 546, and 548, because the non-DAC transistor devices 544, 546, and 548 are in the transistor region, similar to the reference negative feedback MOS transistor device 542.

[0085] Figure 7 To show in more detail Figure 6 A schematic diagram of a DCO 600 of an exemplary embodiment of the operating condition circuit 610. In an exemplary embodiment, the operating condition circuit 610 includes PMOS transistor devices 702 and 704 and NMOS transistor devices 706 and 708. In an exemplary embodiment, current Isense = k * Idco, where "k" is a scalar value configured at node 518 such that current Isense is a scaled version of current Idco. For example, a current mirror formed by NMOS devices 706 and 708 can generate current Isense.

[0086] The current Idac flowing through PMOS transistors 702 and 704 at connection 707 increases with the DAC code (FCW) in a manner similar to how the FCW controls the output current Idco of the DAC circuit 515. For example, when the output current Idco of the DAC circuit at connection 518 increases or decreases, the current Idac through PMOS transistors 702 and 704 also increases or decreases proportionally. The current Idco is controlled by the FCW. In the example implementation, the relative sizes of transistors 702 and 704 can be scaled so that Idac is a small fraction of Idco, to reduce the total current consumption of the DAC circuit 515.

[0087] The current Isense at connection 567 (which is the same as the current Isink in this example) can be coupled from the drain of NMOS device 708 to node 564. In an exemplary embodiment, the current Isense at node 564 increases the total current flowing through the reference negative feedback MOS transistor device 542.

[0088] In the example embodiment, when the PLL and DCO (or VCO) operate at very high frequencies, the current Idco is also very high to maintain high-frequency operation. As a result, assuming the on-resistance Ron of the non-DAC transistor devices 544, 546, and 548 remains constant, the voltage drop I*R across the non-DAC transistor devices 544, 546, and 548 is very high. The on-resistance Ron of the non-DAC transistor devices 544, 546, and 548 is also referred to as the negative feedback resistance. Additionally, during high-frequency operation, the voltage Vdco at connection 554 and node 518 is also very high because more current flows into the ring oscillator 406 during high-frequency operation than during low-frequency operation. Therefore, the available voltage margin of the DAC circuit 515 is limited because of the high I*R voltage drop across the non-DAC transistor devices 544, 546, and 548 and the high voltage Vdco at node 518. This can be problematic if the system voltage Vdd is attempted to be minimized, for example, to reduce power consumption.

[0089] Under the aforementioned high-frequency operation, the negative feedback resistance and on-resistance Ron of the non-DAC transistor device 542 can be reduced, and the scaled versions of Ron across the non-DAC transistor devices 544, 546, and 548 can be reduced accordingly to alleviate voltage margin constraints. Regarding the scaled versions of Ron across the non-DAC transistor devices 544, 546, and 548, assuming that the reference negative feedback MOS transistor device 542 is ten (10) times larger than the non-DAC transistor device 544, if the on-resistance Ron of the reference negative feedback MOS transistor device 542 is 1 kohms, then the Ron of the non-DAC transistor device 544 will be 10 x 1 kohm = 10 kohms. In the example shown, as described above, the relative resistances of the reference negative feedback MOS transistor device 542, the non-DAC transistor devices 544 and 546, and the non-DAC transistor device 548 will be inversely proportional to their relative dimensions.

[0090] Since OpAmp 532 ensures that the reference negative feedback MOS transistor 542 operates in the linear (transistor) region, the negative feedback on-resistance Ron of the reference negative feedback MOS transistor 542 is such that Ron = ΔV / Iref, depending on the voltage across it and the current flowing through it. To reduce the on-resistance Ron (and scaled versions of Ron limited by the dimensions of the non-DAC transistors 544, 546, and 548), the current flowing through the reference negative feedback MOS transistor 542 can be increased. This can be achieved by adding an additional current Isense at node 564, thereby increasing the current flowing through the reference negative feedback MOS transistor 542. When this additional current Isense is added to the current Iref flowing through the reference negative feedback MOS transistor 542, the total current flowing through the reference negative feedback MOS transistor 542 increases (i.e., the current flowing through the non-DAC transistor 542 is Iref + Isense), and the negative feedback on-resistance Ron thus decreases because the voltage drop (ΔV) across resistor 533 remains constant.

[0091] like Figure 7 The example implementation shown can be used to improve voltage margin constraints under high-frequency operation. For example... Figure 7 As shown, the current Isense on connection 567 is a scaled version of Idco, where Isink = k * Idco. In other words, the total current flowing out of the reference negative feedback MOS transistor device 542 is Iref + k * Idco, where k is a constant scaling factor determined by the size ratio of PMOS transistor devices 702 and 704 and NMOS transistor devices 706 and 708.

[0092] In an exemplary embodiment, at high frequencies, the total current flowing out of the reference negative feedback MOS transistor device 542 increases because the current Idco at node 518 increases at high frequencies. Therefore, the increased total current flowing out of the reference negative feedback MOS transistor device 542 leads to a decrease in the negative feedback on-resistance Ron of the reference negative feedback MOS transistor device 542, and consequently reduces the negative feedback on-resistance Ron of the non-DAC transistor devices 544, 546, and 548. This reduced negative feedback on-resistance Ron at high frequencies improves the voltage margin of the DAC circuit 515 at high frequencies. This is important because the system voltage Vdd may be limited by the expectation of lower power consumption while simultaneously desiring to maximize the clock speed of the DAC circuit 515; therefore, maximizing the voltage allows the DAC circuit 515 to operate at a higher speed than when the voltage margin is limited.

[0093] DAC transistor devices 512, 514, and 516 are the primary PMOS devices responsible for generating the DAC output current Idco. DAC transistor devices 512, 514, and 516 should be configured to operate in the saturation region for proper operation. Conversely, non-DAC transistor devices 544, 546, and 548 are MOS devices that are biased in the transistor region and act as linear resistors responsive to the gate voltage. The DAC transistor devices 512, 514, and 516 combined with the non-DAC transistor devices 544, 546, and 548 constitute a DAC with active MOS negative feedback. In an exemplary embodiment, each DAC transistor device 512, 514, and 516 may have the same dimensions as the respective corresponding non-DAC transistor devices 544, 546, and 548 and may be configured to flow a defined amount of current related to its size when enabled by a corresponding switching transistor device (e.g., switching transistor device 586). Figure 7 In an exemplary embodiment, DAC transistor device 512 is connected in series with non-DAC transistor device 544, and can also be described as DAC transistor device 512 being negatively fed back by non-DAC transistor device 544. Since DAC transistor devices 512, 514, and 516 are negatively fed back by non-DAC transistor devices 544, 546, and 548, respectively, the transconductance of DAC transistor devices 512, 514, and 516 is reduced. This may result in less noise contribution than when DAC transistor devices 512, 514, and 516 are not negatively fed back, thus reducing the overall 1 / f noise of the DAC circuit 515.

[0094] Figure 8 This is a detailed schematic diagram of an exemplary embodiment of a digitally controlled oscillator (DCO) 800, which is similar to... Figure 5 DCO, including Figure 5 An exemplary embodiment of the operating condition circuit. Figure 8 Zhongyu Figure 5 Components that correspond to each other in the diagram are numbered the same and are not described in detail again. Figure 8 In an exemplary embodiment, the operating condition circuit 810 is represented by a current source 811, which is configured to respond to the system voltage Vdd on connection 541. In this exemplary embodiment, the magnitude of the sensed current Isense is equal to the magnitude of the source current Isrc generated by the current source 811, where Isense = -Isrc. For example, Isrc is always positive or 0, such that when Isrc increases, the current flowing through the reference negative feedback MOS transistor device 542 decreases, resulting in an increase in the on-resistance Ron of the reference negative feedback MOS transistor device 542. Conversely, when Isrc decreases, the current flowing through the reference negative feedback MOS transistor device 542 increases, resulting in a decrease in the on-resistance Ron of the reference negative feedback MOS transistor device 542. Therefore, when the operating condition circuit 810 is turned on, the on-resistance Ron of the reference negative feedback MOS transistor device 542 is equal to ΔV / (Iref - Isrc).

[0095] In an exemplary embodiment, the current Isrc is a function "f" of the system voltage Vdd. In other words, the output current Isrc varies with the system voltage Vdd. The current Isrc can be a function of the system voltage Vdd such that as the voltage level of Vdd increases, the output of the current source 811 increases and as the voltage level of Vdd decreases, the output of the current source 811 decreases.

[0096] In an exemplary embodiment, if the system voltage Vdd decreases, the current Isrc decreases, thereby increasing the current through the reference negative feedback MOS transistor device 542. OpAmp 532 responds to this increased current in the reference negative feedback MOS transistor by decreasing the voltage on connection 566, such that the voltage on the non-inverting input 562 remains the same as the voltage on the inverting input 561. In an exemplary embodiment, the reference voltage Vref supplied to the inverting input of OpAmp 532 on connection 561 can be limited by the voltage drop ΔV across resistor 533. Because the decrease in system voltage Vdd decreases the current Isrc in current source 811, the current flowing in the reference negative feedback MOS transistor device 542 increases and the resulting on-resistance of the reference negative feedback MOS transistor device 542 decreases while the drain-source voltage Vds across the reference negative feedback MOS transistor device 542 remains constant (i.e., ΔV), because Ron = ΔV / (current in the reference negative feedback MOS transistor device 542). As described in this article, the reduced voltage on the output of OpAmp 532 connected to 566 also proportionally reduces the on-resistance Ron of the non-DAC transistor devices 544, 546, and 548.

[0097] Conversely, in the exemplary embodiment, if the system voltage Vdd increases, the current Isrc increases, which reduces the current flowing through the reference negative feedback MOS transistor device 542. OpAmp 532 responds to the reduced current in the reference negative feedback MOS transistor device 542 by increasing the voltage at connection 566, such that the voltage at the non-inverting input 562 remains the same as the voltage at the inverting input 561. In the exemplary embodiment, the reference voltage Vref provided to the inverting input of OpAmp 532 at connection 561 can be limited by the voltage drop ΔV across resistor 533. Because the increase in system voltage Vdd increases the current Isrc in current source 811 and reduces the current flowing in the reference negative feedback MOS transistor device 542, while keeping the drain-source voltage Vds across the reference negative feedback MOS transistor device 542 constant (i.e., ΔV), the on-resistance Ron of the reference negative feedback MOS transistor device 542 increases due to Ron = ΔV / (current in the reference negative feedback MOS transistor device 542). As described in this article, the added voltage across the output of the OpAmp 532 connected to the 566 also increases the on-resistance Ron of the non-DAC transistor devices 544, 546, and 548.

[0098] In an exemplary embodiment, a current Isrc can be supplied to node 564 such that the current at node 564 (and the current flowing through the reference negative feedback MOS transistor device 542) responds to the system voltage Vdd. In an exemplary embodiment, if the system voltage Vdd decreases, the on-resistance Ron of the reference negative feedback MOS transistor device 542 also decreases, resulting in an additional voltage margin. If the system voltage Vdd increases, the on-resistance Ron of the reference negative feedback MOS transistor device 542 also increases, resulting in a greater improvement in 1 / f noise performance.

[0099] Figure 9 To show in more detail Figure 8 A schematic diagram of an exemplary embodiment of the operating condition circuit 810 of the DCO 800. The operating condition circuit 810 includes PMOS transistor devices 902 and 904 and an NMOS transistor device 906. The current Isrc on connection 567 flows through the PMOS transistor device 904 and affects the current at node 564 via node 907, thus affecting the current flowing through the reference negative feedback MOS transistor device 542. In the exemplary embodiment, the current Isrc = f(Vdd), where "f" is a function of the system voltage Vdd on connection 541 and the associated current source current Isrc on connection 567.

[0100] When the supply voltage Vdd decreases, the current flowing through transistor device 904 decreases, increasing the current flowing through reference negative feedback MOS transistor device 542. As described above, this reduces the on-resistance Ron of non-DAC transistor devices 542, 544, 546, and 548. In this way, the operating condition circuit 810 responds to the decreased system voltage Vdd and allows the operating condition circuit 810 to improve voltage margin when the system voltage Vdd decreases.

[0101] As the supply voltage Vdd increases, the current flowing through transistor device 904 increases, reducing the current flowing through reference negative feedback MOS transistor device 542. As described above, this increases the on-resistance Ron of non-DAC transistor devices 542, 544, 546, and 548. In this way, the operating condition circuit 810 responds to the increased system voltage Vdd and allows the operating condition circuit 810 to improve 1 / f noise performance when the system voltage Vdd level is permissible.

[0102] Figure 10 This is a detailed schematic diagram of an exemplary embodiment of a digitally controlled oscillator (DCO) 900, which is similar to... Figure 5 DCO, including Figure 5 An exemplary embodiment of the operating condition circuit. Figure 10 Zhongyu Figure 5 Components that correspond to each other in the diagram are numbered the same and are not described in detail again. Figure 10 In an exemplary embodiment, the DAC circuit 519 includes an operating condition circuit 910 represented by a current source 611, as described above regarding... Figure 6 As described above, current source 611 is configured to respond to current Idco on connection 518; and as stated above regarding Figure 8 As described, current source 811 is configured to respond to system voltage Vdd on connection 541. In this exemplary embodiment, the sense current Isense is equal to the absorb current Isink generated by current source 611 minus the source current Isrc generated by current source 811, such that Isense = Isink - Isrc.

[0103] In this way, both the current Isink generated by current source 611 and the current Isrc generated by current source 811 affect the total current flowing through the reference negative feedback MOS transistor device 542, thereby controlling the on-resistance Ron of the reference negative feedback MOS transistor device 542 and the on-resistance Ron of the non-DAC transistor devices 544, 546 and 548 in response to the current Idco and the system voltage Vdd, as described above.

[0104] Figure 11 It shows more details Figure 9 A schematic diagram of a DCO 900 of an exemplary embodiment of the operating condition circuit 910. In the exemplary embodiment, the operating condition circuit 910 ( Figure 10 The operating condition circuit 610, which is implemented together with the DAC circuit 519, is included. Figure 7 ) and operating condition circuit 810 ( Figure 9 ).

[0105] In this exemplary embodiment, the sense current Isense is equal to the absorption current Isink generated by the operating condition circuit 610 minus the source current Isrc generated by the operating condition circuit 810, such that Isense = Isink - Isrc.

[0106] As described herein with respect to the operating condition circuit 610, in an exemplary embodiment, at high frequencies, the total current flowing out of the reference negative feedback MOS transistor device 542 increases because the current Idco at node 518 increases at high frequencies. Therefore, the increased total current flowing out of the reference negative feedback MOS transistor device 542 leads to a decrease in the negative feedback on-resistance Ron of the reference negative feedback MOS transistor device 542 and consequently the non-DAC transistor devices 544, 546, and 548. This reduced negative feedback on-resistance Ron at high frequencies improves the voltage margin of the DAC circuit 519 at high frequencies.

[0107] Furthermore, as described herein with respect to the operating condition circuit 810, in an exemplary embodiment, when the supply voltage Vdd decreases, the current flowing through transistor device 904 decreases, thereby increasing the current flowing through reference negative feedback MOS transistor device 542. This, in turn, reduces the on-resistance Ron of non-DAC transistor devices 542, 544, 546, and 548 as described above. In this way, the operating condition circuit 810 responds to a decrease in system voltage Vdd and allows the operating condition circuit 810 to improve voltage margin when the system voltage Vdd decreases.

[0108] As the supply voltage Vdd increases, the current flowing through transistor device 904 increases, thereby reducing the current flowing through reference negative feedback MOS transistor device 542. Therefore, as described above, the on-resistance Ron of reference negative feedback MOS transistor devices 542, 544, 546, and 548 is increased. In this way, the operating condition circuit 810 responds to the increased system voltage Vdd and allows the operating condition circuit 810 to improve 1 / f noise performance when the system voltage Vdd level is permissible.

[0109] In this way, both the operating condition circuit 610 and the operating condition circuit 810 can be implemented together in the DAC circuit 519 to provide feedback signals to the control circuit 530 in response to both the current Idco and the system voltage Vdd, thereby tuning (e.g., optimizing) the voltage margin of the DAC circuit 510 over a wide voltage range and improving the 1 / f noise performance of the DAC circuit 519.

[0110] Figure 12 This is a flowchart 1200 illustrating an example of the operation of a DAC circuit. The blocks in method 1200 may be executed in or out of the order shown, and in some embodiments, they may be executed at least partially in parallel.

[0111] In box 1202, a variable resistor is provided at the input side of the DAC. The variable resistor can be, for example... Figures 5 to 11 Non-DAC transistor devices 544, 546, and 548 are provided, and are coupled to corresponding DAC transistor devices 512, 514, and 516. In an exemplary embodiment, the non-DAC transistor devices 544, 546, and 548 include corresponding negative feedback resistors for the DAC transistor devices 512, 514, and 516.

[0112] In block 1204, a control signal for the variable resistor is provided. The control signal can be, for example, provided by... Figures 5 to 11 The control circuit 530 is provided.

[0113] In some embodiments, providing control signals in block 1204 includes providing voltage margin information to control circuitry 530 based on one or more of the DAC's system voltage and the DAC's current output, as shown in block 1206. For example, Figures 5 to 11 The operating condition circuits (e.g., 570, 610, 810, 910) can be configured to provide voltage margin information to the control circuit 530 based on one or more of the DAC's system voltage and the DAC's current output.

[0114] In some embodiments, providing the control signal in block 1204 may further include, as shown in block 1208, adjusting the bias of the variable resistor via control circuitry 530. For example, the bias of the reference negative feedback MOS transistor device 542 may be determined by... Figures 5 to 11 The control circuit is adjusted to adjust the resistance of non-DAC transistor devices 542, 544, 546 and 548.

[0115] Figure 13 This is a functional block diagram of a device for a DAC circuit according to an exemplary embodiment. Device 1300 includes means 1302 for providing a variable resistance at the input side of the DAC. In some embodiments, means 1302 for providing a variable resistance at the input side of the DAC may be configured to perform method 1200. Figure 12 One or more of the functions described in operation block 1202. In an exemplary embodiment, means 1302 for providing a variable resistance at the input side of the DAC may include Figures 5 to 11 Non-DAC transistor devices 544, 546 and 548 are coupled, for example, to corresponding DAC transistor devices 512, 514 and 516.

[0116] The device 1300 also includes means 1304 for providing control signals to the variable resistor. Means 1304 for providing control signals to the variable resistor can be configured to perform in method 1200 (…). Figure 12 One or more of the functions described in operation block 1204. In an exemplary embodiment, means 1304 for providing control signals may include... Figures 5 to 11 The control circuit 530.

[0117] In some embodiments, the means for providing a control signal for a variable resistor may include means 1306 for providing voltage margin information. In some embodiments, means 1306 for providing voltage margin information may be configured to perform in method 1200 ( Figure 12 One or more of the functions described in operation block 1206. In an exemplary embodiment, the means 1306 for providing voltage margin information may include... Figures 5 to 11 The operating condition circuit provides voltage margin information to the control circuit 530 based on one or more of the DAC's system voltage and the DAC's current output.

[0118] In some embodiments, the means for providing a control signal to the variable resistor may further include means 1308 for adjusting the bias of the variable resistor. In some embodiments, the means 1308 for adjusting the bias of the variable resistor may be configured to perform in method 1200 ( Figure 12 One or more of the functions described in operation block 1208. In an exemplary embodiment, the means 1308 for adjusting the bias of the variable resistor may include... Figures 5 to 11 The control circuit adjusts the resistors of the reference negative feedback MOS transistor device 542 and the non-DAC transistor devices 544, 546 and 548 based on the voltage margin information provided by the device 1306.

[0119] The circuit architecture described in this article can be implemented on one or more ICs, analog ICs, RFICs, mixed-signal ICs, ASICs, printed circuit boards (PCBs), electronic devices, etc. The circuit architecture described in this article can also be manufactured using various IC process technologies, such as complementary metal-oxide-semiconductor (CMOS), N-channel MOS (NMOS), P-channel MOS (PMOS), bipolar junction transistors (BJTs), bipolar CMOS (BiCMOS), silicon-germanium (SiGe), gallium arsenide (GaAs), heterojunction bipolar transistors (HBTs), high electron mobility transistors (HEMTs), silicon-on-insulator (SOI), etc.

[0120] The device implementing the circuit described herein may be a standalone device or may be part of a larger device. The device may be (i) a standalone IC, (ii) a collection of one or more ICs, which may include a memory IC for storing data and / or instructions, (iii) an RF IC, such as an RF receiver (RFR) or an RF transmitter / receiver (RTR), (iv) an ASIC, such as a mobile station modem (MSM), (v) a module that may be embedded in other devices, (vi) a receiver, a cellular phone, a wireless device, a telephone, or a mobile unit, (vii) and so on.

[0121] As used in this description, the terms "component," "database," "module," "system," etc., are intended to refer to computer-related entities, hardware, firmware, hardware and software combinations, software, or software being executed. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program, and / or a computer. By way of example, both an application running on a computing device and the computing device itself can be components. One or more components may reside within a process and / or an execution thread, and components may reside on a single computer and / or be distributed across two or more computers. Additionally, these components can be executed from various computer-readable media on which various data structures are stored. Components can communicate, for example, via local and / or remote processes based on signals having one or more data packets (e.g., data from one component interacts with another component in a local system, a distributed system, and / or with other systems across a network, such as the Internet).

[0122] Although selected aspects have been illustrated and described in detail, it should be understood that various substitutions and changes may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A digital-to-analog converter (DAC), comprising: Multiple DAC transistor devices have an input side configured to selectively couple to the system voltage based on a digital input signal and an output side configured to provide an analog output signal; Multiple non-DAC transistor devices are coupled to the input side of the DAC transistor device, and the non-DAC transistor devices are configured as variable resistors; as well as A control circuit configured to adjust the bias of the non-DAC transistor device, wherein the bias is used to control the variable resistance of the non-DAC transistor device.

2. The DAC according to claim 1, wherein the control circuit comprises: A resistor, a current source, and a reference non-DAC transistor coupled to the non-DAC transistor, the reference non-DAC transistor being coupled to a bias operational amplifier (OpAmp) in response to a reference voltage and a voltage at the drain of the reference non-DAC transistor.

3. The DAC of claim 1, wherein the plurality of non-DAC transistor devices are biased in the transistor region.

4. The DAC of claim 1, wherein the control circuitry is configured to adjust the resistance of the plurality of non-DAC transistor devices.

5. The DAC of claim 1, further comprising an operating condition circuit coupled to the control circuit, the operating condition circuit having a current source generating a sense current proportional to the current output (Idco) of the DAC, the sense current being provided to the control circuit to allow the control circuit to adjust the resistance of at least one of the non-DAC transistor devices based on the current output (Idco) of the DAC.

6. The DAC according to claim 1, further comprising: An operating condition circuit coupled to the control circuit has a current source that generates a sense current proportional to the input voltage level of the DAC, the sense current being provided to the control circuit to allow the control circuit to adjust the resistance of at least one of the non-DAC transistor devices based on the input voltage level of the DAC.

7. The DAC according to claim 1, further comprising: An operating condition circuit coupled to the control circuit has multiple current sources that generate a sense current proportional to the current output (Idco) of the DAC and proportional to the input voltage level of the DAC. The sense current is provided to the control circuit to allow the control circuit to adjust the resistance of at least one of the non-DAC transistor devices based on one or more of the input voltage level of the DAC and the current output (Idco) of the DAC.

8. The DAC of claim 5, wherein the current source comprises a plurality of transistor devices configured to generate a scaled current output (k*Idco) of the DAC.

9. The DAC of claim 6, wherein the current source comprises a plurality of transistor devices configured to generate a current that varies with the input voltage level of the DAC.

10. A method for operating a digital-to-analog converter (DAC), comprising: A variable resistor is provided at the input side of the digital-to-analog converter (DAC), which is created by a plurality of non-DAC transistor devices coupled to the input side of a plurality of DAC transistor devices, which are selectively coupled to the system voltage based on the digital input signal and have an output side configured to provide an analog output signal. A signal indicating the voltage margin of the DAC is provided to a control circuit, the control circuit being used to adjust the bias of the plurality of non-DAC transistor devices, wherein the bias is used to control the variable resistance of the non-DAC transistor devices; as well as The control circuit is used to adjust the variable resistor.

11. The method of claim 10, further comprising biasing the variable resistor in the transistor region.

12. The method of claim 10, further comprising: A feedback signal is provided to the control circuit, the feedback signal including a sensed current proportional to the current output (Idco) of the DAC, the sensed current being provided to the control circuit to allow the control circuit to adjust the variable resistor based on the current output (Idco) of the DAC.

13. The method of claim 10, further comprising: A feedback signal is provided to the control circuit, the feedback signal including a sensed current proportional to the input voltage level of the DAC, the sensed current being provided to the control circuit to allow the control circuit to adjust the variable resistor based on the input voltage level of the DAC.

14. The method of claim 10, further comprising: A feedback signal is provided to the control circuit, the feedback signal including a sensed current proportional to the current output (Idco) of the DAC and proportional to the input voltage level of the DAC, the sensed current being provided to the control circuit to allow the control circuit to adjust the variable resistor based on one or more of the input voltage level of the DAC and the current output (Idco) of the DAC.

15. The method of claim 12, wherein the sensed current includes the scaled current output (k*Idco) of the DAC.

16. The method of claim 13, wherein the sensed current includes a current related to the input voltage level of the DAC.

17. An apparatus comprising: A means for providing a variable resistance at the input side of a digital-to-analog converter (DAC), the variable resistance being created by a plurality of non-DAC transistor devices coupled to the input side of a plurality of DAC transistor devices, the plurality of DAC transistor devices being selectively coupled to a system voltage based on a digital input signal and having an output side configured to provide an analog output signal; A means for providing a signal indicating the voltage margin of the DAC; as well as A means for adjusting the variable resistor based on the signal indicating the voltage margin is configured to adjust the bias of the plurality of non-DAC transistor devices, wherein the bias is used to control the variable resistor of the non-DAC transistor devices.

18. The apparatus of claim 17, further comprising means for biasing the variable resistor in the transistor region.

19. The apparatus of claim 17, further comprising: A means for providing a feedback signal to an adjustment device, the feedback signal including a sensed current proportional to the current output (Idco) of the DAC, the sensed current being provided to the adjustment device to allow the adjustment device to adjust the variable resistor based on the current output (Idco) of the DAC.

20. The apparatus of claim 17, further comprising: A means for providing a feedback signal to an adjustment device, the feedback signal including a sensed current proportional to the input voltage level of the DAC, the sensed current being provided to the adjustment device to allow the adjustment device to adjust the variable resistor based on the input voltage level of the DAC.

21. The apparatus of claim 17, further comprising: A means for providing a feedback signal to an adjustment device, the feedback signal including a sensed current proportional to the current output (Idco) of the DAC and proportional to the input voltage level of the DAC, the sensed current being provided to the adjustment device to allow the adjustment device to adjust the variable resistor based on one or more of the input voltage level of the DAC and the current output (Idco) of the DAC.

22. A phase-locked loop (PLL) circuit, comprising: A phase detector is configured to provide control signals; A filter is configured to receive the control signal and provide a frequency codeword; A digitally controlled oscillator (DCO) is configured to receive the frequency codeword. The DCO has a digital-to-analog converter (DAC) circuit and a ring oscillator. The DAC circuit includes: Multiple DAC transistor devices, each having an input side coupled to the output of the filter and an output side coupled to the ring oscillator; as well as Multiple non-DAC transistor devices are coupled to the input side of the DAC transistor device, and the non-DAC transistor devices are configured as variable resistors.

23. The PLL circuit according to claim 22, further comprising: A control circuit configured to adjust the bias of the non-DAC transistor device, wherein the control circuit includes a resistor, a current source, and a reference non-DAC transistor device coupled to the non-DAC transistor device, the reference non-DAC transistor device being coupled to a bias operational amplifier (OpAmp) in response to a reference voltage and a voltage at the drain of the reference non-DAC transistor device.

24. The PLL circuit of claim 23, wherein the plurality of non-DAC transistor devices are biased in the transistor region.

25. The PLL circuit of claim 23, wherein the control circuit is configured to adjust the resistance of the plurality of non-DAC transistor devices.

26. The PLL circuit according to claim 23, further comprising: An operating condition circuit coupled to the control circuit has a current source that generates a sense current proportional to the current output (Idco) of the DAC, the sense current being provided to the control circuit to allow the control circuit to adjust the resistance of at least one of the non-DAC transistor devices based on the current output (Idco) of the DAC.

27. The PLL circuit according to claim 23, further comprising: An operating condition circuit coupled to the control circuit has a current source that generates a sense current proportional to the input voltage level of the DAC, the sense current being provided to the control circuit to allow the control circuit to adjust the resistance of at least one of the non-DAC transistor devices based on the input voltage level of the DAC.

28. The PLL circuit according to claim 23, further comprising: An operating condition circuit coupled to the control circuit has multiple current sources that generate a sense current proportional to the current output (Idco) of the DAC and proportional to the input voltage level of the DAC. The sense current is provided to the control circuit to allow the control circuit to adjust the resistance of at least one of the non-DAC transistor devices based on one or more of the input voltage level of the DAC and the current output (Idco) of the DAC.

29. The PLL circuit of claim 26, wherein the current source comprises a plurality of transistor devices configured to generate a scaled current output (k*Idco) of the DAC.

30. The PLL circuit of claim 27, wherein the current source comprises a plurality of transistor devices configured to generate a current related to the input voltage level of the DAC.

31. A digital-to-analog converter (DAC), comprising: Multiple DAC transistor devices have an input side configured to selectively couple to the system voltage based on a digital input signal and an output side configured to provide an analog output signal; Multiple non-DAC transistor devices are coupled to the input side of the DAC transistor device, and the gate voltage of the non-DAC transistor devices is adjustable; as well as A control circuit configured to adjust the bias of the non-DAC transistor device, wherein the bias is used to control the gate voltage of the non-DAC transistor device.

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