Method and system for communicating data and control information via a serial link

Abstract

The present disclosure relates to methods and systems for communicating data and control information via a serial link. A communication system includes a digital data processor that generates digital data samples and one or more control bits. A serialization transmit interface combines the digital data samples and the one or more control bits into one or more data packets and transmits the data packets via a signal line. A serialization receive interface receives the one or more transmitted data packets from the signal line and generates reconstructed digital data samples and control bits from the transmitted data packets. A control circuit coupled to the serialization receive interface generates a control signal from the one or more control bits. The communication system can include a converter circuit that generates an RF input signal by performing digital-to-analog conversion on the reconstructed digital data samples and by up-converting the resulting analog data sample signal to RF. A power amplifier amplifies the RF input signal and modifies the operation of a sub-circuit based on the control signal.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to radio frequency (RF) communication systems, and more specifically, to RF transmitters utilizing a serial link between a digital signal processor and a data converter coupled to an RF power amplifier. Background Technology

[0002] In some wireless communication systems, a cellular base station transmitter group includes a digital signal processor (DSP) connected to one or more radio frequency (RF) transmit front-end circuits via one or more communication links. The DSP generates digital samples that are transmitted to the one or more RF transmit front-end circuits via the one or more communication links. Each RF transmit front-end circuit includes a data converter (e.g., a digital-to-analog converter), a transmit power amplifier, and an antenna. The data converter converts the digital samples received from the DSP into an analog signal, which is up-converted and amplified by the power amplifier and transmitted via the antenna through an air interface.

[0003] In some systems, digital samples to be transmitted from a digital signal processor to a data converter are sent according to one of several known serial link communication protocols, and more specifically, protocols defining the serialized communication interface between the logic device and the data converter (e.g., digital-to-analog converter and analog-to-digital converter). According to some serial link communication protocols, the logic device sends digital samples to a serialization transmitter, which buffers, frames, and serializes the digital samples, and transmits the serialized sample stream to the data converter via one or more "channels" (i.e., differential signal pairs used for data transmission). As noted above, the data converter, and more specifically the digital-to-analog converter, converts the digital samples into analog signals. The analog signals are up-converted and amplified by power transistors and finally transmitted by an antenna via an air interface.

[0004] In some cases, control information that should be synchronized (or time-aligned) with digital samples may also need to be transmitted from the digital signal processor to downstream components. This control information is transmitted via a separate communication link, independent of the serial communication interface. Given the ever-increasing frequency of wireless communication, system designers are increasingly finding it challenging to synchronize analog signals (i.e., converted digital samples) with control information at downstream components. Therefore, there is a need for improved devices and methods for conveying and synchronizing control information with the analog signals converted from digital samples transmitted via serial communication links at downstream components. Summary of the Invention

[0005] According to one aspect of the present invention, a communication system is provided, comprising:

[0006] A digital data processor configured to generate digital data samples and one or more control bits;

[0007] A serialized transmit interface, coupled to the first end of the digital data processor and signal line, wherein the serialized transmit interface is configured to...

[0008] The digital data sample is combined with the one or more control bits into one or more data packets, and

[0009] The one or more data packets are transmitted via the signal line as one or more transmitted data packets;

[0010] A serialized receiving interface, wherein the serialized receiving interface is coupled to the second end of the signal line, wherein the serialized receiving interface is configured to

[0011] Receive one or more transmitted data packets from the signal line.

[0012] Reconstructed digital data samples are generated from the one or more transmitted data packets, and

[0013] Generate the one or more control bits from the one or more transmitted data packets; and

[0014] A control circuit coupled to the serialized receive interface and configured to generate control signals from one or more control bits provided by the serialized receive interface.

[0015] According to one or more embodiments, the serialized transmit interface and the serialized receive interface implement the JESD204 serial link communication protocol.

[0016] According to one or more embodiments, the serialized transmit interface is configured to combine the digital data sample and the one or more control bits into the one or more data packets by combining at least one bit of the digital data sample and at least one control bit of the one or more control bits into the data packets in the one or more data packets.

[0017] According to one or more embodiments, the serialized transmit interface is configured to transmit the one or more data packets as one or more transmitted data packets via the signal line by: encoding the one or more data packets to generate one or more encoded symbols; and transmitting the one or more data packets via the serial link within the one or more encoded symbols.

[0018] According to one or more embodiments, the serialized receive interface is configured to receive the one or more transmitted data packets from the signal line by decoding the one or more encoded symbols.

[0019] According to one or more embodiments, the communication system further includes: a converter circuit configured to generate an RF input signal by performing digital-to-analog conversion on the reconstructed digital data samples to generate an analog data sample signal and upconverting the analog data sample signal to radio frequency (RF); and a power amplifier including a sub-circuit controllable based on a control signal generated by the control circuit, wherein the power amplifier is configured to amplify the RF input signal and modify the operation of the sub-circuit based on the control signal.

[0020] According to one or more embodiments, the control circuit includes a buffer with a programmable delay configured to synchronize the amplification of the RF input signal in the power amplifier with the modification of the operation of the sub-circuit based on the control signal.

[0021] According to one or more embodiments, the control circuit is configured to generate the control signal from the one or more control bits in the form of an analog control signal.

[0022] According to one or more embodiments, the sub-circuit of the power amplifier includes a switch, and the power amplifier is configured to modify the operation of the sub-circuit by changing the state of the switch based on the analog control signal.

[0023] According to one or more embodiments, the power amplifier is a Dougherty power amplifier having a carrier amplifier path and a peaking amplifier path, wherein the switch is connected to the peaking amplifier path in a parallel configuration.

[0024] According to one or more embodiments, the control circuit is configured to generate the control signal from the one or more control bits in the form of a digital control signal.

[0025] According to one or more embodiments, the sub-circuit of the power amplifier includes a digital control circuit, and the power amplifier is configured to modify the operation of the sub-circuit by changing the operation of the digital control circuit based on the digital control signal.

[0026] According to one or more embodiments, the power amplifier is a Dougherty power amplifier having a carrier amplifier path and a peaking amplifier path, the Dougherty power amplifier including a power divider configured to divide the RF input signal into a carrier RF signal and a peaking RF signal, the digital control circuit including one or more variable phase shifters coupled to either or both of the carrier amplifier path and the peaking amplifier path, and the power amplifier being configured to modify the operation of the digital control circuit by changing one or more phase shifts applied to either or both of the carrier RF signal and the peaking RF signal by the one or more variable phase shifters.

[0027] According to one or more embodiments, the converter circuit includes: a digital-to-analog converter configured to perform the digital-to-analog conversion to generate the analog signal; and an upconversion converter configured to upconvert the analog signal to RF.

[0028] According to a second aspect of the present invention, a method performed by a communication system is provided, the method comprising:

[0029] A digital data processor generates digital data samples and one or more control bits.

[0030] The digital data samples and one or more control bits are combined into one or more data packets through a serialized transmission interface;

[0031] The one or more data packets are transmitted via the serialized transmit interface through the signal line as one or more transmitted data packets;

[0032] Receive one or more transmitted data packets from the signal line through the serialized receive interface;

[0033] Reconstructed digital data samples are generated from the one or more transmitted data packets through the serialized receive interface;

[0034] The one or more control bits are generated from the one or more transmitted data packets through the serialized receive interface; and

[0035] Control signals are generated from one or more control bits produced by the serialized receive interface via a control circuit.

[0036] According to one or more embodiments, the serialized transmit interface and the serialized receive interface implement the JESD204 serial link communication protocol.

[0037] According to one or more embodiments, transmitting the one or more data packets as one or more transmitted data packets via the signal line through the serialized transmit interface includes encoding the one or more data packets to generate one or more encoded symbols, and transmitting the one or more data packets within the one or more encoded symbols via the serial link; and receiving the one or more transmitted data packets from the signal line through the serialized receive interface includes decoding the one or more encoded symbols.

[0038] According to one or more embodiments, the method further includes: generating an RF input signal by performing digital-to-analog conversion on the reconstructed digital data samples to generate an analog data sample signal and upconverting the analog data sample signal to radio frequency (RF) via a converter circuit; amplifying the RF input signal via a power amplifier, the power amplifier including a sub-circuit controllable based on a control signal generated by the control circuit; and modifying the operation of the sub-circuit based on the control signal via the power amplifier.

[0039] According to one or more embodiments, generating the control signal via the control circuitry includes delaying the generation of the control signal with a programmable delay, the programmable delay being configured to synchronize the amplification of the RF input signal with the operation of modifying the sub-circuit in the power amplifier based on the control signal.

[0040] According to one or more embodiments, generating the control signal includes generating an analog control signal; the sub-circuit of the power amplifier includes a switch; and modifying the sub-circuit includes changing the state of the switch based on the analog control signal.

[0041] According to one or more embodiments, generating the control signal includes generating a digital control signal; the sub-circuit of the power amplifier includes a digital control circuit; and modifying the sub-circuit includes changing the digital control circuit based on the digital control signal.

[0042] According to one or more embodiments, the power amplifier is a Dougherty power amplifier, and the operation of modifying the sub-circuit based on the control signal includes the operation of modifying the Dougherty power amplifier. Attached Figure Description

[0043] A more complete understanding of the subject matter can be derived by referring to the detailed embodiments and claims when considering the following figures, wherein similar reference numerals throughout the figures refer to similar elements.

[0044] Figure 1 This is a simplified block diagram of a wireless communication system according to an example embodiment;

[0045] Figure 2 This is a block diagram of a multi-antenna radio frequency (RF) subsystem according to an example embodiment, wherein a digital front-end (DFE) processor is connected to the RF front-end circuitry via a serialized interface;

[0046] Figure 3 A more detailed block diagram of a serialized transmitter and a serialized receiver coupled between a processor and an RF transmit front-end circuit according to an example embodiment;

[0047] Figure 4 Depicting, according to an example embodiment, several data formats associated with combining converter samples with associated control bits for communication via a serialized interface;

[0048] Figure 5 A simplified block diagram of a Doherty power amplifier with externally controllable sub-circuit according to an example embodiment;

[0049] Figure 6A and 6B A graph depicting the operational performance of embodiments of an idealized Dougherty amplifier, a conventional Dougherty amplifier, and a Dougherty amplifier with externally controllable sub-circuit.

[0050] Figure 6C A graph depicting the resistance versus voltage of a switch according to an example embodiment;

[0051] Figure 7 A simplified block diagram of a Dougherty power amplifier with digitally controllable sub-circuit according to another example embodiment; and

[0052] Figure 8 This is a flowchart of a method for transmitting data and control signals via a serial link between an amplifier of a processor, a digital-to-analog converter, and an RF transmitter group, according to an example embodiment. Detailed Implementation

[0053] Figure 1 The simplified block diagram of the wireless communication system 100 includes devices 102, 110 comprising digital front-ends (DFEs) 105, 115 that use a serial link communication protocol to transmit both data and control information to a group of radio frequency (RF) transmitters within RF transceivers 106, 116. More specifically, the wireless communication system 100 includes multiple wireless devices or subscriber stations 102 (e.g., handheld computers, personal digital assistants (PDAs), cellular phones, etc.) that wirelessly communicate with one or more base station systems (BSSs) 110 (e.g., evolved NodeBs or eNBs in LTE (Long Term Evolution) networks) using RF communication signals.

[0054] Each wireless device 102 may include a baseband processor 108 (e.g., a digital signal processor) connected via a DFE processor 105 to an RF transceiver 106, which in turn is connected to one or more antennas 109. The baseband processor 105 and the DFE processor 105 may be implemented as one or more integrated circuits to provide digital processing functionality for the wireless device 102. The digital processing components mounted on the DFE processor 105 may include one or more control processors and digital transmit / receive filters, as well as interface peripherals and other I / O for RF subsystem functions. Essentially, each RF transceiver 106 (including an RF transmitter and an RF receiver) is configured to receive or transmit voice, data, or both using one or more antennas 109, and provides an interface for signals between the antennas 109 and the DFE processor 105. More specifically, each RF transceiver 106 is configured to perform digital-to-analog conversion and amplification of signals from the DFE processor 105, and amplify and perform analog-to-digital conversion of signals received by the antennas 109 via the air interface. Additionally, each wireless device 102 may include one or more input / output devices 104 (e.g., camera, keypad, display, etc.) and other components (not shown).

[0055] BSS 110 includes a Base Station Controller (BSC) 112 and one or more Base Transceiver Stations (BTSs) 114, wherein each BTS 114 provides a communication interface between the BSC 112 and antennas 119. The BSC 112 may, for example, be configured to schedule communications of radio device 102. Each radio device 102 communicates with the BSC 112 of BSS 110 via one of the BTSs 114, through antennas 109 and 119.

[0056] Essentially, each BTS 114 is configured to receive or transmit signals, including processed voice, data, or both, via one or more antennas 119, and provides an interface for signals between the antennas 119 and the BSC 112. Each of the one or more BTS 114 includes a DFE processor 115, which may be implemented as one or more integrated circuits to provide the digital processing functionality of the BTS 114. The digital processing components mounted on the DFE processor 115 may include one or more control processors and digital transmit / receive filters, as well as interface peripherals and other I / O for RF subsystem functions. Additionally, each of the one or more BTS 114 includes an RF transceiver 116 (including an RF transmitter and an RF receiver), which is configured to perform digital-to-analog conversion and amplification of signals from the DFE processor 115, and amplify and perform analog-to-digital conversion of signals received by the antennas 119 via the air interface. As will be described in more detail below, the RF transmitters of the DFE processor 115 and RF transceiver 116 transmit digital samples via one or more serialized links, and according to an embodiment, control information may be multiplexed with at least some of the digital samples.

[0057] As will be understood, the digital sample and control information communication techniques disclosed herein with reference to base station system 110 can also be used in conjunction with, for example, wireless communication devices of wireless device 102. For this purpose, and as previously mentioned, each wireless device 102 may also include a DFE processor 105 connected to a corresponding RF transceiver 106, and the DFE processor 105 and the RF transmitter of the RF transceiver 106 may also be configured to transmit digital samples via one or more serialized links, wherein control information may be multiplexed with at least some of the digital samples.

[0058] To further illustrate the digital sample and control information communication technology disclosed herein, reference is now made to... Figure 2 , Figure 2 For multi-antenna RF BTS 200 (e.g., BTS 114, Figure 1 This is a high-level architecture block diagram of a portion of the BTS 200. The BTS 200 is connected to the base station controller (e.g., BSC 112). Figure 1 The BTS 200 includes a DFE processor 201 (or more generally, a “digital data processor”) connected via multiple channels 271 to 273, 291 to 293 (i.e., differential signal line pairs for transmitting data in one direction) to multiple RF transmit front-end circuits 250 to 252 and RF receive front-end circuits 280 to 282. As will be understood, the DFE processor 201 may be located in conjunction with a base station controller (e.g., BSC 112). Figure 1 The shared radio head end may be located at a remote radio head end not shared with the base station controller. For simplicity of illustration, transmitting antennas 253 to 255 and receiving antennas 283 to 285 are shown as separate from each other, but it will be understood that multiple shared antennas can be used for both signal transmission and reception in a shared or switched circuit arrangement. In such an arrangement, during operation, a duplexer (e.g., a circulator) and / or RF switch between each antenna and the transceiver (consisting of RF transmitting front-end circuitry and receiving front-end circuitry) can be used to isolate the transmitted signal from the received signal.

[0059] The DFE processor 201 is essentially a digital signal processor (or digital data processor) provided to perform digital signal processing on the BTS 200 across individual transmit antennas 253 to 255 and / or receive antennas 283 to 285. For this purpose, the DFE processor 201 separates the transmit and receive signals entering and exiting the antennas into transmit processing paths and receive processing paths, and communicates with a baseband modem (not shown) via a modem interface (e.g., a Common Public Radio Interface (CPRI) interface and / or a JESD204 interface, not shown). For example, a base station controller (e.g., BSC 112, Figure 1 It can generate real (I) and hypothetical (Q) samples (i.e., instantaneous values ​​of the signal measured or determined in discrete time) for each transmitted signal path to be transmitted via diversity antennas 253 to 255.

[0060] The DFE processor 201 may include one or more control processors or CPUs 202 (e.g., one or more ARM processor cores), a memory subsystem (e.g., instruction and data cache memory), a memory controller (not shown) for interfacing with external memory (e.g., flash memory, SDRAM, etc.), one or more modem interfaces, and I / O facilities (e.g., host bridge) for I / O devices (not shown). Generally, any of a variety of memory designs and hierarchies may be used in or in combination with the DFE processor 201. Furthermore, it should be understood that I / O devices may include any desired I / O devices, such as Ethernet, I2C, SPI, GPIO, and / or UART devices. All processor subsystems are linked via a multi-layer interconnect structure 208.

[0061] To digitally process the transmitted signals, the DFE processor 201 may also include programmable transmit signal processing paths for each transmit antenna 253 to 255, wherein each processing path includes a transmit signal processor 220, serialized transmit (TX) interfaces 221 to 223 (SER TX IFC), transmit channels 271 to 273 (i.e., differential signal pairs), and RF transmit front-end circuitry 250 to 252. In this manner, a first transmission signal processing path is formed by connecting the transmission signal processor 220 and the serialized TX interface 221 (including interfaces 221-I and 221-Q). The transmission signal processor 220 and the serialized TX interface 221 are connected via the first transmission channel 271 to the real and imaginary (I and Q) signal lines of the RF transmission front-end circuit 250 and the antenna 253. A second transmission signal processing path is formed by connecting the transmission signal processor 220 and the serialized TX interface 222. The transmission signal processor 220 and the serialized TX interface 222 are connected via the second transmission channel 272 to the differential signal lines of the RF transmission front-end 251 and the antenna 254. A third transmission signal processing path is formed by connecting the transmission signal processor 220 and the serialized TX interface 223. The transmission signal processor 220 and the serialized TX interface 223 are connected via the third transmission channel 273 to the differential signal lines of the RF transmission front-end 252 and the antenna 255. Although in Figure 2 Three transmit signal processing paths are described, but fewer or more transmit signal processing paths can be implemented in other systems.

[0062] The transmit signal processor 220 may include one or more processors (e.g., vector processors) and associated memory (e.g., RAM) for performing carrier-related signal processing and antenna-specific processing on I and Q samples received from a baseband modem. Additionally, according to an embodiment, the transmit signal processor 220 may generate control information (in the form of one or more control bits) that is temporally related to the processed sample. According to an embodiment, the transmit signal processor 220 determines the values ​​of one or more control bits based on the instantaneous voltage value (or magnitude) of the sample processed by the transmit signal processor 220. For example, as will be discussed in more detail later, the control bits may be selected when the instantaneous voltage value is relatively high (e.g., near or above the transition point α). Figure 6A , 6B When the amplifier is activated, the external controllable sub-circuit (e.g., sub-circuit 520, 720) will be used. Figure 5 , 7 (described in more detail below) is configured in the first state, and a control bit can be selected to be in the state when the instantaneous voltage value is relatively low (e.g., below the transition point α). Figure 6A , 6BWhen the external controllable sub-circuit in the amplifier is configured in a second state, the transmit signal processor 220 determines the value of one or more control bits based on the envelope amplitude of the transmit signal. For example, the control bits can be selected to configure the external controllable sub-circuit in the amplifier in a first state when the envelope amplitude is relatively high, and the control bits can be selected to configure the external controllable sub-circuit in the amplifier in a second state when the envelope amplitude is relatively low.

[0063] Once signal processing is complete, and if combined Figure 3 In more detail, the transmit signal processor 220 can send processed I and Q samples, along with one or more control bits, to an associated transmit-side serialization interface (e.g., corresponding serialization TX interfaces 221-I and 221-Q). Essentially, each of the serialization TX interfaces 221-I and 221-Q includes circuitry for serializing an input frame (e.g., a set of consecutive words / octets whose position can be identified by a frame alignment signal) and transmitting the resulting bit stream across a channel (e.g., channel 271). According to embodiments, each serialization TX interface 221-I and 221-Q implements the JESD204 serial link communication protocol (e.g., according to the JESD204A (2006), JESD204B (2012), or JESD204C (2017) serial interface, including future versions, for data converter standards published by the JEDEC Solid State Technology Association). The JESD204 serial link communication protocol represents a family of serial link communication protocols. It should be understood that although the JESD204 serial link communication protocol is used as an example in this document, the data interface can be implemented by other suitable serialized interfaces, or alternatively by parallel interfaces, or by other protocols with similar capabilities.

[0064] According to an embodiment, the serialized TX interface 221-I can combine one or more control bits with I samples, and the serialized TX interface 221-Q can combine (e.g., multiplex) one or more control bits with Q samples, or both the serialized TX interface 221-I and the serialized TX interface 221-Q can combine control bits with both I and Q samples. The serialized TX interface 221-I is then framed, encoded as needed, and serialized into an I data stream, which is then sent to a transceiver (e.g., RF transmit front-end circuitry 250) via one of the differential signal lines of the first transmit channel 271. The serialized TX interface 221-Q is framed, encoded as needed, and serialized into a Q data stream, which is then sent to the transceiver via the other of the differential signal lines of the first transmit channel 271. According to another embodiment, instead of combining one or more control bits with any one or two of the I and / or Q samples, the serialized TX interface 221 can insert an eight-bit byte or word into any one or two of the I and / or Q data streams that include control information (e.g., no-sample data). It should be understood that a particular data link can be composed of a single channel (e.g., channel 271) or multiple channels (e.g., multiple channels among channels 271 to 273) as needed to support the required data transmission volume. Furthermore, each channel 271 to 273 can transmit synchronization and alignment data that allows the transmitted data to be recombined in the RF transmit front-end circuitry 250, thus enabling the reproduction of the original data samples.

[0065] According to an embodiment, the RF transmit front-end circuitry 250 includes one or two serialized receive (RX) interfaces 260-I, 260-Q (SER RX IFC), one or more control circuits 266, 267, digital-to-analog converters (DACs) 262, 263, a low-pass filter (LFF), an oscillator, a mixer, a signal combiner 264, and a power amplifier 265. Essentially, each of the serialized RX interfaces 260-I and 260-Q includes circuitry attached to a channel (e.g., channel 271), wherein said circuitry is configured to reconstruct a serial bit stream into time-aligned frames. According to an embodiment, each of the serialized RX interfaces 260-I and 260-Q implements the JESD204 serial link communication protocol, but other protocols, as mentioned above, may also be implemented. The serialized RX interface 260-I is configured to receive an I data stream from one of the differential signal lines of the first transmit channel 271. When included, the serialized RX interface 260-Q is configured to receive a Q-sample stream from another differential signal line of the first transmit channel 271. In embodiments where the serialized TX interface 221 combines one or more control bits with an I-sample stream (rather than a Q-sample stream), the serialized RX interface 260-Q and control circuitry 267 may be omitted, and the associated differential signal lines of the first transmit channel 271 may instead be directly coupled to the DAC 263, as indicated by the dashed arrow. In other embodiments where the serialized TX interface 221 combines one or more control bits with a Q-sample stream (rather than an I-sample stream), the serialized RX interface 260-I and control circuitry 266 may be omitted, and the associated differential signal lines of the first transmit channel 271 may instead be directly coupled to the DAC 262, as indicated by another dashed arrow.

[0066] Upon receiving an I or Q serialized data stream, each serialized RX interface 260-I, 260-Q is configured to separate one or more control bits from sample bits within the serialized data stream and reconstruct the I or Q sample from the extracted sample bits. Each serialized RX interface 260-I, 260-Q sends the I or Q sample to DAC 262 or 263. Each DAC 262, 263 includes circuitry for converting the digitally sampled data stream into an analog signal. Because the analog signal is derived from a composite data stream, each DAC 262, 263 can be defined as a sub-block receiving the real (I) or imaginary (Q) components of the data stream. Each DAC 262, 263 performs digital-to-analog conversion on each received sample and filters the resulting analog sample (e.g., via an LPF). An oscillator generates an RF sine wave signal for upconverting the analog I and Q samples (to RF). The filtered analog I-sample stream is mixed with the RF signal, and the filtered analog Q-sample stream is mixed with a 90-degree delayed version of the RF signal to realign the I and Q sample streams. Combiner 264 then combines the two sample streams and provides a single RF input signal to power amplifier 265.

[0067] As mentioned above, power amplifier 265 may include one or more externally controllable sub-circuits (e.g., circuits 520, 720, ...). Figure 5 , 7 The operation of the sub-circuit is controlled using one or more control bits received in the I and / or Q serialized data stream. Therefore, after separating one or more control bits from the sample bits within the serialized data stream, each serialized RX interface 260-I, 260-Q sends the control bits to control circuits 266, 267. According to an embodiment, each control circuit 266, 267 can convert one or more received control bits into a control signal and can send the control signal to power amplifier 265 such that the control signal is time-aligned with the converted I or Q sample. In other words, control circuits 266, 267 can buffer the control signal, and more specifically, give the control signal a programmable delay to ensure that amplifier 265 performs the desired circuit modification operation (e.g., controlled by the control signal) while simultaneously amplifying the converted I or Q sample from the same word that extracts one or more control bits associated with the control signal.

[0068] Turn now Figure 2On the receiving side of the system, received signals can be received and digitally processed at the DFE processor 201 in a programmable receive signal processing path for each receive antenna 283 to 285. Each receive signal processing path is formed by RF receive front-end circuits 280 to 282, which are connected to the receive antennas 283 to 285, receive channels 291 to 293 (i.e., differential signal pairs), associated serialized RX interfaces 225 to 227 (e.g., JESD204 RX interfaces), and receive signal processor 224. In this manner, a first receiving signal processing path is formed by connecting antenna 283 and RF receiving front-end circuit 280. Antenna 283 and RF receiving front-end circuit 280 are connected via the differential signal lines of serialized RX interface 225 and receiving signal processor 224 through the first receiving channel 291. A second receiving signal processing path is formed by connecting antenna 284 and RF receiving front-end circuit 281. Antenna 284 and RF receiving front-end circuit 281 are connected via the differential signal lines of serialized RX interface 227 and receiving signal processor 224 through the second receiving channel 292. A third receiving signal processing path is formed by connecting antenna 285 and RF receiving front-end circuit 282. Antenna 285 and RF receiving front-end circuit 282 are connected via the differential signal lines of serialized RX interface 227 and receiving signal processor 224 through the third receiving channel 293. Although in Figure 2 Three receive signal processing paths are described, but fewer or more receive signal processing paths can be implemented in other systems.

[0069] Each RF receiver front-end circuit 280 to 282 includes RF conversion circuit components (e.g., a distributor, oscillator, mixer, low-pass filter (LPF), amplifier, analog-to-digital converter (ADC), etc.) that process RF signals from a corresponding antenna (e.g., antenna 283) by separating the signal into I and Q signal components and converting the I and Q signals into digital serial I and Q data streams for processing by the DFE processor 201.

[0070] The receive signal processor 224 may include one or more processors (e.g., vector processors) and associated memory (e.g., RAM) for performing receive signal processing on IQ samples received from each RF receive front-end circuitry 280-282 via one of the serialized RX interfaces 225-227. Once the signal processing is complete, the receive signal processor 224 may transmit the processed samples to the baseband modem.

[0071] In cases where there are multiple transmit and / or receive signal paths between the DFE processor 201 and antennas 253 to 255, 283 to 285, different signal path delays may exist on each signal path due to different hardware implementations and link delays for each path. For example, different inherent signal path delays can occur along each signal path due to digital filtering, analog-to-digital or digital-to-analog converters, analog components, coaxial length, and other line delays. To avoid potential problems arising from the different inherent delays in each transmit signal path, software-based and / or hardware-based synchronization can be implemented by the DFE processor 201, which controls the serialization interfaces 221 to 223, 225 to 227, to provide timing alignment for data entering and leaving the DFE processor 201.

[0072] To provide additional details of the selected embodiments, reference is now made to... Figure 3 , Figure 3 A more detailed description of RF BTS 200 (e.g., BTS 114, Figure 1 A block diagram of a portion of the invention. To avoid confusion regarding the subject matter of this invention, Figure 3 Depicts a single transmit signal path within BTS 200, the transmit signal path including serialized TX interfaces 221-I and 221-Q (within DFE 201) coupled to serialized RX interfaces 260-I and 260-Q (within RF transmit front end 250).

[0073] As previously combined Figure 2 As discussed above, the RF BTS 200 includes a DFE 201 and an RF transmit front-end circuit 250, which are communicatively coupled via the IQ signal lines of transmit channel 271. As described above, the DFE 201 includes a sample memory 314, a serialized TX interface 221-I, and a serialized TX interface 221-Q, as well as other components. The sample memory 314 (e.g., RAM) is configured to store I and Q data samples for transmission to the RF transmit front-end circuit 250 and ultimately via antenna 253 through the air interface.

[0074] In operation, the base station controller 312 (e.g., BSC 112, Figure 1The system generates I and Q data samples to be transmitted via antenna 253. According to embodiments, each I and Q data sample comprises N bits, where, according to various embodiments, N can be any integer not being an integer multiple of the number of bits M in the data packet (e.g., N can be an integer between 7 and 15 bits). In the examples described below, N = 15 bits (i.e., each I and Q sample is a 15-bit sample). However, in other examples, N can be less than or greater than 15 bits. Regardless, the I and Q data samples used for the transmit signal path are stored in sample memory 314 (e.g., including RAM with I sample buffers and Q sample buffers).

[0075] Each of the serialized TX interfaces 221-I and 221-Q includes first-in-first-out (FIFO) input buffers 302 and 303, encoders 306 and 307, and serializers 308 and 309 connected in series with switchable framer modules 304 and 305 (hereinafter referred to as "framers"). Each FIFO input buffer 302 and 303 receives input from the sample memory 314 (e.g., via interconnect structure 208). Figure 2 It receives I or Q data (and more specifically, a sample stream of I or Q data) and stores the I or Q data as one or more data packets. Each data packet may have the same number of bits M. In a particular embodiment, each data packet is an octet (i.e., a set of eight adjacent binary digits similar to a byte), and therefore M = 8 bits. In other example embodiments, M may be less than or greater than 8 bits.

[0076] According to one embodiment, the number of bits N in the data sample is not equal to the number of bits M in the data packet. According to another embodiment, N is also not an integer multiple of M (e.g., 2×M, 3×M, etc.). Therefore, when an N-bit data sample is stored in one or more M-bit data packets in FIFO input buffer 302 or 303, the N bits of the sample will only partially fill the M available bits of one or more data packets, and at least one bit of one or more data packets will be "unfilled" or "empty" (i.e., no data sample bit). In various embodiments, the number of unfilled or empty bits in the data packet may include as few as one bit or as many as M-1 bits.

[0077] Should be with Figure 3 Viewing at the same time Figure 4 The following is provided to further illustrate data formatting and operations performed by serialized TX interface 221-I and serialized TX interface 221-Q according to an example embodiment. Figure 4The example depicted corresponds to an embodiment where each data sample is 15 bits long (i.e., N = 15) and each data packet is 8 bits long (i.e., M = 8). Specifically, data format 401 depicts a data sample 410 (I or Q) comprising 15 bits (S0 to S14), and data format 402 depicts the bits of data sample 410 stored in two equally sized data packets 420, 421 (e.g., in FIFO 302 or 303). More specifically, the first 8 bits of data sample 410 are stored in the first data packet 420, and the next 7 bits of data sample 410 are stored in the second data packet 421. This leaves one bit 422 of data packet 421 unpadded. It should be noted that although the last bit 422 of data packet 421 is... Figure 4 The data sample 410 is shown as unpadded, but the bits in the data sample 410 can be modified to be stored in data packets 420 and 421 so that different bits in data packets 420 or 421 are unpadded.

[0078] Please refer to again Figure 3 Each framer 304, 305 receives I or Q data packets (e.g., data packets 420, 421) from the FIFO input buffers 302, 303. Figure 4 The framer processes the data into a stream and adds markers to frame each data packet. Additionally, according to an embodiment, each framer 304, 305 also receives one or more control bits from the transmit processor 220 via inputs 316, 317, wherein the one or more control bits are time-aligned with I or Q data packets received from the FIFO input buffers 302, 303. The framers 304, 305 are configured to combine (or multiplex) one or more received control bits into one or more data packets in the received data packets. More specifically, each framer 304, 305 inserts one or more control bits into unfilled bits (e.g., bit 422) of the received data packets. Figure 4 In one or more bits of ). For example, each framer 304, 305 may include a multiplexer (not shown) that receives I or Q data packets as one input and receives one or more control bits as another input, and outputs a modified version of the I or Q data packets including the inserted control bits. Refer again Figure 4 For example, data format 403 describes data packets 420, 421', where data packet 421' includes control bit 423 (C1) inserted into previously unfilled bits 422 of data packet 421. After one or more control bits are inserted into the data packet, each framer 304, 305 delivers an M-bit data packet to encoders 306, 307.

[0079] Each encoder 306, 307 can be configured to convert M-bit data packets into encoded symbols with more than M bits. Encoding in this manner enhances DC balance and provides defined parallax, while providing a sufficient number of state changes to allow for reasonable clock recovery. For example, in an embodiment, each encoder 306, 307 can be an 8b / 10b encoder that receives 8-bit data packets (e.g., packets 420, 421'). Figure 4 The encoders 306 and 307 convert each 8-bit data packet into a 10-bit symbol. In other embodiments, each encoder in 306 and 307 may be a 64b66b encoder, which converts the 64-bit output from framers 304 and 305 into a 66-bit format, or each encoder in 306 and 307 may be a 64b80b encoder, which converts the 64-bit output from framers 304 and 305 into an 80-bit format. The 8b / 10b link layer organizes the data into multiple frames containing K×F octets, where K is the number of frames in the multiple frames and F is the number of octets in each frame. The 64b / 66b and 64b / 80b link layers organize the data into multiple blocks containing 32 blocks, where each block contains eight octets. Other encoding schemes may also be implemented. In some embodiments, the data is transmitted without encoding, in which case encoders 306 and 307 and decoders 363 and 364 may not be included.

[0080] Encoded symbols (or framed data without encoding) generated by encoders 306 and 307 are provided to serializers 308 and 309, which then transmit the encoded symbols serially to the RF transmitter front-end circuit 250 via the IQ signal lines of the transmit channel 271.

[0081] As previously discussed, the RF transmit front-end circuit 250 includes serialized RX interfaces 260-I and / or 260-Q, respectively coupled to the I and Q signal lines of the transmit channel 271. Essentially, upon receiving an I or Q serialized symbol, each serialized RX interface 260-I, 260-Q is configured to decode the symbol (assuming prior encoding), separate one or more control bits from sample bits within the resulting data packet stream, and reconstruct the I or Q sample from the extracted sample bits. The RF transmit front-end circuit 250 is further configured to convert the I and Q samples into analog signals, and to upconvert, combine, and amplify the analog I and Q samples. Additionally, the RF transmit front-end circuit 250 is configured to use one or more control circuits 266, 267 to convert one or more control bits into control signals (e.g., analog or digital control signals) provided to the amplifier 265. According to an embodiment, the amplifier 265 utilizes the control signals to control one or more aspects of the amplification process. Finally, the amplified RF signal generated by the amplifier 265 is delivered to the antenna 253, which transmits the amplified RF signal via an air interface.

[0082] Each of the serialized RX interfaces 260-I and 260-Q includes deserializers 361 and 362 connected in series with decoders 363 and 364, and switchable deframer modules 365 and 366 (hereinafter simply referred to as "deframers"). Essentially, these components are configured to reconstruct data packets previously supplied to framer 304 on the transmit side and also extract control bits from the I and / or Q data streams. More specifically, deserializers 361 and 362 receive encoded serialized I and Q symbols, respectively, transmitted by DFE processor 201 via the IQ signal lines of transmit channel 271. Deserializers 361 and 362 convert the serialized symbol stream into discrete symbols. Assuming encoding is performed on the transmit side, decoders 363 and 364 then decode the symbols by performing the inverse operation of the encoding operation previously performed by encoders 306 and 307. For example, when encoders 306 and 307 are 8b / 10b encoders, decoders 363 and 364 should be 8b / 10b decoders, which generate a stream of 8-bit decoded I and Q data packets from the received 10-bit symbols (e.g., reconstructed versions of packets 420 and 421). Figure 4 Alternatively, encoders 363 and 364 can be 64b66b decoders (i.e., generating 64-bit data packets from 66-bit symbols), 64b80b decoders (i.e., generating 64-bit data packets from 80-bit symbols), or other compatible types of decoders.

[0083] The reconstructed I and Q packets are provided to deframers 365 and 366, respectively. According to an embodiment, each deframer 365 and 366 is configured to demultiplex (or demultiplex) one or more control bits from the received data packets. More specifically, each deframer 365 and 366 extracts one or more bits (e.g., bit 422) from the received data packets. Figure 4 Extract one or more control bits. For example, each deframer 365, 366 may include a demultiplexer (not shown) that receives I or Q packets from decoders 363, 364 and extracts one or more control bits (e.g., C1 423, ...) from one or more specified bits (e.g., bit 422) of the I or Q packets. Figure 4 ), and transmits the control bits to the corresponding control circuits 266 and 267. Although Figure 3 Separate control circuits 266 and 267 are shown, but in some embodiments, a single control circuit (e.g., control circuit 266 or 267) may be implemented, even if control bits are transmitted in both I and Q packets. For example, an embodiment of system 200 may include only control circuit 266, and both frame deframers 365 and 366 may be coupled to a single control circuit 266. In another embodiment, system 200 may include only control circuit 267, and both frame deframers 365 and 366 may be coupled to a single control circuit 267. In either of these embodiments, control circuit 266 or 267 may combine control bits extracted from corresponding time-aligned I and Q packets into a multi-bit control signal.

[0084] In addition to extracting one or more control bits, when each data sample includes data from multiple data packets (e.g., the data sample length N is 15 bits and the length M of each data packet is 8 bits), each deframer 365, 366 reconstructs each data sample from the data bits within multiple (e.g., two or more) consecutive I or Q data packets. For example, refer again... Figure 4 Each frame deframer 365, 366 can combine 15 data bits (e.g., bits S0 to S14) from the reconstructed data packets 420, 421 into a reconstructed data sample that should be the same as the data sample 410.

[0085] Deframers 365 and 366 provide the reconstructed I and Q data samples to digital-to-analog converters 262 and 263, respectively. As previously discussed, each DAC 262 and 263 then performs digital-to-analog conversion on each received sample and filters the resulting analog samples (e.g., via LPFs 370 and 371). Oscillator 372 generates an RF sinusoidal signal for upconverting (to RF) the analog I and Q sample streams generated by DACs 262 and 263 and LPFs 370 and 371. Mixer 373 mixes the filtered analog I sample stream with the RF signal, and mixer 374 mixes the filtered analog Q sample stream with a 90-degree delayed version of the RF signal to realign the upconverted I and Q sample streams in time. Combiner 264 then combines the two sample streams and provides a single RF signal 376 to power amplifier 265.

[0086] As mentioned above, power amplifier 265 may include one or more externally controllable sub-circuits (e.g., circuits 520, 720, ...). Figure 5 , 7 The operation of the externally controllable sub-circuit is controlled using one or more control bits extracted from the I or Q serialized data stream by frame deframers 365 and 366 and provided to control circuits 266 and 267. According to embodiments, each control circuit 266 and 267 may convert one or more received control bits into a control signal (e.g., a TTL signal having low and high logic levels). In some embodiments, control circuits 266 and 267 may include logic circuitry configured to perform the conversion, and in other embodiments, each control circuit 266 and 267 may include a lookup table (LUT) that associates control bit values ​​with control signal characteristics. In a later embodiment, each control circuit 266 and 267 may include additional circuitry to generate control signals having signal characteristics associated with the control bit values ​​(e.g., in the LUT). Regardless, each control circuit 266 and 267 sends control signals 380 and 381 to power amplifier 265 such that the control signals are synchronized (or time-aligned) with the RF signals provided to power amplifier 265 by combiner 264. According to an embodiment, each control circuit 266, 267 may assign a programmable delay to control signals 380, 381 to ensure that amplifier 265 performs the desired operation (as controlled by control signals 380, 381) while extracting one or more converted I and / or Q samples of the associated control bits from the amplifier. The programmable delay should be substantially equal to the delay in the amplifier control circuitry (e.g., after passing through DACs 262, 263, LPF 370, 371, mixers 373, 374, combiner 364, and amplifier 265) (e.g., Figure 5The accumulated sample processing delay is associated with the switch 522 or the variable phase shifter / attenuator 721 to 724, which is connected to one or more points before the transmission path. In some systems, this accumulated sample processing delay may be substantially fixed, and therefore the programmable delay may be a substantially fixed value. In other systems, this accumulated sample processing delay may be variable but deterministic (e.g., using feedback circuitry, for example, between amplifier 265 and DFE 201, not shown), and therefore the programmable delay may be a dynamically variable value. In any case, after the RF signal is amplified by power amplifier 265, the amplified RF signal is provided to antenna 253 for radiation via the air interface.

[0087] As mentioned above, the power amplifier 265 may include one or more externally controllable sub-circuits, the operation of which is controlled using one or more control bits received in the I or Q serialized data stream. For example, Figure 5 The following is a simplified block diagram of a Dougherty power amplifier 500 with an externally controllable sub-circuit 520 according to an example embodiment, which can operate based on the value of one or more control bits received in an I or Q serialized data stream.

[0088] More specifically, the Dougherty amplifier 500 (e.g., amplifier 265, Figure 2 , 3 The circuit includes an input terminal 501, a power divider 502, a carrier amplifier path 504, a peaking amplifier path 506, a summing node 518, an external controllable sub-circuit 520, and an output terminal 503. The power divider 502 is coupled to both the carrier amplifier path 504 and the peaking amplifier path 506, and is configured to receive the input signal (RF-IN, characterized by V) at the input terminal 501. in (instantaneous voltage) (e.g., signal 376, Figure 3 The signal is divided into a carrier RF signal and a peaked RF signal. More specifically, the output of power divider 502 is connected to carrier amplifier 510 (also referred to as the main amplifier) ​​and peaked amplifier 512. Impedance matching networks or circuits (not shown) may be included along the signal transmission path between the output of power divider 502 and the inputs of carrier amplifier 510 and peaked amplifier 512. To ensure proper Dougherty operation, carrier amplifier 510 along carrier amplifier path 504 is biased to operate in Class AB, and peaked amplifier 512 along peaked amplifier path 506 is biased to operate in Class C.

[0089] In the illustrated embodiment, the Dougherty amplifier 500 has a “non-inverting” Dougherty amplifier configuration, wherein an impedance inverter and / or a λ / 4 (90-degree) phase shift element 514 are connected between the output of the carrier amplifier 510 and the summing node 518. The output of the peaking amplifier 512 is also connected to the summing node 518. In some embodiments, the phase shift introduced by element 514 is compensated by a 90-degree relative phase shift present on path 506 introduced by phase shift element 516, which is present between the power divider 502 and the input to the peaking amplifier 512. In an alternative embodiment, the amplifier 500 may have an “inverting” Dougherty configuration. In this configuration, the impedance inverter and / or the λ / 4 line phase shift element 514 are instead connected between the output of the peaking amplifier 512 and the summing node 518, rather than between the output of the carrier amplifier 510 and the summing node 518. Additionally, in the inverted Dougherty implementation, the phase shift introduced by element 514 between the output of peaking amplifier 512 and summing node 518 can be compensated by a 90-degree relative phase shift present on path 504 (e.g., between power divider 502 and the input to carrier amplifier 510) rather than on path 506. An impedance transformation network 528 between summing node 518 and amplifier output 503 is used to present appropriate load impedances to each of carrier amplifier 510 and peaking amplifier 512, and outputs the combined signal generated at summing node 518 as an output signal (RF-OUT) to output terminal 503. The output signal RF-OUT can then be provided to an antenna (e.g., antenna 253). Figure 2 , 3 ), for use in radiating via the air interface.

[0090] The operation of the Dougherty amplifier is based on a well-known first-order concept, where the carrier amplifier 510 and the peaking amplifier 512 are modeled as current sources when unsaturated and as voltage sources when saturated. The Dougherty amplifier operation concept is... Figure 6A and 6B As shown in the figure, Figure 6A and 6B It is depicted in Figure 5 The graphs depict the operation of an idealized Dougherty amplifier, a conventional Dougherty amplifier, and a Dougherty amplifier. Each graph shows data for the carrier amplifier and peaking amplifier used in the Dougherty amplifier. Figure 6A In the diagram, line 600 shows the voltage used for the carrier amplifier, and line 602 shows the voltage used for the peaking amplifier in the idealized Dougherty amplifier. Figure 6B In the graph, line 604 shows the current of the carrier amplifier, and line 606 shows the current of the peaked amplifier in the ideal Dougherty amplifier. In both graphs, the voltage and current values ​​have been normalized around the value 1.0.

[0091] At low input power levels, the peaking amplifier is non-conductive due to its Class C bias. Therefore, all amplification produced by the amplifier is achieved using only the carrier amplifier. As the input power level increases (e.g., VC), the amplification increases. in The level increases, reaching a point (i.e., as in...). Figure 6A and 6B The transition point α marked on both is when the radio frequency (RF) input signal is large enough that the carrier amplifier begins to saturate and produces a constant RF output voltage of 1V (normalized) (see...). Figure 6A (The horizontal portion of line 600). When saturated, the carrier amplifier can be represented and modeled as a voltage source by a first-order principle, such that as the input power further increases, V 载波 Maintain a unit voltage (normalized). This is attributed to the impedance inverters 514 and 528 ( Figure 5 (As shown in the figure), voltage V 峰化 Less than unit voltage. As the input power further increases, the operation of the carrier amplifier and peaking amplifier shifts beyond point α. The carrier amplifier begins to conduct and induces current I. 峰化 This modulates the impedance experienced by the carrier amplifier. This further allows the carrier amplifier to induce additional RF current. At V in / V in_max Under full drive conditions equal to unit voltage, both the carrier amplifier and the peaking amplifier are saturated and produce maximum power.

[0092] In reality, peaking amplifiers are not ideal voltage and current sources. This is due to the Class C operation of peaking amplifiers, at V... in / V in_max When I transitions from below α to above α, 峰化 It won't suddenly jump from zero to above zero. In other words, in Figure 6A and 6B The sharp bends in lines 600, 602, 604, and 606 at the transition point α do not accurately depict the operation of a real Dougherty amplifier. In practice, for I... 峰化 and V 载波 Both have a more gradual response.

[0093] The dashed lines 702 and 704 represent the actual voltage and current curves of a conventional Dougherty amplifier around the transition point α. (As shown in...) Figure 6A As seen in the diagram, regarding the transition point α, the voltage of the carrier amplifier (described by line 602) does not change abruptly from increasing to its maximum value of 1.0V. Instead, as shown by dashed line 702, the transition is gradual. Therefore, in a real amplifier, even at some power output levels greater than the transition point α, the carrier amplifier has not yet reached full saturation, again contradicting the idealized model. Similarly, as in... Figure 6B As seen, the current in the peaking amplifier (described by line 606) does not change abruptly when the peaking amplifier begins to conduct near the transition point α. Instead, as shown by dashed line 704, the transition is gradual. Thus, in a real amplifier, the peaking amplifier is already conducting even at some power outputs below the transition point α, which contradicts the idealized model. These effects can be detrimental to the overall Dougherty efficiency with respect to the transition operating point α.

[0094] By incorporating switch 522 into Dougherty amplifier 500 and controlling the variable resistance of switch 522 according to the method described below, the performance of Dougherty amplifier 500 can be made to more closely approximate the performance of an ideal amplifier compared to conventional devices.

[0095] exist Figure 5 In one embodiment, the external controllable subcircuit 520 includes a resistor switch 522 connected in parallel to the peaking path 506. In various embodiments, the resistor switch 522 may include one or more transistors, such as a p-type high electron mobility transistor (PHEMT) made of gallium arsenide (GaAs), a FET (field-effect transistor) using silicon-on-insulator technology, or other types of transistors. In one embodiment, the resistor switch 522 is a circuit element having two ends with an adjustable resistance between its two terminals. Analog control input 524 receives analog control signals (e.g., from...). Figure 2 , 3 (One of the control circuits 266 and 267), the analog control signal is configured to control the resistance between the two terminals.

[0096] In the illustrated embodiment, the first current-carrying terminal of switch 522 is connected to the peaking path 506 between the output of power divider 502 and the input of peaking amplifier 512. The second current-carrying terminal of switch 522 is connected to a reference voltage (e.g., Vdd or ground) via a ground voltage node. Switch 522 includes a function for receiving an analog control signal V. 控制 The control input 524. According to an embodiment, the analog control input 524 may be coupled to a control circuit (e.g., control circuitry 266 or 267). Figure 2 , 3 The control circuit generates analog control signals (e.g., signal 380 or 381). Figure 2 , 3 The voltage of the control signal sets switch 522 to the desired resistance level between the current-carrying terminals. In this way, it can be based on a control circuit (e.g., control circuit 266 or 267). Figure 2 , 3 The analog control signals provided are used to modify the operation of the external controllable sub-circuit 520.

[0097] In one implementation, switch 522 may be binary, and therefore based on the voltage V of the control signal present at control input 524. 控制 The switch 522 is controlled to be in either a first or second state. For example, a first input value or voltage at input 524 can configure switch 522 to a low-resistance or conductive state (i.e., a "closed" state, where the resistance between the current-carrying terminals is relatively low), and a second input value or voltage at input 524 can configure switch 522 to a high-resistance or non-conductive state (i.e., an "open" state, where the resistance between the current-carrying terminals is relatively high). Alternatively, the input V at input 524 of switch 522... 控制 This can be simulated. In this case, the resistance of switch 522 can respond to V 控制 The analog voltage value is set to a specific analog voltage value. This analog voltage value can then be mapped to a specific resistance value via switch 522. In other embodiments, switch 522 can be configured as multiple different resistors, wherein the V at input 524 of switch 522... 控制 It can be one of several values ​​to select a specific resistor from among those different resistors.

[0098] exist Figure 5 In the embodiment of the Dougherty amplifier 500 depicted herein, a variable resistor or resistor-switching element 522 is used to modulate the RF voltage at the input of the peaking amplifier 512. This modulation controls the operation of the peaking amplifier and improves the overall efficiency of the Dougherty amplifier 500. (See again...) Figure 6A and 6B Curves 802 and 804 represent the curves around the curves according to... Figure 5 The voltage and current curves at the transition point α of the configured Doherty amplifier. (As shown in...) Figure 6A As seen in the amplifier 500 with switch 522, compared to a conventional device (see line 702), the carrier amplifier 510 reaches saturation voltage at a reduced output beyond the transition point α. Similarly, regarding Figure 6B In the amplifier 500 with switch 522, the peaking amplifier 512 begins to conduct at a higher input power level compared to conventional devices (see line 704). These two properties of the Dougherty amplifier 500 can lead to a more desirable and efficient Dougherty power amplifier by enhancing the effective switching characteristics of the peaking amplifier 512. More specifically, as Figure 6A and 6B As shown, by incorporating switch 522 into Dougherty amplifier 500 and controlling the variable resistance of switch 522 according to the method described herein, the performance of Dougherty amplifier 500 can more closely approximate the performance of an ideal amplifier compared to conventional devices.

[0099] In one implementation, for an input signal level of RF-IN that is less than the signal level corresponding to the threshold α, a control signal V is provided at input 524 of switch 522. 控制 This causes switch 522 to be set to low resistance, thereby shunting the RF signal energy present on peaking amplifier path 506 to ground and thus preventing the Class C bias peaking amplifier 512 from turning on and conducting current. Specifically, when switch 522 is set to low resistance, the RF voltage present at the input of peaking amplifier 512 decreases, thereby keeping the peaking amplifier in a non-conductive state. In this state, the equivalent resistance of resistor switch 522 does not need to be close to zero ohms, and in fact, a value greater than zero ohms can be used to limit the RF voltage standing wave ratio (VSWR) mismatch effect attributable to the switching action. Therefore, resistor switch 522 operates as a resistive element, switching between two resistance values ​​or states, where the lower resistance value can be tens of ohms (e.g., between about 5 ohms and about 50 ohms or more), and the higher resistance value can be several orders of magnitude larger (e.g., between about 1000 ohms and about 5000 ohms or more). This allows the carrier amplifier 510 to approach its saturation voltage without interference from the peaking amplifier 512, thus improving the Dougherty efficiency at the transition point α. Conversely, when the input signal level increases to greater than α (at which point the carrier amplifier 510 saturates), the control signal V provided at input 524 of switch 522... 控制 This allows switch 522 to be set to a relatively high resistance, thereby allowing peaking amplifier 512 to start operating.

[0100] Typically, when transitioning from low resistance to high resistance, the control signal V provided at input 524... 控制 This allows switch 522 to switch within a relatively small switching voltage range. For example, the voltage switching range can be as low as V. in_max The resistance is between approximately 1% and approximately 10%. As the resistance of switch 522 increases, an increase in the magnitude of the input signal is observed at the input of peaking amplifier 512, and it begins to conduct. The transition of the resistance of switch 522 from low to high at a relatively small transition voltage results in a smooth but relatively abrupt turn-on of peaking amplifier 512, thereby maintaining a smooth gain response of the overall Dougherty amplifier 500. However, if switch 522 changes from low to high resistance instantaneously or nearly instantaneously, such a resistance change may introduce transient signals into the signal path of the Dougherty amplifier.

[0101] By keeping the resistance of switch 522 low at input levels below the transition point α, the input signal to peaking amplifier 512 is kept small due to the low resistance of switch 522, as most of the signal supplied by power divider 502 to peaking amplifier path 506 passes through switch 522. Therefore, the input signal amplitude remains sufficiently small to prevent peaking amplifier 512 from conducting before carrier amplifier 510 has reached saturation. Under fully driven conditions and when the input level exceeds the transition point α, switch 522 is set to a relatively high resistance, achieving normal Dougherty operation. In one embodiment, the low resistance value of switch 522 is greater than about 10 ohms and can be between about 10 ohms and about 20 ohms. In alternative embodiments, the low resistance value of switch 522 can be in the range of about 20 ohms to about 100 ohms or greater. The high resistance value of switch 522 can be greater than 1,000 ohms, and in some cases, high resistance values ​​(e.g., up to about 5,000 ohms or greater) are permissible for amplifier design.

[0102] In this embodiment, the low resistance value of switch 522 is required to be not equal to or approximately equal to about 0 ohms. If the low resistance of switch 522 would be close to a short circuit, then when the state is changed (from low resistance to high resistance or from high resistance to low resistance), switch 522 could generate an unwanted transient surge in the composite gain response of the amplifier and cause the amplifier to degrade linearity. This transient can be observed in the amplifier's gain, amplitude modulation / phase modulation, linearity, etc. Linearity performance and the amplifier's linearization capability (e.g., using a DPD) are important for cellular infrastructure transmitter applications. Therefore, in the system of the present invention, switch 522 exhibits a resistance of at least 10 ohms for a 50-ohm system when it is in its low resistance state.

[0103] In some embodiments, switch 522 exhibits a response to V. in / V in_max And the resistance changes. Figure 6C To depict the resistance of switch 522 and V in / V in_max A curve graph. For example... Figure 6C As shown, the response of switch 522 is piecewise linear, but other functions can also be used. At V below the transition point α in / V in_max At the specified voltage level, the resistance of switch 522 is set to a relatively low value. As V... in / V in_max When the value changes to above the transition point α, the resistance of switch 522 is expressed as V. 转变 The resistance increases linearly within the transition range. At the end of the transition range, switch 522 is set to a relatively high (e.g., maximum) resistance. In various other embodiments, the resistance of switch 522 may not be determined by V. in / Vin_max Instead of being fixed, the value of switch 522 varies with the amplitude of the envelope of the input signal to the Dougherty amplifier. For example, when the envelope amplitude is relatively low, switch 522 can be set to a first resistance state (e.g., a low resistance state), and when the envelope amplitude is relatively high, switch 522 can be set to a second resistance state (e.g., a high resistance state).

[0104] An alternative implementation of the Dougherty amplifier 500 requires switch 522 to be connected in series between power divider 502 and peaking amplifier 512, rather than in... Figure 5 In the parallel configuration depicted, more specifically, the first current-carrying terminal of switch 522 is connected to the peaking path output of power divider 502, and the second current-carrying terminal of switch 522 is connected to the input of peaking amplifier 512. When connected in series, switch 522 will exhibit resistive characteristics opposite to those described above in the parallel configuration of switch 522. Therefore, when switch 522 is series coupled, for V below the transition point α... in / V in_max At the specified level, the resistance of the switch will be set to a high value, and the resistance will be controlled to decrease linearly throughout the transition range. At the end of the transition range, the resistance of switch 522 will be set to a low (e.g., minimum) resistance value. In a series configuration, although the low resistance state may be at or near zero ohms (e.g., between about 0 ohms and about 5 ohms) compared to the parallel configuration described above, the high resistance state should be limited to a maximum higher value (e.g., between about 100 ohms and about 300 ohms or greater), for example, about 200 ohms, to prevent VSWR mismatch effects that could cause discontinuities in amplifier gain and / or phase, for example.

[0105] As indicated above, the Dougherty amplifier 500 with externally controllable sub-circuit 520 can be used as Figure 2 and 3 Amplifier 265. Therefore, control signals 380 or 381 may correspond to control signals provided to control input 524. In other embodiments, a Dougherty amplifier with additional or different external controllable sub-circuit may be used for amplifier 265. For example, another embodiment of the Dougherty amplifier may include variable phase and / or variable amplitude circuitry along carrier and / or peaking paths 504, 506, and control signals 380, 381 may provide signals affecting the operation of the variable phase and / or variable amplitude circuitry to the Dougherty amplifier.

[0106] For example, Figure 7 This is a simplified block diagram of another embodiment of a Dougherty power amplifier 700 with an externally controllable sub-circuit 720 according to an example embodiment, which can operate based on the values ​​of one or more control bits received in an I or Q serialized data stream.

[0107] More specifically, the Dougherty amplifier 700 (e.g., amplifier 265, Figure 2 , 3 The circuit includes an input terminal 701, a power divider 702, a carrier amplifier path 704, a peaking amplifier path 706, a summing node 718, an external controllable sub-circuit 720, and an output terminal 703. The power divider 702 is coupled to both the carrier amplifier path 704 and the peaking amplifier path 706 and is configured to receive the input signal (RF-IN) (e.g., signal 376) at the input terminal 701. Figure 3 The signal is divided into a carrier RF signal and a peaked RF signal. The output of power divider 702 is connected to carrier amplifier 710 and peaked amplifier 712, and an impedance matching network or circuit (not shown) may be included along the signal transmission path between the output of power divider 702 and the inputs of carrier amplifier 710 and peaked amplifier 712. To ensure proper Dougherty operation, carrier amplifier 710 is biased to operate in Class AB mode, and peaked amplifier 712 is biased to operate in Class C mode.

[0108] In the illustrated embodiment, the Dougherty amplifier 700 has a “non-inverting” Dougherty amplifier configuration as described above, wherein an impedance inverter and / or a λ / 4 (90-degree) phase shift element 714 are connected between the output of the carrier amplifier 710 and the summing node 718. The output of the peaking amplifier 712 is also connected to the summing node 718. In some embodiments, the phase shift introduced by element 714 is compensated by a 90-degree relative phase shift present on path 706 introduced by phase shift element 716, which is present between the power divider 702 and the input to the peaking amplifier 712. In alternative embodiments, amplifier 700 may have the configuration described above. Figure 5 The described "inverted" Dougherty configuration. An impedance transformation network 728 between the summing node 718 and the amplifier output 703 is used to present the appropriate load impedance to each of the carrier amplifier 710 and the peaking amplifier 712, and outputs the combined signal generated at the summing node 718 as an output signal (RF-OUT) to the output terminal 703. The output signal RF-OUT can then be provided to an antenna (e.g., antenna 253). Figure 2 , 3 ), for use in radiating via the air interface.

[0109] The Dougherty amplifier 700 also includes an externally controllable sub-circuit 720. Specifically, the sub-circuit 720 includes any one or more of a first variable phase shifter 721 and / or a first variable attenuator 722 disposed along a carrier amplification path 704 between the power divider 702 and the input to the carrier amplifier 710, and a second variable phase shifter 723 and / or a second variable attenuator 724 disposed along a peaking amplification path 706 between the power divider 702 and the input to the peaking amplifier 712. Each of the variable phase shifters 721, 723 can be controlled by a controller 725 to apply one of a plurality of phase shifts to the carrier RF signal or the peaking RF signal, respectively. Similarly, each of the variable attenuators 722, 724 can be controlled by the controller 725 to attenuate the carrier RF signal or the peaking RF signal to one of a plurality of attenuation levels, respectively.

[0110] The controller 725 includes a function for receiving digital control signals D. 控制 The control input 726, this digital control signal can be a single or multi-bit value. 控制 The value can specifically indicate one (or a combination of) a plurality of phase shift and / or attenuation settings for variable phase shifters 721, 723 and / or variable attenuators 722, 724. According to an embodiment, digital control input 726 can be coupled to control circuitry (e.g., control circuitry 266 or 267). Figure 2 , 3 The control circuit generates a control signal (e.g., signal 380 or 381). Figure 2 , 3 The controller 725 determines the phase shift and / or attenuation level to be applied by one or more of the variable phase shifters 721, 723 or variable attenuators 722, 724 based on the digital value of the control signal. In this way, the phase shift and / or attenuation level can be determined based on the control circuitry (e.g., control circuitry 266 or 267). Figure 2 , 3 The provided digital control signals are used to modify the operation of the external controllable sub-circuit 720. Although combined with... Figures 5 to 7 Two example amplifiers with controllable sub-circuits are shown and described, but in other embodiments, other types of amplifiers, including other types of external controllable sub-circuits, may also be used in amplifier 265. Figure 2 , 3 ).

[0111] Figure 8 For use according to the example embodiment via a digital data processor (e.g., DFE201, Figure 2 , 3 ), digital-to-analog converters (e.g., DAC 262, 263, Figure 2 , 3) and amplifiers for the RF transmitter group (e.g., amplifiers 265, 500, 700, Figure 2 , 3 A flowchart illustrating a method for transmitting data and control signals via a serial link between (5, 7). In block 802, the digital data processor (e.g., transmitter processor 220, ...) Figure 2 This generates multiple digital data samples (e.g., I and / or Q samples) and one or more control bits. In block 804, this is achieved through one or more serialized transmit interfaces (e.g., interface 221-I and / or 221-Q). Figure 2 , 3 This combines digital data samples and one or more control bits into one or more data packets. In block 806, the serialization transmit interface is transmitted via signal lines (e.g., one of signal lines 271). Figure 2 , 3 One or more data packets may be transmitted as one or more transmit data packets via a signal channel (e.g., including two of signal lines 271) or a signal channel.

[0112] In box 808, on the receiving side, one or more serialized receive interfaces (e.g., interface 260-I and / or 260-Q, Figure 2 , 3 One or more transmitted data packets are received from a signal line (or signal channel). One or more serialized receive interfaces then generate one or more reconstructed digital data samples from the one or more transmitted data packets. Furthermore, according to an embodiment, the one or more serialized receive interfaces also generate one or more control bits from the one or more transmitted data packets. In block 810, one or more control circuits (e.g., control circuits 266, 267, ...) Figure 2 , 3 One or more analog and / or digital control signals are generated from one or more control bits produced by the serialized receive interface.

[0113] In block 812, the converter circuit (e.g., including...) Figure 2 , 3 The DACs 262, 263, LPFs 370, 371, mixers 373, 374, and combiner 264 generate an RF input signal (e.g., signal 376) by performing digital-to-analog conversion on reconstructed digital data samples to produce an analog data sample signal, and upconverting the analog data sample signal to RF. Figure 3 Finally, in box 814, the power amplifier (e.g., PA 265, 500, 700, ...) Figure 2 , 35, 7) Amplify the RF input signal. As previously described, the power amplifier includes sub-circuits (e.g., sub-circuits 520, 720, etc.) that can be controlled based on control signals generated by the control circuitry. Figure 5 , 7 According to an embodiment, the power amplifier modifies the operation of the sub-circuit based on control signals.

[0114] Although the embodiments of the subject matter of the invention described above and illustrated in the figures include a receiver circuit system having a digital-to-analog converter that converts received digital data samples into analog signals (the analog signals being coupled to a power amplifier having sub-circuit controllable based on received control bits), the subject matter of the invention can also be applied to other types of systems. More generally, the subject matter of the invention includes encapsulating (e.g., combining in one or more data packets) control bits with digital data samples such that when the combined control bits and digital data samples are transmitted through a communication link (e.g., a signal line or channel) with variable delay, the control bits and digital data samples remain synchronized (i.e., time-aligned with each other) all the way to the receiver circuit system. As discussed in detail above, control bits are inserted into bits in the data packets that were originally unused (i.e., not filled with data bits). On the receiving side of the system, the utilization and / or processing of control bits and digital data samples is application-specific. Therefore, while some embodiments include applications associated with a receiver comprising a digital-to-analog converter that generates an analog signal from received digital data samples and up-converts the resulting analog signal into an RF signal amplified by a power amplifier (e.g., where the amplification is influenced by received control bits), other embodiments may include receiver circuitry systems different from digital-to-analog converters (i.e., digital devices different from digital-to-analog converters) and / or applications different from RF amplification. In other words, how control bits and digital data samples are utilized and processed on the receiving side of the system is application-specific and not limited to receiver circuitry systems including digital-to-analog converters or RF power amplifiers. Furthermore, while some embodiments discussed above and illustrated in the figures are associated with communication systems that transmit / receive RF signals via an air interface using an antenna, in other embodiments, the communication medium may include physical transmission media, such as cables, optical fibers, etc., rather than an air interface.

[0115] An embodiment of a communication system includes: a digital data processor configured to generate digital data samples and one or more control bits; and a serialized transmit interface coupled to the digital data processor and a first end of a signal line. The serialized transmit interface is configured to combine the digital data samples with the one or more control bits into one or more data packets, and transmit the one or more data packets as one or more transmitted data packets via the signal line. The system further includes a serialized receive interface coupled to a second end of the signal line. The serialized receive interface is configured to receive the one or more transmitted data packets from the signal line, generate reconstructed digital data samples from the one or more transmitted data packets, and generate the one or more control bits from the one or more transmitted data packets. The system further includes control circuitry coupled to the serialized receive interface and configured to generate control signals from the one or more control bits provided by the serialized receive interface.

[0116] According to another embodiment, the system may further include a converter circuit configured to generate an RF input signal by performing digital-to-analog conversion on the reconstructed digital data samples to generate an analog data sample signal and up-converting the analog data sample signal to radio frequency (RF). The system may further include a power amplifier comprising sub-circuits controllable based on a control signal generated by the control circuit, wherein the power amplifier is configured to amplify the RF input signal and modify the operation of the sub-circuits based on the control signal. According to another embodiment of the system, the serialized transmit interface and the serialized receive interface implement the JESD204 serial link communication protocol.

[0117] According to another further embodiment of the system, the serialized transmit interface is configured to combine the digital data sample and the one or more control bits into the one or more data packets by combining at least one bit of the digital data sample and at least one of the one or more control bits into the data packet in the one or more data packets. According to yet another further embodiment of the system, the serialized transmit interface is configured to transmit the one or more data packets as one or more transmitted data packets via the signal line by: encoding the one or more data packets to generate one or more encoded symbols; and transmitting the one or more data packets via the serial link within the one or more encoded symbols. According to another embodiment, the serialized receive interface is configured to receive the one or more transmitted data packets from the signal line by decoding the one or more encoded symbols.

[0118] According to another further embodiment of the system, the control circuitry includes a buffer with a programmable delay configured to synchronize the amplification of the RF input signal in the power amplifier with the modification of the operation of the sub-circuit based on the control signal. According to another further embodiment of the system, the control circuitry is configured to generate the control signal from the one or more control bits in the form of an analog control signal. According to another embodiment, the sub-circuit of the power amplifier includes a switch, and the power amplifier is configured to modify the operation of the sub-circuit by changing the state of the switch based on the analog control signal. According to another further embodiment, the power amplifier is a Dougherty power amplifier having a carrier amplifier path and a peaking amplifier path, and wherein the switch is connected to the peaking amplifier path in a parallel configuration. According to another further embodiment, the control circuitry is configured to generate the control signal from the one or more control bits in the form of a digital control signal. According to another embodiment, the sub-circuit of the power amplifier includes a digital control circuit, and the power amplifier is configured to modify the operation of the sub-circuit by changing the operation of the digital control circuit based on the digital control signal.

[0119] According to another further embodiment, the power amplifier is a Dougherty power amplifier having a carrier amplifier path and a peaking amplifier path. The Dougherty power amplifier includes a power divider configured to divide the RF input signal into a carrier RF signal and a peaking RF signal. The digital control circuit includes one or more variable phase shifters coupled to either or both of the carrier amplifier path and the peaking amplifier path. The power amplifier is configured to modify the operation of the digital control circuit by changing one or more phase shifts applied to either or both of the carrier RF signal and the peaking RF signal by the one or more variable phase shifters. According to another embodiment, the converter circuit includes: a digital-to-analog converter configured to perform the digital-to-analog conversion to generate the analog signal; and an upconversion converter configured to upconvert the analog signal to RF.

[0120] A method performed by a communication system includes generating digital data samples and one or more control bits via a digital data processor. The method further includes: combining the digital data samples and the one or more control bits into one or more data packets via a serialized transmit interface; and transmitting the one or more data packets as one or more transmitted data packets via the serialized transmit interface through the signal line. The method further includes: receiving the one or more transmitted data packets from the signal line via a serialized receive interface; generating reconstructed digital data samples from the one or more transmitted data packets via the serialized receive interface; and generating the one or more control bits from the one or more transmitted data packets via the serialized receive interface. The method further includes generating control signals from the one or more control bits generated by the serialized receive interface via control circuitry.

[0121] According to another embodiment, the method may further include generating an RF input signal by performing digital-to-analog conversion on the reconstructed digital data samples to generate an analog data sample signal and upconverting the analog data sample signal to radio frequency (RF). The method may further include amplifying the RF input signal by a power amplifier including a sub-circuit controllable based on a control signal generated by the control circuit. The method may further include modifying the operation of the sub-circuit based on the control signal using the power amplifier.

[0122] According to another embodiment of the method, the serialized transmit interface and the serialized receive interface implement the JESD204 serial link communication protocol. According to a further embodiment of the method, transmitting the one or more data packets as one or more transmitted data packets via the signal line through the serialized transmit interface includes encoding the one or more data packets to generate one or more encoded symbols, and transmitting the one or more data packets within the one or more encoded symbols via the serial link; and receiving the one or more transmitted data packets from the signal line through the serialized receive interface includes decoding the one or more encoded symbols. According to yet another embodiment of the method, generating the control signal through the control circuitry includes delaying the generation of the control signal with a programmable delay, the programmable delay being configured to synchronize the amplification of the RF input signal with the operation of modifying the sub-circuit in the power amplifier based on the control signal. According to yet another embodiment of the method, generating the control signal includes generating an analog control signal, the sub-circuit of the power amplifier includes a switch, and modifying the operation of the sub-circuit includes changing the state of the switch based on the analog control signal. According to another further embodiment of the method, generating the control signal includes generating a digital control signal, the sub-circuit of the power amplifier includes a digital control circuit, and modifying the sub-circuit includes changing the digital control circuit based on the digital control signal. According to yet another further embodiment of the method, the power amplifier is a Dougherty power amplifier, and modifying the sub-circuit based on the control signal includes modifying the Dougherty power amplifier.

[0123] The preceding detailed description is illustrative in nature only and is not intended to limit embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, illustration, or description." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, one is not to be bound by any expressed or implied theories presented in the foregoing prior art, background art, or detailed description.

[0124] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of the subject matter. Furthermore, certain terms may be used herein for reference only and therefore are not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to a reference structure do not imply a sequence or order.

[0125] As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity exists. Furthermore, two or more nodes can be implemented with a single physical element (and although received or output at a common node, two or more signals can still be multiplexed, modulated, or otherwise distinguished).

[0126] The above description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly communicates with) another element, and not necessarily mechanically engaged. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly communicates with) another element electrically or otherwise, and not necessarily mechanically engaged. Therefore, although the schematic diagrams shown depict an exemplary arrangement of elements, additional intervening elements, means, features, or components may be present in embodiments of the depicted subject matter.

[0127] While at least one exemplary embodiment has been presented in the detailed description above, it should be understood that numerous variations exist. It should also be understood that the one or more exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the detailed description above will provide a convenient guide for those skilled in the art to implement the one or more described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. A communication system, characterized in that, include: A digital data processor configured to generate digital data samples and one or more control bits; A serialized transmit interface, coupled to the first end of the digital data processor and signal line, wherein the serialized transmit interface is configured to... The digital data sample is combined with the one or more control bits into one or more data packets, and The one or more data packets are transmitted via the signal line as one or more transmitted data packets; A serialized receiving interface, wherein the serialized receiving interface is coupled to the second end of the signal line, wherein the serialized receiving interface is configured to Receive one or more transmitted data packets from the signal line. Reconstructed digital data samples are generated from the one or more transmitted data packets, and The one or more control bits are generated from the one or more transmitted data packets; A converter circuit configured to generate an RF input signal by performing digital-to-analog conversion on the reconstructed digital data samples to generate an analog data sample signal and upconverting the analog data sample signal to radio frequency (RF). Power amplifier; A control circuit coupled to the serialized receive interface and configured to generate a control signal from one or more control bits provided by the serialized receive interface and send the control signal to the power amplifier so that the control signal is time-aligned with the RF input signal; The power amplifier includes a sub-circuit controllable based on the control signal generated by the control circuit, wherein the power amplifier is configured to amplify the RF input signal and modify the operation of the sub-circuit based on the control signal.

2. The communication system according to claim 1, characterized in that, The serialized transmit interface and the serialized receive interface implement the JESD204 serial link communication protocol.

3. The communication system according to claim 1, characterized in that, The serialized transmit interface is configured to combine the digital data sample and the one or more control bits into the one or more data packets by combining at least one bit of the digital data sample and at least one control bit of the one or more control bits into the data packets in the one or more data packets.

4. The communication system according to claim 1, characterized in that, The serialized transmit interface is configured to transmit the one or more data packets as one or more transmitted data packets via the signal line by the following operation: Encode the one or more data packets to produce one or more encoded symbols; and The one or more data packets are transmitted via a serial link within the one or more encoded symbols.

5. The communication system according to claim 4, characterized in that, The serialized receive interface is configured to receive one or more transmitted data packets from the signal line by: Decode the one or more encoded symbols.

6. The communication system according to claim 1, characterized in that, The control circuitry includes a buffer with a programmable delay configured to synchronize the amplification of the RF input signal in the power amplifier with the modification of the operation of the sub-circuit based on the control signal.

7. The communication system according to claim 6, characterized in that, The control circuit is configured to generate the control signal from the one or more control bits in the form of an analog control signal.

8. The communication system according to claim 7, characterized in that, The sub-circuit of the power amplifier includes a switch, and the power amplifier is configured to modify the operation of the sub-circuit by changing the state of the switch based on the analog control signal.

9. A method executed by a communication system, characterized in that, The method includes: A digital data processor generates digital data samples and one or more control bits. The digital data samples and one or more control bits are combined into one or more data packets through a serialized transmission interface; The one or more data packets are transmitted via the serialized transmit interface as one or more transmitted data packets through the signal lines; Receive one or more transmitted data packets from the signal line through the serialized receive interface; Reconstructed digital data samples are generated from the one or more transmitted data packets through the serialized receive interface; The one or more control bits are generated from the one or more transmitted data packets through the serialized receive interface; An RF input signal is generated by performing digital-to-analog conversion on the reconstructed digital data sample to generate an analog data sample signal and upconverting the analog data sample signal to radio frequency (RF). A control signal is generated from one or more control bits produced by the serialized receive interface by a control circuit and the control signal is sent to a power amplifier so that the control signal is time-aligned with the RF input signal.

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