Driving substrate and display panel

Abstract

The application discloses a driving substrate and a display panel. The driving substrate comprises a substrate, a first gate, a first gate insulating layer, an active layer, a passivation layer, a source and a drain. The first gate is arranged on the substrate. The active layer is arranged on the substrate. The first gate insulating layer is arranged between the active layer and the first gate. The first gate insulating layer comprises a first barrier layer, a second barrier layer and a third barrier layer arranged in sequence. The adhesion between the first barrier layer and the second barrier layer and / or the adhesion between the second barrier layer and the third barrier layer is greater than the adhesion between the first barrier layer and the third barrier layer. The passivation layer is arranged on the substrate. The source and the drain are arranged on the passivation layer and are electrically connected to the active layer respectively.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving substrate and a display panel. Background Technology

[0002] Currently, the adhesion of the stacked structure in any insulating layer of the driving substrate is poor. Furthermore, the main material of the gate and source / drain metal layers is copper, and copper ions readily diffuse, resulting in high defect states at the interface between the insulating layer and the active layer. This makes it easy to trap electrons, thus affecting the carrier concentration in the active layer channel. Additionally, the metal oxide active layer material is sensitive to moisture; external moisture easily penetrates and reacts, affecting the carrier concentration in the back channel and thus degrading the characteristics of the active layer.

[0003] Therefore, it is necessary to propose a new technical solution to solve the above-mentioned technical problems. Summary of the Invention

[0004] This application provides a driving substrate and a display panel to solve the technical problem of poor adhesion between the layers of insulating layers in existing multi-layer stacked structures.

[0005] This application provides a driving substrate, the driving substrate comprising:

[0006] Substrate;

[0007] A first gate, wherein the first gate is disposed on the substrate;

[0008] An active layer is disposed on the substrate;

[0009] A first gate insulating layer is disposed between the active layer and the first gate. The first gate insulating layer includes a first barrier layer, a second barrier layer and a third barrier layer stacked sequentially, wherein the adhesion between the first barrier layer and the second barrier layer and / or the adhesion between the second barrier layer and the third barrier layer is greater than the adhesion between the first barrier layer and the third barrier layer.

[0010] A passivation layer is disposed on the substrate;

[0011] The source electrode is disposed on the passivation layer and electrically connected to the active layer;

[0012] The drain electrode is disposed on the passivation layer and electrically connected through the active layer.

[0013] Optionally, in some embodiments of this application, the substrate includes a first portion and a second portion located on both sides of the first portion, and the active layer includes a channel region and doped regions located on both sides of the channel region, the channel region corresponding to the first portion; wherein

[0014] The first barrier layer, the second barrier layer, and the third barrier layer are disposed corresponding to the first portion, and at least one of the first barrier layer and the third barrier layer is disposed corresponding to the second portion.

[0015] Optionally, in some embodiments of this application, the second blocking layer includes a first blocking portion, a plurality of first supporting portions, and a second blocking portion; wherein

[0016] The first blocking portion is disposed on the side of the first blocking layer near the substrate, a plurality of first supporting portions are disposed at intervals on the first blocking portion, and the second blocking portion is disposed on the side of the first supporting portion near the third blocking layer.

[0017] Optionally, in some embodiments of this application, the driving substrate further includes an organic filler layer that fills the gaps formed by the plurality of first supports.

[0018] Optionally, in some embodiments of this application, the materials of the first barrier layer and the third barrier layer include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the second barrier layer includes at least one of aluminum oxide, chromium oxide, silver oxide, and titanium oxide.

[0019] Optionally, in some embodiments of this application, the passivation layer includes a first barrier layer, an adsorption layer, and a second barrier layer stacked sequentially.

[0020] Optionally, in some embodiments of this application, the adsorption layer includes a first adsorption section, a plurality of adsorption columns, and a second adsorption section; wherein

[0021] The first adsorption part is disposed on the side of the first isolation layer near the substrate, and a plurality of adsorption columns are disposed at intervals on the first adsorption part, and the second adsorption part is disposed on the side of the adsorption columns near the second isolation layer.

[0022] Optionally, in some embodiments of this application, the materials of the first insulating layer and the second insulating layer include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the adsorption layer includes a nanopolymer material.

[0023] Optionally, in some embodiments of this application, the driving substrate further includes:

[0024] A second gate insulating layer is disposed on the side of the active layer away from the first gate insulating layer. The second gate insulating layer corresponding to the first portion includes a fourth barrier layer, a fifth barrier layer, and a sixth barrier layer stacked sequentially.

[0025] The fifth barrier layer includes a third barrier portion, a plurality of second support portions and a fourth barrier portion. The third barrier portion is disposed on the side of the active layer near the substrate. The plurality of second support portions are spaced apart on the third barrier portion. The fourth barrier portion is disposed on the side of the second support portion near the sixth barrier layer.

[0026] The second gate is disposed on the side of the second gate insulating layer away from the active layer;

[0027] Connecting electrodes are used to connect the first gate and the second gate.

[0028] Accordingly, this application also provides a display panel including the aforementioned driving substrate, wherein the driving substrate is used to drive the display panel to emit light.

[0029] This application provides a driving substrate, which includes a substrate, a first gate, a first gate insulating layer, an active layer, a passivation layer, a source, and a drain. The first gate is disposed on the substrate. The active layer is disposed on the substrate. The first gate insulating layer is disposed between the active layer and the first gate. The first gate insulating layer includes a first barrier layer, a second barrier layer, and a third barrier layer stacked sequentially, wherein the adhesion between the first and second barrier layers and / or the adhesion between the second and third barrier layers is greater than the adhesion between the first and third barrier layers. The passivation layer is disposed on the substrate. The source and drain are disposed on the passivation layer and are electrically connected to the active layer, respectively. In the driving substrate provided in this application, the adhesion between the stacked structures in the multi-layered first gate insulating layer is improved because the adhesion between the first and second barrier layers and / or the adhesion between the second and third barrier layers is greater than the adhesion between the first and third barrier layers. Furthermore, since the first gate insulating layer is a three-layer stacked structure, the path for metal atoms in the first gate to diffuse to the active layer is extended, preventing defects from forming at the interface between the active layer and the first gate insulating layer, which would make it easier for electrons to be trapped at the interface, thereby affecting the carrier concentration of the channel of the active layer. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a schematic diagram of a first structure of the driving substrate provided in an embodiment of this application;

[0032] Figure 2 for Figure 1 Enlarged view of some of the structures in the image;

[0033] Figure 3 This is a schematic diagram of the structure of the adsorption layer provided in an embodiment of this application;

[0034] Figure 4 This is a schematic diagram of a second structure of the driving substrate provided in an embodiment of this application;

[0035] Figure 5 This is a schematic diagram of a third structure of the driving substrate provided in an embodiment of this application;

[0036] Figure 6 This is a schematic diagram of a fourth structure of the driving substrate provided in the embodiments of this application;

[0037] Figure 7 for Figure 6 Enlarged view of part of the structure. Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Please refer to the figures in the drawings, where the same component symbols represent the same components. The following description is based on the specific embodiments of this application shown, and should not be considered as limiting other specific embodiments not detailed herein. The term "embodiment" as used in this specification means example, illustration, or illustration.

[0039] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0040] This application provides a driving substrate. Detailed descriptions follow. It should be noted that the order of description of the following embodiments is not intended to limit the preferred order of the embodiments.

[0041] This application provides a driving substrate, which includes a substrate, a first gate, a first gate insulating layer, an active layer, a passivation layer, a source, and a drain. The first gate is disposed on the substrate. The active layer is disposed on the substrate. The first gate insulating layer is disposed between the active layer and the first gate. The first gate insulating layer includes a first barrier layer, a second barrier layer, and a third barrier layer stacked sequentially, wherein the adhesion between the first and second barrier layers and / or the adhesion between the second and third barrier layers is greater than the adhesion between the first and third barrier layers. The passivation layer is disposed on the substrate. The source and drain are disposed on the passivation layer and are electrically connected to the active layer, respectively. In the driving substrate provided in this application, the adhesion of the multilayered structure in the first gate insulating layer is improved because the adhesion between the first and second barrier layers and / or the adhesion between the second and third barrier layers is greater than the adhesion between the first and third barrier layers. Furthermore, since the first gate insulating layer is a three-layer stacked structure, the path for metal atoms in the first gate to diffuse to the active layer is extended, preventing defects from forming at the interface between the active layer and the first gate insulating layer, which would make it easier for electrons to be trapped at the interface, thereby affecting the carrier concentration of the channel of the active layer.

[0042] The driving substrate provided in this application will be described in detail below through specific embodiments.

[0043] Please refer to Figure 1 , Figure 1This is a schematic diagram of a first structure of a driving substrate provided in an embodiment of this application. The driving substrate 100 provided in this embodiment includes a substrate 101, a first gate 104a, an active layer 102, a first gate insulating layer 103, a passivation layer 105, a source 106, and a drain 107. Specifically, the first gate 104a is disposed on the substrate 101. The first gate insulating layer 103 is disposed on the side of the first gate 104a away from the substrate 101. The first gate insulating layer 103 includes a first barrier layer 103a, a second barrier layer 103b, and a third barrier layer 103c stacked sequentially. The adhesion between the first barrier layer 103a and the second barrier layer 103b and / or the adhesion between the second barrier layer 103b and the third barrier layer 103c is greater than the adhesion between the first barrier layer 103a and the third barrier layer 103c. The active layer 102 is disposed on the side of the first gate insulating layer 103 away from the first gate 104a. A passivation layer 105 is disposed on the side of the first gate insulating layer 103 away from the substrate 101. The passivation layer 105 covers the first gate insulating layer and the active layer 102. A source electrode 106 and a drain electrode 107 are disposed on the passivation layer 105 and electrically connected to the active layer 102, respectively. In the driving substrate 100 provided in this embodiment, the adhesion between the first barrier layer 103a and the second barrier layer 103b and / or the adhesion between the second barrier layer 103b and the third barrier layer 103c is greater than the adhesion between the first barrier layer 103a and the third barrier layer 103c, thus improving the adhesion of the multilayered structure in the first gate insulating layer 103. Furthermore, since the first gate insulating layer 103 is a three-layer stacked structure, it extends the path for metal atoms in the first gate 104a to diffuse to the active layer 102, preventing defects from being caused at the interface between the active layer 102 and the first gate insulating layer 103, which would make it easy for electrons to be trapped at the interface, thereby affecting the carrier concentration of the channel of the active layer 102.

[0044] Optionally, the substrate 101 includes a first portion 101a and a second portion 101b located on both sides of the first portion 101a. The active layer 102 includes a channel region 102a and doped regions 102b located on both sides of the channel region 102a. The channel region 102a corresponds to the first portion 101a. Furthermore, a first barrier layer 103a, a second barrier layer 103b, and a third barrier layer 103c are disposed corresponding to the first portion 101a. At least one of the first barrier layer 103a and the third barrier layer 103c corresponds to the second portion 101b. In this embodiment, since the first gate insulating layer 103 corresponding to the channel region 102a is a three-layer stacked structure, the path for metal atoms in the first gate 104a to diffuse to the active layer 102 is extended, preventing defects at the interface between the active layer 102 and the first gate insulating layer 103, which would otherwise easily trap electrons at the interface, thus affecting the carrier concentration of the channel in the active layer 102. In addition, since the first gate insulating layer 103 corresponding to the second part 101b does not have a second barrier layer 103b, parasitic capacitance is avoided between the second barrier layer 103b and the doped region 102b, the source 106, and the drain 107.

[0045] In some embodiments, the substrate 101 may be a glass substrate or a flexible substrate. The substrate 101 may further include a first flexible substrate layer, a silicon dioxide layer, a second flexible substrate layer, and a buffer layer sequentially stacked on top of each other. The second flexible substrate layer is made of the same material as the first flexible substrate, and may include at least one of PI (polyimide), PET (polyethylene dicarboxylate), PEN (polyethylene naphthalate), PC (polycarbonate), PES (polyethersulfone), PAR (aromatic fluorotoluene containing polyarylate), or PCO (polycyclic olefin). The buffer layer is composed of one or more stacked structures of silicon-containing nitrides, silicon-containing oxides, or silicon-containing oxide oxynitrides.

[0046] In some embodiments, the material of the first gate 104a can be metals or alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu; a gate metal layer composed of multiple metals can also meet the requirements. The material of the active layer 102 can be low-temperature polycrystalline silicon, such as N-type doped low-temperature polycrystalline silicon, or metal oxide semiconductor materials, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium zinc oxide (IZO), gallium indium oxide (IGO), indium gallium tin oxide (IGTO), indium zinc tin oxide (IZTO), and indium tin oxide (ITO). The source 106 and drain 107 can be metals or alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu; a gate metal layer composed of multiple metals can also meet the requirements.

[0047] Please combine Figure 1 and Figure 2 , Figure 2for Figure 1 The diagram shows a partial enlarged view of the structure. The second barrier layer 103b includes a first barrier portion 103b1, a plurality of first support portions 103b2, and a second barrier portion 103b3. The first barrier portion 103b1 is disposed on the side of the first barrier layer 103a near the substrate 101. The plurality of first support portions 103b2 are spaced apart on the first barrier portion 103b1. The second barrier portion 103b3 is disposed on the side of the first support portion 103b2 near the third barrier layer 103c. In this embodiment, since the array of first support portions 103b2 is arranged between the first barrier portion 103b1 and the second barrier portion 103b3, this arrangement method can avoid the generation of parasitic capacitance. Furthermore, since the gap between two adjacent first support portions 103b2 forms a closed space, when metal atoms in the first gate 104a diffuse to the second barrier layer 103b, the metal atoms can be sealed in the closed space, thereby preventing metal atoms from diffusing into the channel region 102a of the active layer 102 on the first gate 104a. This prevents defects from being caused at the interface between the active layer 102 and the first gate insulating layer 103, which would make it easy for electrons to be captured at the interface, thereby affecting the carrier concentration of the channel of the active layer 102.

[0048] It should be noted that, in the embodiments of this application, the structure of the second barrier layer 103b can be regarded as being composed of multiple back-shaped structures.

[0049] In some embodiments, the materials of the first barrier layer 103a and the third barrier layer 103c include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The material of the second barrier layer 103b includes at least one of aluminum oxide, chromium oxide, silver oxide, and titanium oxide. The material of the second barrier layer 103b can be one of aluminum oxide (Al₂O₃), silver oxide (Ag₂O), titanium dioxide (TiO₂), and chromium oxide (Cr₂O₃), or any combination thereof. For example, in one embodiment, the material of the first barrier layer 103a is silicon nitride, the material of the second barrier layer 103b is aluminum oxide, and the material of the third barrier layer 103c is silicon oxide. In this embodiment, a dense metal oxide film is used as the material of the second barrier layer 103b, thereby preventing metal atoms from diffusing into the channel region 102a of the active layer 102 on the first gate 104a, and further preventing defects at the interface between the active layer 102 and the first gate insulating layer 103, which would make the interface prone to trapping electrons and thus affect the carrier concentration of the channel of the active layer 102.

[0050] In some embodiments, the passivation layer 105 includes a first insulating layer 105a, an adsorption layer 105b, and a second insulating layer 105c, which are sequentially stacked. In this embodiment, the passivation layer 105 has a three-layer stacked structure, which extends the path of water and oxygen intrusion, thereby preventing water and oxygen from intruding into the channel region 102a of the active layer 102 from the side away from the substrate 101. In addition, the adsorption layer 105b has the function of adsorbing water and oxygen, further isolating water and oxygen from damaging the channel region 102a.

[0051] Please refer to Figure 3 , Figure 3 This is a schematic diagram of an adsorption layer provided in an embodiment of this application. In some embodiments, the adsorption layer 105b includes a first adsorption portion 105b1, a plurality of adsorption columns 102b2, and a second adsorption portion 102b3. The first adsorption portion 105b1 is disposed on the side of the first isolation layer 105a near the substrate 101. The plurality of adsorption columns 105b2 are spaced apart on the first adsorption portion 105b1. The second adsorption portion 105b3 is disposed on the side of the adsorption columns 105b2 near the second isolation layer 105c. In this embodiment, since the adsorption columns 105b2 are arranged in an array between the first adsorption portion 105b1 and the second adsorption portion 105b3, and since the gap between two adjacent adsorption columns 105b2 forms a closed space, when water vapor diffuses to the adsorption layer 105b, the water vapor can be sealed in the closed space, thereby preventing water vapor from diffusing into the channel region 102a of the active layer 102 and isolating water and oxygen from damaging the channel region 102a.

[0052] It should be noted that, in this embodiment, the structure of the adsorption layer 105b can be considered as being composed of multiple U-shaped structures. In this embodiment, since the adsorption layer 105b and the second blocking layer 103b have the same structure, there is no need to add an additional photomask, thus saving the manufacturing cost of the driving substrate 100.

[0053] In some embodiments, the materials of the first insulating layer 105a and the second insulating layer 105c include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the adsorption layer 105b includes a nanopolymer material. The material of the adsorption layer 105b may be a nano-superabsorbent resin including polyacrylic acid or polyacrylate. In this embodiment, because the material of the adsorption layer 105b is a highly absorbent nanopolymer material, it can prevent water vapor from intruding into the channel region 102a, thus avoiding damage to the channel region 102a by water and oxygen.

[0054] In some embodiments, the driving substrate 100 further includes a planarization layer 108 and a first electrode 109. The planarization layer 108 is disposed on the passivation layer 105 and covers the source electrode 106 and the drain electrode 107. The first electrode 109 is electrically connected to the drain electrode 107 through a via.

[0055] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a second structure of the driving substrate provided in an embodiment of this application. The driving substrate 100 provided in this embodiment of the application and... Figure 1 The difference between the driving substrate 100 and the previous one is that the driving substrate 100 also includes an organic filler layer 110. The organic filler layer 110 fills the gaps formed by the plurality of first support portions 103b2. The material of the organic filler layer 110 can be a nano-superabsorbent polymer including polyacrylic acid or polyacrylate. In the embodiments of this application, by using a superabsorbent nanopolymer material in the gaps formed by the first support portions 103b2, water vapor can be prevented from intruding into the channel region 102a, thus avoiding damage to the channel region 102a by water and oxygen.

[0056] Please refer to Figure 5 , Figure 5 This is a schematic diagram of a third structure of the driving substrate provided in an embodiment of this application. The driving substrate 100 provided in this embodiment of the application and... Figure 1 The difference between the driving substrate 100 and the previous one is that the active layer 102 is disposed on the substrate 101. The first gate insulating layer 103 is disposed on the side of the active layer 102 away from the substrate 101 and covers both the active layer 102 and the substrate 101. The first gate 104a is disposed on the side of the first gate insulating layer 103 away from the active layer 102. In this embodiment, since the first gate insulating layer 103 corresponding to the channel region 102a has a three-layer stacked structure, the path for metal atoms in the first gate 104a to diffuse to the active layer 102 is extended, preventing defects from forming at the interface between the active layer 102 and the first gate insulating layer 103, which would make the interface more prone to trapping electrons and thus affect the carrier concentration of the channel of the active layer 102.

[0057] Please combine Figure 6 and Figure 7 , Figure 6 This is a schematic diagram of a fourth structure of the driving substrate provided in an embodiment of this application. Figure 7 for Figure 6 Enlarged view of a portion of the structure. The driving substrate 100 provided in this embodiment of the application and... Figure 1The difference between the driving substrate 100 and the one in the figure is that the driving substrate 100 further includes a second gate insulating layer 111, a second gate electrode 104b, and a connection electrode (not shown in the figure). The second gate insulating layer 111 is disposed on the side of the active layer 102 away from the first gate insulating layer 103. The second gate insulating layer 111 corresponding to the first portion 101a includes a fourth barrier layer 111a, a fifth barrier layer 111b, and a sixth barrier layer 111c stacked sequentially. The fifth barrier layer 111b includes a third barrier portion 111b1, a plurality of second support portions 111b2, and a fourth barrier portion 111b3. The third barrier portion 111b1 is disposed on the side of the active layer 102 near the substrate 101. The plurality of second support portions 111b2 are spaced apart on the third barrier portion 111b1. The fourth barrier portion 111b3 is disposed on the side of the second support portion 111b2 near the sixth barrier layer 111c. The second gate electrode 104b is disposed on the side of the second gate insulating layer 111 away from the active layer 102. The connecting electrode is used to connect the first gate 104a and the second gate 104b. In this embodiment, by providing a second gate insulating layer 111 between the active layer 102 and the second gate 104b, since the second gate insulating layer 111 is a three-layer stacked structure, the path for metal atoms in the second gate 104b to diffuse to the active layer 102 is extended, preventing defects from forming at the interface between the active layer 102 and the second gate insulating layer 111, which would make the interface prone to trapping electrons and thus affect the carrier concentration of the channel of the active layer 102. Furthermore, since the gap between two adjacent second support portions 111b2 forms a closed space, when metal atoms in the second gate 104b diffuse to the fifth barrier layer 111b, the metal atoms can be confined within the closed space. This prevents metal atoms from diffusing into the channel region 102a of the active layer 102 on the second gate 104b, thus preventing defects at the interface between the active layer 102 and the second gate insulating layer 111, which would make the interface prone to trapping electrons and thus affect the carrier concentration in the channel of the active layer 102. Moreover, since the array of second support portions 111b2 is arranged between the third barrier portion 111b1 and the fourth barrier portion 111b3, this arrangement method can avoid the generation of parasitic capacitance.

[0058] The material of the second gate 104b can be metals or alloys such as Cr, W, Ti, Ta, Mo, Al, and Cu. A gate metal layer composed of multiple metals can also meet the requirements.

[0059] In summary, although the present application has disclosed the preferred embodiments as described above, the above preferred embodiments are not intended to limit the present application. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be determined by the scope defined in the claims.

Claims

1. A driving substrate, characterized in that, The driving substrate includes: Substrate; A first gate, wherein the first gate is disposed on the substrate; An active layer is disposed on the substrate; A first gate insulating layer is disposed between the active layer and the first gate. The first gate insulating layer includes a first barrier layer, a second barrier layer and a third barrier layer stacked sequentially, wherein the adhesion between the first barrier layer and the second barrier layer and / or the adhesion between the second barrier layer and the third barrier layer is greater than the adhesion between the first barrier layer and the third barrier layer. A passivation layer is disposed on the substrate; The source electrode is disposed on the passivation layer and electrically connected to the active layer; The drain electrode is disposed on the passivation layer and electrically connected to the active layer.

2. The driving substrate according to claim 1, characterized in that, The substrate includes a first portion and a second portion located on both sides of the first portion, and the active layer includes a channel region and doped regions located on both sides of the channel region, the channel region corresponding to the first portion; in The first barrier layer, the second barrier layer, and the third barrier layer are disposed corresponding to the first portion, and at least one of the first barrier layer and the third barrier layer is disposed corresponding to the second portion.

3. The driving substrate according to claim 1, characterized in that, The second barrier layer includes a first barrier portion, a plurality of first support portions, and a second barrier portion; wherein The first blocking portion is disposed on the side of the first blocking layer near the substrate, a plurality of first supporting portions are disposed at intervals on the first blocking portion, and the second blocking portion is disposed on the side of the first supporting portion near the third blocking layer.

4. The driving substrate according to claim 3, characterized in that, The driving substrate further includes an organic filler layer, which fills the gaps formed by the plurality of first support portions.

5. The driving substrate according to claim 3, characterized in that, The materials of the first barrier layer and the third barrier layer include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the second barrier layer includes at least one of aluminum oxide, chromium oxide, silver oxide, and titanium oxide.

6. The driving substrate according to claim 1, characterized in that, The passivation layer includes a first barrier layer, an adsorption layer, and a second barrier layer stacked sequentially.

7. The driving substrate according to claim 6, characterized in that, The adsorption layer includes a first adsorption section, multiple adsorption columns, and a second adsorption section; wherein The first adsorption part is disposed on the side of the first isolation layer near the substrate, and a plurality of adsorption columns are disposed at intervals on the first adsorption part, and the second adsorption part is disposed on the side of the adsorption columns near the second isolation layer.

8. The driving substrate according to claim 6, characterized in that, The materials of the first and second insulating layers include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the material of the adsorption layer includes a nanopolymer material.

9. The driving substrate according to claim 2, characterized in that, The driving substrate further includes: A second gate insulating layer is disposed on the side of the active layer away from the first gate insulating layer. The second gate insulating layer corresponding to the first portion includes a fourth barrier layer, a fifth barrier layer, and a sixth barrier layer stacked sequentially. The fifth barrier layer includes a third barrier portion, a plurality of second support portions and a fourth barrier portion. The third barrier portion is disposed on the side of the active layer near the substrate. The plurality of second support portions are spaced apart on the third barrier portion. The fourth barrier portion is disposed on the side of the second support portion near the sixth barrier layer. The second gate is disposed on the side of the second gate insulating layer away from the active layer; Connecting electrodes are used to connect the first gate and the second gate.

10. A display panel, characterized in that, The invention includes the driving substrate according to any one of claims 1 to 9, the driving substrate being used to drive the display panel to emit light.

Images