An accelerator, an acceleration method, and an electronic device

Abstract

The application provides an accelerator, an acceleration method and an electronic device. The accelerator comprises a computing unit; the computing unit comprises a general operation logic composed of a basic operation logic; the general operation logic implements operations of different operation types in response to different inputs. The accelerator further comprises: an acquisition unit configured to acquire a target microcode instruction generated according to a target type operation to be implemented; the target microcode instruction is used to indicate target input data required for the general operation logic to implement the target type operation; an analysis unit configured to analyze the target microcode instruction to obtain an analysis result corresponding to the target input data; and a control unit configured to control the computing unit in response to the analysis result, so that the computing unit acquires the target input data and runs the general operation logic based on the target input data to complete the target type operation. Thus, the configuration difficulty of the accelerator is reduced, and the hardware resources are saved.

Description

Technical Field

[0001] This application relates to computer technology, and more specifically to an accelerator, an acceleration method, and an electronic device. Background Technology

[0002] Elliptic Curve Cryptography (ECC) is a mainstream asymmetric cryptographic algorithm widely used in many security fields, such as secure transmission, key exchange, digital signatures, privacy computation, and secure multi-party computation. The ECC algorithm includes operations such as dot multiplication, modular addition, modular multiplication, and modular subtraction. Dot multiplication can be achieved by performing several modular additions, modular multiplications, and modular subtractions. Currently, the ECC algorithm is implemented using accelerators.

[0003] One related technology involves strictly controlling each computational stage of the accelerator through a state machine to achieve a specific computational process and thus a specific function. However, because the control and modification of the state machine are quite cumbersome, these accelerators can only achieve specific functions and are not flexible enough in use.

[0004] The second related technology involves using different instructions to call different computing units in the accelerator to perform operations such as dot multiplication, modular multiplication, and modular addition, which leads to a waste of hardware resources. Summary of the Invention

[0005] In view of this, this application discloses at least one accelerator. The accelerator includes a computing unit for implementing operations related to elliptic curve algorithms; wherein the computing unit includes general-purpose computing logic composed of basic computing logic; the general-purpose computing logic responds to different inputs to implement operations of different types; the accelerator further includes: an acquisition unit for acquiring target microcode instructions corresponding to the target type operation generated according to the target type operation to be implemented; the target microcode instructions are used to indicate target input data required for the general-purpose computing logic to implement the target type operation; a parsing unit for parsing the target microcode instructions to obtain a parsing result corresponding to the target input data; and a control unit for controlling the computing unit in response to the parsing result, so that the computing unit acquires the target input data and runs the general-purpose computing logic based on the target input data to complete the target type operation.

[0006] In some embodiments, the accelerator is communicatively connected to a processor CPU; the accelerator or the CPU is configured to: acquire an operation program that performs a target type operation on operands; and, based on the operands included in the operation program, generate a target microcode instruction corresponding to the target type operation.

[0007] In some embodiments, the accelerator further includes a preset data storage space; the data storage space stores preset operands for generating microcode instructions; the accelerator or the CPU is further configured to: store the parsed operands into the data storage space; and perform operations according to the target type, generating the target microcode instructions based on the storage addresses of the operands and / or the preset operands in the data storage space.

[0008] In some embodiments, the parsing result includes the storage address of the target input data; the control unit, according to the storage address, controls the computing unit to read the target input data from the data storage space and perform the target type operation based on the target input data.

[0009] The basic operations include modular addition and modular multiplication, and the general operation logic is to perform modular multiplication on the result of two modular addition operations.

[0010] In some embodiments, the inputs required by the general arithmetic logic include a first input, a second input, a third input, and a fourth input; the general arithmetic logic operation process includes: performing a modular addition operation on the first input and the second input to obtain a first modular addition result; performing a modular addition operation on the third input and the fourth input to obtain a second modular addition result; and performing a modular multiplication operation on the first modular addition result and the second modular addition result to obtain a final calculation result.

[0011] In some embodiments, the operands include a first operand and a second operand; the accelerator or the CPU further comprises: in response to the target type operation being a modulo addition operation on the first operand and the second operand, setting the first input to the first operand, setting the second input to the second operand, setting the third input to 1, and setting the fourth input to 0; in response to the target type operation being a modulo subtraction operation on the first operand and the second operand, setting the first input to the first operand, setting the second input to the second operand and adjusting the sign corresponding to the second input to a negative sign, and setting the third input to 0. The first input is set to 1, and the fourth input is set to 0; in response to the target type operation being a modular multiplication of the first operand and the second operand, the first input is set to the first operand, the third input is set to the second operand, and the second input and the fourth input are set to 0; in response to the target type operation being a modular square operation of the first operand and the second operand, the first input and the third input are set to the first operand, and the second input and the fourth input are set to the second operand; the target microcode instruction is generated based on the first input, the second input, the third input, and the fourth input.

[0012] In some embodiments, the operation procedure further includes a dot product scalar; the target type operation is to perform a dot product operation on the dot product scalar and the operand; the accelerator or the CPU further: generates multiple target microcode instructions for implementing the dot product operation based on the dot product scalar and operand included in the operation procedure; the accelerator further: controls the computing unit to execute each of the multiple target microcode instructions to complete the dot product operation.

[0013] In some embodiments, the modular multiplication operation includes a first type of modular multiplication operation and a second type of modular multiplication operation; the accelerator further includes a preset data storage space; the data storage space stores preset constants; the preset constants are used for mutual conversion between a first data domain and a second data domain; the first data domain is used for the first type of modular multiplication operation; the second data domain is used for the second type of modular multiplication operation; the computing unit, in response to the modular multiplication operation changing from the first type to the second type, obtains the preset constants, and according to the preset constants, converts the first data domain to the second data domain to implement the second type of modular multiplication operation; in response to the modular multiplication operation changing from the second type to the first type, obtains the preset constants, and according to the preset constants, converts the second data domain to the first data domain to implement the first type of modular multiplication operation.

[0014] In some embodiments, the control unit includes a breakpoint subunit; the breakpoint subunit, in response to receiving an interrupt instruction, interrupts the execution of subsequent microcode instructions by the computing unit, so that the debugging unit corresponding to the accelerator obtains the calculation result of the computing unit and outputs a comparison result between the calculation result and a preset calculation result.

[0015] In some embodiments, the accelerator is a coprocessor for accelerating elliptic curve algorithms, implemented on an FPGA or ASIC; or an auxiliary acceleration module for accelerating the elliptic curve algorithm, implemented on a CPU.

[0016] This application also proposes an acceleration method applied to an accelerator. The accelerator includes a computing unit for implementing operations related to elliptic curve algorithms; wherein the computing unit includes general computing logic composed of basic computing logic; the general computing logic responds to different inputs to implement operations of different types; the method includes: acquiring target microcode instructions corresponding to the target type operation generated according to the target type operation to be implemented; the target microcode instructions are used to indicate target input data required for the general computing logic to implement the target type operation; parsing the target microcode instructions to obtain a parsing result corresponding to the target input data; controlling the computing unit in response to the parsing result, so that the computing unit acquires the target input data and runs the general computing logic based on the target input data to complete the target type operation.

[0017] This application also proposes an electronic device that includes an accelerator as shown in any of the foregoing embodiments.

[0018] In the aforementioned method, firstly, a target microcode instruction can be generated based on the target type operation to be performed, and the relevant configuration of the input required for the general operation logic within the computing unit to perform the target type operation can be completed based on the target microcode instruction, so that the accelerator can perform the target type operation. Compared with the first related technology, the accelerator can perform different types of operations by changing the microcode instruction, which simplifies the configuration operation of the accelerator, reduces the configuration difficulty of the accelerator, and allows the accelerator to be used more flexibly.

[0019] Second, a general-purpose arithmetic logic consisting of basic arithmetic logic is deployed in the computing unit; the general-purpose arithmetic logic responds to different inputs and performs different types of operations. Compared with related technology 2, at least two types of operations can be performed by one computing unit, saving hardware resources.

[0020] It should be understood that the general description above and the detailed description below are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in one or more embodiments or related technologies of this application, the accompanying drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments recorded in one or more embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a schematic diagram of the structure of an accelerator as shown in an embodiment of this application;

[0023] Figure 2 This is a schematic diagram of the structure of an accelerator as shown in an embodiment of this application;

[0024] Figure 3 This application provides a schematic diagram of the structure of an accelerator.

[0025] Figure 4 This is a schematic diagram of a method flow for an acceleration method as shown in an embodiment of this application. Detailed Implementation

[0026] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of devices and methods consistent with some aspects of this application as detailed in the appended claims.

[0027] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The singular forms “a,” “the,” and “the” used in this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items. It should also be understood that the word “if” as used herein, depending on the context, can be interpreted as “when,” “in response to a determination,” or “when…”.

[0028] Based on this, this application proposes an accelerator. The accelerator includes a computing unit for implementing operations related to elliptic curve algorithms; wherein the computing unit includes general-purpose computing logic composed of basic computing logic; the general-purpose computing logic responds to different inputs to implement operations of different types; the accelerator further includes: an acquisition unit for acquiring target microcode instructions corresponding to the target type operation generated according to the target type operation to be implemented; the target microcode instructions are used to indicate target input data required for the general-purpose computing logic to implement the target type operation; a parsing unit for parsing the target microcode instructions to obtain a parsing result corresponding to the target input data; and a control unit for controlling the computing unit in response to the parsing result, so that the computing unit acquires the target input data and runs the general-purpose computing logic based on the target input data to complete the target type operation.

[0029] In the aforementioned method, firstly, a target microcode instruction can be generated based on the target type operation to be performed, and the relevant configuration of the input required for the general operation logic within the computing unit to perform the target type operation can be completed based on the target microcode instruction, so that the accelerator can perform the target type operation. Compared with the first related technology, the accelerator can perform different types of operations by changing the microcode instruction, which simplifies the configuration operation of the accelerator, reduces the configuration difficulty of the accelerator, and allows the accelerator to be used more flexibly.

[0030] Second, a general-purpose arithmetic logic consisting of basic arithmetic logic is deployed in the computing unit; the general-purpose arithmetic logic responds to different inputs and performs different types of operations. Compared with related technology 2, at least two types of operations can be performed by one computing unit, saving hardware resources.

[0031] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an accelerator as shown in an embodiment of this application.

[0032] like Figure 1 As shown, the accelerator 10 may include an acquisition unit 11, a parsing unit 12, a control unit 13, and a calculation unit 14 connected in sequence. The calculation unit 14 includes general-purpose arithmetic logic composed of basic arithmetic logic; the general-purpose arithmetic logic responds to different inputs to perform different types of operations.

[0033] The accelerator can achieve ECC acceleration based on a combination of hardware and software. The various functional units included in the accelerator can be hardware units, software device units, or units combining software devices and hardware.

[0034] In some embodiments, the accelerator is implemented based on a coprocessor or a CPU; wherein the accelerator is a coprocessor for accelerating elliptic curve algorithms implemented based on an FPGA or ASIC; or, an auxiliary acceleration module for accelerating the elliptic curve algorithm implemented based on a CPU.

[0035] The acquisition unit 11 can acquire the target microcode instruction corresponding to the target type operation generated according to the target type operation to be implemented; the target microcode instruction is used to indicate the target input data required for the general operation logic to implement the target type operation.

[0036] The target type operation may be an operation related to elliptic curve algorithms. In some embodiments, the target type operation may include at least one of the following:

[0037] Modular addition; modular subtraction; modular multiplication; square of modular addition; square of modular subtraction; modular addition multiplication and modular subtraction; modular addition multiplication and modular addition; modular subtraction multiplication and modular subtraction.

[0038] The target microcode instruction is used to trigger the accelerator 10 to complete the target type operation. Because microcode instructions are logically simple and easy to write, they simplify the development process for developers.

[0039] The target microcode instruction can indicate the target input data in at least two ways: First, the target microcode instruction directly carries the target input data; second, the target microcode instruction carries the storage address of the target input data.

[0040] In some embodiments, the target microcode instructions may be program instructions manually written according to requirements. These target microcode instructions can be encoded by an encoder and then sent to the acquisition unit 11 via a configuration bus. The accelerator can acquire the target microcode instructions through the acquisition unit 11.

[0041] In some embodiments, the target microcode instruction can be obtained by non-manually converting an operating program. The operating program is a code program written according to requirements. The conversion operation can be executed in the accelerator 10 or a CPU communicatively connected to the accelerator. After the conversion operation is completed, the target microcode instruction can be sent to the acquisition unit 11.

[0042] The accelerator or the CPU can be used to: acquire an operation program that performs a target type operation on operands; and, based on the operands included in the operation program, generate the target microcode instruction corresponding to the target type operation. This allows for a non-manual conversion of the operation program to generate the target operation that enables the accelerator to perform the target type operation. Researchers do not need to understand the internal computational logic of the accelerator, simplifying the development code and thus improving the accelerator's practicality.

[0043] In some approaches, the input data configuration rules required for the computing unit to perform each type of operation can be pre-maintained. During the conversion operation, the corresponding target configuration rule can be determined based on the target type operation, and then, based on the target configuration rule and the operands, input data is configured for the target microcode instruction to generate the target microcode instruction.

[0044] The parsing unit 12 can parse the target microcode instruction to obtain a parsing result corresponding to the target input data.

[0045] In some embodiments, the acquisition unit 11 may store the acquired target microcode instruction in a preset instruction storage space. The parsing unit 12 may acquire the unexecuted target microcode instruction from the instruction storage space, perform relevant parsing, and obtain the parsing result.

[0046] If the target microcode instruction directly carries the target input data, then the parsing result includes the target input data.

[0047] If the target microcode instruction carries the storage address of the target input data, then the parsing result includes the storage address.

[0048] In some embodiments, the parsing unit 12 can also parse the instruction type of the target microcode instruction to assist the control unit in executing the microcode instruction. For example, some microcode instructions may be data transfer (MOV) instructions, in which case the control unit only needs to perform the data transfer operation and does not need to control the calculation unit to perform calculations. As another example, some microcode instructions may involve subtraction operations (such as modular subtraction, modular addition multiplication modular subtraction, modular subtraction square, etc.), and the control unit can control the calculation unit to adjust the sign of the acquired input data to a negative sign.

[0049] The control unit 13 can control the calculation unit 14 in response to the parsing result, so that the calculation unit 14 can acquire the target input data and run the general operation logic based on the target input data to complete the target type operation.

[0050] If the parsing result includes the target input data, the computing unit can obtain the target input data from the parsing result.

[0051] If the parsing result includes the storage address of the target input data, the computing unit can read the target input data from the preset data storage space according to the storage address.

[0052] In some embodiments, the basic operations include modular addition and modular multiplication, and the general operation logic is to perform modular multiplication on the result of two modular addition operations. Thus, at least two operations can be implemented through a single general operation logic.

[0053] For example, the general operation logic can be expressed by the formula ((A+B)mod(p)*(C+D)mod(p))mod(p). If C is set to 0 and D to 1, the general operation logic can be transformed into (A+B)mod(p), which is equivalent to implementing the modular addition operation of A and B. If B and D are set to 0, the general operation logic can be transformed into (A*C)mod(p), which is equivalent to implementing the modular multiplication operation of A and C.

[0054] In some embodiments, the basic operations include modular addition and modular multiplication, and the inputs required by the general operation logic include a first input, a second input, a third input, and a fourth input;

[0055] The general-purpose logical operation process includes:

[0056] Perform a modulo addition operation on the first input and the second input to obtain the first modulo addition result;

[0057] Perform a modular addition operation on the third input and the fourth input to obtain a second modular addition result;

[0058] Modular multiplication is performed on the first and second modular addition results to obtain the final calculation result.

[0059] Through the aforementioned design of the computing unit, the computing unit can respond to input data indicated by different microcode instructions and implement at least two of the following types of operations by running general arithmetic logic: modular addition; modular subtraction; modular multiplication; modular addition squared; modular subtraction squared; modular addition multiplied by modular subtraction; modular addition multiplied by modular subtraction; modular addition multiplied by modular addition; and modular subtraction multiplied by modular subtraction. This allows a single computing unit to perform multiple types of operations, improving hardware utilization and saving hardware resources.

[0060] It should be noted that solutions obtained by simply modifying the aforementioned general operational logic are also within the scope of protection of this application.

[0061] The following further explains the process by which the computing unit implements the different types of operations. It is assumed that each operation corresponds to two operands: a first operand and a second operand, and that the target microcode instructions are generated based on a CPU or accelerator.

[0062] To simplify the explanation, the general operation logic of the computing unit is represented by the formula ((A+B)mod(p)*(C+D)mod(p))mod(p).

[0063] Here, A, B, C, and D represent the first to fourth inputs, respectively. p is the data field, indicating that A, B, C, and D are all within the range of 0 to p. mod(p) indicates taking the modulus of p. (A+B)mod(p) indicates performing a modulo addition operation on A and B, i.e., taking the sum of A and B modulo p. ((A+B)mod(p)*(C+D)mod(p))mod(p) indicates performing a modulo addition operation on A and B, a modulo addition operation on C and D, and then performing a modulo multiplication on the results of the two modulo additions.

[0064] In the first operation scenario, the target type operation is a modular addition operation on the first operand and the second operand.

[0065] The accelerator or the CPU further includes:

[0066] In response to the target type operation being a modulo addition operation on the first operand and the second operand, the first input is set to the first operand, the second input is set to the second operand, the third input is set to 1, and the fourth input is set to 0;

[0067] The target microcode instruction is generated based on the first input, the second input, the third input, and the fourth input. It is understood that the target microcode instruction may include the above four inputs (including the first input, the second input, the third input, and the fourth input), or the storage addresses of the above four inputs.

[0068] The computing unit 14 may further:

[0069] Obtain the first input, the second input, the third input, and the fourth input;

[0070] Perform a modulo addition operation on the first input and the second input to obtain the first modulo addition result;

[0071] Perform a modulo addition operation on the third input and the fourth input to obtain 1;

[0072] The first modular addition result is multiplied by 1 to obtain the first modular addition result, thus completing the modular addition operation for the operand.

[0073] Taking the aforementioned formula as an example, where A is the first operand, B is the second operand, C = 1, and D = 0, then ((A+B)mod(p)*(C+D)mod(p))mod(p) = (A+B)mod(p), which is equivalent to the computation unit performing a modulo addition operation on the first and second operands.

[0074] In the second operation scenario, the target type operation is a modulo subtraction operation between the first operand and the second operand.

[0075] The accelerator or the CPU further includes:

[0076] In response to the target type operation being a modulo subtraction operation on the first operand and the second operand, the first input is set to the first operand, the second input is set to the second operand and the sign corresponding to the second input is adjusted to a negative sign, the third input is set to 1, and the fourth input is set to 0;

[0077] The target microcode instruction is generated based on the first input, the second input, the third input, and the fourth input.

[0078] The computing unit 14 further includes:

[0079] Obtain the first input, the second input, the third input, and the fourth input;

[0080] In response to the target type operation being a modulo subtraction operation, the sign corresponding to the second input is adjusted to a negative sign;

[0081] Perform a modulo addition operation on the first input and the second input to obtain the first modulo addition result;

[0082] Perform a modulo addition operation on the third input and the fourth input to obtain 1;

[0083] The first modular addition result is multiplied by 1 to obtain the first modular addition result, thus completing the modular subtraction operation on the operand.

[0084] Taking the aforementioned formula as an example, where A is the first operand, B is the second operand, C = 1, D = 0, and the sign of B is "-". Then ((A+B)mod(p)*(C+D)mod(p))mod(p) = (AB)mod(p), which is equivalent to the computation unit performing a modulo subtraction operation on the first and second operands.

[0085] In the third operation scenario, the target type operation is a modular multiplication operation on the first operand and the second operand.

[0086] The accelerator or the CPU further includes:

[0087] In response to the target type operation being a modular multiplication of the first operand and the second operand, the first input is set to the first operand, the third input is set to the second operand, and the second input and the fourth input are set to 0;

[0088] The target microcode instruction is generated based on the first input, the second input, the third input, and the fourth input.

[0089] The computing unit 14 can further:

[0090] Obtain the first input, the second input, the third input, and the fourth input;

[0091] Perform a modulo addition operation on the first input and the second input to obtain the first input;

[0092] The third input is obtained by performing a modulo addition operation on the third input and the fourth input;

[0093] Modular multiplication is performed on the first input and the third input to obtain the calculation result, thus completing the modular multiplication operation on the operands.

[0094] Taking the aforementioned formula as an example, where A is the first operand, C is the second operand, and B = D = 0, then ((A+B)mod(p)*(C+D)mod(p))mod(p) = (A*C)mod(p), which is equivalent to the computation unit performing a modular multiplication operation on the first and second operands.

[0095] The fourth operation scenario is that the target type operation is a square operation involving modulo addition of the first operand and the second operand.

[0096] The accelerator or the CPU further includes:

[0097] In response to the target type operation being a modulo addition square operation on the first operand and the second operand, the first input and the third input are set as the first operand, and the second input and the fourth input are set as the second operand;

[0098] The target microcode instruction is generated based on the first input, the second input, the third input, and the fourth input.

[0099] The computing unit 14 further includes:

[0100] Obtain the first input, the second input, the third input, and the fourth input;

[0101] Perform a modulo addition operation on the first input and the second input to obtain the first modulo addition result;

[0102] Perform a modular addition operation on the third input and the fourth input to obtain the first modular addition result;

[0103] Modular multiplication is performed on the first modulo addition result to obtain a calculation result to complete the square operation of the modulo addition of the operand.

[0104] Taking the aforementioned formula as an example, where A = C = the first operand and B = D = the second operand. Then ((A+B)mod(p)*(C+D)mod(p))mod(p) = ((A+B)mod(p))2mod(p), which is equivalent to the computation unit performing the square operation of the modulo addition of the seventh and eighth operands.

[0105] Referring to the explanations of the four operations implemented by the computing unit in the first to fourth operation scenarios above, it can be concluded that by adjusting the above four inputs required by the general operation logic, the computing unit can also implement the square of modulo subtraction, modulo addition multiplication of modulo subtraction, modulo addition multiplication of modulo addition, and modulo subtraction multiplication of modulo subtraction. Detailed explanations will not be provided here.

[0106] In some embodiments, the basic operations include modular multiplication operations comprising a first type of modular multiplication operation and a second type of modular multiplication operation. The accelerator also includes a preset data storage space; the data storage space stores preset constants; the preset constants are used for mutual conversion between a first data domain and a second data domain; the first data domain is used for the first type of modular multiplication operation; the second data domain is used for the second type of modular multiplication operation.

[0107] The calculation unit 14, in response to the modular multiplication operation changing from the first type to the second type, obtains the preset constant, and converts the first data field to the second data field according to the preset constant to realize the modular multiplication operation of the second type; in response to the modular multiplication operation changing from the second type to the first type, obtains the preset constant, and converts the second data field to the first data field according to the preset constant to realize the modular multiplication operation of the first type.

[0108] This application does not limit the first type and the second type. For example, the first type can be a regular type and the second type can be a Montgomery type.

[0109] One difference between the two different types of modular multiplication lies in their data domains. Data domain conversion can be achieved using a preset constant. For example, if the preset constant is 'a', and the first data domain is 0 to p, then p + a yields the second data domain, 0 to (p + a). By storing the preset constant in the data storage space, the corresponding data domain can be adjusted when the modular multiplication type changes, thus ensuring compatibility with multiple modular multiplication types within the computational unit.

[0110] Taking the first type as the regular type and the second type as the Montgomery type as an example, preset constants for conversion between the Montgomery data domain and the regular data domain can be pre-stored in the data storage space via the configuration bus. The computing unit can realize the data domain conversion by obtaining the preset constants, thereby achieving modular multiplication compatible with both the regular type and the Montgomery type.

[0111] In some embodiments, the accelerator can be debugged using a debugging unit corresponding to the accelerator.

[0112] The control unit in the accelerator may include a breakpoint subunit.

[0113] The breakpoint subunit is configured to interrupt the execution of subsequent microcode instructions by the computing unit in response to an interrupt command, so that the debugging unit corresponding to the accelerator can obtain the calculation result of the computing unit and output a comparison result between the calculation result and a preset calculation result. This allows for the debugging of the accelerator by monitoring the calculation process of the computing unit.

[0114] Suppose the accelerator is executing multiple consecutive target microcode instructions, including interrupt instructions. When the breakpoint subunit receives this interrupt instruction, it can send an interrupt parsing request to the parsing unit to interrupt the accelerator's continued execution of microcode instructions. The breakpoint subunit can also send a request to the debugging unit, allowing the debugging unit to read the computation results from the data storage space via the configuration bus and compare them with preset computation results. If they match, a green light is emitted through the connector; if they do not match, a red light is emitted through the connector. This allows developers to understand the accelerator's operating status and facilitates debugging.

[0115] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of an accelerator as shown in an embodiment of this application.

[0116] like Figure 2 As shown, the accelerator 20 may include an acquisition unit 21, a parsing unit 22, a control unit 23, a computing unit 24, and a data storage space 25 connected in sequence.

[0117] The accelerator 20 has the same functional units as the aforementioned accelerator 10 and can perform the same purpose, so it will not be described in detail here.

[0118] Figure 2 The schematic configuration bus allows the accelerator 20 to connect to other devices. For example, the configuration bus can connect the accelerator 20 to a CPU or GPU. Using the configuration bus for data and instruction transmission improves transmission stability.

[0119] The configuration bus can input target microcode instructions and target input data that enable the computing unit to perform target type operations, etc. The microcode instructions can be stored in a preset instruction storage space, and the target input data can be stored in a preset data storage space 25.

[0120] In some methods, the target microcode instructions are derived from the operating program by an accelerator or CPU. The accelerator or CPU is further used for:

[0121] The parsed operands are stored in the data storage space;

[0122] Based on the target type operation, and based on the storage address of the operand and / or the preset operand in the data storage space, the target microcode instruction is generated.

[0123] The operands are those parsed from the operating procedure and used to perform operations on the target type.

[0124] The operands can be sent to the data storage space for storage via the configuration bus, and the data storage space can return the storage address corresponding to the operand. Pre-defined operands for generating microcode instructions can also be pre-stored in the data storage space via the configuration bus.

[0125] The preset operands can assist the calculation unit in performing target type operations. The preset operands can be set according to requirements, and may include 0 and 1. For example, the calculation unit includes the general operation logic shown in the aforementioned formula. If the calculation unit needs to perform modular addition, A and B can be set as operands parsed from the operation program, C can be set as preset operand 0, and D can be set as preset operand 1.

[0126] After operand storage is complete, target configuration rules can be determined based on the target type operation to configure each input included in the target microcode instruction. Then, each input is configured according to the target configuration rules to generate the target microcode instruction. Specifically, each input can be configured based on the storage address of the operand and / or the preset operand in the data storage space to generate the target microcode instruction.

[0127] The resulting target microcode instructions may include the storage addresses of the target input data in the data storage space. In this case, the parsing result obtained from parsing the target microcode instructions may also include the storage addresses of the target input data. The control unit, based on the storage addresses, controls the computing unit to read the target input data from the data storage space and perform the target type operation based on the target input data.

[0128] In some embodiments, the data storage space 25 may include a data buffer and a data register. The data buffer may include an input buffer and an output buffer. Input data transmitted via the configuration bus and calculation results obtained by the calculation unit 24 may be stored in the data buffer and data register as needed, without particular limitation in this application. Of course, if the calculation unit 24 performs multiple calculations consecutively, the intermediate calculation results may be stored in the data register, thereby improving calculation efficiency.

[0129] In some embodiments, the operation procedure further includes dot product of a scalar; the target type operation is to perform a dot product operation on the dot product scalar and the operand; the accelerator or the CPU further includes:

[0130] Based on the dot product scalar and operands included in the operation procedure, generate multiple target microcode instructions for implementing the dot product operation;

[0131] The accelerator further includes:

[0132] The computing unit is controlled to execute each of the multiple target microcode instructions to complete the dot multiplication operation.

[0133] Therefore, by parsing the operation procedure, multiple target microcode instructions are obtained, and the calculation unit is controlled to perform dot multiplication based on these multiple target microcode instructions.

[0134] Please see Figure 3 , Figure 3 This is a schematic diagram of the structure of an accelerator as shown in an embodiment of this application.

[0135] like Figure 3 As shown, the accelerator 30 may include an acquisition unit 31, a parsing unit 32, a control unit 33, a computing unit 34, and a data storage space 35 connected in sequence; and a cache unit 36 ​​connected to the control unit 33 and the computing unit 34. The descriptions of units 31 to 35 can be found in the foregoing embodiments and will not be detailed here.

[0136] Cache unit 36 ​​stores the dot product scalar for dot product operations. The dot product scalar can be a number in a preset base with a preset number of bits, such as a 256-bit binary number. In some embodiments, the dot product scalar can be stored in cache unit 36 ​​via a configuration bus.

[0137] It is understandable that the dot product operation is actually a series of simple operations performed on each bit of the dot product scalar. These simple operations can include modular addition, modular subtraction, modular multiplication, the square of modular addition, the square of modular subtraction, modular addition multiplied by modular subtraction, modular addition multiplied by modular addition, and modular subtraction multiplied by modular subtraction. Therefore, to implement the dot product operation, multiple target microcode instructions corresponding to these simple operations can be manually written or converted by an accelerator or CPU to control the computing unit to complete the aforementioned simple operations to perform the dot product.

[0138] The following explanation uses asymmetric encryption via ECC as an example.

[0139] Given a base point G on an ellipse, we can select two points d and Q on the ellipse, where Q = dG, as the private key and public key, respectively.

[0140] When encrypting plaintext M using public key Q, a random number r can be obtained, and the ciphertext C can be obtained using the formula M + rQ.

[0141] When decrypting ciphertext C using private key d, the plaintext M can be obtained by using the formula Cd(rG)=M+r(dG)-d(rG)=M.

[0142] In the aforementioned encryption and decryption process, frequent dot multiplication operations (such as Rq, Dg, etc.) are required. Using the accelerator shown in the previous embodiment for ECC computation offers several advantages. First, by changing the microcode instructions, the accelerator can perform different types of operations, simplifying configuration and reducing the difficulty of setting it up, thus allowing for more flexible use. Second, at least two types of ECC operations can be implemented through a single computing unit, saving hardware resources.

[0143] This application discloses an acceleration method. The acceleration method can be applied to the accelerator shown in any of the foregoing embodiments. The accelerator includes a computational unit for implementing operations related to elliptic curve algorithms; wherein the computational unit includes general computational logic composed of basic computational logic; the general computational logic responds to different inputs to implement operations of different types.

[0144] Please see Figure 4 , Figure 4 This is a schematic diagram of a method flow for an acceleration method illustrated in an embodiment of this application. Figure 4 As shown, the method may include steps S402-S406. Unless otherwise specified, this application does not limit the order in which these steps are performed.

[0145] S402, obtain the target microcode instruction corresponding to the target type operation generated according to the target type operation to be implemented; the target microcode instruction is used to indicate the target input data required for the general operation logic to implement the target type operation.

[0146] S404, parse the target microcode instruction to obtain the parsing result corresponding to the target input data.

[0147] S406, in response to the parsing result, control the computing unit to obtain the target input data and run the general operation logic based on the target input data to complete the target type operation.

[0148] In the aforementioned scheme, firstly, a target microcode instruction can be generated based on the target type operation to be performed, and the relevant configuration of the input required for the target type operation to be performed on the general operation logic within the computing unit can be completed based on the target microcode instruction, so that the accelerator can perform the target type operation. Compared with the first related technology, the accelerator can perform different types of operations by changing the microcode instruction, which simplifies the configuration operation of the accelerator, reduces the configuration difficulty of the accelerator, and allows the accelerator to be used more flexibly.

[0149] Second, a general-purpose arithmetic logic consisting of basic arithmetic logic is deployed in the computing unit; the general-purpose arithmetic logic responds to different inputs and performs different types of operations. Compared with related technology 2, at least two types of operations can be performed by one computing unit, saving hardware resources.

[0150] The following describes some embodiments related to the acceleration method. The implementation process of these embodiments can be referred to the previous embodiments concerning accelerators, and will not be described in detail here.

[0151] In some embodiments, the accelerator is communicatively connected to a processor CPU; the method further includes:

[0152] Retrieves the procedure for performing operations on the target type of the operands;

[0153] Based on the target type operation, and using the operands included in the operation procedure, the target microcode instruction corresponding to the target type operation is generated.

[0154] In some embodiments, the accelerator further includes a preset data storage space; the data storage space stores preset operands for generating microcode instructions;

[0155] The step of generating the target microcode instruction corresponding to the target type operation based on the operands included in the operation procedure includes:

[0156] The parsed operands are stored in the data storage space;

[0157] Based on the target type operation, and based on the storage address of the operand and / or the preset operand in the data storage space, the target microcode instruction is generated.

[0158] In some embodiments, the parsing result includes the storage address of the target input data;

[0159] In response to the parsing result, the calculation unit is controlled to acquire the target input data, so that the calculation unit performs the target type operation based on the target input data, including:

[0160] Based on the storage address, the computing unit is controlled to read the target input data from the data storage space and perform the target type operation based on the target input data.

[0161] In some embodiments, the basic operations include modular addition and modular multiplication, and the general operation logic is to perform modular multiplication on the result of two modular addition operations.

[0162] In some embodiments, the inputs required by the general-purpose arithmetic logic include a first input, a second input, a third input, and a fourth input;

[0163] The general-purpose logical operation process includes:

[0164] Perform a modulo addition operation on the first input and the second input to obtain the first modulo addition result;

[0165] Perform a modular addition operation on the third input and the fourth input to obtain a second modular addition result;

[0166] Modular multiplication is performed on the first and second modular addition results to obtain the final calculation result.

[0167] In some embodiments, the operands include a first operand and a second operand;

[0168] The accelerator or the CPU further includes:

[0169] In response to the target type operation being a modulo addition operation on the first operand and the second operand, the first input is set to the first operand, the second input is set to the second operand, the third input is set to 1, and the fourth input is set to 0;

[0170] In response to the target type operation being a modulo subtraction operation on the first operand and the second operand, the first input is set to the first operand, the second input is set to the second operand and the sign corresponding to the second input is adjusted to a negative sign, the third input is set to 1, and the fourth input is set to 0;

[0171] In response to the target type operation being a modular multiplication of the first operand and the second operand, the first input is set to the first operand, the third input is set to the second operand, and the second input and the fourth input are set to 0;

[0172] In response to the target type operation being a modulo addition square operation on the first operand and the second operand, the first input and the third input are set as the first operand, and the second input and the fourth input are set as the second operand;

[0173] The target microcode instruction is generated based on the first input, the second input, the third input, and the fourth input.

[0174] In some embodiments, the operation procedure further includes dot product of a scalar; the target type operation is to perform a dot product operation on the dot product scalar and the operand;

[0175] The step of generating the target microcode instruction corresponding to the target type operation based on the operands included in the operation procedure includes:

[0176] Based on the dot product scalar and operands included in the operation procedure, generate multiple target microcode instructions for implementing the dot product operation;

[0177] The method further includes:

[0178] The computing unit is controlled to execute each of the multiple target microcode instructions to complete the dot multiplication operation.

[0179] In some embodiments, the modular multiplication operation includes a first type of modular multiplication operation and a second type of modular multiplication operation; the accelerator further includes a preset data storage space; the data storage space stores preset constants; the preset constants are used for mutual conversion between a first data domain and a second data domain; the first data domain is used for the first type of modular multiplication operation; the second data domain is used for the second type of modular multiplication operation;

[0180] The method further includes:

[0181] In response to the modular multiplication operation changing from the first type to the second type, the computing unit obtains the preset constant and converts the first data field into the second data field according to the preset constant to realize the modular multiplication operation of the second type.

[0182] In response to the modular multiplication operation changing from the second type to the first type, the preset constant is obtained, and the second data field is converted into the first data field according to the preset constant to realize the modular multiplication operation of the first type.

[0183] In some embodiments, the method further includes:

[0184] In response to receiving an interrupt command, the computing unit is interrupted from executing subsequent microcode instructions, so that the debugging unit corresponding to the accelerator can obtain the computing unit's calculation results and output a comparison result between the calculation results and a preset calculation result.

[0185] In some embodiments, the accelerator is a coprocessor for accelerating elliptic curve algorithms, implemented on an FPGA or ASIC; or an auxiliary acceleration module for accelerating the elliptic curve algorithm, implemented on a CPU.

[0186] This application also proposes an electronic device. The electronic device includes an accelerator as shown in any of the foregoing embodiments. ECC acceleration via the electronic device offers several advantages. First, by changing the microcode instructions, the accelerator can perform different types of operations, simplifying the configuration process and reducing the difficulty of configuring the accelerator. This, in turn, reduces the operational complexity of the electronic device, allowing for more flexible use. Second, a single computing unit within the accelerator can perform at least two types of ECC operations, saving hardware resources.

[0187] This application proposes a computer-readable storage medium storing a computer program for enabling an accelerator in the computer to perform an acceleration method as shown in any of the foregoing embodiments.

[0188] Those skilled in the art will understand that one or more embodiments of this application can be provided as a method, system, or computer program product. Therefore, one or more embodiments of this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, one or more embodiments of this application can take the form of a computer program product implemented on one or more computer-usable storage media (which may include, but are not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0189] In this application, “and / or” means having at least one of two options. For example, “A and / or B” can include three options: A, B, and “A and B”.

[0190] The various embodiments in this application are described in a progressive manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the data processing device embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0191] The specific embodiments of this application have been described above. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps described in the claims may be performed in a different order than that shown in the embodiments and may still achieve the desired results. Furthermore, the processes depicted in the drawings do not necessarily require the specific or sequential order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0192] The embodiments of the subject matter and functional operation described in this application can be implemented in: digital electronic circuits, tangibly embodied computer software or firmware, computer hardware that may include the structures disclosed in this application and their structural equivalents, or combinations thereof. Embodiments of the subject matter described in this application can be implemented as one or more computer programs, i.e., one or more modules of computer program instructions encoded on a tangible, non-transitory program carrier for execution by a data processing apparatus or for controlling the operation of a data processing apparatus. Alternatively or additionally, the program instructions may be encoded on artificially generated propagation signals, such as machine-generated electrical, optical, or electromagnetic signals, which are generated to encode information and transmit it to a suitable receiving device for execution by the data processing apparatus. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or combinations thereof.

[0193] The processing and logic flow described in this application can be executed by one or more programmable computers that execute one or more computer programs to perform corresponding functions by operating on input data and generating output. The processing and logic flow can also be executed by dedicated logic circuitry—such as FPGA (Field-Programmable Gate Array) or ASIC (Application-Specific Integrated Circuit)—and the device can also be implemented as dedicated logic circuitry.

[0194] A computer suitable for executing computer programs may include, for example, a general-purpose and / or special-purpose microprocessor, or any other type of processing unit. Typically, the processing unit receives instructions and data from read-only memory and / or random access memory. The basic components of a computer may include a processing unit for implementing or executing instructions and one or more memory devices for storing instructions and data. Typically, a computer may also include one or more mass storage devices for storing data, such as disks, magneto-optical disks, or optical disks, or the computer may be operatively coupled to such mass storage devices to receive data from or transfer data to them, or both. However, a computer is not required to have such devices. Furthermore, a computer may be embedded in another device, such as a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS) receiver, or a portable storage device such as a universal serial bus (USB) flash drive, to name a few.

[0195] Computer-readable media suitable for storing computer program instructions and data can include all forms of non-volatile memory, media, and memory devices, such as semiconductor memory devices (e.g., EPROM, EEPROM, and flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, and CD-ROMs and DVD-ROMs. Processors and memory may be supplemented by or incorporated into dedicated logic circuitry.

[0196] While this application contains numerous specific implementation details, these should not be construed as limiting the scope of any disclosure or the scope of the claims, but rather are primarily used to describe the features of specific embodiments of a particular disclosure. Certain features described in the multiple embodiments of this application may also be implemented in combination in a single embodiment. Conversely, various features described in a single embodiment may also be implemented separately in multiple embodiments or in any suitable sub-combination. Furthermore, while features may function in certain combinations as described and even initially claimed in this way, one or more features from a claimed combination may be removed from that combination in some cases, and a claimed combination may refer to a sub-combination or a variation of a sub-combination.

[0197] Similarly, although operations are depicted in a specific order in the accompanying drawings, this should not be construed as requiring these operations to be performed in the specific order shown or sequentially, or requiring all illustrated operations to be performed to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the described embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0198] Thus, specific embodiments of the subject matter have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions recited in the claims may be performed in a different order and still achieve the desired result. Furthermore, the processes depicted in the drawings are not necessarily shown in a specific order or sequence to achieve the desired result. In some implementations, multitasking and parallel processing may be advantageous.

[0199] The above are merely preferred embodiments of one or more embodiments of this application and are not intended to limit the scope of one or more embodiments of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of one or more embodiments of this application should be included within the scope of protection of one or more embodiments of this application.

Claims

1. An accelerator, characterized in that, The accelerator includes a computing unit for implementing operations related to elliptic curve algorithms; wherein, the computing unit includes general computing logic composed of basic computing logic; the general computing logic responds to different inputs to implement operations of different types; the inputs required by the general computing logic include a first input, a second input, a third input, and a fourth input; the operation process of the general computing logic includes: performing a modular addition operation on the first input and the second input to obtain a first modular addition result; performing a modular addition operation on the third input and the fourth input to obtain a second modular addition result; and performing a modular multiplication operation on the first modular addition result and the second modular addition result to obtain a final calculation result. The computing unit, in response to the input data of the first input, the second input, the third input, and the fourth input indicated by different microcode instructions, implements at least two of the following types of operations by running general arithmetic logic: modular addition, modular subtraction, modular multiplication, the square of modular addition, the square of modular subtraction, modular addition multiplied by modular subtraction, modular addition multiplied by modular addition, and modular subtraction multiplied by modular subtraction; The accelerator also includes: The acquisition unit acquires target microcode instructions generated according to the target type operation to be implemented; the target microcode instructions are used to indicate the target input data required for the general operation logic to implement the target type operation. The parsing unit parses the target microcode instruction to obtain a parsing result corresponding to the target input data; The control unit controls the computing unit in response to the parsing result, so that the computing unit acquires the target input data and runs the general arithmetic logic based on the target input data to complete the target type operation.

2. The accelerator according to claim 1, characterized in that, The accelerator is communicatively connected to the processor CPU; the accelerator or the CPU is used for: Retrieves the procedure for performing target type operations on operands; Based on the target type operation, and using the operands included in the operation procedure, the target microcode instruction corresponding to the target type operation is generated.

3. The accelerator according to claim 2, characterized in that, The accelerator also includes a preset data storage space; the data storage space stores preset operands for generating microcode instructions; The accelerator or the CPU is also used for: The parsed operands are stored in the data storage space; Based on the target type operation, and based on the storage address of the operand and / or the preset operand in the data storage space, the target microcode instruction is generated.

4. The accelerator according to claim 3, characterized in that, The parsing result includes the storage address of the target input data; The control unit, based on the storage address, controls the computing unit to read the target input data from the data storage space and perform the target type operation based on the target input data.

5. The accelerator according to claim 1, characterized in that, The target type operation targets operands including a first operand and a second operand; The accelerator or CPU further includes: In response to the target type operation being a modulo addition operation on the first operand and the second operand, the first input is set to the first operand, the second input is set to the second operand, the third input is set to 1, and the fourth input is set to 0; In response to the target type operation being a modulo subtraction operation on the first operand and the second operand, the first input is set to the first operand, the second input is set to the second operand and the sign corresponding to the second input is adjusted to a negative sign, the third input is set to 1, and the fourth input is set to 0; In response to the target type operation being a modular multiplication of the first operand and the second operand, the first input is set to the first operand, the third input is set to the second operand, and the second input and the fourth input are set to 0; In response to the target type operation being a modulo addition square operation on the first operand and the second operand, the first input and the third input are set as the first operand, and the second input and the fourth input are set as the second operand; The target microcode instruction is generated based on the first input, the second input, the third input, and the fourth input.

6. The accelerator according to claim 1, characterized in that, The procedure for performing target type operations on operands further includes dot product of scalar; the target type operation is to perform dot product of the dot product scalar and the operand. The accelerator or CPU further includes: Based on the dot product scalar and operands included in the operation procedure, generate multiple target microcode instructions for implementing the dot product operation; The accelerator further includes: The computing unit is controlled to execute each of the multiple target microcode instructions to complete the dot multiplication operation.

7. The accelerator according to claim 1, characterized in that, The modular multiplication operation includes a first type of modular multiplication operation and a second type of modular multiplication operation; the accelerator also includes a preset data storage space; the data storage space stores preset constants; the preset constants are used for mutual conversion between a first data domain and a second data domain; the first data domain is used for the first type of modular multiplication operation; the second data domain is used for the second type of modular multiplication operation; The computing unit, in response to the modular multiplication operation changing from the first type to the second type, obtains the preset constant, and converts the first data field into the second data field according to the preset constant to implement the modular multiplication operation of the second type; In response to the modular multiplication operation changing from the second type to the first type, the preset constant is obtained, and the second data field is converted into the first data field according to the preset constant to realize the modular multiplication operation of the first type.

8. The accelerator according to claim 1, characterized in that, The control unit includes a breakpoint subunit; The breakpoint subunit, in response to receiving an interrupt command, interrupts the execution of subsequent microcode instructions by the computing unit, so that the debugging unit corresponding to the accelerator can obtain the calculation result of the computing unit and output a comparison result between the calculation result and the preset calculation result.

9. The accelerator according to claim 1, characterized in that, The accelerator is a coprocessor for accelerating elliptic curve algorithms, implemented based on FPGA or ASIC; or an auxiliary acceleration module for accelerating the elliptic curve algorithm, implemented based on CPU.

10. An acceleration method applied to an accelerator, characterized in that, The accelerator includes a computing unit for implementing operations related to elliptic curve algorithms; wherein the computing unit includes general computing logic composed of basic computing logic; the general computing logic responds to different inputs to implement operations of different types; the inputs required by the general computing logic include a first input, a second input, a third input, and a fourth input; the general computing logic operation process includes: performing a modular addition operation on the first input and the second input to obtain a first modular addition result; performing a modular addition operation on the third input and the fourth input to obtain a second modular addition result; performing a modular multiplication operation on the first modular addition result and the second modular addition result to obtain a final calculation result; the computing unit, responding to the input data of the first input, the second input, the third input, and the fourth input indicated by different microcode instructions, implements at least two of the following types of operations by running the general computing logic: modular addition, modular subtraction, modular multiplication, the square of modular addition, the square of modular subtraction, modular addition multiplied by modular subtraction, modular addition multiplied by modular addition, and modular subtraction multiplied by modular subtraction; The method includes: Obtain the target microcode instruction corresponding to the target type operation, generated according to the target type operation to be implemented; the target microcode instruction is used to indicate the target input data required for the general operation logic to implement the target type operation. Parse the target microcode instruction to obtain the parsing result corresponding to the target input data; In response to the parsing result, the computing unit is controlled to acquire the target input data and run the general operation logic based on the target input data to complete the target type operation.

11. An electronic device, characterized in that, The electronic device includes an accelerator as described in any one of claims 1-9.

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