A semiconductor device

Abstract

A semiconductor device (200) includes a substrate (210), and an active circuit (220) and a redundant circuit (230) insulated from each other. The redundant circuit (230) includes a lightly doped P substrate (231) disposed in the substrate (210), a heavily doped redundant source-drain region (232) disposed in the P substrate (231), a redundant metal layer (235) disposed on a surface of the substrate (210), and a metal pillar (233) connecting the redundant source-drain region (232) and the redundant metal layer (235). The heavily doped redundant source-drain region (232) and the lightly doped P substrate (231) form a non-directional low impedance resistor, so that the accumulated charge on the metal conductor is quickly transferred in a direction perpendicular to the substrate (210), reducing the damage of the charge to the circuit, thereby improving the reliability and yield of the chip.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and more particularly to a semiconductor device. Background Technology

[0002] In chip manufacturing, wafers undergo processes such as cleaning, thin film formation, etching, and diffusion / ion implantation to form circuits on a substrate. Afterward, the wafers are diced into dies and further packaged to form chip products. Conductors such as metal lines or polysilicon within the wafer act like "antennas," collecting charge and causing their potential to rise. The longer the "antenna," the more charge it collects, resulting in a higher potential. This high potential on the conductors can potentially break down the thin gate oxide layer in MOS (Metal-Oxide-Semiconductor) devices, causing circuit failure; this phenomenon is known as the "antenna effect."

[0003] Both wafer cleaning and plasma etching can lead to the "antenna effect." The purpose of wafer cleaning is to remove excess particles, organic matter, metals, and native oxide layers from the wafer surface, preventing short circuits or open circuits within the wafer and thus improving die yield. Wet cleaning is the mainstream technique for wafer cleaning, primarily involving removing organic matter and inorganic residues from the wafer surface. However, during cleaning, contact between pure water and the wafer can generate static electricity, carrying away positive charges and leaving negative charges (electrons) on the wafer surface. Furthermore, in deep submicron integrated circuit fabrication processes, wafers are typically subjected to plasma-based ion etching. During ion etching, free charges are generated on the wafer surface. When etching conductors (such as metals or polysilicon), the exposed conductor surface collects these free charges, and the amount of accumulated charge is proportional to the area of ​​the conductor exposed to the plasma beam. When these charges accumulate on the gate, they tunnel through the thin oxide layer beneath the polysilicon to dissipate the charge. The discharge of a large amount of charge can damage the gate oxide layer, thereby reducing the reliability and lifespan of the device and even the entire chip.

[0004] Both the ion etching and wet cleaning processes described above may generate charges on the wafer surface, which can damage the circuitry on the wafer and reduce the wafer's yield and reliability. Summary of the Invention

[0005] This application provides a semiconductor device that achieves charge accumulation conduction through a low-impedance resistor formed by heavily doped redundant source / drain regions and lightly doped P-wells in a redundant circuit, thereby improving the yield of the semiconductor device.

[0006] In a first aspect, embodiments of this application provide a high-yield semiconductor device. The semiconductor device includes a substrate, an active circuit disposed on one side of the substrate, and a redundant circuit disposed on the same side. The active circuit is a circuit with actual circuit function in the semiconductor device, while the redundant circuit does not have actual circuit function and is insulated from the active circuit. The redundant circuit includes a first redundant metal layer, heavily doped redundant source / drain regions disposed in the substrate, a first metal pillar connecting the first redundant metal layer and the redundant source / drain regions, and a lightly doped P-substrate (i.e., a P-well), wherein the P-substrate is disposed in the substrate at a position surrounding the redundant source / drain regions. The first metal pillar can be a metal plug, such as a cobalt plug or a copper plug. The semiconductor device can be a wafer, a bare die, a packaged chip, or a bare die within a packaged chip.

[0007] Because the doping concentration of the heavily doped redundant source / drain regions is greater than that of the P-substrate, a non-directional and low-impedance resistor is formed between the redundant source / drain regions and the P-substrate. This resistor allows charge to flow either from the substrate through the P-substrate to the redundant source / drain regions, and then through the first metal pillar to the first redundant metal layer, or vice versa, from the first redundant metal layer through the first metal pillar to the redundant source / drain regions, and finally through the P-substrate to the substrate. Since charge can transfer and flow in two opposite directions, both positive and negative charges accumulated on the metal conductors in the semiconductor device can be transferred, making these metal conductors equipotential with the substrate. Therefore, the accumulated charge on the metal conductors can be cleared, reducing charge damage to the circuit and improving the reliability and yield of the semiconductor device.

[0008] In one possible implementation, the redundant circuit is manufactured using the same process as the active circuit, either using the FinFET process or the planar device process.

[0009] In one possible implementation, two different manufacturing processes can be implemented on the semiconductor device, such as manufacturing redundant circuitry for a FinFET and active circuitry for a planar device, or manufacturing redundant circuitry for a planar device and active circuitry for a FinFET. The semiconductor device provided in this embodiment is applicable to various processes and fabrications and supports different manufacturing processes on the same substrate.

[0010] In one possible implementation, the redundant circuit further includes a second redundant metal layer and a second metal pillar, wherein the second redundant metal layer is disposed on the side of the first redundant metal layer away from the substrate, and the second metal pillar connects the first redundant metal layer and the second redundant metal layer. The second metal pillar can be one or more metal pillars. In the redundant circuit of this embodiment, adjacent redundant metal layers are connected, allowing charge to be rapidly conducted in a direction perpendicular to the substrate, thereby further increasing the yield of the semiconductor device and reducing the possibility of damage from charges.

[0011] In one possible implementation, the second metal pillar is a copper via.

[0012] In one possible implementation, the redundant circuit further includes multiple redundant metal layers, each of which is connected to an adjacent redundant metal layer via a metal pillar, or to other redundant metal layers further away from that layer via metal pillars. Connecting multiple redundant metal layers allows for better dissipation of ionized charges.

[0013] In one possible implementation, the doping concentration of the heavily doped redundant source / drain regions is 100 to 10,000 times that of the P-substrate. Maintaining this doping concentration ratio results in a lower resistance between the P-substrate and the redundant source / drain regions.

[0014] In one possible implementation, the doping concentration of the redundant source / drain regions 232 is 10. 19 / cm 3 ~10 22 / cm 3 .

[0015] In one possible implementation, the aforementioned redundant source / drain regions comprise p-type heavily doped silicon (Si) or p-type heavily doped silicon-germanium (SiGe). Using p-type heavily doped silicon-germanium (SiGe) facilitates the transfer of free charges.

[0016] In one possible implementation, the redundant circuit further includes a third metal pillar disposed between the first redundant metal layer and the redundant gate region, and a redundant gate region disposed between the third metal pillar and the P-substrate. The structure described above can be a planar device structure or a FinFET device structure.

[0017] In one possible implementation, the first and third metal posts can be metal plugs, such as cobalt plugs or copper plugs.

[0018] In one possible implementation, the redundant circuit further includes a gate metal layer disposed between the third metal pillar and the redundant gate region, and a source / drain metal layer disposed between the first metal pillar and the redundant source / drain region. This structure is that of a FinFET device.

[0019] In one possible implementation, the gate metal layer comprises cobalt (Co) or titanium (Ti), and the source / drain metal layer comprises Co or Ti.

[0020] Secondly, embodiments of this application provide a packaged chip, including a die, a molding compound, and a connector disposed on one side of the molding compound, wherein the connector connects the molding compound and an external circuit, such as another substrate or PCB. The die can be any of the possible embodiments in the first aspect. The connector can be a solder ball.

[0021] In one possible implementation, the packaged chip further includes a redistribution layer disposed on one side of the molding compound, wherein the connector connects the molding compound and external circuitry.

[0022] Thirdly, embodiments of this application provide an electronic device, including a packaged chip and a PCB, wherein the packaged chip and the PCB are electrically connected. Attached Figure Description

[0023] Figure 1a This is a schematic diagram of a wafer;

[0024] Figure 1b This is a cross-sectional schematic diagram of a packaged chip;

[0025] Figure 1c This is a cross-sectional schematic diagram of an electronic device.

[0026] Figure 2 This is a cross-sectional view of a semiconductor device according to an embodiment of this application.

[0027] Figure 3 This is a cross-sectional view of a more specific semiconductor device in an embodiment of this application.

[0028] Figure 4 This is a cross-sectional view of another more specific semiconductor device in the embodiments of this application.

[0029] Figure 5a The image shown is a cross-sectional view of AA' of a more specific semiconductor device provided in an embodiment of this application.

[0030] Figure 5b The image shown is a cross-sectional view of the BB' section of another more specific semiconductor device provided in the embodiments of this application. Detailed Implementation

[0031] The technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings.

[0032] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0033] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0034] Redundant circuits (also known as dummy patterns or dummy circuits) are typically circuit components manufactured during chip production to meet occupancy requirements specified in design rules. Redundant circuits can be manufactured using the same processes as active circuits. For example, when the active circuit is a MOS device, the redundant circuit, similar to the active circuit, also includes a gate, drain, and source. However, because the redundant circuit does not have an electrical connection with the active circuit, it is not used as a normal operating circuit; that is, the redundant circuit itself does not have the ability to process signals, such as signal amplification, filtering, or conversion. When manufacturing redundant circuits, there is no need to consider whether there are connections between the various metal layers, and therefore no need to connect the metal layers through vias or other structures to achieve electrical conduction. Typically, there is no electrical conduction between the metal layers in a redundant circuit, or no intentionally designed electrical conduction.

[0035] Figure 1a This is a schematic diagram of a wafer 100, including multiple dies 110, each of which can include independent circuitry to implement a preset circuit function. During chip manufacturing, the wafer 100 can be diced into multiple dies 110, and each die 110 can be packaged to obtain a packaged chip; alternatively, the wafer 100 can be packaged first and then diced to obtain a packaged chip. Figure 1bThis is a cross-sectional schematic diagram of a packaged chip 111, including a die 110, a molding material 115, and a redistribution layer (RDL) 112 and connectors 113 disposed on the lower surface of the molding material 115. The connectors 113 connect the redistribution layer 112 to external circuitry, such as other substrates or printed circuit boards (PCBs). The connectors 113 can be metal pillars or solder balls, such as solder balls. Figure 1c This is a cross-sectional schematic diagram of an electronic device 130, including the aforementioned packaged chip 111 and a PCB 140, wherein the packaged chip 111 is disposed on and electrically connected to the PCB 140. The aforementioned die 110 can be a radio frequency (RF) chip, a memory chip, or a field-programmable gate array (FPGA) chip, etc. The packaged chip 111 can be an application processor (AP) containing multiple dies 110, a memory chip with multiple dies 110 stacked and packaged, or a chip with other functions. The aforementioned electronic device 130 can be a mobile terminal such as a mobile phone or laptop, or a personal computer (PC), server, router, switch, etc.

[0036] This application provides a high-yield semiconductor device. This semiconductor device can be used for... Figure 1a The nude film 110 in the middle can also be Figure 1b The nude film 110, or for Figure 1c The electronic device 130 includes a bare die 110. The semiconductor device can also be understood as the packaged chip 111 described above, or a packaged chip that includes more of the bare dies 110 described above.

[0037] like Figure 2 The diagram shown is a cross-sectional view of a semiconductor device 200 provided in an embodiment of this application, including a substrate 210, and a first side of the substrate 210 (i.e. Figure 2The circuit arranged above the substrate 210 includes an active circuit 220 and a redundant circuit 230. The active circuit 220, also called an active device, includes electronic components that require power to perform specific functions, such as signal amplification and conversion. In one embodiment, the active circuit 220 may include vacuum tubes, transistors, or application-specific integrated circuits (ASICs). Specifically, the active circuit 220 may include an NMOS (N-channel Metal Oxide Semiconductor) field-effect transistor (FET), a PMOS (P-channel Metal Oxide Semiconductor) field-effect transistor, or a CMOS (Complementary Metal-Oxide-Semiconductor) field-effect transistor. The active circuit 220 may also be a FinFET (Fin Field Effect Transistor), a TFET (Tunnel Field Effect Transistor), etc. The aforementioned redundant circuits and active circuits are disposed on one side of the substrate. This can be understood as the various components contained therein being disposed in the substrate and close to the substrate surface, or disposed on the surface of the substrate, or disposed on one side of the substrate but not in direct contact with the substrate.

[0038] In such Figure 2 In the semiconductor device 200 shown, the redundant circuit 230 is manufactured using the same process as the active circuit 220, both being FinFET manufacturing processes. In one possible implementation, both the redundant circuit 230 and the active circuit 220 can be manufactured using planar device manufacturing processes. In another possible implementation, two different manufacturing processes can be implemented on the semiconductor device 200, for example, manufacturing the FinFET redundant circuit 230 and the planar device active circuit 220, or manufacturing the planar device redundant circuit 230 and the FinFET active circuit 220.

[0039] The active circuit 220 of the semiconductor device 200 includes a substrate 221 and source / drain regions 222 disposed in a substrate 210, a plurality of fourth metal pillars 336 disposed on the surface of the substrate 210, and a first metal layer 224 connected to the plurality of fourth metal pillars 336. The redundant circuit 230 includes a lightly doped P-substrate 231 disposed in the substrate 210, redundant source / drain regions 232, a first metal pillar 233, a third metal pillar 234, and a first redundant metal layer 235 disposed on the surface of the substrate 210. One end of the first metal pillar 233 is connected to the first redundant metal layer 235, and the other end is connected to the redundant source / drain regions 232; one end of the third metal pillar 234 is connected to the first redundant metal layer 235, and the other end is connected to the P-substrate 231. It should be noted that... Figure 2 The image shown is a cross-sectional view of the semiconductor device 200, therefore Figure 2 The components of the first metal layer 224 are actually electrically connected in another cross section, and the first redundant metal layer 235 is also electrically connected in another cross section. Furthermore, since the source and drain regions in the redundant circuit do not have actual circuit function, the source and drain regions in the redundant circuit are collectively referred to as redundant source-drain regions, and in this embodiment, they are represented by only one region. Parts of the active circuit 220 and the redundant circuit 230 (e.g., the P-substrate and source-drain regions) are disposed in the substrate 210, while other parts (e.g., the gate and metal pillars) are disposed on the surface of the substrate 210. In this embodiment, both the active circuit 220 and the redundant circuit 230 can be considered to be disposed on one side of the substrate 210. The P-substrate in this embodiment can also be called a P-type substrate, P-well, or P-well; correspondingly, the N-substrate can also be called an N-type substrate, N-well, or N-well.

[0040] The aforementioned fourth metal pillar 336, first metal pillar 233, and third metal pillar 234 may include cobalt (Co) or copper (Cu). In one embodiment, the aforementioned fourth metal pillar 336, first metal pillar 233, and third metal pillar 234 are all Co plugs or Cu plugs. The aforementioned metal layers and redundant metal layers are both metal wiring layers, which may include copper wires or cobalt wires, and the metal wirings are insulated from each other by a barrier material.

[0041] The redundant circuit 230 and the active circuit 220 are kept insulated from each other. Specifically, the first redundant metal layer 235 and the first metal layer 224 in the redundant circuit 230 are located on the same metal layer, but the first redundant metal layer 235 and the first metal layer 224 are kept insulated from each other. In addition, the redundant source / drain regions 232 and the P-substrate 231 in the redundant circuit 230 are also insulated from the source / drain regions 22 and the substrate 221 in the active circuit 220.

[0042] In the redundant circuit 230, the redundant source / drain region 232 is a heavily P-type doped region, while the P-substrate 231 surrounding the redundant source / drain region 232 is a lightly doped region. That is, the doping concentration of the redundant source / drain region 232 is greater than the doping concentration of the P-substrate 231. In one embodiment, the doping concentration of the redundant source / drain region 232 is 100 to 10000 times that of the P-substrate 231. In one embodiment, the doping concentration of the P-substrate 231 is 100 to 10000 times that of the substrate 210. In one embodiment, the doping concentration of the redundant source / drain region 232 is 10... 19 / cm 3 ~10 22 / cm 3 Specifically, the doping concentration of redundant source / drain regions 232 can be 10. 20 / cm 3 .

[0043] The aforementioned semiconductor device 200 can be a wafer, a bare die, or a packaged chip. The metal plug in this embodiment can be a metal pillar structure or other metal structures to connect the metal layers at both ends and provide lower impedance.

[0044] Because the doping concentration of the heavily doped redundant source / drain region 232 is greater than that of the P-substrate 231, a non-directional and low-impedance resistor is formed between the redundant source / drain region 232 and the P-substrate 231. This resistor allows charge to flow either from the substrate 210 through the P-substrate 231 to the redundant source / drain region 232, and then through the first metal pillar 233 to the first redundant metal layer 235, or in the opposite direction, from the first redundant metal layer 235 through the first metal pillar 233 to the redundant source / drain region 232, and finally through the P-substrate 231 to the substrate 210. Since charge can transfer and flow in two opposite directions, both positive and negative charges accumulated on the metal conductors in the semiconductor device 200 can be transferred, making these metal conductors equipotential with the substrate 210. Therefore, the accumulated charge on the metal conductors can be cleared, reducing charge damage to the circuit and improving the reliability and yield of the semiconductor device 200. Furthermore, the structure of the redundant circuit 230 in the semiconductor device 200 is the same as that of the redundant circuit in the prior art. Therefore, the manufacturing process can be changed without changing the manufacturing process when manufacturing the semiconductor device 200, thereby saving costs.

[0045] In one embodiment, the redundant source / drain region 232 is P-type heavily doped silicon (Si). To improve charge conduction, in another embodiment, the redundant source / drain region 232 can also be P-type heavily doped silicon (SiGe). Using P-type heavily doped SiGe can further reduce the impedance between the redundant source / drain region 232 and the P-substrate 231, which is more conducive to bidirectional charge conduction.

[0046] Figure 3 The diagram shows a cross-sectional view of a more specific semiconductor device 300 provided in an embodiment of this application. The semiconductor device 300 includes a substrate 210, an active circuit 230, and a redundant circuit 230. The active circuit 220 is a FinFET, and may include an NMOS device and a PMOS device. The NMOS device includes a P-substrate 321 disposed in the substrate 210, a source 323 and a drain 324 located in the P-substrate 321 and disposed opposite to each other, a source metal layer 326 disposed on the surface of the substrate 210 and connected to the source 323, a drain metal layer 328 disposed on the surface of the substrate 210 and in contact with the drain 324, a gate 325, and a gate metal layer 327 connected to the gate 325. Furthermore, the source metal layer 326, gate metal layer 327, and drain metal layer 328 in the NMOS device are respectively connected to the first signal layer 341 via a fourth metal pillar 336. Similarly, the PMOS device includes an N substrate 322 disposed in the substrate 210, and the same components as the NMOS device, which will not be described in detail here.

[0047] The redundant circuit 230 and the active circuit 220 can be manufactured using the same semiconductor manufacturing process, meaning that the redundant circuit 230 can include a semiconductor structure similar to that of the active circuit 220. Therefore, the redundant circuit 230 can also include a P-substrate 231 disposed in the substrate 210, and a redundant source / drain region 232 disposed in the P-substrate 231, wherein the P-substrate 231 surrounds the redundant source / drain region 232. Figure 3 The redundant circuit 230 shown may further include a source / drain metal layer 332 disposed between the first metal pillar 233 and the redundant source / drain region 232; and a redundant gate region 333 and a gate metal layer 334, wherein the redundant gate region 333 is disposed on the surface of the substrate 210 and connected to the P-substrate 231, and the gate metal layer 334 is disposed between the third metal pillar 234 and the redundant gate region 333. The first redundant metal layer 235 is insulated from the first signal layer 341. In one embodiment, the first redundant metal layer 235 and the first signal layer 341 are located on the same metal layer.

[0048] In one embodiment, the gate metal layer 334 may be Co or Cu to reduce the impedance between the third metal pillar 234 and the redundant gate region 333. In another embodiment, the source / drain metal layer 332 may also be a low-impedance material, such as Co, titanium (Ti), or tungsten (W).

[0049] The semiconductor device 300 may further include multiple metal layers. In one embodiment, the semiconductor device 300 further includes a second signal layer 342 and a second redundant metal layer 236 located on the same layer and insulated from each other. The second signal layer 342 and the first signal layer 341 may or may not be electrically connected. The second redundant metal layer 236 and the first redundant metal layer 235 are electrically connected, for example, through a second metal pillar 335. Figure 3 The cross-sectional electrical connection shown may also be present, or it may be connected in other cross-sections. In one embodiment, the second metal pillar 335 may be a metal via. In one embodiment, the semiconductor device 300 further includes a third signal layer 343 and a third redundant metal layer 237 located on the same layer and insulated from each other, wherein the third signal layer 343 and the second signal layer 342 may or may not be electrically connected. The third redundant metal layer 237 and the second redundant metal layer 236 are electrically connected via metal pillars (e.g., vias) in such a cross-section. Figure 3 The cross-sectional electrical connection shown may be used, or it may be used in other cross-sectional connections. The semiconductor device 300 may also include a fourth signal layer 344, which may be connected to the third signal layer 343 via a via, but remains insulated from the third redundant metal layer 237. It is readily understood that the fourth signal layer 344 is also insulated from the second redundant metal layer 236 and the first redundant metal layer 235.

[0050] The semiconductor device 300 may further include additional redundant metal layers and signal layers. In one embodiment, each of the redundant metal layers in the semiconductor device 300 is electrically connected to an adjacent redundant metal layer. In another embodiment, each of the aforementioned redundant metal layers is connected to other redundant metal layers further away from it via metal pillars.

[0051] Connecting adjacent redundant metal layers allows charges to flow between them, which facilitates charge flow to substrate 210 or from substrate 210 to redundant circuit 230.

[0052] like Figure 4The diagram shows a cross-sectional view of another more specific semiconductor device 400 provided in this application embodiment. Semiconductor device 400 is similar to semiconductor device 300, and its components and connections are identical to those in semiconductor device 300 and will not be described again here. The difference is that the active circuit 220 in semiconductor device 400 is a planar device. Specifically, the source 323 in active circuit 220 is directly connected to the first signal layer 341 via a fourth metal pillar 336. Similarly, the drain 324 in active circuit 220 is directly connected to the first signal layer 341 via a fourth metal pillar 336. In one embodiment, the gate 325 is directly connected to the first signal layer 341 via a fourth metal pillar 336. Furthermore, semiconductor device 400 also includes multiple isolation regions 351, disposed adjacent to the source 323 or drain 324 of active circuit 220, such as... Figure 4 As shown. The aforementioned isolation zone 351 can be a shallow trench isolation (STI) area.

[0053] The redundant circuit 230 and the active circuit 220 can be manufactured using the same semiconductor manufacturing process; that is, the redundant circuit 230 can include a semiconductor structure similar to that of the active circuit 220. Specifically, the redundant source-drain region 232 in the redundant circuit 230 is directly connected to the first redundant metal layer 235 through the first metal pillar 233. Similarly, the redundant gate region 333 in the redundant circuit 230 is directly connected to the first redundant metal layer 235 through the third metal pillar 234.

[0054] The multiple redundant metal layers in the redundant circuit 230 can be connected through vias on the same cross section, or they can be connected through vias on different cross sections.

[0055] In the redundant circuit 230 of the semiconductor devices 300 and 400 described above, the first redundant metal layer 235, the second redundant metal layer 236, and the third redundant metal layer 237 are all connected vias on the cross-section shown in the figure. In one embodiment, the redundant metal layers can be connected vias on different cross-sections. Figure 5a The diagram shows a cross-sectional view of a more specific semiconductor device 500 provided in this application embodiment, at section AA'. Semiconductor device 500 is similar to semiconductor device 300, and its components and connections are identical to those in semiconductor device 300 and will not be described again here. The difference is that, in section AA', a portion of the first redundant metal layer 235 connected to the third metal pillar 234 is directly connected to the second redundant metal layer 236 through the second metal pillar 335 (e.g., a via), but the second redundant metal layer 236 is not directly connected to the third redundant metal layer 237 in section AA'. Figure 5bThe diagram shows a cross-sectional view of the semiconductor device 500 at section BB', where sections AA' and BB' are two parallel sections of the semiconductor device 500 perpendicular to the direction of the substrate 210. Figure 5b In this configuration, a portion of the first redundant metal layer 235, connected to the first metal pillar 233, is connected to the second redundant metal layer 236 at section BB' via a second metal pillar 335 (e.g., a via). The second redundant metal layer 236, in turn, is connected to the third redundant metal layer 237 at section BB' via a metal pillar (e.g., a via). Therefore, the first redundant metal layer 235, the second redundant metal layer 236, and the third redundant metal layer 237 are electrically connected at different sections via metal pillars.

[0056] It should be noted that in the embodiments of this application, one component (or structure) is disposed between, on the surface or on one side of other components (or structures), which can be used to indicate the physical connection relationship between the component (or structure) and other components (or structures).

[0057] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, The semiconductor device includes: substrate; An active circuit is disposed on a first side of the substrate; and A redundant circuit, disposed on the first side and insulated from the active circuit, wherein the redundant circuit includes: First redundant metal layer; P-type heavily doped redundant source / drain regions are disposed in the substrate; A first metal pillar is disposed between the first redundant metal layer and the redundant source / drain region; and A lightly doped P-substrate is disposed in the substrate, the P-substrate surrounding the redundant source / drain regions.

2. The semiconductor device as claimed in claim 1, characterized in that, The redundant circuit also includes: A second redundant metal layer is disposed on the side of the first redundant metal layer away from the substrate; The second metal pillar, wherein the first redundant metal layer and the second redundant metal layer are connected by the second metal pillar.

3. The semiconductor device as described in claim 1, characterized in that, The redundant source / drain regions include P-type heavily doped silicon-germanium (SiGe).

4. The semiconductor device according to any one of claims 1 to 3, characterized in that, The doping concentration of the redundant source / drain regions is 100 to 10000 times that of the doping concentration of the P substrate.

5. The semiconductor device according to any one of claims 1 to 3, characterized in that, The redundant circuit also includes: A third metal pillar is disposed between the first redundant metal layer and the redundant gate region; and The redundant gate region is disposed between the third metal pillar and the P substrate.

6. The semiconductor device as claimed in claim 5, characterized in that, The redundant circuit also includes: A gate metal layer is disposed between the third metal pillar and the redundant gate region; A source / drain metal layer is disposed between the first metal pillar and the redundant source / drain region.

7. The semiconductor device as claimed in claim 6, characterized in that, The gate metal layer comprises cobalt (Co) or titanium (Ti), and the source / drain metal layer comprises Co or Ti.

8. The semiconductor device as claimed in claim 5, characterized in that, The plurality of first metal pillars and the third metal pillar are cobalt (Co) plugs or copper (Cu) plugs.

9. The semiconductor device as claimed in claim 2, characterized in that, The second metal pillar is a copper via.

10. The semiconductor device according to any one of claims 1-3 and 6-9, characterized in that, The active circuit includes planar devices or FinFETs (Fin Field-Effect Transistors).

11. A packaged chip, comprising a molding compound and a die disposed in the molding compound, wherein the die is a semiconductor device according to any one of claims 1 to 10.

12. An electronic device comprising a printed circuit board (PCB) and a packaged chip as claimed in claim 11, wherein the PCB and the packaged chip are electrically connected.

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