Memory device for multiple read operations

Abstract

This application relates to a memory device for multiple read operations. A memory device can include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read a first page of data from a respective memory cell coupled to a selected access line of the plurality of access lines; read a second page of data from the respective memory cell coupled to the selected access line; and close the array of memory cells after reading the first page of data and the second page of data.

Description

[0001] Related applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63 / 126,001, filed on December 16, 2020, which is hereby incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure generally relates to memory, and more specifically, in one or more embodiments, to multiple read operations in a memory device. Background Technology

[0004] Memory (e.g., memory devices) is typically provided in computers or other electronic devices as internal semiconductor integrated circuit devices. Many different types of memory exist, including random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.

[0005] Flash memory has evolved into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory typically uses single-transistor memory cells that allow for high memory density, high reliability, and low power consumption. The data state (e.g., data value) of each memory cell is determined by changes in the threshold voltage (Vt) of the memory cell, often referred to as writing, through programming (often called writing) of the charge storage structure (e.g., floating gate or charge trap) or other physical phenomena (e.g., phase transition or polarization). Common applications of flash memory and other non-volatile memories include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and removable memory modules, and the applications of non-volatile memory continue to expand.

[0006] NAND flash memory is a common type of flash memory device, so named because of the logical arrangement of its basic memory cell configuration. Typically, the memory cell arrays used in NAND flash memory are arranged such that the control gates of each memory cell in a row of the array are connected together to form access lines, such as word lines. Columns of the array consist of strings of memory cells (often called NAND strings) connected in series between a pair of select gates, such as source select transistors and drain select transistors. Each source select transistor can be connected to the source, and each drain select transistor can be connected to a data line, such as a column bit line. Variations using more than one select gate between the memory cell string and the source and / or between the memory cell string and the data line are known.

[0007] In memory programming, memory cells can be broadly programmed as memory cells commonly referred to as Single-Level Cell (SLC) or Multi-Level Cell (MLC). An SLC uses a single memory cell to represent a single digital (e.g., one bit) of data. For example, in an SLC, a Vt of 2.5V can indicate a programmed memory cell (e.g., representing logic 0), while a Vt of -0.5V can indicate an erased cell (e.g., representing logic 1). As an example, the erase state in an SLC can be represented by any threshold voltage less than or equal to 0V, while the programmed data state can be represented by any threshold voltage greater than 0V.

[0008] MLCs use more than two Vt ranges, each indicating a different data state. As is generally known, margins such as dead space (e.g., a certain number of volts) can separate adjacent Vt ranges, for example, to facilitate distinction between data states. Multilevel cells can leverage the analog properties of traditional non-volatile memory cells by assigning bit patterns to specific Vt ranges. While MLCs typically use memory cells to represent one of several binary data states (e.g., 4, 8, 16…), memory cells operating as MLCs can be used to represent several non-binary data states. For example, where the MLC uses three Vt ranges, two memory cells can be used together to represent one of eight data states.

[0009] In programming MLC memory, data values ​​are typically programmed in more than one pass; for example, one or more numbers are programmed in each pass. For instance, in a four-level MLC (often simply called an MLC), a first number, typically called the least significant bit (LSB) of the lower page (LP) data, is programmed into the memory cell in the first pass, thereby creating two (e.g., first and second) threshold voltage ranges. Subsequently, a second number, typically called the most significant bit (MSB) of the upper page (UP) data, is programmed into the memory cell in the second pass, typically moving a portion of those memory cells in the first threshold voltage range into the third threshold voltage range, and a portion of those memory cells in the second threshold voltage range into the fourth threshold voltage range. Similarly, an eight-level MLC (commonly referred to as a TLC) can represent a bit pattern containing the following three bits: a first number, such as the least significant bit (LSB) or lower page (LP) data; a second number, such as the upper page (UP) data; and a third number, such as the most significant bit (MSB) or extra page (XP) data. In operating a TLC, the LP data is programmed into the memory cells in the first pass, resulting in two threshold voltage ranges, and then the UP and XP data are programmed into the memory cells in the second pass, resulting in eight threshold voltage ranges. Similarly, a sixteen-level MLC (commonly referred to as a QLC) can represent a four-bit bit pattern, and a 32-level MLC (commonly referred to as a PLC) can represent a five-bit bit pattern.

[0010] When reading data from a memory device, there is read overhead that increases the total read time (e.g., preamble, read initialization, read recovery). This read overhead can be repeated each time the memory device is accessed to read a single page of data. Summary of the Invention

[0011] One aspect of this disclosure provides a memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; a plurality of access lines, each of the plurality of access lines being connected to a control gate of a corresponding memory cell in each of the plurality of serially connected memory cell strings; and control logic configured to: turn on the memory cell array for a plurality of read operations; read a first page of data from a corresponding memory cell coupled to a selected access line of the plurality of access lines; read a second page of data from a corresponding memory cell coupled to a selected access line; and turn off the memory cell array after reading the first page of data and the second page of data.

[0012] Another aspect of this disclosure provides a memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; a plurality of access lines, each of the plurality of access lines being connected to a control gate of a corresponding memory cell in each of the plurality of serially connected memory cell strings; a page buffer connected to the memory cell array; and control logic configured to: enable the memory cell array for a plurality of read operations; read a first page of data from a corresponding memory cell coupled to a selected access line of the plurality of access lines to latch the first page of data in the page buffer; pass the latched first page of data out of the page buffer; read a second page of data from a corresponding memory cell coupled to a selected access line to latch the second page of data in the page buffer; pass the latched second page of data out of the page buffer; and disable the memory cell array.

[0013] Another aspect of this disclosure provides a memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; a plurality of access lines, each of the plurality of access lines being connected to a control gate of a corresponding memory cell in each of the plurality of serially connected memory cell strings; a plurality of data lines, each of the plurality of data lines being connected via a corresponding select gate of a plurality of select gates to a corresponding subset of the plurality of serially connected memory cell strings; and a plurality of select lines, each of the plurality of select lines being connected to a control gate of a corresponding select gate of the plurality of select gates for phase selection of the plurality of select gates. The subset; and control logic configured to: enable the memory cell array for multiple read operations; bias a first select line of a plurality of select lines to connect each of a plurality of data lines to a corresponding first cascaded memory cell string of a plurality of cascaded memory cell strings via a corresponding select gate of a plurality of select gates; read a first page of data from a corresponding memory cell of a first selected access line of a plurality of access lines coupled to the corresponding first cascaded memory cell string; and after reading the first page of data, read a second page of data from a corresponding memory cell of a first selected access line of a plurality of access lines coupled to the corresponding first cascaded memory cell string without turning off the memory cell array. Attached Figure Description

[0014] Figure 1 This is a simplified block diagram of a memory that communicates with a processor, which is part of an electronic system, according to one embodiment.

[0015] Figures 2A to 2C It can be used for reference. Figure 1 A schematic diagram of a portion of the memory cell array in the described type of memory.

[0016] Figure 3A and3B It can be used for reference. Figure 1 A simplified block diagram of a portion of the page buffer in the memory of the described type.

[0017] Figure 4 Timing diagrams depict methods for operating a memory used in various embodiments.

[0018] Figure 5 A timing diagram depicts another method for operating a memory used in various embodiments.

[0019] Figure 6 A timing diagram depicts another method for operating a memory used in various embodiments.

[0020] Figure 7 A timing diagram depicts another method for operating a memory used in various embodiments.

[0021] Figure 8 A timing diagram depicts another method for operating a memory used in various embodiments.

[0022] Figure 9 This is a flowchart of a method for operating a memory according to one embodiment.

[0023] Figure 10 This is a flowchart of a method for operating a memory according to another embodiment.

[0024] Figures 11A to 11D This is a flowchart of a method for operating a memory according to another embodiment. Detailed Implementation

[0025] In the following detailed description, reference is made to the accompanying drawings, which form part of the invention, and in which specific embodiments are illustrated by way of description. In the drawings, the same reference numerals throughout the various views describe generally similar components. Other embodiments may be utilized, and structural, logical, and electrical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0026] For example, the term "semiconductor" as used herein may refer to a layer of material, a wafer, or a substrate, and includes any substrate semiconductor structure. "Semiconductor" should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial silicon layers supported by a substrate semiconductor structure, and other semiconductor structures well known to those skilled in the art. Furthermore, when referenced to a semiconductor in the following description, regions / junctions may have been formed in the substrate semiconductor structure using prior process steps, and the term semiconductor may include an underlying layer containing such regions / junctions.

[0027] Unless otherwise apparent from the context, the term "conductive" as used herein, and its various related forms (e.g., conduct, conductively, conducting, conduction, conductivity, etc.), refer to electrical conductivity. Similarly, unless otherwise apparent from the context, the term "connecting" as used herein, and its various related forms (e.g., connect, connected, connection, etc.), refer to electrical connection.

[0028] This paper recognizes that even when values ​​are expected to be equal, the variability and precision of industrial processing and operation can still cause differences from their expected values. These variability and precision will typically depend on the technology used in the manufacture and operation of integrated circuit devices. Therefore, if values ​​are expected to be equal, then those values ​​are considered equal regardless of their resulting values.

[0029] Figure 1 This is a simplified block diagram illustrating communication between a first device in the form of memory (e.g., a memory device) 100 and a second device in the form of a processor 130 as part of a third device in the form of an electronic system, according to one embodiment. Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, electrical equipment, vehicles, wireless devices, mobile phones, and the like. The processor 130 (e.g., a controller external to the memory device 100) may be a memory controller or other external host device.

[0030] Memory device 100 includes an array 104 of memory cells that can be logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (collectively referred to as a word line), while memory cells in logical columns are typically selectively connected to the same data line (collectively referred to as a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in the memory cell array 104 ( Figure 1 (Not shown in the text) can be programmed to be one of at least two target data states.

[0031] Row decoding circuit 108 and column decoding circuit 110 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 100 also includes input / output (I / O) control circuitry 112 to manage inputs of commands, addresses, and data to memory device 100, as well as outputs of data and status information from memory device 100. Address register 114 communicates with I / O control circuitry 112, row decoding circuitry 108, and column decoding circuitry 110 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 112 and control logic 116 to latch incoming commands.

[0032] A controller (e.g., control logic 116 within memory device 100) controls access to memory cell array 104 in response to the command and may generate status information for external processor 130, i.e., control logic 116 is configured to perform access operations (e.g., sensing operations [which may include read and verification operations], programming operations, and / or erase operations) on memory cell array 104. Control logic 116 communicates with row decoding circuitry 108 and column decoding circuitry 110 to control row decoding circuitry 108 and column decoding circuitry 110 in response to an address. Control logic 116 may include instruction register 128, which may represent computer-available memory for storing computer-readable instructions. In some embodiments, instruction register 128 may represent firmware. Alternatively, instruction register 128 may represent a grouping of memory cells of memory cell array 104, such as a reserved block of memory cells.

[0033] Control logic 116 may also communicate with cache register 118. Cache register 118 latches incoming or outgoing data, such as that guided by control logic 116, to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data may be transferred from cache register 118 to data register 120 for transfer to memory cell array 104; subsequently, new data may be latched into cache register 118 from I / O control circuitry 112. During read operations, data may be transferred from cache register 118 to I / O control circuitry 112 for output to external processor 130; subsequently, new data may be transferred from data register 120 to cache register 118. Cache register 118 and / or data register 120 may form a page buffer of memory device 100 (e.g., may form a portion thereof). The page buffer may further include sensing devices ( Figure 1(Not shown) The data status of the memory cells in the memory cell array 104 can be sensed, for example, by sensing the status of the data lines connected to the memory cells. The status register 122 can communicate with the I / O control circuitry 112 and the control logic 116 to latch status information for output to the processor 130.

[0034] The memory device 100 receives control signals from the processor 130 via control link 132 at control logic 116. These control signals may include chip enable (CE#), command latch enable (CLE), address latch enable (ALE), write enable (WE#), read enable (RE#), and write protection (WP#). Depending on the nature of the memory device 100, additional or alternative control signals (not shown) may be received further via control link 132. The memory device 100 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the processor 130 via a multiplexed input / output (I / O) bus 134 and outputs data to the processor 130 via the I / O bus 134.

[0035] For example, commands can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134, and the commands can then be written to command register 124. Addresses can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134, and the addresses can then be written to address register 114. Data can be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices, and the data can then be written to cache register 118. Data can then be written to data register 120 for programming memory cell array 104. In another embodiment, cache register 118 can be omitted, and data can be written directly to data register 120. Data can also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. While references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that enable electrical connections to the memory device 100 via external devices (e.g., processor 130).

[0036] Those skilled in the art will understand that additional circuitry and signals can be provided, and the process has been simplified. Figure 1 The memory device 100. It should be understood that, with reference to Figure 1 The functionality of the various block components described need not be separated from the different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1 The functionality can exceed that of a single component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1 The functionality of a single block component.

[0037] In addition, while specific I / O pins are described according to the general conventions for receiving and outputting various signals, it should be noted that other combinations of I / O pins or other numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0038] Figure 2A It can be, for example, as part of memory cell array 104 in reference Figure 1 A schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array, used in the described type of memory. The memory array 200A includes access lines (e.g., word lines) 2020 to 2022. N And data lines (e.g., bit lines) 2040 to 204 M Access line 202 can be connected in a many-to-one relationship. Figure 2A Global access lines (e.g., global word lines) not shown in the diagram. In some embodiments, the memory array 200A may be formed over a semiconductor, which may be conductively doped to have a conductivity type such as p-type conductivity to form a p-well, for example, or to have n-type conductivity to form an n-well, for example.

[0039] The memory array 200A can be arranged in rows (each corresponding to an access line 202) and columns (each corresponding to a data line 204). Each column can contain strings of memory cells (e.g., non-volatile memory cells) connected in series, such as NAND strings 2060 to 206. M One of them. Each NAND string 206 may be connected (e.g., selectively connected) to a common source (SRC) 216 and may contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for storing data. Memory cells 2080 to 208 N It may include memory cells intended for storing data, and may further include other memory cells not intended for storing data, such as dummy memory cells. Dummy memory cells are generally not accessible to the user of the memory, and are often alternatively incorporated into a series-connected string of memory cells to obtain well-known operational advantages.

[0040] Each NAND string 206 memory cell 208 can be connected in series at select gates 2100 to 210. MOne of them (e.g., it may be a source selection transistor collectively referred to as a select gate source) has a select gate 210 (e.g., a field-effect transistor) and select gates such as 2120 to 212. M Between one of the select gates 212 (e.g., a field-effect transistor) (which may be a drain-select transistor collectively referred to as the select gate drain). Select gates 2100 to 210 M They can be commonly connected to select line 214, such as the source select line (SGS), and select gates 2120 to 212. M They can be commonly connected to select line 215, such as a drain select line (SGD). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent a plurality of select gates connected in series, wherein each select gate connected in series is configured to receive the same or independent control signal.

[0041] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0042] The drain of each select gate 212 can be connected to the data line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the data line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding data line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0043] Figure 2A The memory array in the array can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and data line 204 extend in a generally parallel plane. Alternatively, Figure 2AThe memory array in the array can be a three-dimensional memory array, for example, in which the NAND string 206 extends substantially perpendicular to the plane containing the common source 216 and substantially perpendicular to the plane containing the data line 204, which may be substantially parallel to the plane containing the common source 216.

[0044] like Figure 2A As shown, a typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or other structure configured to store charge) that determines the data state of the memory cell (e.g., by a change in threshold voltage), and a control gate 236. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 may further have defined source / drain (e.g., source) 230 and defined source / drain (e.g., drain) 232. Memory cell 208 has its control gate 236 connected to (and in some cases formed) access line 202.

[0045] A column of memory cells 208 may be a NAND string 206 or multiple NAND strings 206 selectively connected to a given data line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may (but does not necessarily) contain all memory cells 208 commonly connected to a given access line 202. A row of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically contains every other memory cell 208 commonly connected to a given access line 202. For example, commonly connected to access line 202 N Furthermore, memory cells 208 selectively connected to even-numbered data lines 204 (e.g., data lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while being commonly connected to access line 202. N Furthermore, the memory cell 208 selectively connected to the odd-numbered data lines 204 (e.g., data lines 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., the odd-numbered memory cell). Although data lines 2043 to 2045 are not explicitly depicted in... Figure 2A However, it is obvious from the diagram that the data line 204 of the memory cell array 200A can be from data line 2040 to data line 204. MMemory cells 208 that are commonly connected to a given access line 202 are numbered sequentially. Other groups of memory cells 208 that are commonly connected to a given access line may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given access line may be considered physical pages of the memory cells. A portion of a physical page of a memory cell (which in some embodiments may still be an entire row) that is read during a single read operation or programmed during a single programmable operation (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to access lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing common access line 202). Unless explicitly distinguished, a reference to a memory cell page herein refers to the memory cell of the logical page of the memory cell.

[0046] Although combined with the NAND flash memory theory Figure 2A Examples are provided, but the embodiments and concepts described herein are not limited to a particular array architecture or structure and may include other structures (e.g., SONOS or other data storage structures configured to store charge) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0047] Figure 2B It can be, for example, part of memory cell array 104 in reference Figure 1 Another schematic diagram of a portion of the memory cell array 200B used in the type of memory described. Figure 2B The same numbered elements in the text correspond to, for example, regarding... Figure 2A The description provided. Figure 2B Further details are provided for an example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B may be incorporated into a vertical structure that may contain semiconductor pillars, a portion of which may serve as channel regions for the memory cells of NAND strings 206. Each of the NAND strings 206 may be selectively connected to data lines 2040 to 2046 via a select transistor 212 (e.g., which may be a drain select transistor, collectively referred to as select gate drain). M And a selection transistor 210 (e.g., which may be a source selection transistor, collectively referred to as the select gate source) is selectively connected to a common source 216. Multiple NAND strings 206 can be selectively connected to the same data line 204. A subset of the NAND strings 206 can be connected via select lines 2150 to 215... KA bias voltage selectively activates specific select transistors 212, each connected to its corresponding data line 204, located between the NAND string 206 and the data line 204. Select transistor 210 can be activated by biasing select line 214. Each access line 202 can be connected to multiple rows of memory cells in the memory array 200B. Rows of memory cells commonly connected to each other via specific access lines 202 are collectively referred to as a hierarchy.

[0048] A three-dimensional NAND memory array 200B may be formed above peripheral circuitry 226. Peripheral circuitry 226 may represent various circuits used to access the memory array 200B. Peripheral circuitry 226 may include complementary circuit elements. For example, peripheral circuitry 226 may include both n-channel and p-channel transistors formed on the same semiconductor substrate; this process is commonly referred to as CMOS or Complementary Metal-Oxide-Semiconductor. Although CMOS often no longer utilizes a strictly metal-oxide-semiconductor construction due to advancements in integrated circuit manufacturing and design, the designation CMOS is retained for convenience.

[0049] Figure 2C It can be, for example, as part of memory cell array 104 in reference Figure 1 Another schematic diagram of a portion of the memory cell array 200C used in the type of memory described. Figure 2C The same numbered elements in the text correspond to, for example, regarding... Figure 2A The provided description. The memory cell array 200C may contain, for example: Figure 2A The memory cell array 200A depicts a series-connected string of memory cells (e.g., a NAND string) 206, an access (e.g., a word) line 202, a data (e.g., a bit) line 204, a select line 214 (e.g., a source select line), a select line 215 (e.g., a drain select line), and a source 216. For example, a portion of the memory cell array 200A may be a portion of the memory cell array 200C. Figure 2C The diagram depicts the NAND string 206 being grouped into memory cell blocks 250, such as memory cell blocks 2500 to 250. L Memory cell block 250 may be a group of memory cells 208 that can be erased together in a single erase operation, sometimes referred to as an erase block. Each memory cell block 250 may contain those NAND strings 206 that are commonly associated with a single select line 215 (e.g., select line 2150). The source 216 of memory cell block 2500 may be associated with memory cell block 250. L The source 216 is the same as the source. For example, each memory cell block 2500 to 250 L They can be selectively connected together to source 216. Access lines 202 and select lines 214 and 215 of a memory cell block 250 can be connected to memory cell blocks 2500 to 2500 respectively.L Access lines 202 and select lines 214 and 215 of any other memory cell blocks are not directly connected.

[0050] Data cable 2040 to 204 M It can be connected (e.g., selectively connected) to buffer portion 240, which may be part of a data buffer in a memory. Buffer portion 240 may correspond to a memory plane (e.g., memory cell blocks 2500 to 250). L The buffer section 240 may include sensing circuitry for sensing the data value indicated on the corresponding data line 204. Figure 2C (Not shown in the text).

[0051] Although Figure 2C Each memory cell block 250 is depicted as having only one select line 215, but the memory cell block 250 may contain NAND strings 206 that are commonly associated with more than one select line 215. For example, the select line 2150 of the memory cell block 2500 may correspond to Figure 2B The selection line 2150 of the memory array 200B, and Figure 2C The memory cell blocks of the memory array 200C can further include... Figure 2B Selection line 2151 to 215 K The associated NAND strings 206. In such a memory cell block 250 having NAND strings 206 associated with multiple select lines 215, those NAND strings 206 typically associated with a single select line 215 may be referred to as memory cell sub-blocks. Each such memory cell sub-block may be selectively connected to the buffer section 240 in response to its respective select line 215.

[0052] Figure 3A This is a simplified block diagram of a portion of page buffer 240a. In one instance, page buffer 240a could be... Figure 2C The buffer section 240. Data lines 2040 to 204. M It can be connected to page buffer 240a. Page buffer 240a may contain separate buffers for each data line 2040 to 2040. M latches 2600 to 260 M In one instance, each latch has 2600 to 260 latches. M Page data (e.g., upper page data, lower page data, and additional page data) read from a memory cell array (e.g., memory cell array 200C) can be stored sequentially, such that previously read page data (e.g., first page data) is read from latches 2600 to 2600 before additional page data (e.g., second page data) is read. MThe extra page data is then latched in latches 2600 to 260. M In another instance (collectively referred to as cache reads), each latch has 2600 to 260 latches. M Page data read from the memory cell array can be stored sequentially, such that previously read page data (e.g., the first page data) and read additional page data (e.g., the second page data) are read in parallel from latches 2600 to 2600. M The extra page data is then latched in latches 2600 to 260. M middle.

[0053] Figure 3B This is a simplified block diagram of another portion of page buffer 240b. In one instance, page buffer 240b could be... Figure 2C The buffer section 240. Data lines 2040 to 204. M It can be connected to page buffer 240b. Page buffer 240b may contain separate buffers for each data line 2040 to 2040. M Multiple latches 262 0,0 up to 262 0,Y and 262 M,0 up to 262 M,Y . Used for each data line 2040 to 204 respectively. M latch 262 0,0 up to 262 0,Y and 262 M,0 up to 262 M,Y Each set can store multiple pages of data (e.g., lower page data, upper page data, additional page data, etc.) read in parallel from a memory cell array (e.g., memory cell array 200C). For example, latch 262... 0,0 Latch 262 can store the lower page data read from the selected memory cell coupled to data line 2040. 0,1 It can store data from the previous page, and the latch 262 0,2 Additional page data can be stored. In one instance, previously read multiple pages of data can be retrieved from latch 262 before additional page data is read. 0,0 up to 262 0,Y and 262 M,0 up to 262 M,Y Passed out. In another instance (collectively referred to as cache read), previously read multi-page data can be read from latch 262 in parallel with the read of additional page data. 0,0 up to 262 0,Y and 262 M,0 up to 262 M,Y Pass it on.

[0054] Figure 4 Depicting a memory used for operation in various embodiments (e.g., Figure 1 Timing diagram of the method for using memory device 100. For simplicity, Figure 4 and afterwards Figures 5 to 8 This assumes multiple read operations for a TLC memory cell, for example, an eight-level memory cell using eight threshold voltage ranges to represent data states L0, L1, L2, L3, L4, L5, L6, and L7, each representing a bit pattern corresponding to three digits. While discussed with reference to a TLC memory cell, the same applies to multiple read operations performed on lower-density memory cells (e.g., SLC (two data states)) or higher-density memory cells (e.g., QLC (16 data states) or PLC (32 data states) memory cells). In this example, multiple pages of data are read from a memory cell coupled to a single access line within a single memory cell block (or sub-block).

[0055] exist Figure 4 In this context, trace 300 may represent a voltage level applied to a selected access line (e.g., a selected word line) connected to a memory cell (e.g., a target memory cell) selected for multiple read operations. The following discussion will refer to at least... Figure 2C The process will proceed as follows, and it will be assumed that the memory cells selected for multiple read operations are NAND strings 2060 to 206 of memory cell block 2500. M memory cell 208 N This allows trace 300 to represent an application applied to access line 202. N The voltage level. Access line 202 N These can be called selected access lines because they contain the target memory cell, while the remaining access lines 202 can be called unselected access lines.

[0056] At time t0 (for example, from...) Figure 1 The control logic 116) receives a command to open a memory cell array (e.g., memory cell array 200C) for multiple read operations. In response to the command to open the memory cell array, the selected access line 202... N The voltage can be increased from the reference voltage 302 to a level sufficient to initiate coupling to the selected access line 202. N Each corresponding memory cell 208 N The voltage is 304. Although Figure 4Not shown, but in response to a command to open the memory cell array, the memory cell array can also be opened between time t0 and t1 for multiple read operations by: increasing the voltage of each unselected access line 202 from the reference voltage 302 to a voltage 304 sufficient to activate each corresponding memory cell 208 coupled to each unselected access line 202, and biasing select lines 2150 and 2140 to activate the corresponding select gates 212 and 210 to select the corresponding NAND string 206 within the memory cell block 2500.

[0057] At time t1, the selected access line 202 N The voltage has reached 304. The period between time t0 and t1 is the read overhead portion, as no data is read during this period. At time t1, data can be received from the coupling to the selected access line 202. N The corresponding memory unit 208 N A command to read the first page of data (e.g., data from the next page). Between time t1 and t2, this is achieved by adjusting the selected access line 202. N The voltage level is (for example, via connected to bit lines 2040 to 204) M The sensing circuit senses the corresponding memory cell 208. N The lower page data is used to read the first page data. At time t2, data can be received from the selected access line 202. N The corresponding memory unit 208 N A command to read the second page of data (e.g., data from the previous page). Between times t2 and t3, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 N The upper page data is used to read the second page data. At time t3, data can be received from the selected access line 202. N The corresponding memory unit 208 N A command to read the third page of data (e.g., extra page data). Between times t3 and t4, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 N The extra page data is used to read the third page data.

[0058] At time t4, multiple read operations are completed and a command to shut down the memory cell array is received. In response to the command to shut down the memory cell array, the selected access line 202... N The voltage ramps up sufficiently to initiate coupling to the selected access line 202. N Each corresponding memory cell 208 N The voltage 304, which in turn causes the selected access line 202 to... NThe voltage is sloping down to the reference voltage of 302. Although Figure 4 Not shown, but in response to a command to shut down the memory cell array, the memory cell array is also shut down between time t4 and t5 by: ramping up the voltage of each unselected access line 202 to a voltage 304 sufficient to activate each corresponding memory cell 208 coupled to the unselected access line 202, then ramping down the unselected access line 202 to a reference voltage 302, and biasing the select lines 2150 and 2140 to disable the corresponding select gates 212 and 210 to deselect the corresponding NAND string 206 within the memory cell block 2500.

[0059] The period between times t4 and t5 is the read overhead portion, as no data is read during this period. By utilizing the single array open overhead between times t0 and t1 and the single array close overhead between times t4 and t5, instead of the array open and close overhead for each individual page read, the overall read time for multiple read operations within a single memory cell block (or sub-block) can be reduced for selected access lines. Figure 4 In a specific instance, by not closing the array between page reads, the overall read time is reduced by the amount of time equal to the sum of the overhead of opening two arrays and the overhead of closing two arrays.

[0060] It should be noted that the array open-end overhead and array close-end overhead described herein are different from those incurred by the memory device (e.g., 130) in response to receiving a read command from a processor (e.g., 130) connected to the memory device. Figure 1 The global startup / shutdown activity (100%) is executed. The global startup activity may include activities that prepare memory for read operations, such as starting the internal controller (e.g., Figure 1 The control logic 116) includes voltage generation devices and analog circuitry, and senses the temperature of the memory to adjust for any temperature-dependent variables during read operations. Global shutdown activities may include activities that return the memory to some initialization state, such as deactivating the voltage generation devices and analog circuitry of the internal controller. In contrast, the array enable and array disable overheads described herein are specific to memory cell arrays.

[0061] Figure 5 A timing diagram depicts another method for operating a memory used in various embodiments. In this example, a single access line (e.g., 202) coupled to multiple memory cell blocks (or sub-blocks) is used. N The memory cell reads multiple pages of data. Figure 5 In this context, trace 310 may represent a first selection line applied to a corresponding selection gate 212 (e.g., Figure 2CThe voltage level of the select line 2150 of the memory cell block 2500. Trace 312 may represent the voltage level applied to a second select line (e.g., select line 2151 of the memory cell block 2501) connected to a corresponding select gate 212. Trace 312 may represent the voltage level applied to a third select line (e.g., select line 2152 of the memory cell block 2502) connected to a corresponding select gate 212. Although Figure 5 Three traces 310, 312, and 314 are depicted corresponding to three memory cell blocks (or sub-blocks) for multiple read operations, but in other embodiments, multiple read operations may involve two or more memory cell blocks.

[0062] At time t0 (for example, from...) Figure 1 The control logic 116) receives a command to open the memory cell array for multiple read operations. In response to the command to open the memory cell array, the voltage of each select line 2150, 2151, 2152 can be increased from the reference voltage 316 to a voltage 318 sufficient to connect each data line 204 to the corresponding serially connected string of memory cells 206 via the corresponding select gate 212. Although Figure 5 Not shown in the text, but in response to a command to open the memory cell array, the memory cell array can also be opened between time t0 and t1 for multiple read operations by: enabling the selected access line 202 N The voltage of each unselected access line 202 is increased from the reference voltage to a level sufficient to initiate coupling to the selected access line 202. N The voltage of each corresponding memory cell 208 of each unselected access line 202, and the biasing of select lines 2140, 2141, 2142 to activate the corresponding select gate 210 to connect the common source 216 to each corresponding series-connected string of memory cells 206.

[0063] At time t1, the voltage of each selection line 2150, 2151, and 2152 has reached voltage 318. The period between time t0 and t1 is the read overhead portion, as no data is read during this period. At time t1, selected access lines 202 coupled to the first memory cell block 2500 are available for reception. N The corresponding memory unit 208 NA command to read the first page of data. Between times t1 and t2, the voltage on select line 2150 is maintained to keep the corresponding select gate 212 active, as indicated by trace 310 for the first memory cell block 2500, while the voltage on select lines 2151 and 2152 is reduced to deactivate the corresponding select gate 212 for memory cell blocks 2501 and 2502, as indicated by traces 312 and 314. Therefore, the coupling to the selected access line 202 within the first memory cell block 2500 is selected. N The corresponding memory cell. Then the first page of data (e.g., the lower page data) is read from the first memory cell block 2500.

[0064] At time t2, the selected access line 202 coupled to the second memory cell block 2501 can be received. N The corresponding memory unit 208 N A command to read the second page of data. Between times t2 and t3, the voltage on select line 2152 increases to activate the corresponding select gate 212, as indicated by trace 312 for the second memory cell block 2501, while the voltage on select lines 2150 and 2152 decreases (or is maintained) to deactivate the corresponding select gate 212 for memory cell blocks 2500 and 2502, as indicated by traces 310 and 314. Therefore, the selected access line 202 within the second memory cell block 2501 is selected. N The corresponding memory cell. Then the second page data (e.g., the lower page data) is read from the second memory cell block 2501.

[0065] At time t3, the selected access line 202 coupled to the third memory cell block 2502 can be received. N The corresponding memory unit 208 N A command to read the third page of data. Between times t3 and t4, the voltage on select line 2152 increases to activate the corresponding select gate 212, as indicated by trace 314 for the third memory cell block 2502, while the voltage on select lines 2151 and 2152 decreases (or is maintained) to deactivate the corresponding select gate 212 for memory cell blocks 2500 and 2501, as indicated by traces 310 and 312. Therefore, the selected access line 202 within the third memory cell block 2502 is coupled to the selected access line. N The corresponding memory cell. Then the third page data (e.g., the lower page data) is read from the third memory cell block 2502.

[0066] At time t4, multiple read operations are completed and a command to shut down the memory cell array is received. In response to the command to shut down the memory cell array, the voltage of each select line 2150, 2151, 2152 ramps up to a voltage 318 sufficient to activate the voltage 318 coupled to the corresponding select gate 212 of each select line 2150, 2151, 2152, and then ramps down to a reference voltage 316, as indicated by traces 310, 312, 314. Although Figure 5 Not shown in the text, but in response to the command to shut down the memory cell array, the memory cell array is also shut down between time t4 and t5 by the following operation: the selected access line 202 is turned off. N The voltage of the unselected access line 202 is ramped up to be sufficient to initiate coupling to the selected access line 202. N The voltage of each corresponding memory cell 208 of the unselected access line 202, thereby causing the selected access line 202 to... N The unselected access line 202 is ramped down to the reference voltage, and the select lines 2140, 2141, and 2142 are biased to disable the corresponding select gate 210 to disconnect the common source 216 from each corresponding series-connected memory cell string 206.

[0067] The period between times t4 and t5 is the read overhead portion, as no data is read during this period. By utilizing the single array open overhead between times t0 and t1 and the single array close overhead between times t4 and t5, instead of the array open and close overhead for each individual page read, the overall read time for multiple read operations can be reduced for selected access lines used for multiple memory cell blocks (or sub-blocks). Figure 5 In a specific instance, by not shutting down the array when switching between memory cell blocks, the overall read time is reduced by the amount of time equal to the overhead of opening two arrays and closing two arrays.

[0068] Figure 6 A timing diagram depicts another method for operating a memory used in various embodiments. In this example, coupling from a single memory cell block (e.g., 2500) to multiple access lines (e.g., 202) is described. N 202 N-1 202 N-2 The memory cell reads multiple pages of data. Figure 6 In this context, trace 320 can represent an application applied to a corresponding memory cell 208 connected within the memory cell block 2500. N First access line 202 N The voltage level. Trace 322 can represent the voltage applied to the corresponding memory cell 208 connected within the memory cell block 2500.N-1 Second access line 202 N-1 The voltage level. Trace 324 can represent the voltage applied to the corresponding memory cell 208 connected within the memory cell block 2500. N-2 The third access line 202 N-2 The voltage level. Although Figure 6 Three traces 320, 322, and 324 are depicted corresponding to three access lines for multiple read operations, but in other embodiments, multiple read operations may involve two or more access lines.

[0069] At time t0 (for example, from...) Figure 1 The control logic 116) receives a command to open the memory cell array for multiple read operations. In response to the command to open the memory cell array, each access line 202... N 202 N-1 202 N-2 The voltage can be increased from the reference voltage 326 to a voltage 328 sufficient to activate each corresponding memory cell 208 coupled to each access line, as indicated by traces 320, 322, 324. Although Figure 6 Not shown, but in response to a command to open the memory cell array, the memory cell array can also be opened between time t0 and t1 for multiple read operations by: increasing the voltage of each unselected access line 202 from the reference voltage 326 to a voltage 328 sufficient to activate each corresponding memory cell 208 coupled to each unselected access line 202, and biasing select lines 2150 and 2140 to activate the corresponding select gates 212 and 210 to select the corresponding NAND string 206 within the memory cell block 2500.

[0070] At time t1, each access line 202 N 202 N-1 202 N-2 The voltage has reached 328. The period between time t0 and t1 is the read overhead portion, as no data is read during this period. At time t1, data can be received from the coupling to the first access line 202. N The corresponding memory unit 208 N A command to read the first page of data (e.g., data from the next page). Access line 202 between times t1 and t2. N The voltage is reduced from the coupling to the access line 202 N The corresponding memory unit 208 N Read the first page of data, as indicated by trace 320, while access line 202 N-1 202 N-2 The voltage is maintained at a level sufficient to initiate coupling to each access line 202.N-1 202 N-2 The corresponding memory unit 208 N-1 208 N-2 At voltage 328, as indicated by traces 322 and 324.

[0071] At time t2, the line from coupling to access line 202 can be received. N-1 The corresponding memory unit 208 N-1 Command to read the second page of data. Between timest2 andt3, access line 202... N-1 The voltage is reduced from the coupling to the access line 202 N-1 The corresponding memory unit 208 N-1 Read the second page of data (e.g., the data from the next page), as indicated by trace 322, while access line 202... N 202 N-2 The voltage is increased (or maintained) to a level sufficient to initiate coupling to each access line 202. N 202 N-2 The corresponding memory unit 208 N 208 N-2 The voltage is 328, as indicated by traces 320 and 324.

[0072] At time t3, data can be received from the coupling to the selected access line 202. N-2 The corresponding memory unit 208 N-2 Command to read data from the third page. Access line 202 between timest3 and t4. N-2 The voltage is reduced from the coupling to the access line 202 N-2 The corresponding memory unit 208 N-2 Read the third page of data (e.g., the data from the bottom page), as indicated by trace 324, while access line 202... N 202 N-1 The voltage is increased (or maintained) to a level sufficient to initiate coupling to each access line 202. N 202 N-1 The corresponding memory unit 208 N 208 N-1 The voltage is 328, as indicated by traces 320 and 322.

[0073] At time t4, multiple read operations are completed and a command to close the memory cell array is received. In response to the command to close the memory cell array, each access line 202... N 202 N-1 202 N-2 The voltage ramps up sufficiently to activate the corresponding memory cell 208 coupled to each access line. N 208N-1 208 N-2 The voltage is 328, which in turn causes each access line 202 to... N 202 N-1 202 N-2 The voltage is ramped down to the reference voltage of 326. Although Figure 6 Not shown, but in response to a command to shut down the memory cell array, the memory cell array is also shut down between time t4 and t5 by: ramping up the voltage of the unselected access line 202 to a voltage 328 sufficient to activate each corresponding memory cell 208 coupled to the unselected access line 202, then ramping down the unselected access line 202 to a reference voltage 326, and biasing the select lines 2150 and 2140 to disable the corresponding select gates 212 and 210 to deselect the corresponding NAND string 206 of the memory cell block 2500.

[0074] The period between times t4 and t5 is the read overhead portion, as no data is read during this period. By utilizing the single array open overhead between times t0 and t1 and the single array close overhead between times t4 and t5, instead of the array open and close overhead for each individual page read, the overall read time for multiple read operations within a single memory cell block (or sub-block) can be reduced by reading multiple pages between times t1 and t4. Figure 6 In a specific instance, by not closing the array between page reads, the overall read time is reduced by the amount of time equal to the overhead of opening two arrays and closing two arrays.

[0075] Figure 7 A timing diagram depicts another method for operating a memory used in various embodiments. In this example, multiple memory cell blocks (or sub-blocks) are coupled to multiple access lines (e.g., 202) within a plurality of memory cell blocks (or sub-blocks) (e.g., 2500, 2501, 2502). N and 202 N-1 The memory cell reads multiple pages of data. Figure 7 In the diagram, trace 330 may represent the currently selected access line 202 applied to the corresponding memory cell 208 (the selected access line is in...). Figure 7 (Changes in voltage level). Although Figure 7 Depicts two access lines 202 for multiple read operations N and 202 N-1 And three memory cell blocks 2500, 2501, 2502, but in other embodiments, multiple read operations may involve one access line, more than two access lines, less than three memory cell blocks, or more than three memory cell blocks.

[0076] At time t0 (for example, from...) Figure 1The control logic 116) receives a command to open the memory cell array for multiple read operations. In response to the command to open the memory cell array, the selected access line 202... N The voltage can be increased from the reference voltage 332 to a level sufficient to initiate coupling to the selected access line 202. N Each corresponding memory cell 208 N The voltage is 334. Although Figure 7 Not shown in the diagram, but in response to a command to open the memory cell array, the memory cell array can also be opened between time t0 and t1 for multiple read operations by: enabling unselected access lines (e.g., 202). N-1 The voltage of the other access lines (202) is increased from the reference voltage 332 to a voltage 334 sufficient to activate each corresponding memory cell 208 coupled to each unselected access line, and the select lines 2150, 2151, 2152 and 2140, 2141, 2142 are biased to activate the corresponding select gates 212 and 210 to select each corresponding serially connected string of memory cells 206 within the memory cell blocks 2500, 2501, 2502.

[0077] At time t1, the selected access line 202 N The voltage has reached 334. The period between time t0 and t1 is the read overhead portion, as no data is read during this period. At time t1, the selected access line 202 coupled to the first memory cell block 2500 can be received. N The corresponding memory unit 208 N A command to read the first page of data (e.g., data from the next page). Between time t1 and t2, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 for the first memory cell block 2500. N The lower page data is used to read the first page data. At time t2, the selected access line 202 coupled to the first memory cell block 2500 can be received. N The corresponding memory unit 208 N A command to read the second page of data (e.g., data from the previous page). Between times t2 and t3, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 for the first memory cell block 2500. N The upper page data is used to read the second page data. At time t3, the selected access line 202 coupled to the first memory cell block 2500 can be received. N The corresponding memory unit 208 NA command to read the third page of data (e.g., extra page data). Between times t3 and t4, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 for the first memory cell block 2500. N The extra page data is used to read the third page data.

[0078] Multiple read operations, such as by Figure 7 The time t4 in the first line and Figure 7 The second line continues from time t4, as indicated by 336. At time t4, access line 202 coupled to the selected access line 202 for the second memory cell block 2501 can be received. N The corresponding memory unit 208 N A command to read the first page of data (e.g., data from the next page). Between times t4 and t5, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 for the second memory cell block 2501. N The lower page data is used to read the first page data. At time t5, the selected access line 202 coupled to the second memory cell block 2501 can be received. N The corresponding memory unit 208 N A command to read the second page of data (e.g., data from the previous page). Between times t5 and t6, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 for the second memory cell block 2501. N The upper page data is used to read the second page data. At time t6, the selected access line 202 coupled to the second memory cell block 2501 can be received. N The corresponding memory unit 208 N A command to read the third page of data (e.g., extra page data). Between times t6 and t7, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 for the second memory cell block 2501. N The extra page data is used to read the third page data.

[0079] After time t7 as indicated by 338, multiple read operations continue for coupling to selected access line 202 for the third memory cell block 2502. N The corresponding memory unit 208 N From the selected access line 202 coupled to the third memory cell block 2502. NAfter data (e.g., lower page data, upper page data, and extra page data) is read from the corresponding memory cell, as indicated by 340, multiple read operations continue for coupling to the selected access line 202 for the first memory cell block 2500. N-1 The corresponding memory unit 208 N-1 Multiple read operations then proceed to couple to a selected access line 202 for the second memory cell block 2501. N-1 The corresponding memory unit 208 N-1 .

[0080] At time t(t-4), the selected access line 202 coupled to the third memory cell block 2502 can be received. N-1 The corresponding memory unit 208 N-1 A command to read the first page of data (e.g., the data from the next page). Between times t(t-4) and t(t-3), adjust the selected access line 202. N-1 The voltage level is used to sense the corresponding memory cell 208 of the third memory cell block 2502. N-1 The state is used to read the first page of data. At time t(t-3), the selected access line 202 coupled to the third memory cell block 2502 can be received. N-1 The corresponding memory unit 208 N-1 A command to read the second page of data (e.g., data from the previous page). Between times t(t-3) and t(t-2), this is achieved by adjusting the selected access line 202. N-1 The voltage level is used to sense the corresponding memory cell 208 for the third memory cell block 2502. N-1 The upper page data is used to read the second page data. At time t(t-2), the selected access line 202 coupled to the third memory cell block 2502 can be received. N-1 The corresponding memory unit 208 N-1 A command to read the third page of data (e.g., extra page data). Between times t(t-2) and t(t-1), this is achieved by adjusting the selected access line 202. N-1 The voltage level is used to sense the corresponding memory cell 208 of the third memory cell block 2502. N-1 The state is used to read the data on the third page.

[0081] At time t(t-1), multiple read operations are completed and a command to close the memory cell array is received. In response to the command to close the memory cell array, the currently selected access line 202... N-1 The voltage ramps up to a level sufficient to initiate coupling to the currently selected access line 202. N-1 Each corresponding memory cell 208 N-1The voltage is 334, which in turn causes the currently selected access line 202 to... N-1 The voltage is ramped down to the reference voltage of 332. Although Figure 7 Not shown, but in response to a command to shut down the memory cell array, the memory cell array is also shut down between time t(t-1) and t(t) by: ramping up the voltage of the unselected access line 202 to a voltage 334 sufficient to activate each corresponding memory cell 208 coupled to the unselected access line 202, then ramping down the unselected access line 202 to a reference voltage 332, and biasing the select lines 2150, 2151, 2152 and 2140, 2141, 2142 to disable the corresponding select gates 212 and 210 to deselect each corresponding serially connected string of memory cells 206 within the memory cell blocks 2500, 2501, 2502.

[0082] The period between time t(t-1) and t(t) is the read overhead portion, due to the absence of data reads during this period. By utilizing the single array open overhead between time t0 and t1 and the single array close overhead between time t(t-1) and t(t), instead of the array open and close overhead for each individual page read, the overall read time for multiple access lines within multiple memory cell blocks (or sub-blocks) can be reduced to read multiple pages between time t1 and t(t-1). Figure 7 In a specific instance, by not closing the array between page reads, the overall read time is reduced by an amount equal to the time required for 12 array open overheads and 12 array close overheads.

[0083] Figure 8 Timing diagrams depict another method for operating a memory used in various embodiments. Figure 8 In this context, trace 350 may represent a voltage level applied to an access line (e.g., a selected word line) connected to a memory cell (e.g., a target memory cell) selected for multiple read operations. The following discussion will refer to at least... Figure 2A The process will proceed as follows, and it will be assumed that the memory cell selected for the read operation is NAND string 2060 to 206 of memory cell block 2500. M memory cell 208 N This allows trace 350 to represent an application applied to access line 202. N The voltage level. Access line 202 N These can be called selected access lines because they contain the target memory cell, while the remaining access lines 202 can be called unselected access lines.

[0084] At time t0 (for example, from...) Figure 1The control logic 116) receives a command to open the memory cell array for multiple read operations. In response to the command to open the memory cell array, the selected access line 202... N The voltage can be increased from the reference voltage 352 to a level sufficient to initiate coupling to the selected access line 202. N Each corresponding memory cell 208 N The voltage is 354. Although Figure 8 Not shown, but in response to a command to open the memory cell array, the memory cell array can also be opened between time t0 and t1 for multiple read operations by: increasing the voltage of each unselected access line 202 from the reference voltage 352 to a voltage 352 sufficient to activate each corresponding memory cell 208 coupled to each unselected access line 202, and biasing select lines 2150 and 2140 to activate corresponding select gates 212 and 210 to select the corresponding NAND string 206 within the memory cell block 2500.

[0085] At time t1, the selected access line 202 N The voltage has reached 354. The period between time t0 and t1 is the read overhead portion, as no data is read during this period. At time t1, data can be received from the coupling to the selected access line 202. N The corresponding memory unit 208 N A command to read the first page of data (e.g., data from the next page). Between time t1 and t2, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 N The lower page data is used to read the first page data. At time t2, data can be received from the selected access line 202. N The corresponding memory unit 208 N A command to read the second page of data (e.g., data from the previous page). Between times t2 and t3, this is achieved by adjusting the selected access line 202. N The voltage level is used to sense the corresponding memory cell 208 N The upper page data is used to read the second page data. At time t3, no data is received from the selected access line 202 coupled to it. N The corresponding memory unit 208 N The command to read the third page of data (e.g., extra page data) causes a delay between times t3 and t4. This delay can be due to memory array timing and control logic inputs based on the read bandwidth of the memory array. After the delay at time t4, data can be received from the connection to the selected access line 202. N The corresponding memory unit 208 N The command to read the third page of data (e.g., additional page data) and multiple read operations as previously described continue.

[0086] During the delay between times t3 and t4, the applied pressure is maintained on the selected access line 202. N The bias voltage for unselected access line 202 (and selected lines 215 and 214). In one example, if the delay exceeds a threshold period, the memory cell array is shut down before reading the third page of data and reopened in response to shutting down the memory cell array before reading the third page of data for multiple read operations. Although Figure 8 The latency shown in the example is between times t3 and t4, but in other instances, the latency could be at other times. Furthermore, multiple latency may exist when performing multiple read operations without shutting down the memory cell array.

[0087] Figure 9 This is a flowchart of a method 400 for operating a memory according to one embodiment. Method 400 can be performed by... Figure 1 The control logic 116 of the memory device 100 is implemented and may at least partially correspond to Figure 4 The timing diagram. Method 400 can be implemented by a memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; and a plurality of access lines, wherein each of the plurality of access lines is connected to the control gate of a corresponding memory cell in each of the plurality of serially connected memory cell strings, as previously at least referenced. Figure 2C As described.

[0088] At 402, the control logic can be configured to enable the memory cell array for multiple read operations. In one example, the control logic can be configured to enable the memory cell array for multiple read operations by ramping up each of the multiple access lines (e.g., 202) from a reference voltage to a voltage sufficient to initiate each corresponding memory cell (e.g., 208) coupled to each of the multiple access lines.

[0089] At 404, the control logic can be configured to read a first page of data (e.g., a first logical page) from a corresponding memory cell coupled to a selected access line among a plurality of access lines. At 406, the control logic can be configured to read a second page of data (e.g., a second logical page) from a corresponding memory cell coupled to a selected access line. In one example, the control logic can be configured to read the second page of data after reading the first page of data without causing any unselected access lines among the plurality of access lines to ramp down to a reference voltage. In another example, the control logic can be configured to read the second page of data after reading the first page of data without causing any unselected access lines among the plurality of access lines to ramp down to a reference voltage.

[0090] At 408, the control logic can be configured to shut down the memory cell array after reading the first page of data and the second page of data. In one example, the control logic can be configured to shut down the memory cell array by ramping up each of the plurality of access lines to a voltage sufficient to activate each corresponding memory cell coupled to each of the plurality of access lines, and then ramping down each of the plurality of access lines to a reference voltage.

[0091] The first page of data and the second page of data can be stored sequentially in the page buffer (e.g., Figure 3A The corresponding latches of 240a) (e.g., 2600 to 260) M In one embodiment, the control logic may be configured to pass the first page data from the corresponding latch before reading the second page data. In another embodiment, the control logic may be configured to pass the first page data from the corresponding latch in parallel with reading the second page data. In yet another embodiment, the first page data and the second page data may be stored in parallel in a page buffer (e.g., ...). Figure 3B The corresponding multiple latches of 240b) (e.g., 262) 0,1 up to 262 0,Y and 262 M,1 up to 262 M,Y )middle.

[0092] Figure 10 This is a flowchart of a method 500 for operating a memory according to another embodiment. Method 500 can be... Figure 1 The control logic 116 of the memory device 100 is implemented and may at least partially correspond to Figure 4 and 8 The timing diagram is provided. Method 500 can be implemented by a memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; a plurality of access lines, wherein each of the plurality of access lines is connected to a control gate of a corresponding memory cell in each of the plurality of serially connected memory cell strings; and a page buffer connected to the memory cell array, as previously at least referenced. Figures 2C to 3B describe.

[0093] At 502, the control logic can be configured to open the memory cell array for multiple read operations. At 504, the control logic can be configured to read first page data from a corresponding memory cell (e.g., 208) coupled to a selected access line (e.g., 202) of the multiple access lines to latch the first page data in a page buffer (e.g., ...). Figure 3A Page buffer 240a latch 2600 to 260 M(In the middle). At 506, the control logic can be configured to pass the latched first page data out of the page buffer. At 508, the control logic can be configured to read the second page data from the corresponding memory cell coupled to the selected access line to latch the second page data in the page buffer. In one embodiment, the control logic can be configured to pass the latched first page data out of the page buffer in parallel with reading the second page data. In another embodiment, the control logic can be configured to pass the latched first page data out of the page buffer before reading the second page data. At 510, the control logic can be configured to pass the latched second page data out of the page buffer. At 512, the control logic can be configured to turn off the memory cell array.

[0094] In one embodiment, the control logic may be configured to maintain bias voltages applied to a plurality of access lines in response to a delay between latching the first page of data in a page buffer and reading the second page of data. The control logic may also be configured to shut down the memory cell array before reading the second page of data in response to a delay exceeding a threshold period, and to reopen the memory cell array for multiple read operations in response to shutting down the memory cell array before reading the second page of data.

[0095] Figures 11A to 11D This is a flowchart of a method 600 for operating a memory according to another embodiment. Method 600 can be performed by... Figure 1 The control logic 116 of the memory device 100 is implemented and may at least partially correspond to Figures 5 to 7 The timing diagram. Method 600 can be implemented within a memory device, the memory device comprising: a memory cell array including a plurality of serially connected memory cell strings; a plurality of access lines, wherein each of the plurality of access lines is connected to a control gate of a corresponding memory cell of each of the plurality of serially connected memory cell strings; a plurality of data lines, wherein each of the plurality of data lines is connected via a corresponding selection gate of a plurality of select gates to a corresponding subset of the plurality of serially connected memory cell strings; and a plurality of select lines, wherein each of the plurality of select lines is connected to a control gate of a corresponding selection gate of a plurality of select gates for a corresponding subset of the plurality of select gates, as previously at least referenced. Figure 2C As described.

[0096] like Figure 11AAs described at 602, the control logic can be configured to enable the memory cell array for multiple read operations. In one example, the control logic can be configured to enable the memory cell array for multiple read operations by: ramping up each of the plurality of access lines from a reference voltage to a voltage sufficient to activate each corresponding memory cell coupled to each of the plurality of access lines; and ramping up each of the plurality of select lines from a reference voltage to a voltage sufficient to activate each corresponding select gate coupled to each of the plurality of select lines.

[0097] At 604, the control logic can be configured to bias a first select line (e.g., 215) of a plurality of select lines to connect each of a plurality of data lines (e.g., 204) to a corresponding first cascaded memory cell string (e.g., 206) of a plurality of cascaded memory cell strings via a corresponding select gate (e.g., 212) of a plurality of select gates. At 606, the control logic can be configured to read a first page of data from a corresponding memory cell (e.g., 208) of a first selected access line (e.g., 202) of a plurality of access lines for the corresponding first cascaded memory cell string. At 608, the control logic can be configured to read a second page of data from a corresponding memory cell of a first selected access line of the corresponding first cascaded memory cell string after reading the first page of data without turning off the memory cell array.

[0098] like Figure 11B As described at 610, the control logic may be further configured to read the first page of data from the corresponding memory cell of the second selected access line among the plurality of access lines of the memory cell string coupled to the corresponding first cascaded connection after reading the second page of data from the corresponding memory cell coupled to the first selected access line, without shutting down the memory cell array. At 612, the control logic may be further configured to read the second page of data from the corresponding memory cell of the second selected access line coupled to the corresponding memory cell of the memory cell string coupled to the corresponding first cascaded connection, without shutting down the memory cell array.

[0099] like Figure 11CAs described at 614, the control logic may be further configured to bias a first select line among the plurality of select lines to disconnect each of the plurality of data lines from the corresponding first cascaded memory cell string via a corresponding select gate among the plurality of select gates. At 616, the control logic may be further configured to bias a second select line among the plurality of select lines to connect each of the plurality of data lines to the corresponding second cascaded memory cell string via a corresponding select gate among the plurality of select gates after reading a second page of data from the corresponding memory cell coupled to the first selected access line for the corresponding second cascaded memory cell string. At 618, the control logic may be further configured to read a first page of data from the corresponding memory cell coupled to the first selected access line for the corresponding second cascaded memory cell string. At 620, the control logic may be further configured to read a second page of data from the corresponding memory cell coupled to the first selected access line for the corresponding second cascaded memory cell string without turning off the memory cell array after reading the first page of data from the corresponding memory cell coupled to the first selected access line for the corresponding second cascaded memory cell string.

[0100] like Figure 11D As described at 622, the control logic can be further configured to shut down the memory cell array after all page data has been read from the corresponding memory cell of each of the plurality of access lines coupled to each of the plurality of serially connected memory cell strings. In one example, the control logic can be configured to shut down the memory cell array by: ramping up each of the plurality of access lines to a voltage sufficient to activate each corresponding memory cell coupled to each of the plurality of access lines, and then ramping down each of the plurality of access lines to a reference voltage; and ramping up each of the plurality of select lines to a voltage sufficient to activate each corresponding select gate coupled to each of the plurality of select lines, and then ramping down each of the plurality of select lines to a reference voltage.

[0101] in conclusion

[0102] Although specific embodiments have been illustrated and described herein, those skilled in the art will understand that any arrangement contemplated to achieve the same purpose may replace the specific embodiments shown. Many adaptations to the embodiments will be apparent to those skilled in the art. Therefore, this application is intended to cover any adaptations or variations of the embodiments.

Claims

1. A memory device comprising: A memory cell array comprising multiple strings of memory cells connected in series; Multiple access lines, each of the multiple access lines being connected to the control gate of a corresponding memory cell in each of the multiple series-connected memory cell strings; and The control logic is configured as follows: The memory cell array is turned on for multiple read operations by ramping up each of the plurality of access lines from a reference voltage to a voltage sufficient to initiate each corresponding memory cell coupled to each of the plurality of access lines, while keeping unselected access lines at the voltage without ramping down. Read the first page of data from the corresponding memory cell of the selected access line among the plurality of access lines coupled to the first memory cell block for the memory cell array; The second page of data is read from the corresponding memory cell of the selected access line coupled to the second memory cell block for the memory cell array; and After reading the first page of data and the second page of data, the memory cell array is turned off by sloping each of the plurality of access lines down to the reference voltage.

2. The memory device according to claim 1, further comprising: Multiple data lines, each of the multiple data lines being connected to a corresponding serially connected memory cell string in the multiple serially connected memory cell strings; and A page buffer is connected to the plurality of data lines, the page buffer including a plurality of latches for each of the plurality of data lines to store the first page data and the second page data in parallel.

3. The memory device according to claim 1, further comprising: Multiple data lines, each of the multiple data lines being connected to a corresponding serially connected memory cell string in the multiple serially connected memory cell strings; and A page buffer, connected to the plurality of data lines, includes a corresponding latch for each of the plurality of data lines to sequentially store the first page of data and the second page of data. The control logic is configured to pass the first page of data from the corresponding latch for each of the plurality of data lines before reading the second page of data.

4. The memory device according to claim 1, further comprising: Multiple data lines, each of the multiple data lines being connected to a corresponding serially connected memory cell string in the multiple serially connected memory cell strings; and A page buffer, connected to the plurality of data lines, includes a corresponding latch for each of the plurality of data lines to sequentially store the first page of data and the second page of data. The control logic is configured to pass the first page of data out from the corresponding latch for each of the plurality of data lines in parallel with reading the second page of data.

5. The memory device of claim 1, wherein the first page data includes a first logical page and the second page data includes a second logical page.

6. The memory device of claim 1, wherein the control logic is configured to read the second page data after reading the first page data without sloping the unselected access line of the plurality of access lines to the reference voltage.

7. The memory device of claim 1, wherein the control logic is configured to read the second page data after reading the first page data without sloping any unselected access line of the plurality of access lines down to the reference voltage.

8. A memory device comprising: A memory cell array comprising multiple strings of memory cells connected in series; Multiple access lines, each of the multiple access lines being connected to the control gate of a corresponding memory cell in each of the multiple series-connected memory cell strings; A page buffer, which is connected to the memory cell array; and The control logic is configured as follows: Open the memory cell array for multiple read operations; In response to a first command to read the first page of data, the first page of data is read from the corresponding memory cell of the selected access line coupled to the plurality of access lines to latch the first page of data in the page buffer; The latched first page of data is passed out from the page buffer; In response to a second command to read second page data, second page data is read from the corresponding memory cell coupled to the selected access line to latch the second page data in the page buffer; The latched second page of data is passed out from the page buffer; and The memory cell array is turned off, wherein after reading the first page of data, the first page of data and the second page of data are read from the corresponding memory cell coupled to the selected access line without causing the selected access line to slope down to a reference voltage.

9. The memory device of claim 8, wherein the control logic is configured to maintain a bias voltage applied to the plurality of access lines in response to a delay between latching the first page data in the page buffer and reading the second page data.

10. The memory device of claim 9, wherein the control logic is configured to: In response to the delay exceeding a threshold period, the memory cell array is shut down before reading the second page of data; and The memory cell array is reopened in response to being shut down before reading the second page of data for use in multiple read operations.

11. The memory device of claim 8, wherein the control logic is configured to pass the latched first page data out of the page buffer in parallel with reading the second page data.

12. The memory device of claim 8, wherein the control logic is configured to pass the latched first page data from the page buffer before reading the second page data.

13. A memory device comprising: A memory cell array comprising multiple strings of memory cells connected in series; Multiple access lines, each of the multiple access lines being connected to the control gate of a corresponding memory cell in each of the multiple series-connected memory cell strings; Multiple data lines, each of the multiple data lines being connected via a respective select gate of a plurality of select gates to a corresponding subset of the plurality of serially connected memory cell strings; Multiple selection lines, each of the multiple selection lines being connected to the control gate of a corresponding selection gate among the multiple selection gates for a corresponding subset of the multiple selection gates; and The control logic is configured as follows: Open the memory cell array for multiple read operations; A first select line among the plurality of select lines is biased to connect each of the plurality of data lines to a corresponding first serially connected memory cell string among the plurality of serially connected memory cell strings via a corresponding select gate among the plurality of select gates. Read the first page of data from the corresponding memory cell of the first selected access line among the plurality of access lines coupled to the respective first cascaded connection of the memory cell string; and After reading the first page of data, a second page of data is read from the corresponding memory cell of the first selected access line coupled to the corresponding first cascaded memory cell string without shutting down the memory cell array.

14. The memory device of claim 13, wherein the control logic is configured to: After reading the second page of data from the corresponding memory cell coupled to the first selected access line, the first page of data is read from the corresponding memory cell of the second selected access line among the plurality of access lines coupled to the respective first cascaded memory cell strings without shutting down the memory cell array; and After reading the first page of data from the corresponding memory cell coupled to the second selected access line, the second page of data is read from the corresponding memory cell coupled to the second selected access line for the corresponding first cascaded connection of the memory cell string without shutting down the memory cell array.

15. The memory device of claim 13, wherein the control logic is configured to: The first select line of the plurality of select lines is biased to disconnect each of the plurality of data lines from the corresponding first serially connected memory cell string via the respective select gate of the plurality of select gates; After reading the second page of data from the corresponding memory cell coupled to the first selected access line, the second select line of the plurality of select lines is biased to connect each of the plurality of data lines to the corresponding second serially connected string of memory cells via the corresponding select gate of the plurality of select gates. Read the first page of data from the corresponding memory cell of the first selected access line coupled to the corresponding second cascaded connection of the memory cell string; and After reading the first page of data from the corresponding memory cell coupled to the first selected access line of the memory cell string for the corresponding second cascade connection, the second page of data is read from the corresponding memory cell coupled to the first selected access line of the memory cell string for the corresponding second cascade connection without shutting down the memory cell array.

16. The memory device of claim 13, wherein the control logic is configured to open the memory cell array for a plurality of read operations by: Each of the plurality of access lines is ramped up from a reference voltage to a voltage sufficient to activate each corresponding memory cell coupled to each of the plurality of access lines; and Each of the plurality of select lines is ramped up from the reference voltage to a voltage sufficient to activate each corresponding select gate coupled to each of the plurality of select lines.

17. The memory device of claim 13, wherein the control logic is configured to shut down the memory cell array after all page data has been read from a corresponding memory cell on each of the plurality of access lines coupled to each of the plurality of serially connected memory cell strings.

18. The memory device of claim 17, wherein the control logic is configured to shut down the memory cell array by: Each of the plurality of access lines is ramped up to a voltage sufficient to activate each corresponding memory cell coupled to each of the plurality of access lines, and then each of the plurality of access lines is ramped down to a reference voltage; and Each of the plurality of select lines is ramped up to a voltage sufficient to activate each corresponding select gate coupled to each of the plurality of select lines, and then each of the plurality of select lines is ramped down to the reference voltage.

19. The memory device of claim 13, wherein the memory cell array comprises a three-dimensional NAND memory array.

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