Semiconductor structure and manufacturing method

Abstract

This invention relates to a semiconductor structure and a method for manufacturing the same. The method for manufacturing the semiconductor structure includes: forming a thermoelectric structure on a substrate; forming a dielectric layer on the substrate to cover the thermoelectric structure; forming a first photoresist pattern on the dielectric layer, the first photoresist pattern including a first opening; using the first photoresist pattern as an etching mask and etching the dielectric layer to remove the dielectric layer located below the first opening and expose an exposed area of ​​the substrate; removing the first photoresist pattern; conformally forming a protective layer on the dielectric layer and the exposed area; forming a second photoresist pattern on the protective layer; the second photoresist pattern including a second opening, the second opening being smaller than the first opening; using the second photoresist pattern as an etching mask and etching the protective layer to remove the protective layer located below the second opening. This invention avoids the etching process from damaging the thermoelectric structure containing thermoelectric materials.

Description

Technical Field

[0001] This invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor structure and a method for manufacturing the same that can improve yield and reliability. Background Technology

[0002] Generally, thermoelectric sensors sense temperature using thermoelectric materials that generate a thermoelectric effect. Unlike using metallic conductors with different free electron densities as thermoelectric materials, semiconductor materials with higher carrier sensitivity are currently frequently used. Therefore, the performance of the thermal sensor can be adjusted by selecting different resistance values ​​for the thermoelectric materials.

[0003] However, current thermoelectric sensors use cavities to suspend the thermoelectric material above a substrate. Because the thermoelectric material is suspended above the substrate through the cavity, and the cavity itself has excellent thermal insulation properties, the temperature sensed by the thermoelectric material can be completely converted into an electrical signal, thus reducing the problem of temperature distortion caused by thermal conduction.

[0004] Therefore, known methods for manufacturing thermoelectric sensors employ etching processes to create cavities. However, during etching, the thermoelectric material within the sensor, or other layers surrounding it, is frequently damaged, leading to a decrease in overall sensor performance or even sensor failure. Thus, while existing semiconductor structures have gradually met their intended applications, they are not entirely satisfactory in every aspect. Therefore, several challenges remain regarding semiconductor structures suitable for subsequent fabrication into thermoelectric sensors and their manufacturing methods. Summary of the Invention

[0005] In view of the above problems, some embodiments disclosed in this invention use a two-stage etching process to form a protective layer that can effectively protect the multilayer structure located on the substrate, thereby avoiding the etching process from damaging the thermoelectric structure containing thermoelectric materials, and thus obtaining a semiconductor structure with good reliability.

[0006] According to some embodiments, a method for manufacturing a semiconductor structure is provided. The aforementioned method for manufacturing a semiconductor structure includes: forming a thermoelectric structure on a substrate; forming a dielectric layer on the substrate such that the dielectric layer covers the thermoelectric structure; forming a first photoresist pattern on the dielectric layer, the first photoresist pattern including a first opening; using the first photoresist pattern as an etching mask, and etching the dielectric layer to remove the dielectric layer located below the first opening and expose an exposed area of ​​the substrate; removing the first photoresist pattern; conformally forming a protective layer on the dielectric layer and the exposed area; forming a second photoresist pattern on the protective layer; the second photoresist pattern including a second opening, the second opening being smaller than the first opening; using the second photoresist pattern as an etching mask, and etching the protective layer to remove the protective layer located below the second opening.

[0007] According to some embodiments, a semiconductor structure is provided. The aforementioned semiconductor structure includes a substrate, a thermoelectric structure, a dielectric layer, and a protective layer; the thermoelectric structure is disposed on the substrate; the dielectric layer is disposed on the substrate and exposes an exposed area of ​​the substrate. The dielectric layer covers the thermoelectric structure; the protective layer is disposed on the dielectric layer and covers a portion of the exposed area of ​​the substrate.

[0008] This invention discloses a method for manufacturing a semiconductor structure with good reliability by using a two-stage etching process, that is, using photoresist patterns with openings of different sizes as etching masks, to form a protective layer that can effectively protect multilayer structures such as insulating layers, first dielectric layers, second dielectric layers, and third dielectric layers located on a substrate. In some embodiments, since the area projected onto the substrate by the first photoresist pattern with a larger opening size (i.e., a smaller coverage area) is smaller than the area projected onto the substrate by the second photoresist pattern with a smaller opening size (i.e., a larger coverage area), the protective layer can not only protect all features corresponding to the first photoresist pattern, but also further prevent etching damage that is prone to occur in adjacent substrate areas by being adjacent to the inclined side surface and disposed on the substrate.

[0009] The semiconductor structures of some embodiments disclosed in this invention can be applied to various types of sensing devices. To make the features and advantages disclosed in this invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0010] The following detailed description, in conjunction with the accompanying drawings, will provide a better understanding of the embodiments disclosed in this invention. It is worth noting that, according to industry standard practice, some features may not be drawn to scale. In fact, for clarity of discussion, the dimensions of different features may be increased or decreased.

[0011] Figures 1 to 11These are cross-sectional schematic diagrams illustrating the formation of semiconductor structures at various stages, based on some embodiments disclosed in this invention; and

[0012] Figures 12 to 15 This is a cross-sectional schematic diagram illustrating further processing of a semiconductor structure according to some embodiments disclosed in the present invention.

[0013] Figures 16 to 17 The present invention discloses some embodiments, and respectively illustrates schematic diagrams and top views of performing further processes on the semiconductor structure.

[0014] Explanation of icon numbers:

[0015] 1: Semiconductor Structure

[0016] 100: Substrate

[0017] 200: Insulation layer

[0018] 300: Thermoelectric structure

[0019] 310: Thermoelectric material layer

[0020] 320: Thermoelectric insulation layer

[0021] 410: First dielectric layer

[0022] 420: Second dielectric layer

[0023] 430: Third dielectric layer

[0024] 500: First photoresist pattern

[0025] 600: Protective layer

[0026] 700: Second photoresist pattern

[0027] 800: Contact plug

[0028] 910: First Etching Process

[0029] 920: Trench

[0030] 930: Second Etching Process

[0031] 940: Cavity

[0032] α: included angle

[0033] CT: Through-hole

[0034] OP1: First opening

[0035] OP2: Second opening

[0036] S: Inclined side surface

[0037] T1: First thickness

[0038] T2: Second thickness

[0039] W1: First width

[0040] W2: Second width

[0041] W3: Width Difference Detailed Implementation

[0042] The following disclosure provides many different embodiments or examples for implementing various components of the provided semiconductor structure. Specific examples of each component and its configuration are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to limit the scope of the invention. For instance, if the description mentions a first component formed on top of a second component, it may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components so that they are not in direct contact. Furthermore, in embodiments described in different figures and descriptions, the same or similar component symbols are used to identify the same or similar components. Additionally, the disclosed embodiments may repeat reference numerals and / or letters in different examples. Such repetition is for brevity and clarity, and not to indicate a relationship between the different embodiments and / or forms discussed. It is understood that additional operations may be provided before, during, and after the method, and some described operations may be replaced or deleted for other embodiments of the method.

[0043] Reference Figure 1A substrate 100 is provided, and an insulating layer 200 is formed on the substrate 100. In some embodiments, the substrate 100 may be a wafer, such as a silicon (Si) wafer; it may be a bulk semiconductor or a semiconductor-on-insulation (SOI) substrate. Generally, an SOI substrate comprises a layer of semiconductor material formed on the insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or a similar material, providing an insulating layer on a silicon or glass substrate. Other types of substrates 100 include, for example, multilayer or gradient substrates. In some embodiments, substrate 100 may be an elemental semiconductor comprising silicon or germanium; substrate 100 may also be a compound semiconductor comprising, for example, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide, but is not limited thereto; substrate 100 may also be an alloy semiconductor comprising, for example, silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium arsenide phosphide (GaInAsP), or any combination thereof, but the present invention is not limited thereto. In some embodiments, substrate 100 may be a doped or undoped semiconductor substrate. In some embodiments, substrate 100 may be a silicon substrate.

[0044] In some embodiments, an insulating layer 200 may be optionally formed on the substrate 100 by a deposition process. In some embodiments, the deposition process may be or may include a chemical vapor deposition (CVD) process or a thermal oxidation process. The aforementioned CVD process may be low-pressure chemical vapor deposition (LPCVD), low-temperature chemical vapor deposition (LTCVD), rapid thermal chemical vapor deposition (RTCVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD) of atomic layer chemical vapor deposition, or other suitable CVD processes.

[0045] In some embodiments, the insulating layer 200 may be or may comprise oxides, nitrides, oxynitrides, combinations thereof, or any other suitable insulating material, but the present invention is not limited thereto. For example, the insulating layer 200 may be silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the insulating layer 200 may be silicon nitride. In some embodiments, the insulating layer 200 serves as an electrical connection to the isolating substrate 100 and other layers, components, or features subsequently formed on top of the insulating layer 200.

[0046] Reference Figure 2 A thermoelectric structure 300 is formed on the substrate 100, specifically on the insulating layer 200, such that the insulating layer 200 is located between the substrate 100 and the thermoelectric structure 300. In some embodiments, the thermoelectric structure 300 is a structure capable of generating a thermoelectric effect. In some embodiments, the thermoelectric structure 300 is formed in an island-like manner on the insulating layer 200. In some embodiments, different numbers of thermoelectric structures 300 can be provided in the subsequently formed dielectric layer according to the user's needs and the expected size of the thermoelectric sensing unit. In some embodiments, multiple thermoelectric structures 300 can be disposed on the insulating layer 200 at substantially the same distance interval. In some embodiments, such as Figure 2 The number of thermoelectric structures 300 shown should not be used to limit the number of thermoelectric structures disclosed in this invention.

[0047] In some embodiments, the thermoelectric structure 300 may include a thermoelectric material layer 310 and a thermoelectric insulating layer 320. In some embodiments, the thermoelectric material layer 310 may be or may include aluminum, chromium, gold, copper, platinum, nickel, bismuth, antimony, doped silicon such as n-type polysilicon or p-type polysilicon, combinations thereof, or other suitable thermoelectric materials. In some embodiments, the thermoelectric material layer 310 may be n-type polysilicon because n-type polysilicon has an extremely low Seebeck coefficient. In some embodiments, the resistance value of the thermoelectric material layer 310 is adjusted by the type and concentration of dopant, thereby controlling the thermoelectric effect of the subsequently formed semiconductor structure.

[0048] In some embodiments, the thermoelectric insulating layer 320 may comprise the same or different materials as the insulating layer 200. In some embodiments, the thermoelectric insulating layer 320 may be or comprise oxides, nitrides, oxynitrides, combinations thereof, or any other suitable insulating material, but the invention is not limited thereto. For example, the thermoelectric insulating layer 320 may be silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the thermoelectric insulating layer 320 may be silicon nitride. In some embodiments, the process for forming the thermoelectric insulating layer 320 may be the same as or different from the process for forming the insulating layer 200. In some embodiments, the thermoelectric insulating layer 320 covers the thermoelectric material layer 310, and the thermoelectric insulating layer 320 exposes a portion of the insulating layer 200.

[0049] In detail, in some embodiments, a thermoelectric material is formed on the insulating layer 200, followed by the formation of a patterned photoresist pattern on the thermoelectric material. The thermoelectric material is then etched using the patterned photoresist pattern as an etching mask to form a thermoelectric material layer 310. The patterned photoresist pattern layer used to form the thermoelectric material layer 310 is then removed. A thermoelectric insulating material is then formed on the thermoelectric material layer 310, for example, conformally formed on both the thermoelectric material layer 310 and the insulating layer 200. Next, a patterned photoresist pattern is formed on the thermoelectric insulating material, and the thermoelectric insulating material is etched using the patterned photoresist pattern as an etching mask to form a patterned thermoelectric insulating material, i.e., a thermoelectric insulating layer 320. Similarly, the patterned photoresist pattern layer used to form the thermoelectric insulating layer 320 is removed. In some embodiments, the thermoelectric insulating layer 320 covers the thermoelectric material layer 310 and exposes a portion of the insulating layer 200.

[0050] Reference Figure 3A first dielectric layer 410 is formed on the substrate 100 to cover the thermoelectric structure 300. Specifically, the first dielectric layer 410 is formed on the insulating layer 200 and the thermoelectric structure 300. In other words, the thermoelectric structure 300 may be disposed in the first dielectric layer 410. In some embodiments, the first dielectric layer 410 may be or may contain oxides, nitrides, oxynitrides, combinations thereof, or any other suitable dielectric material, but the present invention is not limited thereto. For example, the first dielectric layer 410 may be silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the first dielectric layer 410 may be silicon oxide. In some embodiments, the first dielectric layer 410 may serve as a functional layer in a subsequently formed semiconductor structure, for example, as an interlayer dielectric layer or an insulating layer.

[0051] Reference Figure 4 A second dielectric layer 420 and a third dielectric layer 430 may be further disposed on the first dielectric layer 410. In some embodiments, other dielectric layers may be further included. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may serve as functional layers with the same or different functions as the first dielectric layer 410 in a subsequently formed semiconductor structure. In some embodiments, the thermoelectric structure 300 may be disposed simultaneously in the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430, or may be disposed only in the first dielectric layer 410 and the second dielectric layer 420. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may contain the same or different materials as the first dielectric layer 410. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may be silicon oxide. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may be formed with the first dielectric layer 410 using the same or different processes. In some embodiments, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 may be formed in the same or different processes. In some embodiments, the second dielectric layer 420 and the third dielectric layer 430 may be omitted.

[0052] For the sake of detailed explanation, the following description assumes the presence of a first dielectric layer 410, a second dielectric layer 420, and a third dielectric layer 430. In the following text, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 will be collectively referred to as "dielectric layers".

[0053] Reference Figure 5A first photoresist pattern 500 is formed on the aforementioned dielectric layer, and the first photoresist pattern 500 includes a first opening OP1. In some embodiments, the first photoresist pattern 500 is formed on the third dielectric layer 430, and a portion of the third dielectric layer 430 is exposed through the first opening OP1. In some embodiments, the first photoresist pattern 500 covers the thermoelectric material layer 310 and the thermoelectric insulating layer 320; in other words, the thermoelectric material layer 310 and the thermoelectric insulating layer 320 are located below the first photoresist pattern 500. In some embodiments, the thermoelectric material layer 310 and the thermoelectric insulating layer 320 are not disposed below the first opening OP1, thus maintaining the complete structure of the thermoelectric material layer 310 and the thermoelectric insulating layer 320.

[0054] In some embodiments, the first photoresist pattern 500 may be or may include oxides, nitrides, or combinations thereof. In some embodiments, the step of forming the first photoresist pattern 500 on the third dielectric layer 430 may further include: depositing a first photoresist pattern material layer, such as an oxide layer, on the third dielectric layer 430; forming a photoresist layer on the aforementioned first photoresist pattern material layer; exposing the photoresist layer as needed to obtain a patterned photoresist layer; and using the patterned photoresist layer as an etching mask to etch the first photoresist pattern material layer to form a patterned first photoresist pattern material layer, thereby obtaining the first photoresist pattern 500 on the third dielectric layer 430. It is understood that suitable photoresist pattern materials can be matched according to process conditions, and therefore the embodiments disclosed in this invention are not limited thereto.

[0055] Reference Figure 6 Using a first photoresist pattern 500 as an etching mask, an insulating layer 200 and a dielectric layer are etched to remove the insulating layer 200 and the dielectric layer located below the first opening OP1 of the first photoresist pattern 500, exposing an exposed area of ​​the substrate 100. That is, the insulating layer 200, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 located below the first opening OP1 of the first photoresist pattern 500 are removed, exposing a portion of the substrate 100. In some embodiments, the dielectric layer is etched to form a plurality of dielectric structures disposed in an island-like pattern on the substrate 100. In some embodiments, vias are formed between the plurality of dielectric structures, for example, tapered vias with inclined sidewalls or vias with vertical sidewalls.

[0056] In some embodiments, the substrates 100 exposed by the first photoresist pattern 500 have a spacing of a first width W1, and the first width W1 corresponds to the width of the first opening OP1. In some embodiments, the shape of the first opening OP1 can be any suitable shape, for example, a square, rectangle, polygon, or irregular shape, and the first width W1 is only the first opening OP1 within such a shape. Figure 5The examples shown in the cross-sectional views are not intended to limit this disclosure.

[0057] Reference Figure 7 The first photoresist pattern 500 is removed by an etching process. In some embodiments, the etching process may be or may include dry etching, wet etching, or other etching methods (e.g., reactive ion etching). In some embodiments, the etching process may also be purely chemical etching (plasma etching), purely physical etching (ion polishing), or a combination thereof. In some embodiments, a dry etching process is used to remove the first photoresist pattern 500, and a portion of the dielectric layer and a portion of the insulating layer 200 are removed simultaneously; that is, the insulating layer 200, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 are removed at the same time as the first photoresist pattern 500. In some embodiments, the area of ​​the removed third dielectric layer 430 may be larger than the area of ​​the removed second dielectric layer 420; the area of ​​the removed second dielectric layer 420 may be larger than the area of ​​the removed first dielectric layer 410; and the area of ​​the removed first dielectric layer 410 may be larger than the area of ​​the removed insulating layer 200. In some embodiments, the insulating layer 200, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 may have a trapezoidal shape that is narrower at the top and wider at the bottom.

[0058] In detail, in some embodiments, the parameters of the dry etching process are adjusted such that the area of ​​the top surface of the dielectric layer is smaller than the area of ​​the bottom surface of the dielectric layer. In some embodiments, the dielectric layer has a sloped side surface S. In some embodiments, the dielectric layer has an area that gradually decreases along the direction away from the substrate 100. For example, the area of ​​the top surface of the third dielectric layer 430 is smaller than the area of ​​the bottom surface of the first dielectric layer 410, and the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430 share sloped side surfaces S with substantially the same slope. In some embodiments, the smaller angle α between the aforementioned sloped side surface S and the top surface of the dielectric layer may be 45 degrees to 85 degrees, but the present invention is not limited thereto. In some embodiments, the smaller angle α may be substantially 90 degrees. In some embodiments, the dielectric layer and the insulating layer 200 share a sloped side surface S, and the smaller angle α between the aforementioned sloped side surface S and the top surface of the dielectric layer may be 45 degrees to 85 degrees.

[0059] In some embodiments, it can be achieved through, as shown in Figure 6 and Figure 7The contents shown are used to form multiple island-shaped dielectric structures. The maximum area of ​​each of the aforementioned multiple island-shaped dielectric structures, for example, is substantially the same as the area of ​​the bottom surface of the dielectric structure as the aforementioned first photoresist pattern 500; however, this invention is not limited thereto. In other embodiments, multiple island-shaped dielectric structures can be formed by adjusting parameters such as the etch selectivity in the etching process. The minimum area of ​​each of the aforementioned multiple island-shaped dielectric structures, for example, is substantially the same as the area of ​​the top surface of the dielectric structure as the aforementioned first photoresist pattern 500.

[0060] Reference Figure 8 A protective layer 600 is compliantly formed on the exposed areas of the dielectric layer and the substrate 100 to cover the exposed areas of the dielectric layer and the substrate 100. In some embodiments, the protective layer 600 is formed on the top surface of the exposed area of ​​the substrate 100, on the inclined side surface S of the dielectric layer and the insulating layer 200, and on the top surface of the dielectric layer; that is, the protective layer 600 is compliantly formed on the dielectric layer. In some embodiments, the protective layer 600 is formed by the aforementioned deposition process.

[0061] In this invention disclosure, "protective layer" refers to a layer that has superior resistance to etching by a particular etchant and / or etching gas, i.e., a layer with a low etch selectivity. In some embodiments, the protective layer 600 may be or may contain oxides, nitrides, oxynitrides, combinations thereof, or any other suitable material, but this invention disclosure is not limited thereto. For example, the protective layer 600 may be silicon nitride.

[0062] It should be noted that, because the dielectric layer and insulating layer 200 have inclined side surfaces S, and the inclined side surfaces S and the top surface of the dielectric layer have a specific angle of 45 degrees to 85 degrees, when the protective layer 600 is compliantly formed on the dielectric layer, the thickness of the protective layer 600 formed on the inclined side surface S may still be slightly smaller than the thickness of the protective layer 600 formed on the top surface of the dielectric layer and substrate 100, but the thickness of the protective layer 600 formed on the inclined side surface S is very close to the thickness of the protective layer 600 formed on the top surface of the dielectric layer and substrate 100. Therefore, during subsequent multiple etching processes to form a thermoelectric sensing device, the protective layer 600 can effectively protect the dielectric layer and insulating layer 200 located under the inclined side surface S from damage by the etching process.

[0063] Reference Figure 9A second photoresist pattern 700 is formed on the protective layer 600, and the second photoresist pattern 700 includes a second opening OP2. In some embodiments, the second opening OP2 of the second photoresist pattern 700 is smaller than the first opening OP1 of the first photoresist pattern 500. In some embodiments, the second photoresist pattern 700 covers a portion of the protective layer 600 and exposes another portion of the protective layer 600. In some embodiments, the second opening OP2 exposes a portion of the protective layer 600, and the area of ​​the protective layer 600 exposed through the second opening OP2 is smaller than the area of ​​the substrate 100 exposed through the first opening OP1. In some embodiments, the second photoresist pattern 700 covers a portion of the exposed area of ​​the substrate 100. In some embodiments, the second photoresist pattern 700 also covers the thermoelectric material layer 310 and the thermoelectric insulating layer 320; in other words, the thermoelectric material layer 310 and the thermoelectric insulating layer 320 are also located below the second photoresist pattern 700.

[0064] In some embodiments, the second photoresist pattern 700 may contain the same or different materials as the first photoresist pattern 500. In some embodiments, the second photoresist pattern 700 may be or may contain oxides, nitrides, or combinations thereof. In some embodiments, the process for forming the second photoresist pattern 700 may be the same or different from the process for forming the first photoresist pattern 500. It is understood that suitable photoresist pattern materials and processes can be matched according to process conditions, therefore the embodiments disclosed in this invention are not limited thereto.

[0065] It should be noted that the area of ​​the second photoresist pattern 700 covering the protective layer 600 is larger than the area of ​​the first photoresist pattern 500 covering the dielectric layer. In other words, all features previously located below the first photoresist pattern 500 are now located below the second photoresist pattern 700. In some embodiments, the area of ​​the first photoresist pattern 500 projected onto the substrate 100 is located within the area of ​​the second photoresist pattern 700 projected onto the substrate 100; that is, the area of ​​the second photoresist pattern 700 projected onto the substrate 100 covers the area of ​​the first photoresist pattern 500 projected onto the substrate 100.

[0066] It should also be noted that in some embodiments, the second photoresist pattern 700 covers the inclined side surface S and the top surface of the dielectric layer, and covers a portion of the protective layer 600 adjacent to the inclined side surface S and located on the substrate 100. That is, in addition to covering all the features previously located below the first photoresist pattern 500, the second photoresist pattern 700 further covers a portion of the protective layer 600 adjacent to the inclined side surface S and located on the substrate 100. Therefore, the aforementioned portion of the protective layer 600 adjacent to the inclined side surface S and located on the substrate 100 can be retained. In other words, the protective layer 600 may include an extension disposed on the exposed portion of the substrate 100 to further protect the substrate 100 from damage by subsequent processes. For example, in some embodiments disclosed in this invention, since the aforementioned portion of the protective layer 600 adjacent to the inclined side surface S is still disposed on the substrate 100, when subsequent etching processes are performed to form a thermoelectric sensing device, even if the etchant and / or etching gas tend to concentrate near the substrate 100, making the features near the substrate 100 more susceptible to damage, the aforementioned portion of the protective layer 600 can still effectively protect the features near the substrate 100 from damage by the etching process.

[0067] Reference Figure 10 The second photoresist pattern 700 is used as an etching mask, and the protective layer 600 is etched to remove the protective layer 600 located below the second opening OP2 of the second photoresist pattern 700. In some embodiments, the substrates 100 exposed by the second photoresist pattern 700 have a spacing of a second width W2, and the aforementioned second width W2 corresponds to the width of the second opening OP2. In some embodiments, since the semiconductor structure disclosed in some embodiments of the present invention can be subsequently processed into a thermoelectric sensing device or a thermoelectric sensing unit, the second width W2 can be the spacing distance between a plurality of subsequently processed thermoelectric sensing units. That is, the size of the thermoelectric sensing unit can be defined by the second width W2, that is, by the second opening OP2.

[0068] In some embodiments, since there is a width difference W3 between the second width W2 and the first width W1, the width of the aforementioned portion of the protective layer 600 adjacent to the inclined side surface S and located on the substrate 100 may be substantially the same as the width difference W3.

[0069] Reference Figure 11The second photoresist pattern 700 is removed by an etching process to obtain the semiconductor structure 1 of some embodiments disclosed in this invention. In some embodiments, the process of removing the second photoresist pattern 700 may be the same as or different from the process of removing the first photoresist pattern 500. In some embodiments, the second photoresist pattern 700 is removed while retaining the features located below the second photoresist pattern 700. In some embodiments, after removing the second photoresist pattern 700, a protective layer 600 may be disposed on the substrate 100, the insulating layer 200, and the dielectric layer, exposing a portion of the substrate 100. That is, the protective layer 600 may be disposed on the substrate 100 adjacent to the inclined side surface S corresponding to the width difference W3, and also disposed on the inclined side surface S of the insulating layer 200, the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430, as well as on the top surface of the third dielectric layer 430, exposing a portion of the substrate 100. In some embodiments, a portion of the protective layer 600 may extend along the top surface of the substrate 100 in a direction away from the thermoelectric structure comprising the thermoelectric material layer 310 and the thermoelectric insulating layer 320. In some embodiments, the width of the protective layer 600 extending in the direction away from the thermoelectric structure corresponds to the aforementioned width difference W3.

[0070] Following the above, a cross-sectional schematic diagram of the further processes performed on semiconductor structure 1 is further described below.

[0071] Reference Figure 12 A through-hole CT is formed, which penetrates the protective layer 600 and exposes the thermoelectric structure containing the thermoelectric material layer 310 and the thermoelectric insulation layer 320.

[0072] Reference Figure 13 Conductive material is filled into the via CT to form a contact plug 800 that contacts the thermoelectric structure comprising the thermoelectric material layer 310 and the thermoelectric insulating layer 320. In some embodiments, the contact plug 800 is disposed in the dielectric layers, that is, the contact plug 800 is disposed in the first dielectric layer 410, the second dielectric layer 420, and the third dielectric layer 430. In some embodiments, the conductive material may be or may include a metallic material, a conductive material, or other suitable conductive material. In some embodiments, a planarization process such as chemical mechanical polishing (CMP) and / or a process for forming a metal layer may be further performed.

[0073] Reference Figure 14A first etching process 910 is performed on the semiconductor structure 1 of some embodiments disclosed in this invention to form trenches 920 on the substrate 100 exposed by the protective layer 600, thereby obtaining the semiconductor structure 2. In some embodiments, the trenches 920 are disposed in another portion of the exposed area of ​​the substrate 100. In some embodiments, the trenches 920 are disposed on both sides of a thermoelectric structure including a thermoelectric material layer 310 and a thermoelectric insulating layer 320. In some embodiments, the trenches 920 may be disposed in pairs on both sides of the thermoelectric structure. In some embodiments, the first etching process 910 may be the same as or different from the aforementioned etching process. In some embodiments, after performing the first etching process 910, the sidewalls of the trenches 920 are substantially aligned with the side surfaces of the protective layer 600 located on the exposed area of ​​the substrate 100; in other words, the substrate 100 is protected from damage by the first etching process 910 by the extension of the protective layer 600 located on the exposed area of ​​the substrate 100.

[0074] In some embodiments, since the thickness of the protective layer 600 located on the inclined side surface S is close to the thickness of the protective layer 600 located on the top surface of the dielectric layer and the substrate 100, the protective layer 600 can effectively prevent the first etching process 910 from damaging the features below the protective layer 600. Figure 14 As shown, since a protective layer 600 with a first thickness T1 is provided on the substrate 100, and the protective layer 600 has a different etch selectivity than the substrate 100, features located below the protective layer 600 can still be protected from damage even if a trench with a second thickness T2 has been formed on the exposed substrate 100. Furthermore, in some embodiments, since the protective layer 600 includes a portion adjacent to the inclined side surface S and located on the substrate 100, the protective layer 600 can effectively protect features located below it even if the etchant and / or etching gas used in the first etching process 910 may concentrate near the substrate 100 due to gravity or density.

[0075] Reference Figures 15 to 17 In a second etching process 930, along the direction from the protective layer 600 toward the substrate 100 and through the aforementioned trenches 920, a cavity 940 is formed on the exposed substrate 100, thereby obtaining a semiconductor structure 3 capable of serving as a thermoelectric sensing device. In some embodiments, the cavity 940 is located below the thermoelectric structure comprising the thermoelectric material layer 310 and the thermoelectric insulating layer 320. In some embodiments, the cavity 940 allows the pairs of aforementioned trenches 920 to communicate with each other. In some embodiments, the cavity 940 can define the size of the thermoelectric sensing unit. In some embodiments, the second etching process 930 may be the same as or different from the aforementioned etching process. Similarly, even with the further execution of the second etching process 930, the protective layer 600 can still effectively protect the features located below the protective layer 600.

[0076] In some embodiments, the second etching process 930 is an anisotropic etching process. In some embodiments, since the semiconductor structure 3 disclosed in this invention includes a cavity 940, the semiconductor structure 3 disclosed in this invention can be used as such Figure 16 The illustrated float-arm supported thermoelectric sensing device. Specifically, because the semiconductor structure 3 has trenches 920 and cavities 940, the thermoelectric structure 300 disposed on the insulating layer 200 can be suspended above the cavity 940, thus serving as a float-arm supported thermoelectric sensing device. In some embodiments, the number of thermoelectric sensing units that can be present in one float arm of the float-arm supported thermoelectric sensing device can be determined based on the number of thermoelectric structures included in the semiconductor structure 3. In some embodiments, the float-arm supported thermoelectric sensing device may include one float arm, two float arms, four float arms, or eight float arms; however, the present invention is not limited thereto. Figure 17 As shown, the float-arm supported thermoelectric sensing device may include only one float arm, and the aforementioned float arm may include multiple parallel semiconductor structures 3. In some embodiments, if the float-arm supported thermoelectric sensing device may include four float arms, then when viewed from above, the aforementioned four float arms may be arranged in an X-shape.

[0077] In summary, according to some embodiments disclosed in this invention, the present invention discloses a method for manufacturing a semiconductor structure with good reliability by using a two-stage etching process, that is, using photoresist patterns with openings of different sizes as etching masks for etching, to form a protective layer that can effectively protect multilayer structures such as insulating layers, first dielectric layers, second dielectric layers, and third dielectric layers located on a substrate. In some embodiments, since the area of ​​the first photoresist pattern with a larger opening size (i.e., a smaller coverage area) projected onto the substrate is smaller than the area of ​​the second photoresist pattern with a smaller opening size (i.e., a larger coverage area) projected onto the substrate, the protective layer can not only protect all features corresponding to the area below the first photoresist pattern, but also further avoid etching damage that is prone to occur near the substrate by being adjacent to the inclined side surface and disposed on the substrate.

[0078] While the embodiments and advantages of this invention have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of this disclosure. Furthermore, the scope of protection disclosed in this invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of this specification. Anyone skilled in the art can understand, from the disclosure of some embodiments of this invention, current or future developed processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps, as long as they can perform substantially the same function or obtain substantially the same results in the embodiments described herein, and can be used according to some embodiments disclosed in this invention. Therefore, the scope of protection disclosed in this invention includes the aforementioned processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection disclosed in this invention also includes combinations of various claim claims and embodiments.

[0079] The foregoing outlines several embodiments to enable those skilled in the art to better understand the viewpoints of the disclosed embodiments. Those skilled in the art should understand that they can design or modify other processes and structures based on the disclosed embodiments to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the invention.

Claims

1. A method of manufacturing a semiconductor structure, characterized by, The manufacturing method comprises: forming a thermoelectric structure on a substrate; forming a dielectric layer on the substrate, such that the dielectric layer covers the thermoelectric structure; forming a first photoresist pattern on the dielectric layer, the first photoresist pattern comprising a first opening; using the first photoresist pattern as an etching mask, and etching the dielectric layer, such that the dielectric layer located under the first opening is removed and an exposed region of the substrate is exposed; removing the first photoresist pattern; compliantly forming a protective layer on the top surface and side surface of the dielectric layer and the top surface of the exposed region; forming a second photoresist pattern on the protective layer, the second photoresist pattern comprising a second opening, and the second opening being smaller than the first opening; using the second photoresist pattern as an etching mask, and etching the protective layer, such that the protective layer located under the second opening is removed, wherein the protective layer covers a portion of the exposed region of the substrate; forming a pair of trenches in another portion of the exposed region, and the pair of trenches are disposed on two sides of the thermoelectric structure; and forming a cavity in the substrate, such that the sidewalls of the pair of trenches and the side surface of the protective layer located on the exposed region are substantially aligned, the cavity is located under the thermoelectric structure, and the pair of trenches are communicated with each other.

2. The production method according to claim 1, wherein The area on the substrate where the first photoresist pattern is projected is located in the area on the substrate where the second photoresist pattern is projected.

3. The production method according to claim 1, wherein The step of removing the first photoresist pattern further comprises: removing a portion of the dielectric layer, such that the top surface of the dielectric layer is smaller than the bottom surface of the dielectric layer, and the dielectric layer has an inclined side surface.

4. The production method according to claim 3, wherein The smaller included angle between the inclined side surface and the top surface of the dielectric layer is 45 degrees to 85 degrees.

5. The production method according to claim 3, wherein The second photoresist pattern covers the inclined side surface and the top surface of the dielectric layer, and covers a portion of the protective layer located on the exposed region and adjacent to the inclined side surface.

6. The manufacturing method of claim 1, wherein: in the step of forming the first photoresist pattern on the dielectric layer, the first photoresist pattern is located above the thermoelectric structure; and in the step of forming the second photoresist pattern on the protective layer, the second photoresist pattern is located above the thermoelectric structure.

7. The production method according to claim 1, wherein The manufacturing method further comprises: removing the second photoresist pattern; forming a via hole penetrating through the protective layer and exposing the thermoelectric structure; and filling a conductive material in the via hole to form a contact plug in contact with the thermoelectric structure.

8. The production method according to claim 1, wherein Before the step of forming the thermoelectric structure on the substrate, an insulating layer is formed on the substrate, and the insulating layer is located between the substrate and the thermoelectric structure.

9. A semiconductor structure, characterized by The semiconductor structure comprises: a substrate: a thermoelectric structure disposed on the substrate; a dielectric layer disposed on the substrate and exposing an exposed region of the substrate, and the dielectric layer covering the thermoelectric structure; a protective layer disposed on the top surface and side surface of the dielectric layer and covering a portion of the exposed region of the substrate; a pair of trenches disposed in another portion of the exposed region and disposed on two sides of the thermoelectric structure; and a cavity in the substrate, such that the sidewalls of the pair of trenches and the side surface of the protective layer located on the exposed region are substantially aligned, the cavity is located under the thermoelectric structure, and the pair of trenches are communicated with each other. A cavity is disposed in the substrate and is located below the thermoelectric structure, so that the pair of trenches are in communication with each other, and the sidewalls of the pair of trenches are substantially aligned with the side surfaces of the protective layer located on the exposed region.

10. The semiconductor structure of claim 9, wherein, The top surface of the dielectric layer is smaller than the bottom surface of the dielectric layer.

11. The semiconductor structure of claim 9, wherein, The dielectric layer has an inclined side surface, and the protective layer is disposed on the inclined side surface.

12. The semiconductor structure of claim 11, wherein, The smaller included angle between the inclined side surface and the top surface of the dielectric layer is 45 degrees to 85 degrees.

13. The semiconductor structure of claim 9, wherein, The semiconductor structure further comprises: An insulating layer is disposed between the substrate and the thermoelectric structure, and the insulating layer and the dielectric layer have an inclined side surface, and the smaller included angle between the inclined side surface and the top surface of the dielectric layer is 45 degrees to 85 degrees.

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