System and method for radical and thermal processing of substrates

Abstract

The present disclosure provides systems and methods for processing a via structure of a substrate, the systems and methods including positioning a substrate in a first processing chamber having a first processing volume. The substrate includes a via structure with high aspect ratio features having an aspect ratio greater than about 20:1. The methods include forming a silicon-containing layer over the via structure to a hydrogen or deuterium plasma at a flow rate of about 10 seem to about 5000 seem in the first processing volume. The substrate is maintained at a temperature of about 100 °C to about 1100 °C during the exposure, which forms a nucleation substrate. After the exposure, a thermal anneal operation is performed on the substrate.

Description

background Technical Field

[0002] Embodiments of this disclosure generally relate to systems and methods for manufacturing semiconductor devices. More specifically, this disclosure relates to systems and methods for thermally treating channel structures in semiconductor devices under a hydrogen radical environment. Background Technology

[0004] The integrated circuit (IC) market continues to demand larger memory capacities, faster switching speeds, and greater feature densities. To enable the fabrication of next-generation devices and structures, three-dimensional (3D) stacking of semiconductor memory chips is frequently used to improve transistor performance. By arranging transistors in three dimensions instead of the traditional two, multiple transistors can be placed very close to each other within an integrated circuit. 3D stacking of semiconductor chips reduces line length, maintains low wiring delay, and increases on-chip device density. When forming a flash memory structure, a film stack is placed on a substrate, and an etching process is performed to etch trenches in the film stack. These trenches are later used to construct silicon channel structures to electrically connect the source to the nearby drain structure. Film stack structures typically contain repeating alternating layers of conductive and insulating layers. Because a large number of repeating alternating layers are required in film stack structures for higher device performance, film stack structures with channel structures often have a high aspect ratio. Furthermore, manufacturers are continuously increasing the height of the stack, which increases the length of the channels. Device speed is limited by the mobility of electrons in the channels and the increased length that electrons must travel.

[0005] To increase electron mobility in channels, conventional methods use only thermal annealing to crystallize and grow semiconductor grains to facilitate electron migration. However, such a process is not ideal because annealing alone results in a high thermal budget, which includes long dwell times at high temperatures. Temperature is often limited because exceeding certain temperatures can lead to defects in the device. Moreover, extended dwell times can affect yield. If the dwell time and / or temperature are insufficient, the grain size cannot grow to a sufficient level, potentially resulting in poor-performing devices.

[0006] In view of the above, there is a need for a system and method for heat-treating substrates with high aspect ratio characteristics. Summary of the Invention

[0007] In one embodiment, a method of processing a substrate is provided, the method comprising positioning the substrate in a first processing chamber having a first processing space. The substrate includes a 3D memory structure with a high aspect ratio feature having an aspect ratio greater than about 20:1. A silicon-containing layer of a channel structure, such as a silicon-containing layer of a channel structure in the 3D memory structure of the substrate, is exposed in the first processing space to hydrogen or deuterium plasma at a flow rate of about 10 sccm to about 5000 sccm. During exposure, the substrate is annealed in the first processing space at a temperature of about 100°C to about 1100°C to form a nucleated substrate. After exposing the substrate, the nucleated substrate is thermally annealed.

[0008] In another embodiment, a method for fabricating a memory device on a substrate is provided, the method comprising forming a channel structure in a film stack structure by etching channels in the film stack structure and placing channel layers on the inner surface and bottom of the channels. The channels and channel layers form a channel structure with a high aspect ratio on the substrate. Each channel structure has an aspect ratio greater than about 20:1. The method comprises exposing the channel structure to hydrogen radicals in a first processing space of a first processing chamber. The channel structure is heated at a temperature of about 100°C to about 1100°C.

[0009] In another embodiment, a method of processing a substrate is provided, the method comprising forming an amorphous silicon-containing layer above the bottom and inner surface of a channel formed in a film stack structure of the substrate. The film stack structure comprises alternating oxide and nitride layers or alternating oxide and polycrystalline silicon layers. The process comprises exposing the amorphous silicon-containing layer to hydrogen radicals. The substrate is heated at a first temperature of about 100°C to about 1100°C to form a nucleation substrate. The nucleation substrate is further heated at a second temperature. Attached Figure Description

[0010] To provide a more detailed understanding of the features described above in this disclosure, a more specific description of the disclosure, which has been briefly outlined above, can be obtained by referring to the embodiments, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings only illustrate typical embodiments of this disclosure and should not be construed as limiting the scope of this disclosure, as other equivalent embodiments are permissible.

[0011] Figure 1A An example channel is depicted in a film stack structure disposed on a substrate in accordance with certain aspects of this disclosure.

[0012] Figure 1B An example channel structure according to certain aspects of this disclosure is depicted, wherein a channel layer is disposed within a channel of a memory structure formed on a substrate.

[0013] Figure 2 A flowchart depicting an example method for fabricating a memory device on a substrate according to certain aspects of this disclosure.

[0014] Figure 3 A schematic diagram depicting an example heat treatment system for processing channel structures on a substrate according to certain aspects of this disclosure.

[0015] Figure 4A and Figure 4B A schematic diagram depicts an example thermal radical processing system for heating and processing channel structures on a substrate using free radical species, according to certain aspects of this disclosure.

[0016] Figure 5 A flowchart depicting an example method for processing a substrate with a high aspect ratio feature according to certain aspects of this disclosure.

[0017] For ease of understanding, the same reference numerals have been used where possible to refer to common elements in the figures. Elements and features of one embodiment are intended to be beneficially incorporated into other embodiments without further description.

[0018] However, it should be noted that the accompanying drawings are merely exemplary embodiments of this disclosure and should not be construed as limiting the scope of this disclosure, as other equivalent embodiments are permissible. Detailed Implementation

[0019] Certain aspects of this disclosure provide systems and methods for thermally processing substrates with high aspect ratio characteristics. Specifically, the high aspect ratio characteristic can be a channel structure formed in certain three-dimensional devices. As the resulting vertical structures have increasingly longer channel lengths, the speed of the device may become limited by the electron mobility in the channels and the increased length that electrons must travel. Therefore, it is necessary to increase the electron mobility in the semiconductor channels to compensate for the increased length that electrons must travel. Specifically, using a thermal annealing process to increase the grain size of the semiconductor (such as silicon in the channels) helps reduce electron scattering at the semiconductor grain boundaries, thus increasing electron mobility.

[0020] Annealing produces a greater crystalline structure from regions of a previously amorphous substrate. During the crystallization process, semiconductor atoms (such as silicon atoms) rearrange into a sequential lattice structure. To crystallize an amorphous semiconductor film, heat is typically used as an energy source to provide the necessary kinetic energy for the atoms to rearrange into a sequential structure. To increase the grain size obtained from the amorphous semiconductor film, the furnace temperature and / or furnace annealing time can be increased. Due to stricter thermal budget requirements, furnace temperatures are greatly limited, and increased furnace annealing times can impair product yield. Therefore, there is a need for systems and methods for processing semiconductor substrates with film stack structures having high aspect ratio channel structures to provide uniform and expanded grain sizes in the channels using high-yield and minimal thermal budget methods, thereby efficiently providing improved device performance. This disclosure provides systems and methods for thermally processing substrates with high aspect ratio characteristics to produce high-performance devices.

[0021] Specifically, the processes and systems of this disclosure improve electron mobility within the channels of a three-dimensional memory structure by increasing the average grain size within the semiconductor channel layer disposed in the channel. The process involves processing a substrate with radical species (such as hydrogen or deuterium radicals) at elevated temperatures to promote an environment conducive to nucleation and grain growth of the semiconductor channel layer. Following radical processing (such as hydrogen or deuterium doping), furnace annealing can be performed at temperatures equal to or higher than those of the radical processing to promote grain growth in the nucleated semiconductor channel layer. Furnace annealing of the nucleated channel layer results in a more uniform grain distribution and further grain growth within the semiconductor channel layer. Hydrogen or deuterium radical processing allows for a reduction in the activation energy required for the nucleation and incubation stages of the semiconductor grains and reduces the heat and time required during furnace annealing.

[0022] Figure 1A and Figure 1B The memory structure 110 formed on substrate 100 at various stages of formation according to certain aspects of this disclosure is depicted. For example... Figure 1A and Figure 1BAs shown in the example embodiment depicted, substrate 100 has a generally flat surface, but may alternatively have a non-flat surface, or a generally flat surface with a structure formed on its surface. A film stack structure 101 is disposed on substrate 100 for forming a memory cell structure within the film stack structure 101. The fabrication process of a 3D NAND device begins with the deposition of multiple alternating film layers, collectively referred to as a "film stack structure". Creating a film stack structure involves depositing multiple thin layers of oxide / nitride (ON) layer pairs or oxide / polysilicon (OP) layer pairs. Substrate 100 is a silicon-based material, but may also be a germanium-based material, a silicon-germanium alloy, or any suitable insulating, semiconductor, or conductive material, such as materials having elements of Group III, IV, or V of the periodic table. In some embodiments, substrate 100 may be a material such as doped or undoped single-crystal silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polycrystalline silicon, doped or undoped silicon wafers and patterned or unpatterned silicon-on-insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, or sapphire. Substrate 100 may have various sizes, such as substrates with diameters of about 200 mm, about 300 mm, about 450 mm, or other diameters, and rectangular or square panels.

[0023] In at least one embodiment, the film stack structure 101 disposed on the substrate 100 has a plurality of vertically stacked layers, such as 34 pairs of layers or more. The film stack structure 101 comprises pairs of layers, each pair containing a first layer 102 (shown as 102a1 to 102a1) that alternates between two nitride layers 103a and 103b and is sandwiched between the two nitride layers 103a and 103b. n ) and the second layer 104 (shown from 104a1 to 104a) n A sandwich layer is stacked on an aluminum oxide layer 108 disposed on a substrate to form a film stack structure 101. The layer pairs comprise alternating first layers 102 and second layers 104, with the alternating first layers 102 and second layers 104 repeated up to n pairs of first and second layers. The film stack structure 101 is part of a memory cell device such as a three-dimensional (3D) memory device, and any predetermined number of repeating pairs of first layers 102 and second layers 104 can be used as needed.

[0024] In at least one embodiment, which can be combined with other embodiments, the film stack structure 101 is used to form a plurality of memory cell structures for a three-dimensional (3D) memory device. The film stack structure 101 is composed of alternating oxide layers and nitride layers (ON) or alternating oxide layers and polysilicon layers (OP). For example, the film stack structure 101 may, among others, include polysilicon, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide, titanium nitride, oxide and nitride composites, at least one or more oxide layers sandwiching nitride layers, and combinations thereof. Figure 1A and Figure 1B As can be seen, the alternating layers of the film stack structure 101 include a first layer 102, which serves as an insulating dielectric layer, such as silicon oxide. The alternating layers of the film stack structure 101 also include a second layer 104, which is a functional layer in which memory storage cells are constructed. The functional layer includes one or more of silicon, polysilicon, and silicon nitride.

[0025] The second layer 104 contains memory storage cells of different structures, such as charge-trap devices (not shown) or floating gate devices. The floating gate device includes a control gate 109, an inter-polysilicon dielectric (IPD) layer 106, a floating gate 107, a tunnel oxide layer 105, and a channel layer 170. The floating gate is made of silicon, and the tunnel oxide layer is made of silicon oxide. However, other materials are also contemplated. The IPD layer 106 is a stacked structure of layers, such as a three-layer stacked structure. The IPD layer 106 is a stacked structure of one or more of silicon oxide layers, silicon nitride layers, and silicon oxide layers. Alternating first layers 102 and second layers 104 are disposed between nitride layers (e.g., 103a, 103b), such as between a cap layer 103a and a stop layer 103b.

[0026] The membrane stack 101 is patterned to form channels 150 in the membrane stack 101, such as Figure 1A As shown in the figure, a hardened layer (not shown) is formed on the membrane stack structure 101 to facilitate the formation of channels 150 in the membrane stack structure 101. Channels 150 are used to form channel structures 160 in the device structure when the manufacturing process is complete. As used herein, channel structure 160 includes channels 150 and channel layers 170. It should be noted that the device structure and configuration can be varied as needed to meet different device performance requirements.

[0027] Patterning is incorporated into the formation of the film stack structure 101. Figure 1A Channel 150 shown Figure 1A Channel 150 shown will later be used as Figure 1BThe channel structure 160 is shown. A patterning process uses any suitable patterning gas mixture to etch the first layer 102 and the second layer 104 in the film stack structure 101. A channel layer 170 is formed in the channel 150 to form the channel structure 160. The channel layer 170 is formed in the inner surface of the channel, along the entire length of the channel, and at the bottom of the channel. The channel layer 170 is formed by a chemical vapor deposition (CVD) process, but may alternatively be formed by an atomic layer deposition (ALD) process, sputtering process, coating process, or other suitable process. The channel layer 170 is amorphous after deposition and crystallizes into polycrystalline silicon after hydrogen or deuterium radical processing, and may additionally or alternatively contain monocrystalline silicon, group III-V semiconductors, or other semiconductors with high electron mobility and low random telegraph noise. Crystallizing the channel layer 170 increases the conductivity of the channel structure 160 and enhances the overall device performance. During the patterning and etching processes, the channels 150 formed in the film stack structure 101 may have sloping sidewalls (e.g., not perpendicular to or at an angle to the horizontal surface or plane of the substrate 100). According to the method of this disclosure, after the channel layer 170 is placed and after the thermally processed channel structure 160, an oxide layer (not shown) may fill the remaining space in the channel structure 160.

[0028] In at least one embodiment that can be combined with other embodiments, the substrate of this disclosure includes a high aspect ratio feature. For example, a channel 150 formed in the film stack structure 101 may be referred to as a high aspect ratio feature, or the channel 150 may be formed together with the channel layer 170 to form a high aspect ratio feature. The high aspect ratio feature has an aspect ratio greater than about 20:1, 30:1, 40:1 or 50:1, such as from 50:1 to about 1000:1, such as from about 50:1 to about 300:1, such as from about 100:1 to about 300:1, or about 200:1 to about 300:1.

[0029] Despite Figure 1A and Figure 1B The present disclosure describes a 3D NAND structure, but the methods described herein can be applied to any semiconductor device with a channel structure, such as resistive RAM (ReRAM) and 3D-DRAM.

[0030] Figure 2 A flowchart depicts an example method 200 for fabricating a memory device on a substrate according to certain aspects of this disclosure. Operation 202 of method 200 includes forming a channel structure in a film stack structure 101. The channel structure 160 is formed by etching a channel 150 in the film stack structure 101 and forming a channel layer 170 in the inner surface and bottom of the channel 150 of the film stack structure 101. The channel structure 160 forms a high aspect ratio feature having an aspect ratio greater than about 20:1. The channel layer 170 is about 100 angstroms to about 200 angstroms.

[0031] Method 200 includes, in operation 204, a first processing chamber (e.g., Figure 3 And the first processing space (e.g., 328) shown in Figure 4) Figure 3 The channel structure 160 is fabricated using hydrogen or deuterium radicals (as illustrated in Figure 4, 308). Channel structures with high aspect ratios are challenging to fabricate using conventional processes because conventional processes using high-energy plasma result in unintentional ion etching from ion bombardment and poor uniformity along the channel length. In conventional processes, high-energy plasma ions are directed directly to the bottom of the channel rather than the sidewalls. While conventional processes are used for horizontal surfaces, they are not suitable for vertical structures such as channels. It has been found that the hydrogen process disclosed herein provides non-directional radical processing along the entire channel length, resulting in improved uniformity of nucleation and grain growth. Specifically, hydrogen radicals are delivered to the processing space (e.g., via a nozzle positioned above the substrate) Figure 3 (and 308 shown in Figure 4). In one example, the nozzle is configured to provide a uniform distribution of free radicals above the substrate, thereby promoting improved diffusion into the channel 150 formed in operation 202.

[0032] In some embodiments that can be combined with other embodiments, at operation 204, the first processing chamber is heated at a temperature of about 100°C to about 1100°C (e.g., Figure 3 And as shown in Figure 4 (328), such as about 200°C to about 800°C, such as about 300°C to about 700°C, about 400°C to about 600°C, such as about 500°C. In at least one embodiment that can be combined with other embodiments, the substrate having high aspect ratio features is exposed to hydrogen or deuterium free radical species for at least about 1 minute, such as about 1 minute to 30 minutes, alternatively about 10 minutes to about 1 hour, such as about 20 minutes to 40 minutes, such as about 30 minutes. See reference Figure 4A and Figure 4B The described thermal radical processing system 400 processes high aspect ratio features using hydrogen or deuterium radical species at the aforementioned temperatures. However, the use of other heat treatment systems is also anticipated.

[0033] Return to reference Figure 2 Operation 206 involves heating the high aspect ratio feature after exposure to hydrogen or deuterium radical species at a temperature of about 400°C to about 1100°C. In some embodiments that can be combined with other embodiments described herein, the high aspect ratio feature is heated in a second processing space 358 of the second processing chamber 352, such as... Figure 3 As depicted in the figure. Alternatively, the high aspect ratio features are heated in the first processing space 308 of the first processing chamber 328.

[0034] Figure 3 This diagram illustrates an example heat treatment system for processing channel structures on a substrate according to certain aspects of this disclosure. The second processing chamber 352 may be a heat treatment chamber, such as a furnace, that can be heated at a temperature ranging from room temperature to about 1100°C or higher. In some embodiments that can be combined with other embodiments, the substrate having high aspect ratio features is heated in the second processing chamber at a temperature of about 400°C to about 1100°C, such as about 600°C to about 1000°C, such as about 700°C. The substrate having high aspect ratio features is annealed in the second processing chamber 352 for at least about 1 minute, such as about 10 minutes to about 1 hour, such as about 20 minutes to 40 minutes, such as about 30 minutes. In at least one embodiment that can be combined with other embodiments, the second processing chamber 352 is operated at a pressure of about 1 Torr to about 3800 Torr, such as atmospheric pressure or a reduced pressure, such as about 1 Torr to about 760 Torr. In some embodiments, the second processing chamber 352 contains nitrogen. Pressure is controlled by flowing an inert gas, such as argon, which is a rare gas.

[0035] Figure 4A A schematic diagram depicts an example thermal radical processing system 400 for processing channel structures 160 on a substrate 100 according to certain aspects of this disclosure. The thermal radical processing system 400 includes a first heat treatment chamber 328, a remote plasma source (RPS) 306, and a gas line 307 coupling the remote plasma source 306 to the first heat treatment chamber 328. The first heat treatment chamber 328 may be a conventional heater-based annealing chamber or a rapid thermal processing (RTP) chamber, such as a rapid thermal annealing (RTA) chamber. In some embodiments, the first heat treatment chamber 328 may be any heat treatment chamber in which it is desired to deliver at least metastable radical molecular species and / or radical atomic species to the processing space. For example, in some embodiments, the processing chamber is a plasma processing chamber, or a plasma-enhanced or plasma-assisted deposition chamber, such as a plasma-enhanced chemical vapor deposition (PECVD) chamber or a plasma-enhanced atomic layer deposition (PEALD) chamber.

[0036] Control module 318 may be coupled to thermal free radical processing system 400 to control the operating parameters of first heat treatment space 308, RPS 306, pump 316, and airflow in gas line 307 leading to first heat treatment chamber 328. Control module 318 may include central processing unit (CPU) 324, memory 320, and support circuitry 322 for CPU 324. Control module 318 controls heat pretreatment system 300 directly or via other computer and / or controller (not shown) coupled to first heat treatment chamber 328, RPS 306, and / or gas line 307. Control module 318 is any form of general-purpose computer processor used in an industrial environment to control various chambers and devices and subprocessors in or within these chambers and devices. Memory 320 or computer-readable medium is one or more readily available memories, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, flash drive, or any other form of local or remote digital storage. Support circuitry 322 is coupled to CPU 324 to support the processor. Support circuitry 322 includes cache, power supply, clock circuitry, input / output circuitry systems and subsystems, and the like. Substrate processing parameters are stored as software routines in memory 320, which are executed or invoked to convert control module 318 into a dedicated controller to control the operation of the thermal radical processing system 300. Control module 318 is configured to perform any of the methods described herein. In some embodiments, vacuum pump 316 is used to maintain the gas pressure in the first heat treatment space 308. Vacuum pump 316 evacuates post-processing gases and / or process byproducts via evacuation device 309. In some embodiments, vacuum pump 316 is controlled by control module 318.

[0037] RPS 306 is coupled to power supply 338. Power supply 338 serves as an excitation source to ignite and sustain the plasma in RPS 306. In at least one embodiment, RPS 306 includes an inductively coupled plasma (ICP) source, a transformer-coupled plasma (TCP) source, and / or a capacitively coupled plasma (CCP) source. In some embodiments that can be combined with other embodiments, power supply 338 is a radio frequency (RF) source. For example, the RF source delivers power between about 5 kW and about 9 kW, such as 7 kW.

[0038] RPS 306 operates at approximately 50 mT to approximately 10 T, such as approximately 100 mT to approximately 1 T. RPS 306 is coupled to a first gas source 302 via a first gas conduit 303 and to a second gas source 304 via a second gas conduit 305. For example, the first gas source 302 may contain a first gas, which may contain non-reactive gases such as He, Ne, Ar, Kr, Xe, and N2. For example, the first gas source 302 may contain Ar gas. In some embodiments, the second gas source 304 may contain a species containing hydrogen, nitrogen, or deuterium, H2, D2, NH3, or a combination of the foregoing. In at least one embodiment, the thermal radical processing system is as follows: Figure 4B The dual-chamber configuration described herein involves processing two substrates in parallel within a chamber body having two process areas. These two spaces are not isolated from each other. However, other configurations are contemplated. The flow rate of the second gas source into the first heat treatment space 308 is approximately 10 sccm to approximately 5000 sccm, such as from approximately 100 sccm to approximately 1500 sccm. The total flow rate of the first and second gases into the first heat treatment space 308 is approximately 10 sccm to approximately 5000 sccm, such as from approximately 100 sccm to approximately 1500 sccm.

[0039] Figure 4B A cross-sectional view depicting an example thermal radical processing system 400 having two chambers according to certain aspects of this disclosure is shown. Specifically, Figure 4B An example of a first heat treatment chamber having two heat treatment chambers 328A and 328B is depicted. Each of the heat treatment chambers 328A and 328B of the first heat treatment system 400 includes a substrate holder 312A and 312B. A substrate having a high aspect ratio is positioned on one of the substrate holders (e.g., 312A and 312B) in one of the first processing spaces (e.g., 308A and 308B).

[0040] Each of the heat treatment chambers 328A and 328B includes a remote plasma source 306A, 306B. In some embodiments, the heat treatment chambers 328A and 328B may share a single RPS (not shown). In some embodiments, each RPS 306A, 306B is coupled to a shared first gas source 302 and a shared second gas source 304. In at least one embodiment, each RPS 306A, 306B may be coupled to a different first gas source (not shown) and a different second gas source (not shown). Each of the substrate holders 312A and 312B has an embedded heater element 314A, 314B adapted to control the temperature of a substrate supported on the substrate holder 312A, 312B. In at least one embodiment that can be combined with other embodiments, the substrate holders 312A, 312B can be resistively heated by applying current from a power source to the heater element 314A, 314B. Each of the heat treatment chambers 328A and 328B also includes process accessories 310A and 310B. Process accessories are one or more components, such as pads, inside the heat treatment chambers 328A and 328B used for wafer performance. Pads may be made of quartz, ceramic, or metal.

[0041] Figure 5 A flowchart depicts an example method 500 for processing a substrate having a high aspect ratio feature according to certain aspects of this disclosure. The high aspect ratio feature has an aspect ratio greater than about 20:1, such as from about 20:1 to about 1000:1, such as from about 50:1 to about 500:1, such as from about 100:1 to about 300:1. Method 500 includes, at operation 502, forming a semiconductor layer (e.g., a semiconductor channel layer 170), such as a silicon-containing layer, over the substrate. The substrate with the semiconductor layer is positioned in a first heat treatment chamber having a first processing space in fluid communication with a gas line.

[0042] At operation 504, the substrate is exposed to hydrogen or deuterium radical species. Formation of hydrogen or deuterium radical species includes: forming plasma from a first gas in a remote plasma source 306; flowing the plasma through a gas line 307 into a first heat treatment chamber 328; and flowing a second gas into the remote plasma source 306 before, simultaneously with, or after ignition of the first gas in the remote plasma source 306. In some embodiments, the plasma and the second gas may be mixed in a first heat treatment space 308. A first gas from a first gas source 302, such as argon, flows into the remote plasma source 306 through a first gas conduit 303. Power is switched on 338, and the mixture in the remote plasma source 306 flows into the first heat treatment space 308. A second gas (such as hydrogen) enters the RPS 306 through a second gas conduit 305, mixes with the plasma, and flows into the first heat treatment space 308 through a gas line 307. The flow rate of the second gas is approximately 5% to approximately 100% of the total flow rate of the first and second gases to the remote plasma source 306. The first gas is ignited into plasma in the RPS 306 and used to dissociate the molecules of the second gas into radical species, such as hydrogen radicals in the mixing space of the remote plasma source and gas line 307. In some embodiments that can be combined with other embodiments, the first gas may be shut off, and the radical species generated by the second gas may flow into the first heat treatment space 308. In some embodiments that can be combined with other embodiments, the first gas may continue to flow into the first heat treatment space in parallel with the radical species generated by the second gas. Hydrogen or deuterium radical species flow into the first heat treatment space 308 to nucleate the amorphous layer of the 3D memory structure of the substrate using the radical species as described in operation 506.

[0043] Although the plasma source is depicted as remote plasma source 306 in the figures, other excitation sources are contemplated. In some embodiments that can be combined with other embodiments described herein, the second gas flows to an inductively coupled plasma (ICP) source before flowing into the first heat treatment space, or the second gas is excited in situ by ICP within the first heat treatment space. In some embodiments, the second gas may flow to a microwave plasma source before flowing into the first heat treatment space, or the second gas may be excited in situ by a microwave plasma source within the first heat treatment space. In some embodiments that can be combined with other embodiments, the thermal process of this disclosure is free of all non-hydrogen and / or non-deuterium radical species. It has been found that forming plasma in a remote plasma source uses less energy to form and sustain plasma compared to forming plasma directly in the treatment space.

[0044] In some aspects of this disclosure, which can be combined with other embodiments, the formation of hydrogen or deuterium radical species includes: switching power 338 to RPS 306 and allowing a second gas (such as a hydrogen-containing gas) from a second gas source 304 to flow into RPS 306 via a second gas conduit 305. The flow rate of the second gas may be about 100% of the total gas flow rate to the remote plasma source 306. Molecules of the second gas dissociate into radical species, such as hydrogen radicals, in the remote plasma source 306 and in the gas line 307. As described in operation 504, the hydrogen or deuterium radical species flow into the first heat treatment space 308.

[0045] The step of allowing hydrogen and / or deuterium radical species to flow into the first heat treatment space 308 includes nucleating the semiconductor channel layer 170. Specifically, prior to processing with the hydrogen and / or deuterium radical species, the semiconductor channel layer is an amorphous layer, such as an amorphous layer and / or a semi-crystalline layer used to generate 3D memory structures. After exposing a substrate having the amorphous semiconductor channel layer, the semiconductor (e.g., silicon) within the channel layer 170 is nucleated to form a nucleated substrate. The step of nucleating the substrate includes heating the substrate during exposure to the hydrogen and / or deuterium radical species.

[0046] In some implementations, the first processing chamber (e.g., Figure 4A and Figure 4B The substrate in (328) shown is heated at a first temperature of about 100°C to about 1100°C, such as about 400°C to about 1100°C, such as about 200°C to about 800°C, such as about 300°C to about 700°C, about 400°C to about 600°C, such as about 500°C. In at least one embodiment, the substrate having a high aspect ratio feature is exposed to hydrogen and / or deuterium radical species at about 100°C to about 1100°C (such as about 400°C to about 600°C) for a first time amount, such as about 1 minute to about 60 minutes, such as about 5 minutes to about 20 minutes, such as about 5 minutes to about 10 minutes, or from about 10 minutes to about 15 minutes.

[0047] The flow rate of hydrogen or deuterium radical species into the first heat treatment space 308 is from about 10 sccm to about 5000 sccm, such as from about 100 sccm to about 1500 sccm. The total flow rate of the radical-containing gas into the first heat treatment space 308 is from about 10 sccm to about 5000 sccm, such as from about 100 sccm to about 1500 sccm. The first temperature of the first heat treatment chamber is from about 100°C to about 1100°C. In at least one embodiment, a substrate with high aspect ratio features is processed using radical species at about 450°C to about 550°C for about 5 minutes to about 10 minutes.

[0048] The pressure in the first heat treatment chamber is at least about 10 mTorr to about 530 Torr, such as about 10 mTorr to about 10 Torr. The pressure in the first heat treatment chamber is controlled by increasing the gas flow rate from the gas line to the first heat treatment chamber and / or decreasing the gas flow rate pumped out of the first heat treatment chamber. In some embodiments that can be combined with other embodiments described herein, the hydrogen gas flow is fixed, and the pressure is controlled by adjusting (e.g., increasing) the flow rate of the inert gas into the first heat treatment chamber. The increased amount of inert gas in the first heat treatment increases the chamber pressure in the first heat treatment chamber, which can absorb free radical species in the heat treatment chamber and cause free radical species to combine. Under certain conditions, this reduces the etching of the channel layer of the channel structure due to a large amount of hydrogen and / or deuterium free radical species.

[0049] Not limited to theory, it is believed that processing amorphous or polycrystalline semiconductor materials of the semiconductor channel layer 170 using radical species (such as hydrogen and / or deuterium radicals) can reduce the activation energy required for nucleation and grain growth of the semiconductor material. Specifically, it is believed that radicals insert into the semiconductor lattice structure and generate "seeds" for grain growth, and can increase the crystallinity of the semiconductor material during annealing. The insertion of hydrogen or deuterium radical species can cause the semiconductor atomic bonds (such as Si-Si bonds) to break / loosen and rearrange. These rearrangements reduce the activation energy for nucleation, thus reducing the heat typically required to crystallize the material. It has been found that using high temperatures (such as 400°C to 600°C) from about 400°C to about 1100°C during radical annealing results in good semiconductor grain growth for several reasons.

[0050] First, high temperatures increase the dissorption efficiency of H radicals on the semiconductor surface, thus minimizing the etching of the semiconductor by radical species. It is theoretically believed that radical species (e.g., hydrogen and / or deuterium) can react with semiconductor atoms to form volatile hydrogen, semiconductor compounds (e.g., silicon compounds), which can etch the semiconductor channel layer 170 (e.g., a silicon layer). At high temperatures, the increased desorption of radicals (such as hydrogen radicals) means that the radicals have little time to react with the semiconductor material before leaving its surface.

[0051] Secondly, the use of high temperatures during radical annealing increases both the diffusion coefficient and diffusion length of hydrogen or deuterium radical species into the semiconductor layer, thus increasing the nucleation efficiency within the amorphous semiconductor layer. Thirdly, the high temperatures during annealing provide more thermal energy to the semiconductor atoms, enabling them to move and rearrange into a crystal structure. Silicon, germanium, germanium alloys, silicon alloys, and combinations thereof similarly benefit. Method 500 may optionally include, at operation 506, heating the nucleation substrate in a first processing space or a second heat treatment chamber having a second processing space. The second heat treatment chamber is an oven or furnace, such as a large industrial furnace, box furnace, split box furnace, tube furnace, split tube furnace, multi-zone split tube furnace, and / or small batch furnace. In some embodiments that can be combined with any embodiment of this disclosure, the second heat treatment chamber is the same as the first heat treatment chamber. For example, the radical species processing in operation 506 of method 500 and the heating in operation 504 occur in the same chamber. Heating the substrate in the second processing space allows for the simultaneous heating of several substrates, thereby allowing additional substrates to be processed in the first processing chamber and thus increasing the overall process yield.

[0052] In a second processing chamber, a nucleating substrate with a high aspect ratio is heated at a second temperature, such as about 100°C to about 1100°C, or about 400°C to about 800°C, or about 700°C. As used herein, the term "nucleating substrate" refers to a substrate that has been processed using hydrogen or deuterium radical species to form nucleation sites. A nucleation site is a site on which additional atoms are deposited as the crystal grows to form a structural pattern feature of a crystalline solid. Depending on the degree of crystallinity introduced by the processing, the nucleating substrate may be partially or fully crystalline. The nucleating substrate with a high aspect ratio is annealed in the second processing chamber 352 for a second time amount, such as at least about 1 minute, such as about 10 minutes to about 1 hour, such as about 20 minutes to 40 minutes, such as about 30 minutes. In at least one embodiment, the second processing chamber may be operated at atmospheric pressure or a reduced pressure, such as about 1 Torr to about 760 Torr. In some embodiments that can be combined with other embodiments, operation 506 may occur in a first heat treatment space 308. In some embodiments, the first heat treatment space 308 may be evacuated via a gas pump 316, and the nucleation substrate may be heated in the first heat treatment space. The total processing time from operation 504 to operation 506 is less than about 3 hours, such as from about 0.5 hours to about 2 hours, such as about 1.5 hours. In some embodiments, operations 504 and 506 may occur in a first processing chamber, and the total processing time of operations 504 and 506 may be at least about 1 minute, such as from about 10 minutes to about 1 hour, such as from about 20 minutes to 40 minutes, such as about 30 minutes.

[0053] In some embodiments that can be combined with other embodiments described herein, a high dose of hydrogen or deuterium radical species, such as at about 300 sccm to about 1500 sccm, is used in the first heat treatment space 308 while the substrate is heated at a first temperature in the first heat treatment chamber for a first time amount, such as about 5 minutes to about 10 minutes, and then the substrate is transferred to a second heat treatment space for further heating at a second temperature for a second time amount. Alternatively, a high dose of hydrogen or deuterium radical species, such as at a flow rate of about 300 sccm to about 1500 sccm, is used in the first heat treatment space 308 while the substrate is heated at a first temperature in the first heat treatment chamber for a first time amount, and the flow rate of the radical species is turned off or reduced for further heating at a second temperature for a second time amount. The dose of hydrogen or deuterium radical species provided herein is high enough, and the duration provided herein is long enough, for hydrogen to be inserted into the substrate to nucleate the substrate without substantially etching the substrate. The dose provided herein is also high enough to address the potential degassing of hydrogen when the substrate is heated at the second temperature. Degassing of hydrogen from the substrate inhibits grain growth. Heating the substrate in a second process space (such as in a furnace) provides the additional benefit of processing a large number of substrates simultaneously in the furnace.

[0054] In some embodiments that can be combined with other embodiments described herein, a low dose of hydrogen or deuterium radical species, such as at about 10 sccm to about 100 sccm, is used in the first heat treatment space 308 while the substrate is heated at a first temperature in the first heat treatment chamber for a third time amount, such as the total processing time from operation 504 to operation 506, such as about 5 minutes to about 1 hour.

[0055] In some embodiments that can be combined with other embodiments described herein, the second temperature is lower than the first temperature. It has been found that the second temperature disclosed herein is high enough to promote grain growth and low enough to reduce the likelihood of over-nucleation. "Nucleation" refers to the formation of nucleation sites, and the term "over-nucleation" refers to the formation of more nucleation sites than expected. It has been found that over-nucleation within a certain volume of substrate results in a lower average grain size. In some embodiments that can be combined with other embodiments described herein, the second temperature is about 5% to 50% lower than the first temperature, such as about 10% to about 30%, such as about 20%. The process disclosed herein provides conformal grain size of the channel structure from top to bottom.

[0056] According to at least one embodiment that can be combined with other embodiments, one or more operations of the above-described method can be included as instructions in a computer-readable medium for execution by a control unit (e.g., a controller module) or any other processing system. The computer-readable medium may include any suitable memory for storing the instructions, such as random access memory (RAM), read-only memory (ROM), floppy disk, hard disk, flash drive, or any other form of local or remote digital storage device. As an example, and in some aspects of this disclosure, a system programmed to perform a method comprising an algorithm stored in the system's memory is provided. The algorithm may have multiple instructions that, when executed by a processor, cause the method to be performed. The method may include positioning a substrate in a first processing chamber having a first processing space in fluid communication with a gas line, and the substrate having a high aspect ratio characteristic having an aspect ratio greater than about 20:1, such as from about 20:1 to about 1000:1, such as from about 50:1 to about 500:1, such as from about 100:1 to about 300:1. Method 500 may further include forming radical species in a remote plasma source and exposing a substrate to the radical species in a first processing chamber to form a nucleating substrate. The nucleating substrate may be positioned in a second processing chamber having a second processing space, and the substrate may be heated in the second processing chamber at a temperature, for example, higher or lower than that of the first processing chamber.

Claims

1. A method for processing a substrate, comprising the following steps: The substrate is positioned in a first processing chamber, the first processing chamber including a first processing space, and the substrate includes a channel structure having a depth-to-width ratio greater than 20:

1. In the first processing space, the silicon-containing layer of the channel structure is exposed to hydrogen or deuterium plasma at a flow rate of 10 sccm to 5000 sccm. During the exposure step, the substrate is maintained at a first temperature of 100°C to 1100°C, and the exposure step forms a nucleation substrate. and Following the exposure step, a thermal annealing operation is performed on the substrate at a second temperature, which is 5% to 50% lower than the first temperature.

2. The method of claim 1, wherein the hydrogen or deuterium plasma is formed from a hydrogen or deuterium-containing gas in a remote plasma source.

3. The method of claim 2, wherein: The hydrogen or deuterium-containing gas includes any two or more of He, Ne, Ar, Kr, Xe, N2, or a combination of He, Ne, Ar, Kr, Xe, N2, and includes any two or more of H2, D2, NH3, or a combination of H2, D2, NH3.

4. The method of claim 1, further comprising positioning the nucleation substrate in a second processing chamber, the second processing chamber including a second processing space; and The thermal annealing operation is performed on the substrate.

5. The method of claim 4, wherein the step of performing the heat annealing operation comprises reaching a temperature of 400°C to 1000°C for 10 minutes to 2 hours under a pressure of 1 Torr to 3800 Torr.

6. The method of claim 1, wherein the step of exposing the silicon-containing layer to the hydrogen or deuterium plasma in the first processing space comprises flowing the hydrogen or deuterium plasma into the first processing space at a flow rate of 100 sccm to 1500 sccm.

7. The method of claim 1, wherein the step of exposing the silicon-containing layer to the hydrogen or deuterium plasma in the first processing space is performed at a pressure of 10 mTorr to 530 Torr for 1 to 30 minutes.

8. The method of claim 1, wherein an inductively coupled plasma source is used to form the hydrogen or deuterium plasma.

9. A system comprising an algorithm stored in the system's memory, wherein the algorithm comprises a plurality of instructions that, when executed by a processor, cause the method of claim 1 to be performed.

10. A method for fabricating a memory device on a substrate, comprising the following steps: A channel structure is formed in the membrane stack by etching channels in the membrane stack and placing channel layers at the bottom and on the inner surface of the channels, the channel structure in the membrane stack having an aspect ratio greater than 20:1; The channel structure is exposed in the first processing space of the first processing chamber in the presence of hydrogen radical species; The channel structure is heated at a first temperature of 100°C to 1100°C; and The channel structure is heated in a second processing space at a second temperature, which is 5% to 50% lower than the first temperature.

11. The method of claim 10, wherein the steps of exposing the channel structure to hydrogen radicals and heating the channel structure comprise heating the channel structure in the first processing space at a temperature of 400°C to 1100°C for 1 minute to 30 minutes.

12. The method of claim 10, wherein the channel structure is heated in the second processing space at a temperature of 400°C to 1100°C.

13. The method of claim 10, wherein the film stack structure is a 3D NAND film stack structure, and the channel layer is an amorphous or polycrystalline layer, the amorphous or polycrystalline layer comprising silicon from 0 to 100 wt% and group III, IV and V elements from 0 to 100 wt%.

14. The method of claim 10, further comprising the step of forming the film stack structure, wherein the step of forming the film stack structure comprises depositing alternating oxide layers and nitride layers, or alternating oxide layers and polysilicon layers.

15. A method for processing a substrate, comprising the following steps: An amorphous silicon-containing layer is formed above the bottom and inner surface of the channel formed in the film stack structure of the substrate, the film stack structure comprising alternating oxide layers and nitride layers or alternating oxide layers and polycrystalline silicon layers. This exposes the amorphous silicon-containing layer to hydrogen free radicals; The substrate is heated at a first temperature of 100°C to 1100°C to form a nucleation silicon-containing layer on the substrate; and The nucleated silicon-containing layer is heated at a second temperature, which is 5% to 50% lower than the first temperature.

16. The method of claim 15, wherein the silicon-containing layer and channel of the substrate form a high aspect ratio feature, the high aspect ratio feature having an aspect ratio greater than 20:

1.

17. The method of claim 15, wherein the substrate is heated at the first temperature in a first process space of a first process chamber, and the nucleated silicon-containing layer of the substrate is heated to the second temperature in a second process space of a second process chamber.

18. The method of claim 17, wherein the flow rate of the hydrogen radicals into the first process space is from 10 sccm to 5000 sccm.

19. The method of claim 17, wherein the substrate is heated in the first process space at a temperature of 400°C to 1100°C for 1 minute to 30 minutes.

20. The method of claim 15, wherein the nucleated silicon-containing layer of the substrate is heated at a temperature of 400°C to 1000°C for 10 minutes to 2 hours and at a pressure of 1 Torr to 3800 Torr.

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