Display device

Abstract

A display device includes a substrate including a plurality of subpixels, a first buffer layer over the substrate, an etching stopper over the first buffer layer, a second buffer layer covering the first buffer layer, and a first transistor over the second buffer layer. The first transistor includes a source electrode and a drain electrode overlapping with the etching stopper. The etching stopper includes a hole in which at least one of the source electrode and the drain electrode is provided. The etching stopper is spaced apart from the source electrode and the drain electrode. Thus, moisture and impurities can be prevented from penetrating into the display device by protecting the buffer layer.

Description

Technical Field

[0001] This disclosure relates to display devices, and more particularly, to display devices capable of protecting a buffer layer. Background Technology

[0002] Recently, as our society has developed towards an information-oriented society, the field of display devices for visually expressing electrical information signals has developed rapidly. Correspondingly, various display devices with excellent performance in terms of thinness, brightness, and low power consumption are being developed.

[0003] Specific examples of such display devices include liquid crystal displays (LCDs) and electroluminescent displays such as organic light-emitting displays (OLEDs) and quantum dot light-emitting displays (QLEDs). For example, electroluminescent displays are a next-generation display device with self-emissive properties and offer superior characteristics compared to liquid crystal displays in terms of viewing angle, contrast ratio, response speed, and power consumption.

[0004] An electroluminescent display device includes a display area for displaying images and a non-display area adjacent to the display area. Furthermore, the pixel area includes pixel circuitry and light-emitting elements. Multiple thin-film transistors are located in the pixel circuitry to drive the light-emitting elements disposed in multiple pixels.

[0005] Thin-film transistors (TFTs) can be classified according to the materials that form the semiconductor layer. Among them, low-temperature polycrystalline silicon (LTPS) TFTs and oxide semiconductor TFTs are the most widely used. Furthermore, research and development is underway on technologies for electroluminescent display devices that can form LTPS and oxide semiconductor TFTs on the same substrate. Summary of the Invention

[0006] The inventors of this disclosure have developed a display device in which a passivation layer is formed beneath a transistor to prevent damage to the active layer of the transistor. In this case, since the passivation layer is formed of a metallic material, parasitic capacitance may form in the passivation layer due to the peripheral configuration of the passivation layer.

[0007] The inventors of this disclosure have developed a structure for electrically connecting the source or drain electrode of a transistor disposed on a passivation layer to the passivation layer. Therefore, variations in parasitic capacitance generated in the passivation layer can be reduced or minimized, and the reliability of the transistor can be improved. Furthermore, the inventors of this disclosure have developed a structure in which contact holes extending to the passivation layer are formed simultaneously with contact holes for contacting the source and drain electrodes to the active layer. Therefore, the number of masks can be reduced, and the source or drain electrode can contact the passivation layer.

[0008] However, the inventors of this disclosure have recognized that when etching is performed in the etching process used to form contact holes up to the buffer layer below the passivation layer, the buffer layer may be damaged. Therefore, the inventors of this disclosure have invented a display device capable of preventing damage to the buffer layer during the formation of contact holes.

[0009] One object of this disclosure is to provide a display device that can protect a buffer layer beneath the etch stopper during the formation of a contact hole by providing an etch stopper to overlap with the source and drain electrodes.

[0010] Another object of this disclosure is to provide a display device that can reduce the generation of unwanted noise by allowing etch stop elements to be spaced apart from the source and drain electrodes.

[0011] The purpose of this disclosure is not limited to the above-described purposes, and other purposes will be clearly understood by those skilled in the art from the following description.

[0012] According to one aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a first buffer layer on the substrate; an etch stop member on the first buffer layer; a second buffer layer covering the first buffer layer; a first transistor on the second buffer layer, the first transistor including a source electrode and a drain electrode overlapping the etch stop member; and a light-emitting element on the first transistor. The etch stop member may include an aperture in which at least one of the source electrode and the drain electrode is disposed. The etch stop member may be spaced apart from at least one of the source electrode and the drain electrode.

[0013] According to another aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a multi-buffer layer on the substrate; an etch stop member on the multi-buffer layer, the etch stop member being configured to prevent etching of the multi-buffer layer; an active buffer layer covering the multi-buffer layer; a low-temperature polycrystalline silicon (LTPS) thin-film transistor on the active buffer layer, the LTPS thin-film transistor including an active layer, a source electrode, and a drain electrode, the source electrode and the drain electrode being connected to the active layer; and a light-emitting element on the LTPS thin-film transistor. The source electrode and the drain electrode may be configured to overlap with the etch stop member. At least one of the source electrode and the drain electrode may be configured to contact the upper surface of the multi-buffer layer and be spaced apart from the etch stop member.

[0014] Further details of the exemplary embodiments are included in the detailed embodiments and the accompanying drawings.

[0015] According to this disclosure, during the contact hole etching process, a buffer layer beneath the etching stop element is protected by an etching stop element, thereby preventing moisture and impurities from penetrating into the display device.

[0016] According to this disclosure, since the etching stop element is electrically insulated from the source electrode or drain electrode, failures caused by noise generation can be reduced.

[0017] The effects of this disclosure are not limited to those illustrated above, and include many more effects in this specification. Attached Figure Description

[0018] Figure 1 This is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure.

[0019] Figure 2 It is along Figure 1 The cross-sectional view taken from line II-II'.

[0020] Figure 3 yes Figure 2 A magnified view of region A.

[0021] Figure 4 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Detailed Implementation

[0022] Please refer to the following and appendix. Figure 1 The advantages and features of this disclosure, as well as the methods for achieving these advantages and features, will become clear from the exemplary embodiments described in detail herein. However, this disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments have been provided by way of example only to enable those skilled in the art to fully understand the disclosure and scope of this disclosure. Therefore, this disclosure will be limited only by the scope of the appended claims.

[0023] The shapes, dimensions, ratios, angles, quantities, etc., illustrated in the accompanying drawings used to describe exemplary embodiments of this disclosure are merely examples, and this disclosure is not limited thereto. Throughout the specification, similar reference numerals generally denote similar elements. Furthermore, in the following description of this disclosure, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of this disclosure. Terms such as “comprising,” “having,” and “consisting of” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” Unless explicitly stated otherwise, any reference to the singular may include the plural.

[0024] Even if not explicitly stated, components are interpreted as including the usual error range.

[0025] When using terms such as “on,” “above,” “below,” and “next to” to describe the positional relationship between two parts, one or more parts may be located between the two parts, unless these terms are used with the terms “immediately” or “directly.”

[0026] When a component or layer is positioned "on" another component or layer, one or more other components or layers may be positioned directly on or interposed between that other component or layer.

[0027] Although the terms "first," "second," etc., are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from others. Therefore, the first component mentioned below can be a second component in the technical concept of this disclosure.

[0028] Throughout the specification, similar reference numerals generally denote similar elements.

[0029] For ease of description, the dimensions and thickness of each component shown in the figures are illustrated, but this disclosure is not limited to the dimensions and thickness of the components shown.

[0030] Features of the various embodiments of this disclosure may be partially or wholly adhered to or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be implemented independently of each other or in relation to each other.

[0031] This disclosure will be described in detail below with reference to the accompanying drawings.

[0032] Figure 1 This is a schematic configuration diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 1 For ease of explanation, only the display panel PN, gating driver GD, data driver DD, and timing controller TC among the various components of the display device 100 are illustrated.

[0033] Reference Figure 1 The display device 100 includes a display panel PN comprising a plurality of sub-pixels SP, a gating driver GD and a data driver DD for supplying various signals to the display panel PN, and a timing controller TC for controlling the gating driver GD and the data driver DD.

[0034] The gating driver GD supplies multiple scan signals to multiple scan lines SL based on multiple gating control signals GCS provided by the timing controller TC. Although in Figure 1 The example shows a gating driver GD set to be spaced apart from one side of the display panel PN, but the gating driver GD can be set in the form of in-panel gating (GIP), and the number and arrangement of gating drivers GD are not limited to this.

[0035] The data driver DD converts the image data (RGB) input from the timing controller TC into a data signal using a reference gamma voltage, based on multiple data control signals (DCS) provided by the timing controller TC. Furthermore, the data driver DD can supply the converted data signal to multiple data lines DL.

[0036] The timing controller TC aligns externally input image data (RGB) and supplies it to the data driver DD. The timing controller TC can use an externally input synchronization signal SYNC (e.g., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal) to generate a gating control signal GCS and a data control signal DCS. Furthermore, the timing controller TC can supply the generated gating control signal GCS and data control signal DCS to the gating driver GD and the data driver DD respectively, thereby controlling the gating driver GD and the data driver DD.

[0037] The display panel PN is a component that displays images to the user and includes multiple subpixels SP. Multiple scan lines SL and multiple data lines DL intersect each other in the display panel PN, and each of the multiple subpixels SP is connected to both the scan lines SL and the data lines DL.

[0038] Multiple subpixels SP are individual light-emitting units, and each of the multiple subpixels SP includes a light-emitting element 180 (e.g., Figure 2 (as shown) and pixel circuitry for driving the light-emitting elements. Multiple sub-pixels SP may include, but are not limited to, red, green, blue, and white sub-pixels.

[0039] Multiple light-emitting elements can be defined differently depending on the type of the display panel PN. For example, when the display panel PN is an organic light-emitting panel, the light-emitting element is an organic light-emitting element that includes an anode, an organic layer, and a cathode. In addition, quantum dot light-emitting diodes (QLEDs), including quantum dots (QDs), can also be used as light-emitting elements. In the following description, it is assumed that the light-emitting element is an organic light-emitting element, but the type of light-emitting element is not limited to this.

[0040] A pixel circuit is a circuit used to control the driving of a light-emitting element. A pixel circuit may include multiple transistors and capacitors. For example, a pixel circuit may include, but is not limited to, driving transistors, switching transistors, sensing transistors, and storage capacitors.

[0041] In the following text, reference will be made to Figure 2 The sub-pixels SP of the display device 100 according to an exemplary embodiment of the present disclosure are described in more detail.

[0042] Figure 2 It is along Figure 1The cross-sectional view taken from line II-II'.

[0043] Reference Figure 2 The display device 100 includes a substrate 110, an etch stop member 121, a passivation layer 122, a first transistor 130, a second transistor 140, a capacitor electrode 151, an auxiliary electrode 152, a third transistor 160, a connection electrode 170, and a light-emitting element 180. Furthermore, the display device 100 includes a first buffer layer 111, a second buffer layer 112, a first gate insulating layer 113, a first interlayer insulating layer 114, a third buffer layer 115, a second gate insulating layer 116, a second interlayer insulating layer 117, a first planarization layer 118a, a second planarization layer 118b, a dam 119, and a packaging unit 190.

[0044] Furthermore, in the display device 100 according to an exemplary embodiment of the present disclosure, at least two types of thin-film transistors are formed on the same substrate 110. Here, low-temperature polycrystalline silicon (LTPS) thin-film transistors using polycrystalline silicon as the active layer and oxide semiconductor thin-film transistors using metal oxide as the active layer are used as examples of at least two types of thin-film transistors. The display device 100 according to the present disclosure can provide optimal functionality by disposing LTPS thin-film transistors and oxide semiconductor thin-film transistors with different properties on the same substrate 110.

[0045] For example, the first transistor 130 and the second transistor 140 can be LTPS thin-film transistors. LTPS thin-film transistors can be thin-film transistors using low-temperature polycrystalline silicon (LTPS) as the active layer. This is because polycrystalline silicon material has a high mobility (100 cm⁻¹). 2 With low power consumption and excellent reliability (Vs or higher), it can be applied to multiplexers (MUX) and / or gate drivers for driving thin-film transistors that drive display elements. Furthermore, polycrystalline silicon material is preferably used for driving thin-film transistors of pixels in the display device 100.

[0046] The third transistor 160 can be an oxide semiconductor thin-film transistor (OSB). An OSB can be a thin-film transistor that uses oxide semiconductor material as the active layer. Because oxide semiconductor material has a larger band gap than silicon, electrons cannot cross the band gap in the off-state, resulting in a lower cutoff current. Therefore, OSB thin-film transistors are suitable for switching thin-film transistors with short on-time and long off-time. Furthermore, due to the lower cutoff current, the size of the auxiliary capacitor can be reduced, making OSB thin-film transistors suitable for high-resolution display devices.

[0047] The substrate 110 can support various components of the display device 100. The substrate 110 can be formed from a flexible plastic material or glass. When the substrate 110 is formed from a plastic material, it can be formed from, for example, polyimide (PI). When the substrate 110 is formed from polyimide, the manufacturing process of the display device is performed with a support substrate formed of glass disposed below the substrate 110. After the manufacturing process is completed, the support substrate can be released. Furthermore, after the support substrate is released, a backplate for supporting the substrate 110 can be disposed below the substrate 110.

[0048] A first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may be referred to as a multi-buffer layer. The first buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. In addition, the first buffer layer 111 can protect transistors 130, 140, and 160 from impurities such as alkali ions leaking from the substrate 110. Furthermore, the first buffer layer 111 can improve the adhesion between the layers formed thereon and the substrate 110. The first buffer layer 111 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0049] An etch stop element 121 may be disposed on the first buffer layer 111. The etch stop element 121 may be selectively formed only in necessary regions on the first buffer layer 111. For example, the etch stop element 121 may be configured to correspond to the source electrodes 133 and 143 and the drain electrodes 134 and 144 of the first transistor 130 and the second transistor 140.

[0050] For example, the etch stop 121 may include a first etch stop 121a, a second etch stop 121b, a third etch stop 121c, and a fourth etch stop 121d. The first etch stop 121a may be configured to overlap with the first source electrode 133 of the first transistor 130 and the first channel region 131a of the first active layer 131. The second etch stop 121b may be configured to overlap with the first drain electrode 134 of the first transistor 130. The third etch stop 121c may be configured to overlap with the second source electrode 143 of the second transistor 140. The fourth etch stop 121d may be configured to overlap with the second drain electrode 144 of the second transistor 140.

[0051] The etching stop element 121 can be configured to stop etching in the contact holes in which active electrodes 133 and 143 and drain electrodes 134 and 144 are formed. For example, the etching stop element 121 can act as a barrier so that the contact holes are not formed up to the first buffer layer 111. Therefore, damage to the first buffer layer 111 can be prevented, and the penetration of moisture or impurities can be reduced. Furthermore, the etching stop element 121 can be spaced apart from the source electrodes 133 and 143 and the drain electrodes 134 and 144. For example, the etching stop element 121 can be electrically insulated from the source electrodes 133 and 143 and the drain electrodes 134 and 144. Therefore, noise generation in transistors 130 and 140 can be prevented by the etching stop element 121. This will be described later.

[0052] The etch stop element 121 may be formed of an oxide semiconductor. For example, the etch stop element 121 may include at least one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), and indium tin gallium zinc oxide (ITGZO).

[0053] A passivation layer 122 may be disposed on the first etch stop 121a. The passivation layer 122 may be formed of a metallic material and may be electrically connected to the first source electrode 133 of the first transistor 130. For example, the passivation layer 122 may be formed of molybdenum (Mo), but is not limited thereto. The passivation layer 122 may be selectively formed only in necessary areas. For example, the passivation layer 122 may be configured to overlap with the first transistor 130, which serves as a driving transistor. In this case, the first active layer 131 of the first transistor 130 may include LTPS, and the passivation layer 122 may be configured to overlap with the first channel region 131a of the first active layer 131. Therefore, the passivation layer 122 may block the generation of potential on the surface of the substrate 110 and block light from entering from the outside.

[0054] For example, when substrate 110 is formed of a plastic material, a separate support substrate is attached to the lower part of substrate 110 to support substrate 110 during the manufacturing process. In this case, a sacrificial layer is disposed between substrate 110 and support substrate. When the manufacturing process is completed, substrate 110 and support substrate can be separated by a laser release process. The first active layer 131 of the first transistor 130 disposed on substrate 110 may be damaged by laser irradiation during the laser release process.

[0055] Additionally, an infrared light sensor can be positioned below the display device 100. Therefore, the first active layer 131 may degrade due to the light emitted from the sensor.

[0056] Furthermore, due to the current drop caused by the substrate 110 and the sacrificial layer, the threshold voltage Vth of the first transistor 130 may shift. For example, a negative charge trap may occur in the sacrificial layer by light or laser light introduced from the outside. Additionally, positive charges may move towards the sacrificial layer in the plastic material (e.g., polyimide (PI)) constituting the substrate 110. Therefore, the potential at the surface of the substrate 110 may increase. As a result, the threshold voltage of the first transistor 130 shifts in the positive direction, and the current flowing through the first transistor 130 may decrease. This shift in threshold voltage degrades the reliability of the display device 100.

[0057] Furthermore, when the display device 100 is driven after the laser emission process, heat can be generated in the substrate 110. As a result, charged particles generated in the substrate 110 move upward. These charged particles can affect the first active layer 131 of the first transistor 130 and reduce the reliability of the display device 100.

[0058] Therefore, the passivation layer 122 can be disposed below the first transistor 130. In this case, the passivation layer 122 can overlap with the first active layer 131, and for example, the passivation layer 122 can overlap with the first channel region 131a. The passivation layer 122 can prevent the degradation of the first channel region 131a due to light irradiation. In addition, the passivation layer 122 can protect the first transistor 130 from the influence of charged particles generated in the substrate 110, and can reduce or minimize the influence of charge flowing through the channel of the first transistor 130. Therefore, the phenomenon of threshold voltage shift and current drop of the first transistor 130 can be reduced, and the reliability of the display device 100 can be improved.

[0059] Since the passivation layer 122 is formed of a metallic material, both the passivation layer 122 and the first active layer 131 become elements that form a capacitor. In this case, when the passivation layer 122 is electrically floated, a change in parasitic capacitance can occur, and the offset of the threshold voltage of the first transistor 130 can vary. This can lead to visual defects such as changes in brightness. Therefore, by electrically connecting the passivation layer 122 and the first source electrode 133, the parasitic capacitance can be maintained constant. For example, the same voltage as the voltage of the first source electrode 133 can be applied to the passivation layer 122. However, this disclosure is not limited to this, and the passivation layer 122 can also be electrically connected to the first drain electrode 134.

[0060] Furthermore, in the accompanying drawings, it is illustrated that the passivation layer 122 is disposed only below the first transistor 130, which serves as a driving transistor. However, this disclosure is not limited to this, and the passivation layer 122 may also be disposed below the second transistor 140. Moreover, when the second transistor 140 is configured as a driving transistor and the first transistor 130 is configured as a switching transistor, the passivation layer 122 may be disposed only below the second transistor 140, which serves as a driving transistor.

[0061] A second buffer layer 112 may be disposed on the first buffer layer 111, the etch stop element 121, and the passivation layer 122. The second buffer layer 112 may be referred to as an active buffer layer. The second buffer layer 112 can protect the active layers 131 and 141 of the first transistor 130 and the second transistor 140. The second buffer layer 112 can block various types of defects introduced from the substrate 110. Contact holes for the active electrodes 133 and 143 and the drain electrodes 134 and 144 may be formed in the second buffer layer 112. The second buffer layer 112 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof, but is not limited thereto.

[0062] The first transistor 130 and the second transistor 140 can be disposed on the second buffer layer 112. The first transistor 130 and the second transistor 140 can be LTPS thin-film transistors. Because LTPS thin-film transistors have good response characteristics, they can be used as driving transistors in pixel circuits. For example, one of the first transistor 130 and the second transistor 140 can be a driving transistor. In the following description, it will be based on the premise that the first transistor 130 is a driving transistor and the second transistor 140 is a switching transistor. However, this disclosure is not limited thereto, and the transistors can be configured such that the first transistor 130 can be a switching transistor and the second transistor 140 can be a driving transistor.

[0063] The first transistor 130 may include a first active layer 131, a first gate electrode 132, a first source electrode 133, and a first drain electrode 134. The second transistor 140 may include a second active layer 141, a second gate electrode 142, a second source electrode 143, and a second drain electrode 144. Alternatively, depending on the pixel circuit design, the source electrodes 133 and 143 may be configured as drain electrodes, and the drain electrodes 134 and 144 may be configured as source electrodes.

[0064] The first active layer 131 may be disposed on the second buffer layer 112. The first active layer 131 includes a first channel region 131a in which a channel is formed when the first transistor 130 is driven, and a first source region 131b and a first drain region 131c on both sides of the first channel region 131a. The first channel region 131a may overlap with the passivation layer 122. Furthermore, the first source region 131b may be the portion of the first active layer 131 connected to the first source electrode 133, and the first drain region 131c may be the portion of the first active layer 131 connected to the first drain electrode 134.

[0065] The first active layer 131 may comprise low-temperature polycrystalline silicon (LTPS). After depositing amorphous silicon (a-Si) material on the second buffer layer 112 and performing dehydrogenation and crystallization processes to thereby form polycrystalline silicon, the first active layer 131 can be formed by patterning the polycrystalline silicon. The first source region 131b and the first drain region 131c can be formed by ion doping (impurity doping) of the first active layer 131. For example, the first source region 131b and the first drain region 131c may be portions in which ion-doped polycrystalline silicon material is present, and the first channel region 131a may be a portion of the polycrystalline silicon material that is not ion-doped and remains as polycrystalline silicon material.

[0066] The second active layer 141 may be disposed on the second buffer layer 112. The second active layer 141 may include a second channel region 141a, a second source region 141b, and a second drain region 141c. The second active layer 141 may be formed in the same or similar manner as the first active layer 131.

[0067] The first gate insulating layer 113 may be disposed on the second buffer layer 112 and the first active layer 131. Contact holes for connecting the source electrodes 133 and 143 and the drain electrodes 134 and 144 to the source regions 131b and 141b and the drain regions 131c and 141c, respectively, may be formed in the first gate insulating layer 113. The first gate insulating layer 113 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof, but is not limited thereto.

[0068] The first gate electrode 132 and the second gate electrode 142 can be disposed on the first gate insulating layer 113. The first gate electrode 132 can be configured to overlap with the first channel region 131a. The second gate electrode 142 can be configured to overlap with the second channel region 141a. Furthermore, since the first channel region 131a overlaps with the first gate electrode 132, the first etch stop 121a and the passivation layer 122 can overlap with the first gate electrode 132. The first gate electrode 132 and the second gate electrode 142 can be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0069] The first interlayer insulating layer 114 may be disposed on the first gate insulating layer 113, the first gate electrode 132, and the second gate electrode 142. Contact holes for connecting the source electrodes 133 and 143 and the drain electrodes 134 and 144 to the source regions 131b and 141b and the drain regions 131c and 141c, respectively, may be formed in the first interlayer insulating layer 114. The first interlayer insulating layer 114 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof, but is not limited thereto.

[0070] The capacitor electrode 151 may be disposed on the first interlayer insulating layer 114. The capacitor electrode 151 may be configured to overlap with the first gate electrode 132. The capacitor electrode 151 may form a storage capacitor together with the first gate electrode 132. The capacitor electrode 151 may be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0071] The auxiliary electrode 152 can be disposed on the first interlayer insulating layer 114. The auxiliary electrode 152 can be formed from the same material and using the same process as the capacitor electrode 151. The auxiliary electrode 152 can be configured to overlap with the third channel region 161a of the third active layer 161 of the third transistor 160, which will be described later. Therefore, the auxiliary electrode 152 can be the second gate electrode of the third transistor 160. Furthermore, the auxiliary electrode 152 can be used to shield external light incident on the third channel region 161a of the third transistor 160. Therefore, the auxiliary electrode 152 can protect the third transistor 160 while improving its characteristics.

[0072] The third buffer layer 115 may be disposed on the first interlayer insulating layer 114, the capacitor electrode 151, and the auxiliary electrode 152. The third buffer layer 115 may be referred to as an oxide buffer layer. The third buffer layer 115 may be a buffer layer for protecting the third active layer 161 of the third transistor 160. In addition, contact holes may be formed in the third buffer layer 115 for connecting the source electrodes 133 and 143 and the drain electrodes 134 and 144 of the first transistor 130 and the second transistor 140 to the source regions 131b and 141b and the drain regions 131c and 141c, respectively. The third buffer layer 115 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0073] The third transistor 160 can be disposed on the third buffer layer 115. The third transistor 160 can be an oxide semiconductor thin-film transistor. Because oxide semiconductor thin-film transistors have good cutoff current characteristics, they can be used as switching transistors in pixel circuits.

[0074] The third transistor 160 may include a third active layer 161, a third gate electrode 162, a third source electrode 163, and a third drain electrode 164. In this case, the third source electrode 163 of the third transistor 160 may be electrically connected to the first drain electrode 134 of the first transistor 130. Alternatively, depending on the pixel circuit design, the third source electrode 163 may be configured as a drain electrode, and the third drain electrode 164 may be configured as a source electrode.

[0075] The third active layer 161 may be disposed on the third buffer layer 115. The third active layer 161 may include a third channel region 161a in which a channel is formed when the third transistor 160 is driven, and a third source region 161b and a third drain region 161c on both sides of the third channel region 161a. The third channel region 161a may overlap with the auxiliary electrode 152. Furthermore, the third source region 161b may be the portion of the third active layer 161 connected to the third source electrode 163, and the third drain region 161c may be the portion of the third active layer 161 connected to the third drain electrode 164.

[0076] The third active layer 161 may include an oxide semiconductor. For example, the third active layer 161 is formed of a metal oxide, and specifically, may include metal oxides such as indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO), or indium gallium oxide (IGO). The third active layer 161 can be formed by depositing a metal oxide on the third buffer layer 115, performing a thermal processing step for stabilization, and then patterning the metal oxide. The third source region 161b and the third drain region 161c can be formed by making the third active layer 161 conductive. For example, the third source region 161b and the third drain region 161c may be conductive portions of the metal oxide, and the third channel region 161a may be a non-conductive portion of the metal oxide. As the resistance of the conductive third source region 161b and the third drain region 161c decreases, the device performance of the third transistor 160 can be improved. Therefore, the reliability of the display device 100 can be improved.

[0077] The second gate insulating layer 116 may be disposed on the third active layer 161. The second gate insulating layer 116 may overlap with the third channel region 161a of the third active layer 161. For example, the second gate insulating layer 116 may be disposed only in the region corresponding to the third channel region 161a, but is not limited thereto. The second gate insulating layer 116 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or multiple layers thereof, but is not limited thereto.

[0078] The third gate electrode 162 may be disposed on the second gate insulating layer 116. The third gate electrode 162 may be disposed overlapping with the third channel region 161a. The third gate electrode 162 may be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni) and neodymium (Nd) or alloys thereof.

[0079] The second interlayer insulating layer 117 may be disposed on the third buffer layer 115, the third active layer 161, the second gate insulating layer 116, and the third gate electrode 162. Contact holes for connecting the source electrodes 133, 143, 163 and the drain electrodes 134, 144, and 164 to the source regions 131b, 141b, and 161b and the drain regions 131c, 141c, and 161c, respectively, may be formed in the second interlayer insulating layer 117. The second interlayer insulating layer 117 may be formed of a single layer of silicon nitride (SiNx) or silicon oxide (SiOx), or multiple layers thereof, but is not limited thereto.

[0080] Source electrodes 133, 143, and 163, and drain electrodes 134, 144, and 164 can be disposed on the second interlayer insulating layer 117. Source electrodes 133, 143, and 163, and drain electrodes 134, 144, and 164 can be formed from the same material using the same process. Source electrodes 133, 143, and 163, and drain electrodes 134, 144, and 164 can be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0081] For example, the first source electrode 133 and the first drain electrode 134 of the first transistor 130 can be connected to the first active layer 131 through contact holes formed in the first gate insulating layer 113, the first interlayer insulating layer 114, the third buffer layer 115, and the second interlayer insulating layer 117. For example, the first source electrode 133 can be connected to the first source region 131b of the first active layer 131 through contact holes. Furthermore, the first drain electrode 134 can be connected to the first drain region 131c of the first active layer 131 through contact holes.

[0082] The first source electrode 133 and the first drain electrode 134 can be configured to extend into a second buffer layer 112 below the first active layer 131. For example, contact holes formed in the first gate insulating layer 113, the first interlayer insulating layer 114, the third buffer layer 115, and the second interlayer insulating layer 117 can be formed to extend into the first active layer 131 and the second buffer layer 112. The first source electrode 133 can be electrically connected to the passivation layer 122 through the contact holes in the second buffer layer 112. The first drain electrode 134 can extend to contact the first buffer layer 111 through the contact holes in the second buffer layer 112 and the holes in the second etch stop 121b, which will be described later. Furthermore, although the contact holes of the first source electrode 133 are illustrated in the figures only to extend to the upper surface of the passivation layer 122, this disclosure is not limited thereto, and the contact holes can also be formed in the passivation layer 122.

[0083] The second source electrode 143 and the second drain electrode 144 of the second transistor 140 can be connected to the second active layer 141 through contact holes formed in the first gate insulating layer 113, the first interlayer insulating layer 114, the third buffer layer 115, and the second interlayer insulating layer 117. For example, the second source electrode 143 can be connected to the second source region 141b of the second active layer 141 through contact holes. Furthermore, the second drain electrode 144 can be connected to the second drain region 141c of the second active layer 141 through contact holes.

[0084] The second source electrode 143 and the second drain electrode 144 can be configured to extend into the second buffer layer 112 below the second active layer 141. For example, contact holes formed in the first gate insulating layer 113, the first interlayer insulating layer 114, the third buffer layer 115, and the second interlayer insulating layer 117 can be formed to extend into the second active layer 141 and the second buffer layer 112. The second source electrode 143 and the second drain electrode 144 can extend to contact the first buffer layer 111 through the contact holes of the second buffer layer 112 and the holes of the third etch stop member 121c and the fourth etch stop member 121d.

[0085] The third source electrode 163 and the third drain electrode 164 of the third transistor 160 can be connected to the third active layer 161 through contact holes formed in the second interlayer insulating layer 117. For example, the third source electrode 163 can be connected to the third source region 161b of the third active layer 161 through a contact hole. Furthermore, the third drain electrode 164 can be connected to the third drain region 161c of the third active layer 161 through a contact hole. Here, a contact hole can refer to a hole in the second interlayer insulating layer 117 in which the third source electrode 163 and the third drain electrode 164 are disposed.

[0086] Contact holes formed in the first gate insulating layer 113, the first interlayer insulating layer 114, the third buffer layer 115, and the second interlayer insulating layer 117 can be formed to extend into the second buffer layer 112. For example, the first source electrode 133 and the first drain electrode 134 of the first transistor 130 can extend into the second buffer layer 112 disposed below the first active layer 131. Furthermore, the second source electrode 143 and the second drain electrode 144 of the second transistor 140 can extend into the second buffer layer 112 disposed below the second active layer 141. In this case, the source electrodes 133 and 143 and the drain electrodes 134 and 144 can overlap with the etch stop member 121 disposed in the lower part of the second buffer layer 112. Etching can be stopped by the etch stop member 121 during the formation of the contact holes. Therefore, etching of the first buffer layer 111 below the etch stop member 121 can be prevented, and the reliability of the display device 100 can be improved.

[0087] Beneath the driving transistor, a passivation layer can be provided to protect it. In this case, the passivation layer can be electrically connected to the source or drain electrode of the driving transistor to maintain a constant parasitic capacitance. Furthermore, when forming contact holes for the source and drain electrodes, the contact holes can be formed up to the top of the passivation layer to reduce or minimize the number of masks. For example, contact holes for contacting the source and drain electrodes with the active layer, and contact holes for contacting the source or drain electrode with the passivation layer, can be formed by a single etching process. Furthermore, to simplify the process, contact hole etching processes can be performed simultaneously in all transistors. Therefore, in transistors without a passivation layer, etching can be performed up to the multi-buffer layer or substrate adjacent to the substrate. Moreover, even if a passivation layer is provided, over-etching may occur up to the passivation layer and the multi-buffer layer or substrate below it. When the multi-buffer layer and substrate are damaged by etching, moisture can penetrate from the outside and cause defects in the display device.

[0088] Therefore, in the display device 100 according to an exemplary embodiment of the present disclosure, the etch stop 121 may be disposed in the regions corresponding to the source electrodes 133 and 143 and the drain electrodes 134 and 144. The etch stop 121 may be disposed on the first buffer layer 111 to overlap with the source electrodes 133 and 143 and the drain electrodes 134 and 144. In this case, the etch stop 121 may comprise an oxide semiconductor. For example, the etch stop 121 may be formed of a material having an etch selectivity different from that of the second buffer layer 112, the first gate insulating layer 113, the first interlayer insulating layer 114, the third buffer layer 115, and the second interlayer insulating layer 117 above it. Therefore, when forming the contact hole, etching is performed only until the etch stop 121 is exposed, and etching is not performed on the lower part of the etch stop 121. Therefore, damage to the first buffer layer 111 and the substrate 110 can be prevented, and moisture and impurities can be prevented from penetrating from the outside.

[0089] Furthermore, despite Figure 2 The passivation layer 122 is shown to be directly disposed on the first etch stop 121a, but embodiments of this disclosure are not limited thereto. For example, another buffer layer or insulating layer may be interposed between the passivation layer 122 and the etch stop 121a. In this case, the first etch stop 121a may be configured to overlap only with the first source region 131b and may not overlap with the first channel region 131a, similar to the second etch stop 121b.

[0090] Furthermore, in the case of the third transistor 160, the third active layer 161 can be formed of an oxide semiconductor. For example, when forming a contact hole, the third active layer 161 can be used as an etch stop. Therefore, it is not necessary to provide a separate etch stop below the third transistor 160.

[0091] A buffered oxide etch (BOE) process can be performed between the contact hole formation process and the process of forming source electrodes 133, 143, 163 and drain electrodes 134, 144, and 164. A hole can be formed in the etch stop 121 by the BOE process, and the etch stop 121 can be spaced apart from the source electrodes 133 and 143 and the drain electrodes 134 and 144 by the hole. This will be referred to later. Figure 3 Describe it.

[0092] A first planarization layer 118a may be disposed on the second interlayer insulating layer 117, source electrodes 133, 143, and 163, and drain electrodes 134, 144, and 164. The first planarization layer 118a may include contact holes for exposing the first drain electrode 134 or the third source electrode 163. The first planarization layer 118a may be an organic material layer for planarizing and protecting the upper portion of transistors 130, 140, and 160. For example, the first planarization layer 118a may be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc., but is not limited thereto.

[0093] The connecting electrode 170 can be disposed on the first planarization layer 118a. The connecting electrode 170 can be used to electrically connect the light-emitting element 180 to the first transistor 130 or the third transistor 160. For example, the connecting electrode 170 can connect the first electrode 181 to the first drain electrode 134 or the third source electrode 163 through the contact holes of the first planarization layer 118a. The connecting electrode 170 can be formed as a single layer or multiple layers of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd) or alloys thereof.

[0094] The second planarization layer 118b may be disposed on the first planarization layer 118a and the connection electrode 170. The second planarization layer 118b may include contact holes for exposing the connection electrode 170. The second planarization layer 118b may be formed of organic materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin or polyimide resin, but is not limited thereto.

[0095] The light-emitting element 180 can be disposed on the second planarization layer 118b. The light-emitting element 180 may include a first electrode 181, a light-emitting layer 182, and a second electrode 183. Here, the first electrode 181 may be an anode electrode, and the second electrode 183 may be a cathode electrode.

[0096] Furthermore, the display device 100 can be implemented using either a top-emitting method or a bottom-emitting method. In the case of the top-emitting method, a reflective layer for reflecting light emitted from the light-emitting layer 182 toward the second electrode 183 can be disposed below the first electrode 181. For example, the reflective layer may include a material with excellent reflectivity, such as aluminum (Al) or silver (Ag), but is not limited thereto. On the other hand, in the case of the bottom-emitting method, the first electrode 181 may be formed solely of a transparent conductive material. Hereinafter, the display device 100 according to an exemplary embodiment of the present disclosure will be described using the top-emitting method.

[0097] The first electrode 181 can be disposed on the second planarization layer 118b. The first electrode 181 can be electrically connected to the connection electrode 170 through a contact hole formed in the second planarization layer 118b. In addition, the first electrode 181 can be connected to the first drain electrode 134 of the first transistor 130 and the third source electrode 163 of the third transistor 160 through the connection electrode 170.

[0098] The first electrode 181 can be formed as a multilayer structure including a transparent conductive layer and an opaque conductive layer with high reflectivity. The transparent conductive layer can be formed of a material with a relatively large work function, such as indium tin oxide (ITO) or indium zinc oxide (IZO). The opaque conductive layer can have a single-layer or multilayer structure including Al, Ag, Cu, Pb, Mo, Ti, or alloys thereof. However, the material of the first electrode 181 is not limited to these.

[0099] A dam 119 may be disposed on the second planarization layer 118b and the first electrode 181. The dam 119 may be formed on the second planarization layer 118b to cover the edge of the first electrode 181. The dam 119 may define a light-emitting area of ​​the display device 100 and may therefore be referred to as a pixel defining layer. The dam 119 may be an organic insulating material. For example, the dam 119 may be formed from a resin based on polyimide, acrylic acid, or benzocyclobutene (BCB), but is not limited thereto.

[0100] The light-emitting layer 182 can be disposed on the first electrode 181 and the embankment 119. The light-emitting layer 182 can be an organic layer for emitting light of a specific color. For example, the light-emitting layer 182 can be one of a red light-emitting layer, a green light-emitting layer, a blue light-emitting layer, and a white light-emitting layer. When the light-emitting layer 182 is formed of a white light-emitting layer, a color filter can be further disposed on the light-emitting element 180. The light-emitting layer 182 can also include various layers such as a hole transport layer, a hole injection layer, a hole blocking layer, an electron injection layer, an electron blocking layer, and an electron transport layer.

[0101] The second electrode 183 can be disposed on the light-emitting layer 182. Since the second electrode 183 supplies electrons to the light-emitting layer 182, it can be formed of a conductive material with a low work function. The second electrode 183 can be formed of, for example, a transparent conductive material (such as indium tin oxide (ITO) or indium zinc oxide (IZO)), a metal alloy (such as MgAg or ytterbium (Yb) alloy), and may also include a metal doped layer, but this disclosure is not limited thereto.

[0102] The encapsulation unit 190 may be disposed on the light-emitting element 180. The encapsulation unit 190 protects the light-emitting element 180 from moisture that penetrates from the outside of the display device 100. The encapsulation unit 190 may include a first encapsulation layer 191, a foreign matter covering layer 192, and a second encapsulation layer 193.

[0103] The first encapsulation layer 191 can be disposed on the second electrode 183 and suppress the penetration of moisture or oxygen. The first encapsulation layer 191 can be formed of inorganic materials such as silicon nitride (SiNx), silicon oxide nitride (SiNxOy), or aluminum oxide (AlyOz), but is not limited thereto.

[0104] Foreign matter capping layer 192 may be disposed on the first encapsulation layer 191 and its surface planarized. Furthermore, foreign matter capping layer 192 may cover foreign matter or particles that may be generated during the manufacturing process. Foreign matter capping layer 192 may be formed of organic materials (e.g., silicon oxycarbide (SiOxCZ), acrylic acid, or epoxy resin), but is not limited thereto.

[0105] The second encapsulation layer 193 can be disposed on the foreign object covering layer 192 and can, together with the first encapsulation layer 191, suppress the permeation of moisture or oxygen. In this case, the second encapsulation layer 193 and the first encapsulation layer 191 can be formed to encapsulate the foreign object covering layer 192. Therefore, the permeation of moisture or oxygen into the light-emitting element 180 can be reduced more effectively by the second encapsulation layer 193. The second encapsulation layer 193 can be formed of inorganic materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxide nitride (SiNxOy), or aluminum oxide (AlyOz), but is not limited thereto.

[0106] Figure 3 yes Figure 2 A magnified view of region A.

[0107] Reference Figure 3The second etch stop 121b may include a hole EH. The hole EH can be formed by etching a portion of the second etch stop 121b below the contact hole CH during a buffer oxide etch (BOE) process. The second etch stop 121b can be spaced apart from the first drain electrode 134 through the hole EH. Therefore, the second etch stop 121b can be insulated from the first drain electrode 134. Therefore, noise can be prevented from being generated in the first transistor 130. Furthermore, although in Figure 3 Only an enlarged view of the second etch stop 121b is shown in the figure, but the same structure can also be applied to the third etch stop 121c and the fourth etch stop 121d.

[0108] Here, hole EH can refer to a hole formed in etch stop elements 121b, 121c, and 121d. Furthermore, contact hole CH can refer to a hole in the second buffer layer 112, active layers 131 and 141, first gate insulating layer 113, first interlayer insulating layer 114, third buffer layer 115, and second interlayer insulating layer 117 through which source electrodes 133 and 143 and drain electrodes 134 and 144 are disposed.

[0109] Typically, a BOE (Boot-Off) process can be performed on the transistor, including the active layer formed by LTPS, after the contact hole is formed. In this case, the BOE process can be an etching process used to remove the oxide layer. For example, when etching the LTPS active layer, an oxide layer may be formed at the interface between the LTPS active layer and the contact hole. Such an oxide film can increase the resistance between the active layer and the source and drain electrodes. Therefore, the oxide layer can be removed by performing a BOE process between the contact hole formation process and the source and drain electrode formation processes.

[0110] The etching for forming the contact hole CH can be stopped above the etch stop 121. For example, the second buffer layer 112 is etched to form the contact hole CH, and this etching can be performed until the etch stop 121 is exposed. Since the active layers 131 and 141 of the first transistor 130 and the second transistor 140 are formed of LTPS, a BOE process can be performed after the contact hole CH is formed. In this case, since the etch stop 121 is formed of oxide semiconductor, they can be etched together with the oxide layers of the active layers 131 and 141 formed in the contact hole CH during the BOE process. For example, the etch stop 121 exposed by the contact hole CH can be etched to form the hole EH. The etch stop 121 can be etched up to the region extending from the contact hole CH and its peripheral region. Therefore, the hole EH can be formed to extend from the region corresponding to the contact hole CH to the lower part of the second buffer layer 112, which is its peripheral region. Furthermore, the hole EH can be formed to expose the first buffer layer 111.

[0111] Furthermore, although this disclosure has been described based on performing BOE processing for etching the oxide layer of the contact hole and the etch stop 121, this disclosure is not limited thereto. For example, etching using nitric acid-based or OZA-based etchants can be performed depending on the material of the etch stop 121.

[0112] After forming the contact hole CH and the BOE process, source electrodes 133, 143, and 163, and drain electrodes 134, 144, and 164 are formed. Since the contact hole CH communicates with the hole EH, the first drain electrode 134 of the first transistor 130 and the second source electrode 143 and the second drain electrode 144 of the second transistor 140 can also be formed in the hole EH. Furthermore, the first drain electrode 134, the second source electrode 143, and the second drain electrode 144 can be positioned to contact the upper surface of the first buffer layer 111. In this case, the source electrodes 133, 143, and 163, and the drain electrodes 134, 144, and 164 can be deposited by sputtering. Therefore, the first drain electrode 134, the second source electrode 143, and the second drain electrode 144 can be formed only in the region within the hole EH corresponding to the contact hole CH. For example, the first drain electrode 134, the second source electrode 143, and the second drain electrode 144 are not formed in the portion within the hole EH covered by the second buffer layer 112. Therefore, the source electrodes 133 and 143 and the drain electrodes 134 and 144 of the first transistor 130 and the second transistor 140 can be spaced apart from the etch stop member 121.

[0113] Furthermore, despite Figure 2 The illustration shows that the hole EH is not formed in the first etch stop 121a, but the present disclosure is not limited thereto. For example, when the contact hole CH in which the first source electrode 133 is formed extends to the passivation layer 122, the hole EH may also be formed below the contact hole at the passivation layer 122.

[0114] The first drain electrode 134, the second source electrode 143, and the second drain electrode 144 can be insulated from the etching stop elements 121b, 121c, and 121d through the hole EH. Therefore, noise generation in the first transistor 130 and the second transistor 140 can be reduced. For example, the first transistor 130, as a driving transistor, is connected to the light-emitting element 180 through the first drain electrode 134. Therefore, it is possible to prevent the light-emitting element 180 from being turned on due to unnecessary noise. Therefore, the operational reliability of the display device 100 can be improved.

[0115] Figure 4 This is a cross-sectional view of a display device according to another exemplary embodiment of the present disclosure. Figure 2 Compared to the display device 100, except for the first etch stop member 421a, Figure 4 The display device 400 has a basically the same configuration, therefore, its redundant description will be omitted.

[0116] Reference Figure 4 The first etch stop 421a can be configured to overlap with the first active layer 131. For example, the first etch stop 421a can overlap with the first source electrode 133 and the first drain electrode 134. In this case, the first etch stop 421a can be spaced apart from the first drain electrode 134.

[0117] The first etch stop 421a may be formed of an oxide semiconductor. For example, the first etch stop 421a may include at least one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium tin zinc oxide (ITZO), and indium tin gallium zinc oxide (ITGZO).

[0118] The first etch stop 421a can be configured to stop etching during the formation of a contact hole for contact between the first drain electrode 134 and the first active layer 131. For example, etching is not performed on the first buffer layer 111 below the first etch stop 421a. Therefore, damage to the first buffer layer 111 can be prevented by the first etch stop 421a, and the penetration of moisture or impurities can be reduced. Furthermore, the first etch stop 421a may include a hole, and the first drain electrode 134 may be spaced apart from the first etch stop 421a in the hole. Therefore, the generation of unwanted noise can be prevented. Thus, malfunction of the first transistor 130 or the light-emitting element 180 due to noise can be prevented, and the operational reliability of the display device 400 can be improved.

[0119] Exemplary embodiments of this disclosure can also be described as follows:

[0120] According to one aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a first buffer layer on the substrate; an etch stop member on the first buffer layer; a second buffer layer covering the first buffer layer; and a first transistor on the second buffer layer, the first transistor including a source electrode and a drain electrode overlapping the etch stop member. The etch stop member includes a hole in which at least one of the source electrode and the drain electrode is disposed. The etch stop member is spaced apart from at least one of the source electrode and the drain electrode.

[0121] At least one of the source electrode and the drain electrode may be configured to be spaced apart from the etch stop in the hole of the etch stop.

[0122] The first buffer layer can be exposed through a hole in the etch stop. At least one of the source and drain electrodes can contact the first buffer layer in the hole.

[0123] The etch stop may include a first etch stop overlapping the source electrode and a second etch stop overlapping the drain electrode. The first etch stop and the second etch stop may be spaced apart from each other.

[0124] The first transistor may further include an active layer connected to the source and drain electrodes. A first etch stop or a second etch stop may overlap with the channel region of the active layer.

[0125] The first transistor may also include an active layer connected to the source and drain electrodes. An etch stop may overlap with the channel region of the active layer.

[0126] The display device may further include a passivation layer disposed above an etch stop element. The first transistor may further include an active layer connected to a source electrode and a drain electrode. The passivation layer may overlap with the channel region of the active layer.

[0127] At least one of the source electrode and the drain electrode can be electrically connected to the passivation layer.

[0128] Etching stop components may include oxide semiconductors.

[0129] The active layer of the first transistor may include low-temperature polycrystalline silicon (LTPS).

[0130] The display device may further include a second transistor disposed on a substrate. The active layer of the second transistor may include an oxide semiconductor.

[0131] According to another aspect of this disclosure, a display device includes: a substrate including a plurality of sub-pixels; a multi-buffer layer on the substrate; an etch stop on the multi-buffer layer and configured to reduce etching of the multi-buffer layer; an active buffer layer covering the multi-buffer layer; and a low-temperature polycrystalline silicon (LTPS) thin-film transistor on the active buffer layer, including an active layer, a source electrode, and a drain electrode, the source electrode and drain electrode being connected to the active layer. The source electrode and drain electrode are configured to overlap with the etch stop. At least one of the source electrode and drain electrode is configured to contact the upper surface of the multi-buffer layer and be spaced apart from the etch stop.

[0132] The etching stop may include a hole exposing multiple buffer layers. At least one of the source electrode and the drain electrode may be disposed in the hole.

[0133] The display device may further include a passivation layer located above the etch stop element. The passivation layer may overlap with the channel region of the active layer.

[0134] The passivation layer can be electrically connected to one of the source electrode and the drain electrode.

[0135] The etch stop can overlap with the channel region of the active layer.

[0136] The etch stop may include a first etch stop overlapping the source electrode and a second etch stop overlapping the drain electrode. The first etch stop and the second etch stop may be spaced apart from each other.

[0137] The first or second etch stop may overlap with the channel region of the active layer.

[0138] Etching stop components may include oxide semiconductors.

[0139] The display device may also include: an oxide semiconductor thin-film transistor on a substrate.

[0140] Although exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all respects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the appended claims, and all technical concepts within their equivalents should be interpreted as falling within the scope of the present disclosure.

[0141] Cross-references to related applications

[0142] This application claims the benefit and priority of Korean Patent Application No. 10-2020-0188972, filed in Korea on December 31, 2020, the entire contents of which are expressly incorporated herein by reference.

Claims

1. A display device, the display device comprising: A substrate, the substrate comprising a plurality of sub-pixels; A first buffer layer is provided on the substrate. An etching stop element, said etching stop element being on the first buffer layer; A second buffer layer, which covers the first buffer layer; A first transistor is located on the second buffer layer. The first transistor includes a first source electrode, a first drain electrode, and a first active layer, wherein the first source electrode and the first drain electrode overlap with the etch stop element. An auxiliary electrode is located on the first transistor; The second transistor is on the auxiliary electrode and includes a second source electrode, a second drain electrode, and a second active layer. A first planarization layer is applied to the first transistor. A connection electrode is provided on the first planarization layer and is connected to the first drain electrode of the first transistor. A second planarization layer, the second planarization layer being on the connection electrode; and A light-emitting element, located on the first transistor, comprising a first electrode connected to the connecting electrode, a light-emitting layer, and a second electrode. The etching stop element includes a hole, and at least one of the first source electrode and the first drain electrode is disposed in the hole. The etching stop element is spaced apart from at least one of the first source electrode and the first drain electrode. The first active layer comprises low-temperature polycrystalline silicon (LTPS), and the second active layer comprises an oxide semiconductor. The first active layer and the second active layer are disposed on different layers, and The second active layer overlaps with the auxiliary electrode.

2. The display device according to claim 1, wherein, The first transistor is a driving transistor used to drive the light-emitting element.

3. The display device according to claim 1, wherein, At least one of the first source electrode and the first drain electrode is configured to be spaced apart from the etch stop in the hole of the etch stop.

4. The display device according to claim 1, wherein, The first buffer layer is exposed through the hole in the etch stop element, and In this process, at least one of the first source electrode or the first drain electrode contacts the first buffer layer in the hole.

5. The display device according to claim 1, wherein, The etching stop element includes a first etching stop element overlapping the first source electrode and a second etching stop element overlapping the first drain electrode, and The first etch stop element and the second etch stop element are spaced apart from each other.

6. The display device according to claim 5, wherein, The first active layer is connected to the first source electrode and the first drain electrode, and The first etch stop element or the second etch stop element overlaps with the channel region of the first active layer.

7. The display device according to claim 1, wherein, The first active layer is connected to the first source electrode and the first drain electrode, and The etching stop element overlaps with the channel region of the first active layer.

8. The display device according to claim 1, further comprising: A passivation layer is disposed above the etch stop element. Wherein, the first active layer is connected to the first source electrode and the first drain electrode, and The passivation layer overlaps with the channel region of the first active layer.

9. The display device according to claim 8, wherein, At least one of the first source electrode or the first drain electrode is electrically connected to the passivation layer.

10. The display device according to claim 8, wherein, One of the first source electrode or the first drain electrode is electrically connected to the passivation layer, and the other of the first source electrode or the first drain electrode is disposed in the hole.

11. The display device according to claim 10, wherein, One of the first source electrode or the first drain electrode passes through the passivation layer to contact the first buffer layer.

12. The display device according to claim 8, wherein, The passivation layer comprises a metallic material.

13. The display device according to claim 8, wherein, The passivation layer is configured to overlap with the etch stop element.

14. The display device according to claim 1, wherein, The etching stop element includes an oxide semiconductor.

15. The display device according to claim 1, wherein, The etching stop element comprises a material having an etching selectivity different from that of the second buffer layer.

16. The display device according to claim 1, wherein, The first transistor further includes: A first gate electrode, the first gate electrode being located on the first active layer; and A capacitor electrode, wherein the capacitor electrode is located on the first gate electrode.

17. The display device according to claim 16, wherein, The capacitor electrode and the auxiliary electrode are on the same layer.

18. A display device, the display device comprising: A substrate, the substrate comprising a plurality of sub-pixels; Multiple buffer layers are provided on the substrate. An etching stop element, the etching stop element being on the multi-buffer layer, the etching stop element being configured to reduce etching of the multi-buffer layer; An active buffer layer that covers the multiple buffer layers; A low-temperature polycrystalline silicon (LTPS) thin-film transistor is provided, wherein the LTPS thin-film transistor is located on an active buffer layer, and the LTPS thin-film transistor includes a first active layer, a first source electrode, and a first drain electrode, wherein the first source electrode and the first drain electrode are connected to the first active layer. An auxiliary electrode is provided on the LTPS thin-film transistor. An oxide semiconductor thin-film transistor, wherein the oxide semiconductor thin-film transistor is on the auxiliary electrode, the oxide semiconductor thin-film transistor includes a second active layer, a second source electrode and a second drain electrode, the second source electrode and the second drain electrode being connected to the second active layer; A first planarization layer is applied to the oxide semiconductor thin-film transistor. A connecting electrode is provided on the first planarization layer and connected to the first drain electrode. A second planarization layer is applied to the connecting electrode. as well as A light-emitting element, wherein the light-emitting element is on the LTPS thin-film transistor, the light-emitting element comprising a first electrode connected to the connection electrode, a light-emitting layer, and a second electrode. The first source electrode and the first drain electrode are configured to overlap with the etching stop element. Wherein, at least one of the first source electrode or the first drain electrode is configured to contact the upper surface of the multi-buffer layer and be spaced apart from the etch stop element, and The second active layer overlaps with the auxiliary electrode.

19. The display device according to claim 18, wherein, The LTPS thin-film transistor is a driving thin-film transistor used to drive the light-emitting element.

20. The display device according to claim 18, wherein, The etching stop element includes a hole exposing the multiple buffer layers, and In this process, at least one of the first source electrode or the first drain electrode is disposed in the hole.

21. The display device according to claim 18, further comprising: A passivation layer is provided above the etch stop element. The passivation layer overlaps with the channel region of the first active layer.

22. The display device according to claim 21, wherein, The passivation layer is electrically connected to one of the first source electrode and the first drain electrode.

23. The display device according to claim 21, wherein, One of the first source electrode or the first drain electrode is electrically connected to the passivation layer, and the other of the first source electrode or the first drain electrode is disposed in the hole.

24. The display device according to claim 23, wherein, One of the first source electrode or the first drain electrode passes through the passivation layer to contact the multi-buffer layer.

25. The display device according to claim 21, wherein, The passivation layer comprises a metallic material.

26. The display device according to claim 21, wherein, The passivation layer is configured to overlap with the etch stop element.

27. The display device according to claim 18, wherein, The etching stop element overlaps with the channel region of the first active layer.

28. The display device according to claim 18, wherein, The etching stop element includes a first etching stop element overlapping the first source electrode and a second etching stop element overlapping the first drain electrode, and The first etch stop element and the second etch stop element are spaced apart from each other.

29. The display device according to claim 28, wherein, The first etch stop or the second etch stop overlaps with the channel region of the first active layer.

30. The display device according to claim 18, wherein, The etching stop element includes an oxide semiconductor.

31. The display device according to claim 18, wherein, The etch stop element comprises a material having an etch selectivity different from that of the active buffer layer.

32. The display device according to claim 18, further comprising: An oxide semiconductor thin-film transistor, wherein the oxide semiconductor thin-film transistor is on the substrate.

33. A display device, the display device comprising: A substrate, the substrate comprising a plurality of sub-pixels; A first buffer layer is provided on the substrate. An etching stop element, said etching stop element being on the first buffer layer; A passivation layer is disposed above the etch stop element; A second buffer layer covers the first buffer layer and the passivation layer; A first transistor, located on the second buffer layer, includes a first active layer, a first source electrode, and a first drain electrode, the first source electrode and the first drain electrode being connected to the first active layer. An auxiliary electrode is located on the first transistor; An oxide semiconductor thin-film transistor, wherein the oxide semiconductor thin-film transistor is on the auxiliary electrode, the oxide semiconductor thin-film transistor includes a second active layer, a second source electrode and a second drain electrode, the second source electrode and the second drain electrode being connected to the second active layer; A first planarization layer is applied to the oxide semiconductor thin-film transistor. A connecting electrode is provided on the first planarization layer and connected to the first drain electrode. A second planarization layer is applied to the connecting electrode. as well as A light-emitting element, wherein the light-emitting element is on an LTPS thin-film transistor, the light-emitting element comprising a first electrode connected to the connection electrode, a light-emitting layer, and a second electrode. The first source electrode and the first drain electrode are configured to overlap with the etching stop element. The passivation layer overlaps with the channel region of the first active layer. In this embodiment, either the first source electrode or the first drain electrode is electrically connected to the passivation layer. The first active layer comprises low-temperature polycrystalline silicon (LTPS), and the second active layer comprises an oxide semiconductor. The first active layer and the second active layer are disposed on different layers, and The second active layer overlaps with the auxiliary electrode.

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