Storage system and method for using memory in a host allocated for reading data as a host memory buffer

Abstract

A storage system and method are provided for using memory allocated in a host for reading data as a host memory buffer. In one embodiment, the controller of the storage system receives from the host a read request for data stored in memory, wherein the read request identifies a host-allocated storage location in the host for storage after the requested data is received from the storage system. Before sending the requested data to the host, the storage system uses the allocated storage location in the host as a host memory buffer to store other data until the host needs to use the allocated storage location to store the requested data. Other embodiments are provided in this invention.

Description

Background Technology

[0001] A host can send read and write requests to a storage system to read data from the storage system's memory and to store data in the storage system's memory. Some storage systems can request to use the host's memory. Attached Figure Description

[0002] Figure 1A This is a block diagram of a non-volatile storage system implementation plan.

[0003] Figure 1B This is a block diagram illustrating a storage module in one implementation scheme.

[0004] Figure 1C This is a block diagram illustrating a hierarchical storage system implementation.

[0005] Figure 2A This illustrates an implementation scheme. Figure 1A The diagram shows a block diagram of the components of the controller for a non-volatile memory system.

[0006] Figure 2B This illustrates an implementation scheme. Figure 1A The diagram shows the components of a non-volatile memory storage system.

[0007] Figure 3 This is a block diagram of the host and storage system of an implementation scheme.

[0008] Figure 4 This is a diagram illustrating the process of allocating host memory buffers.

[0009] Figure 5 This is a diagram illustrating the process of using a host memory allocated for reading data as a host memory buffer. Detailed Implementation

[0010] Overview

[0011] By way of introduction, the following embodiments relate to a storage system and method for using memory allocated in a host for reading data as a host memory buffer. In one embodiment, a storage system is provided, including memory and a controller. The controller is configured to: receive from a host a read request for data stored in the memory, wherein the read request identifies a host-allocated storage location in the host for storage after the requested data is received from the storage system; and store other data in the storage location in the host before sending the requested data to the host.

[0012] In some implementations, storage locations within the host are made available to the storage system without the storage system requesting such access from the host.

[0013] In some implementations, the read request identifies the location and size of the storage location on the host.

[0014] In some implementations, the controller is configured to store other data in a storage location on the host while processing read requests.

[0015] In some implementations, the other data includes data to be written to memory.

[0016] In some implementations, other data includes data used to read error handling operations.

[0017] In some implementations, other data includes mapping tables.

[0018] In some implementations, additional data includes data used in the error correction mechanism.

[0019] In some implementations, other data is moved from one storage location on the host to another storage location before the requested data is received by the host and stored in the storage location.

[0020] In some implementations, other data is overwritten when the requested data is received by the host and stored in the storage location.

[0021] In some implementations, the memory includes a three-dimensional memory.

[0022] In another embodiment, a method is provided to be performed in a storage system including a memory. The method includes receiving a read command from a host requesting data to be stored in the memory; processing the read command; while processing the read command, but before transferring the data to the host, using a buffer allocated for the data in the host as a host memory buffer to store other data; and transferring the data to the host.

[0023] In some implementations, the other data includes data to be written to memory.

[0024] In some implementations, other data includes data used to read error handling operations.

[0025] In some implementations, other data includes mapping tables.

[0026] In some implementations, additional data includes data used in the error correction mechanism.

[0027] In some implementations, other data is moved from one storage location on the host to another storage location before the requested data is received by the host and stored in the storage location.

[0028] In some implementations, other data is overwritten when the requested data is received by the host and stored in the storage location.

[0029] In another embodiment, a storage system is provided, comprising: a memory; means for receiving a read command from a host requesting data to be stored in the memory; and means for storing other data in a storage location allocated for the requested data in the host before sending the requested data to the host.

[0030] Other implementations are feasible, and each of these implementations can be used individually or in combination. Therefore, various implementations will now be described with reference to the accompanying drawings.

[0031] Implementation Plan

[0032] exist Figures 1A-1C The diagram illustrates storage systems suitable for implementing these schemes. Figure 1A This is a block diagram illustrating a non-volatile storage system 100 according to one embodiment of the subject matter described herein. Reference Figure 1A The nonvolatile memory system 100 includes a controller 102 and nonvolatile memory that may be composed of one or more nonvolatile memory dies 104. As described herein, the term die refers to a collection of nonvolatile memory cells formed on a single semiconductor substrate, and the associated circuitry for managing the physical operations of those nonvolatile memory cells. The controller 102 interacts with a host system and transmits sequences of commands for read, program, and erase operations to the nonvolatile memory die 104.

[0033] Controller 102 (which may be a non-volatile memory controller (e.g., flash memory, resistive random access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random access memory (MRAM) controller)) may take the form of, for example, processing circuitry, a microprocessor or processor, and a computer-readable medium storing computer-readable program code (e.g., firmware) executable by the (micro)processor, logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers. Controller 102 may be configured with hardware and / or firmware to perform the various functions described below and shown in the flowcharts. Additionally, some components shown as internal to the controller may also be stored external to the controller, and other components may be used. Furthermore, the phrase "operationally communicating with..." may mean communicating directly or indirectly (wired or wirelessly) with one or more components, or communicating through one or more components, which may or may not be shown herein.

[0034] As used herein, a nonvolatile memory controller is a device that manages data stored on nonvolatile memory and communicates with a host device such as a computer or electronic device. In addition to the specific functions described herein, a nonvolatile memory controller can have various functions. For example, a nonvolatile memory controller can format the nonvolatile memory to ensure that the memory is operating correctly, identify bad nonvolatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells can be used to house firmware to operate the nonvolatile memory controller and implement other features. In operation, when the host needs to read data from or write data to the nonvolatile memory, it can communicate with the nonvolatile memory controller. If the host provides a logical address to read / write data, the nonvolatile memory controller can translate the logical address received from the host into a physical address in the nonvolatile memory. (Alternatively, the host can provide the physical address.) The non-volatile memory controller can also perform various memory management functions, such as, but not limited to, wear leveling (allocating writes to specific memory blocks to avoid wear that would otherwise be repeatedly written to) and garbage collection (moving only valid data pages to a new block after a block is full, so that the entire block can be erased and reused).

[0035] The non-volatile memory die 104 may include any suitable non-volatile memory medium, including resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may be in the form of solid-state (e.g., flash memory) memory cells and may be programmable once, programmable multiple times, or programmable many times. The memory cells may also be single-level cells (SLC), multi-level cells (MLC), three-level cells (TLC), or other memory cell-level technologies known now or developed thereafter. Furthermore, the memory cells may be manufactured in a two-dimensional or three-dimensional manner.

[0036] The interface located between the controller 102 and the non-volatile memory die 104 can be any suitable flash memory interface, such as switching modes 200, 400, or 800. In one embodiment, the storage system 100 can be a card-based system, such as a Secure Digital Card (SD) or a Micro Secure Digital (Micro SD) card. In another embodiment, the storage system 100 can be part of an embedded storage system.

[0037] Although Figure 1A In the example shown, the non-volatile memory system 100 (sometimes referred to herein as a memory module) includes a single channel between the controller 102 and the non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some memory system architectures (such as...) Figure 1B and Figure 1C In the architecture shown, there can be two, four, eight, or more memory channels between the controller and the memory device, depending on the controller's capabilities. In any of the embodiments described herein, even if a single channel is shown in the figures, more than one single channel can exist between the controller and the memory die.

[0038] Figure 1B A storage module 200 comprising multiple non-volatile storage systems 100 is illustrated. Similarly, the storage module 200 may include a storage controller 202 that interacts with a host and a storage system 204 comprising the multiple non-volatile storage systems 100. The interface between the storage controller 202 and the non-volatile storage systems 100 may be a bus interface, such as a Serial Advanced Technology Attachment (SATA), a Peripheral Component Rapid Interconnect (PCIe) interface, or a Double Data Rate (DDR) interface. In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), such as those found in server PCs or portable computing devices such as laptops and tablets.

[0039] Figure 1CThis is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes a plurality of storage controllers 202, each of which controls a corresponding storage system 204. A host system 252 can access memory within the storage system via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Fast (NVMe) or Fibre Channel Ethernet (FCoE) interface. In one embodiment, Figure 1C The system shown can be a rack-mountable mass storage system that can be accessed by multiple host computers, such as in a data center or other locations where mass storage is required.

[0040] Figure 2A This is a block diagram showing exemplary components of controller 102 in more detail. Controller 102 includes a front-end module 108 that interacts with a host, a back-end module 110 that interacts with one or more non-volatile memory dies 104, and various other modules that perform functions now described in detail. Modules may take the form of, for example, packaged functional hardware units designed for use in conjunction with other components, portions of program code (e.g., software or firmware) executable by a (micro)processor or processing circuitry that typically performs a specific function of the associated functions, or stand-alone hardware or software components that interact with a larger system.

[0041] Referring again to the module of controller 102, the buffer management / bus controller 114 manages the buffer in random access memory (RAM) 116 and controls the internal bus arbitration of controller 102. Read-only memory (ROM) 118 stores the system boot code. Although Figure 2A The RAM 116 and ROM 118 are shown positioned separately from the controller 102, but in other embodiments, one or both of them may be located within the controller. In yet another embodiment, portions of the RAM and ROM may be located both inside and outside the controller 102.

[0042] Front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provides an electrical interface to the host or next-level storage controller. The type of host interface 120 can be selected depending on the type of memory used. Examples of host interfaces 120 include, but are not limited to, SATA, SATA Express, Serial Attached Small Computer System Interface (SAS), Fibre Channel, Universal Serial Bus (USB), PCIe, and NVMe. Host interface 120 is typically used for transmitting data, control signals, and timing signals.

[0043] Back-end module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from non-volatile memory. Command sequencer 126 generates command sequences (such as programming and erasing command sequences) to be transmitted to non-volatile memory die 104. RAID (Redundant Array of Independent Drives) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to memory device 104. In some cases, RAID module 128 may be part of ECC engine 124. Memory interface 130 provides command sequences to and receives status information from non-volatile memory die 104. In one embodiment, memory interface 130 may be a double data rate (DDR) interface, such as a switching mode 200, 400, or 800 interface. Flash control layer 132 controls the overall operation of back-end module 110.

[0044] Storage system 100 also includes other discrete components 140, such as external electrical interfaces, external RAM, resistors, capacitors, or other components that can interact with controller 102. In alternative embodiments, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller 114 are optional components that are not required in controller 102.

[0045] Figure 2B This is a block diagram showing the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes peripheral circuitry 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells for storing data. The non-volatile memory cells can be any suitable non-volatile memory cells, including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 also includes a data cache 156 for caching data. The peripheral circuitry 141 includes a state machine 152 that provides status information to the controller 102.

[0046] Return again Figure 2AThe flash control layer 132 (which will be referred to herein as the flash translation layer (FTL), or more generally as the "media management layer," since the memory may not be flash) handles flash errors and interacts with the host. Specifically, the FTL (which may be an algorithm in the firmware) is responsible for the internals of memory management and translates writes from the host into writes to memory 104. An FTL may be necessary because memory 104 may have limited endurance, may only have a few pages written to it, and / or may not have any writes at all (unless it is erased as a block). The FTL understands these potential limitations of memory 104, which may not be visible to the host. Therefore, the FTL attempts to translate writes from the host into writes to memory 104.

[0047] The FTL may include a logical-to-physical address (L2P) mapping and an allocated cache memory. In this way, the FTL translates logical block addresses (“LBA”) from the host into physical addresses in memory 104. The FTL may include other features such as, but not limited to, power-off recovery (enabling the FTL’s data structures to recover in the event of a sudden power loss) and wear leveling (ensuring wear is evenly distributed across memory blocks to prevent some blocks from becoming excessively worn, which would lead to a greater chance of failure).

[0048] Returning to the attached image, Figure 3 This is a block diagram of a host 300 and a storage system 100 according to one embodiment. The host 300 can take any suitable form, including but not limited to a computer, mobile phone, tablet computer, wearable device, digital video recorder, surveillance system, etc. In this embodiment, the host 300 (e.g., a computing device) includes a processor 330 and a memory 340.

[0049] In some cases, volatile memory (e.g., RAM 116) in storage system 100 can be used as a cache for data and / or temporary data (e.g., data used during error handling or error correction, write data to be stored in non-volatile memory 104, etc.) that are otherwise stored in non-volatile memory 104 (e.g., logical-to-physical address mapping tables). However, since the amount of storage in volatile memory 116 is limited, space in volatile memory 116 may be exhausted, which can adversely affect the performance of storage system 100. In one embodiment, storage system 100 uses memory 340 in host 300 as an extension of volatile memory 116 in storage system 100. When memory 340 in host 300 is used for such purposes, it may be referred to as a “host memory buffer (HMB)”.

[0050] Figure 4 This illustrates how to establish a host memory buffer in one implementation scheme. For example... Figure 4 As shown, storage system 100 sends a request for the HMB to host 300 (action 410). In response to the request, host 300 allocates a storage location for the HMB in its memory 340 (action 420) and replies to the storage system's request using buffer information (e.g., the location and size of the allocated storage location) (action 430). The allocated memory becomes available to storage system 100 (action 440), and the HMB becomes available for use by storage system 100 (action 450). However, the host may remove the HMB from storage system 100 at any time (action 460).

[0051] In another embodiment, storage system 100 utilizes allocated unused host memory and uses that host memory at the HMB without requesting its use, or only when requesting its use. This embodiment... Figure 5 As shown in Figure 500. Figure 5 As shown, before host 300 sends a read request to storage system 100 to read data stored in memory 104 of the storage system, host 300 allocates a portion of its memory 340 to store the requested data after receiving it from storage system 100 (action 510). Then, host 300 sends the read request to storage system 100 (action 530). This request identifies the storage location allocated to storage system 100. For example, the request may include the location (e.g., address, offset) and size of the allocated storage location. With this information, storage system 100 knows how much space has been allocated and where that space is located.

[0052] Typically, the allocated space in host memory 340 remains idle until storage system 100 fills that space with data requested and returned to the host by host 300. However, this embodiment recognizes that the allocated memory is empty and available for use before the requested data is sent to host 300 (action 530). After storage system 100 receives a read request (action 540), the storage system knows the location of the allocated memory in host 300. Therefore, while processing read commands (e.g., during the process of reading data from memory 104 and / or processing (e.g., error correction) data) (action 550), storage system 100 can use the allocated memory as a host memory buffer, storing other data therein, until host 300 needs to use the allocated storage location to store the requested data. Unlike Figure 4In the embodiment shown, storage system 100 uses allocated space in host memory 340 without first requesting or requiring permission to use such space. After sending the requested data to host 300 (action 560), storage system 100 may send an acknowledgment to host 300 (action 570). In response to receiving the acknowledgment (action 580), host 300 uses the allocated storage location for another purpose or keeps it as free memory (action 590).

[0053] Storage system 100 may store any desired data in the "unrequested HMB". For example, other data may include data to be written to memory to improve write acknowledgment time. Typically, storage system 100 sends an acknowledgment to host 200 after receiving a write command and buffering it in the volatile memory 116 of the storage system before allocating the write data to non-volatile memory 104. Acknowledgment of the write command is delayed when there is insufficient immediately available space in volatile memory 116 to achieve this. The unrequested HMB can be used to store such data, thereby avoiding the delay in write command acknowledgment. Subsequently, when space becomes available in the volatile memory 116 of the storage system, the data can be read from the unrequested HMB and loaded into the volatile memory of the storage system. As another example, other data may include data used for reading error handling operations (e.g., temporary data, such as soft bits or XOR bits) or temporary data used in error correction mechanisms (e.g., temporary data generated in a low-density parity-checking (LDPC) mechanism). As yet another example, the other data could be part or all of a logical-to-physical address mapping table that is otherwise stored in the volatile memory 116 of the storage system. That is, in some cases, during a read operation, the flash translation layer (FTL) reads the mapping table into a temporary buffer that will not be used later. These tables can then be placed in the host memory 340 and overwritten with the requested data.

[0054] It should be noted that when an allocated storage location in host memory 340 needs to be used to store requested read data, other data stored in the unrequested HMB can be moved to another location (e.g., in host 300 or storage system 100). Alternatively, if the other data is temporary, it can be overwritten with the requested read data. Furthermore, when host 300 sends additional read requests to storage system 100, storage system 100 can use additional unrequested HMBs created by these rolling series of requests.

[0055] As can be seen from the examples above, there are many advantages associated with these implementations. These implementations can be used to reduce the size of the volatile memory required in storage system 100 and can improve the performance of some workloads. Other advantages of using these implementations include utilizing allocated but unused storage locations in the host (e.g., for communication with storage system 100 via a bus).

[0056] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices, such as dynamic random access memory (“DRAM”) or static random access memory (“SRAM”) devices, non-volatile memory devices, such as resistive random access memory (“ReRAM”), electrically erasable programmable read-only memory (“EEPROM”), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (“FRAM”), and magnetoresistive random access memory (“MRAM”), as well as other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in a NAND configuration or a NOR configuration.

[0057] The memory device can be formed from passive and / or active components in any combination. By way of non-limiting example, a passive semiconductor memory element includes a ReRAM device element, which in some embodiments includes resistivity-switching storage elements such as antifuse, phase-change materials, etc., and optionally includes guiding elements such as diodes. Further by way of non-limiting example, an active semiconductor memory element includes EEPROM and flash memory device elements, which in some embodiments include elements having charge storage regions, such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0058] Multiple memory elements can be configured such that they are connected in series or that each element can be accessed individually. By way of non-limiting example, a flash memory device (NAND memory) in a NAND configuration typically contains memory elements connected in series. A NAND memory array can be configured such that the array consists of multiple strings of memory, where a string consists of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured such that each element can be accessed individually, for example, in a NOR memory array. NAND memory configurations and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0059] Semiconductor memory elements located within and / or above a substrate can be arranged in two or three dimensions, such as two-dimensional or three-dimensional memory structures.

[0060] In a two-dimensional memory structure, semiconductor memory elements are arranged in a single plane or a single memory device level. Typically, in a two-dimensional memory structure, the memory elements are arranged in a plane (e.g., in the xz plane) that extends substantially parallel to the main surface of the substrate supporting the memory elements. The substrate may be a wafer on which layers of the memory elements are formed, or it may be a carrier substrate attached to the memory elements after they have been formed. As a non-limiting example, the substrate may include a semiconductor, such as silicon.

[0061] Memory elements can be arranged in a single memory device level in an ordered array (such as in multiple rows and / or columns). However, memory elements can be arranged in unconventional or non-orthogonal configurations. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0062] The three-dimensional memory array is arranged such that the memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0063] As a non-limiting example, a three-dimensional memory structure can be vertically arranged as a stack of multiple two-dimensional memory device levels. As another non-limiting example, a three-dimensional memory array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), wherein each column has multiple memory elements. The columns can be arranged in a two-dimensional configuration, for example, in the xz plane, resulting in a three-dimensional arrangement of the memory elements, where the elements are located on multiple vertically stacked memory planes. Other configurations of the three-dimensional memory elements can also constitute a three-dimensional memory array.

[0064] By way of non-limiting example, in a three-dimensional NAND memory array, memory elements may be coupled together to form NAND strings within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be coupled together to form vertical NAND strings spanning multiple horizontal memory device levels. Other three-dimensional configurations are conceivable, where some NAND strings contain memory elements within a single memory level, while others contain memory elements spanning multiple memory levels. The three-dimensional memory array can also be designed in NOR and ReRAM configurations.

[0065] Typically, in a monolithic three-dimensional memory array, one or more memory device classes are formed over a single substrate. Optionally, the monolithic three-dimensional memory array may also have one or more memory layers at least partially within the single substrate. As a non-limiting example, the substrate may include a semiconductor, such as silicon. In a monolithic three-dimensional array, the layer constituting each memory device class of the array is typically formed on the layer of the underlying memory device class of the array. However, the layers of adjacent memory device classes in a monolithic three-dimensional memory array may be shared or may have intervening layers between memory device classes.

[0066] Two-dimensional arrays can then be formed individually and then packaged together to form a non-monolithic memory device with multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory stages on separate substrates and then stacking the memory stages on top of each other. The substrates can be thinned or removed from the memory device stages before stacking, but since the memory device stages are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packaged together to form a stacked chip memory device.

[0067] Typically, associated circuitry is required to operate and communicate with the memory element. As a non-limiting example, a memory device may have circuitry for controlling and driving the memory element to perform functions such as programming and reading. This associated circuitry may be located on the same substrate as the memory element and / or on a separate substrate. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same substrate as the memory element.

[0068] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described herein, but covers all relevant memory structures as described herein and as understood by those skilled in the art to be of the spirit and scope of the invention.

[0069] The foregoing detailed description is intended to be understood as an illustration of the selected forms in which the invention may take place, and not as a definition of the invention. The scope of the claimed invention is intended to be defined only by the following claims (including all equivalents). Finally, it should be noted that any aspect of any embodiment described herein may be used alone or in combination with each other.

Claims

1. A storage system, the storage system comprising: Memory; and The controller is configured to: Receive a read request from the host for data stored in the memory. The read request identifies a storage location within the host allocated by the host for storage after the requested data is received from the storage system; and Before sending the requested data to the host: When the storage location is empty, awaiting requested data, and becomes available, the storage location in the host is used as an unrequested host memory buffer to store other data in the storage location in the host; and Before the requested data overwrites the other data, the other data from the storage location is stored in another storage location.

2. The storage system according to claim 1, wherein, The read request identifies the location and size of the storage location in the host.

3. The storage system according to claim 1, wherein, The controller is configured to store the other data in the storage location on the host while processing the read request.

4. The storage system according to claim 1, wherein, The other data includes data to be written into the memory.

5. The storage system according to claim 1, wherein, The other data includes data used for reading error handling operations.

6. The storage system according to claim 1, wherein, The other data includes mapping tables.

7. The storage system according to claim 1, wherein, The other data includes the data used in the error correction mechanism.

8. The storage system according to claim 1, wherein, The memory includes a three-dimensional memory.

9. A method, the method comprising: Perform the following operations in a storage system that includes memory: Receives a read request from the host for data stored in the memory, wherein the read request identifies a storage location in the host allocated by the host for storage after the requested data is received from the storage system; as well as Before sending the requested data to the host: When the storage location is empty, awaiting requested data and becoming available, the storage location in the host is used as an unrequested host memory buffer to store other data in the storage location in the host. as well as Before the requested data overwrites the other data, the other data from the storage location is stored in another storage location.

10. The method according to claim 9, wherein, The other data includes data to be written into the memory.

11. The method according to claim 9, wherein, The other data includes data used for reading error handling operations.

12. The method according to claim 9, wherein, The other data includes mapping tables.

13. The method according to claim 9, wherein, The other data includes the data used in the error correction mechanism.

14. The method of claim 9, wherein the other data is stored in the storage location in the host while the read request is being processed.

15. The method according to claim 9, wherein, The memory includes a three-dimensional memory.

16. A storage system, the storage system comprising: Memory; A means for receiving from a host a read command for data stored in the memory, wherein the read request identifies a storage location in the host allocated by the host for storing the requested data after it has been received from the storage system; A means for using the storage location in the host as an unrequested host memory buffer to store other data in the storage location in the host when the storage location is empty, awaiting requested data and becoming available; And means for storing the other data from the storage location in another storage location before the requested data overwrites the other data.

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