Multi-level non-volatile memory device based on silicon-silicon dioxide-silicon nitride-silicon dioxide-silicon and method of operating the same

Abstract

A semiconductor device comprising: a non-volatile memory (NVM) array based on semiconductor-silicon dioxide-silicon nitride-silicon dioxide-semiconductor (SONOS), the non-volatile memory (NVM) array including NVM cells arranged in rows and columns, wherein NVM transistors of the NVM cells are configured to store drain currents (Id) corresponding to the NVM transistors. D ) or threshold voltage (V T The system includes: Nx analog values ​​at each level; a digital-to-analog (DAC) function that receives and converts digital signals from external devices; a column multiplexer (mux) function that is configured to select and combine analog values ​​read from the NVM unit; and an analog-to-digital (ADC) function that is configured to convert the analog result of the column multiplexer function into a digital value and output the digital value.

Description

[0001] Cross-reference to related applications

[0002] This application is an international application of U.S. Non-Provisional Application No. 16 / 827,948, filed March 24, 2020, which claims the benefit of U.S. Provisional Application No. 62 / 940,547, filed November 26, 2019, pursuant to 35 USC §119(e), the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to non-volatile memory devices, and more particularly to multi-level charge-trapping non-volatile memory (NVM) devices based on silicon (semiconductor)-silicon dioxide-silicon nitride-silicon dioxide-silicon (semiconductor) (SONOS) for analog operation, including neuromorphic computing in artificial intelligence (AI) applications. Background Technology

[0004] Non-volatile memory is widely used to store data in computer systems and typically comprises memory arrays with a large number of memory cells arranged in rows and columns. In some implementations, each of the memory cells may include at least a non-volatile element, such as a charge-trapping field-effect transistor (FET) or a floating-gate transistor, which is programmed or erased by applying a voltage of appropriate polarity, amplitude, and duration between the control gate / memory gate and the substrate or the drain / source region. For example, in an n-channel charge-trapping FET, a positive gate-to-substrate voltage bias causes electrons to tunnel through the channel via Fowler-Nordheim (FN) tunneling and be trapped in the charge-trapping dielectric layer, thereby increasing the threshold voltage (V) of the transistor. T A negative gate-to-channel voltage causes holes to tunnel through the channel and be trapped in the charge-trapping dielectric layer, thereby reducing the Vo of the SONOS transistor. T .

[0005] In some implementations, a SONOS-based memory array is utilized and operated as a digital data storage device, wherein two different V's based on SONOS cells are used. T or drain current (I D The binary bits (0 and 1) of the level or value are stored.

[0006] For analog memory and processing, NVM technology, such as SONOS, is required because they offer configurable multiple V's with achievable high precision. T and I D(More than two) levels. SONOS memory cells deliver the low latency, power, and noise operations desired by analog processing, including edge inference computing, such as neuromorphic computing in artificial intelligence (AI) applications.

[0007] Therefore, the object of this invention is to provide optimized bias conditions, operation (erase, program, disable, etc.) sequences, and SONOS-based analog NVM devices and systems to achieve fine-grained NVMs with dense and dissimilar distributions (low-distribution sigma "σ"). T / I D Horizontal tuning. Attached Figure Description

[0008] The invention will be more fully understood from the following detailed description and from the accompanying drawings and claims, in which:

[0009] Figure 1A This is a block diagram showing a cross-sectional side view of a SONOS-based non-volatile memory transistor or device;

[0010] Figure 1B It shows Figure 1A A corresponding schematic diagram of a SONOS-based non-volatile memory transistor or device is depicted in the diagram.

[0011] Figure 2 This is a schematic diagram illustrating a SONOS-based non-volatile memory array according to one embodiment of the present disclosure;

[0012] Figure 3A This is a schematic diagram of a segment of a SONOS-based non-volatile memory array illustrating an implementation of an erase operation according to the present disclosure;

[0013] Figure 3B This is a schematic diagram illustrating a segment of a SONOS-based non-volatile memory array according to an implementation of programming / disabling operations in accordance with this disclosure;

[0014] Figure 4 This is a representative diagram showing the distribution of threshold voltages and drain currents of memory transistors in a SONOS-based non-volatile memory array according to an embodiment of the present disclosure, after programming (Vtp and Idp) and erasing (Vte and Ide).

[0015] Figure 5 This illustrates the drain current (Id) in a multi-level SONOS-based non-volatile memory cell according to an embodiment of this disclosure. D A representative diagram of the horizontal distribution;

[0016] Figure 6This illustrates different I-type memory transistors in a SONOS-based memory array according to an embodiment of this disclosure. D Horizontal diagram;

[0017] Figure 7A This is a diagram illustrating the distribution of trapped charge in the charge trapping layer of a SONOS-based memory transistor in a non-volatile memory array according to an embodiment of the present disclosure.

[0018] Figure 7B This illustrates the I-type of a SONOS-based memory transistor in a non-volatile memory array according to an embodiment of this disclosure. D The distribution diagram shows I D Sigma and retention degradation;

[0019] Figure 8A This is a schematic diagram of a segment of a SONOS-based non-volatile memory array illustrating an implementation of a selective soft erase operation according to the present disclosure.

[0020] Figure 8B This is a schematic diagram illustrating a segment of a SONOS-based non-volatile memory array according to an implementation of refill programming / disable operation according to the present disclosure;

[0021] Figure 9A and Figure 9B This is a schematic flowchart illustrating an implementation of a write operation for a multi-level SONOS-based NVM array according to the present disclosure;

[0022] Figure 10 This illustrates the different I during write operations of SONOS-based memory transistors in a non-volatile memory array according to an embodiment of this disclosure. D A graph showing the level decreasing / increasing;

[0023] Figure 11 This is a schematic flowchart illustrating an implementation of a write operation for a multi-level SONOS-based NVM array according to the present disclosure;

[0024] Figure 12 This is a schematic flowchart illustrating an implementation of a refill / annealing operation for a multi-level SONOS-based NVM array according to the present disclosure;

[0025] Figure 13 This is a schematic block diagram illustrating an implementation of a multi-level SONOS-based NVM device according to the present disclosure;

[0026] Figure 14 This is a representative block diagram illustrating an implementation of a conventional digital multiply-accumulate (MAC) system;

[0027] Figure 15 This is a representative diagram illustrating an implementation of artificial neurons in a deep neural network (DNN) system;

[0028] Figure 16 This is a schematic diagram illustrating an embodiment of a simulated neural network (NN) accelerator device according to the present disclosure; and

[0029] Figure 17 It is shown Figure 16 A schematic flowchart illustrating an implementation method for operating the NN accelerator device. Detailed Implementation

[0030] The following description sets forth numerous specific details, such as examples of specific systems, components, methods, etc., to provide a better understanding of several embodiments of the subject matter. However, it will be apparent to those skilled in the art that at least some embodiments can be practiced without these specific details. In other instances, well-known components or methods have not been described in detail or presented in a simple block diagram format to avoid unnecessarily obscuring the techniques described herein. Therefore, the specific details set forth below are merely exemplary. Specific implementations may differ from these exemplary details and are still considered to be within the spirit and scope of this subject matter.

[0031] Unless otherwise specifically stated, it should be understood from the following discussion that throughout the specification, the use of terms such as “processing,” “calculation,” “operation,” and “determining” refers to the actions and / or processes of a computer or computing system or similar electronic computing device that manipulate data represented as physical (e.g., electronic) quantities in the registers and / or memory of the computing system and / or convert that data into other data similarly represented as physical quantities in the memory, registers, or other such information storage, transmission, or display devices of the computing system.

[0032] Topic Overview

[0033] According to one embodiment of a method of operating a semiconductor device, the method may include the following steps: obtaining a semiconductor device including multi-level memory transistors arranged in rows and columns, wherein the multi-level memory transistors include charge trapping transistors based on silicon-silicon dioxide-silicon nitride-silicon dioxide-silicon (SONOS), the charge trapping transistors being configured to store data corresponding to a threshold voltage (V). T ) and drain current (I DOne of Nx analog values ​​at N levels, where N is a natural number greater than 2; at least one of the multilevel memory transistors is selected for the write process of the target value, where the target value is one of the Nx analog values ​​and corresponds to the value from the target I. D The lower bound (LL) extends to target I. D Target I of Upper Limit (UL) D Scope; Perform partial programming operations on at least one of the multi-level memory transistors to reduce IT D The level, where a first verification read is performed after a partial programming operation to determine the reduced I. D Level and Target I D How are the average values ​​compared? A partial erase operation is performed on at least one of the multi-level memory transistors to improve IL. D The level, where a second verification read is performed after a partial erase operation to determine the increased I. D Level and Target I D How are the average values ​​compared? And when at least one of the multi-level memory transistors has an I... D When the value falls within the target ID range, the writing process to the target value is considered complete.

[0034] In one embodiment, the method may further include the step of: after the writing process of the target value is completed, prohibiting at least one of the multilevel memory transistors from performing further programming and erasing operations, wherein the prohibition includes reducing the magnitude of the gate-to-drain voltage or the gate-to-substrate voltage of at least one of the multilevel memory transistors.

[0035] In one implementation, the partial programming operation may include at least one of a soft programming operation and a refill programming operation, wherein the partial programming operation may be configured to reduce the IT of at least one of the multi-level memory transistors. D Level and increase the V of at least one of the multi-level memory transistors T The level, and within it, multi-level memory transistors that are not selected for some programming operations, can be disabled.

[0036] In one implementation, some programming operations can be performed in a much shorter duration compared to programming operations, wherein the programming operations can be configured to control the I / O of multi-level memory transistors. D Level reduced to fully programmed I D Horizontal, regardless of the initial I of the multi-level memory transistor D level.

[0037] In one embodiment, the partial erase operation may include at least one of a soft erase operation, a selective soft erase operation, and an annealing erase operation, wherein the partial erase operation may be configured to increase the Ig of at least one of the multi-level memory transistors. D Leveling and reducing the V of at least one of the multi-stage memory transistors T The level, and within it, multilevel memory transistors not selected for selective soft erase operations can be disabled.

[0038] In one implementation, soft erase operations and selective soft erase operations can be performed in a much shorter duration compared to erase operations, wherein the erase operation can be configured to move the I / O pins of multi-level memory transistors. D Level increased to complete erasure I D Horizontal, regardless of the initial I of the multi-level memory transistor D What is their skill level?

[0039] In one implementation, the annealing erase operation can be performed over a much longer duration than the erase operation, and wherein, compared to the annealing erase operation, the gate-to-drain voltage or gate-to-substrate amplitude of at least one of the multi-level memory transistors can be greater during the erase operation.

[0040] In one embodiment, the method may further include a refill and annealing algorithm, which includes the steps of: performing a soft erase operation on at least one of the multi-level memory transistors after the writing process to the target value is completed; verifying I D Has the level reached at least target I? D +X% level, where X is in the range of 20 to 50; perform a refill programming operation on at least one of the multi-level memory transistors; verify I D Has the level reached the target I at most? D -Y% level, where Y is in the range of 10 to 20; perform an annealing erase operation on at least one of the multi-level memory transistors; verify the I of each of at least one of the multi-level memory transistors. D Level; make selection and only for I D Level less than target I D At least one of the multi-level memory transistors in LL performs a selective soft erase operation and disables unselected multi-level memory transistors; and verifies the I of at least one of the multi-level memory transistors. D Has the level recovered to target I? D Within the horizontal range.

[0041] In one implementation, the refill and annealing algorithm can be configured to, in the case of replacing the charge in the shallow traps with the charge in the deep traps of the charge trapping layer of at least one of the multi-level memory transistors, reduce the It of the multi-level memory transistors to the It of the shallow traps. D Level maintained at target I D The range, wherein a refill programming operation can facilitate deep trap charges by applying a high gate-to-drain voltage and a short programming pulse to at least one of the multilevel memory transistors, and wherein an annealing erase operation can be configured to clear shallow trap charges by applying a low gate-to-drain voltage and a long erase pulse to at least one of the multilevel memory transistors via Fowler-Nordheim tunneling.

[0042] In one implementation, at least one of the multi-level memory transistors may be arranged in the same row or the same column.

[0043] According to one embodiment of a method of operating a semiconductor device, the method may include the steps of: selecting a first NVM cell of a SONOS-based NVM array for a selective soft erase operation, wherein the SONOS-based NVM array includes NVM cells arranged in rows and columns, and wherein adjacent first and second column NVM cells are coupled to a first shared source line; generating a first negative voltage and coupling the first negative voltage to a first SONOS word line in a first row of the SONOS-based NVM array, and generating a positive voltage and coupling the positive voltage to a first bit line in a first column, to apply a gate-to-drain voltage bias to a first NVM transistor in the first NVM cell, thereby partially erasing the first NVM cell through Fowler-Nordheim (FN) tunneling, wherein the drain current (Id) of the first NVM transistor is... D Level and threshold voltage (V) T The levels are respectively increased and decreased; and a disable voltage is coupled to a second bit line in the second column to reduce the gate-to-drain voltage bias of the second NVM transistor in the second NVM cell in the first row that is not selected for selective soft erase operation, wherein the disable voltage has the same polarity as the first negative voltage and a smaller magnitude than the first negative voltage, and wherein the second NVM transistor has approximately the same I before and after the selective soft erase operation. D and V T level.

[0044] In one embodiment, the method may further include the step of coupling a ground voltage to a second SONOS word line in the second row of the SONOS-based NVM array to prevent all NVM cells in the second row from being selected for selective soft erase operations.

[0045] In one embodiment, the method may further include the steps of: generating a second negative voltage and coupling it to a first word line in the first row and a shallow positive well (SPW) node of a SONOS-based NVM array to turn off a first field-effect transistor (FET) in the first NVM cell and a second FET in the second NVM cell, wherein the second negative voltage has an amplitude smaller than the first negative voltage; and coupling a positive voltage to a deep negative well (DNW) node.

[0046] In one embodiment, each of the NVM cells may include an NVM transistor configured to store a signal corresponding to I. D Horizontal and V T One of Nx values ​​for the level, where N is a natural number greater than 2, and wherein the selective soft erase operation can be configured to increase the Ig of the first NVM transistor. D Horizontal and reduced V of the first NVM transistor T The level is such that the value stored in the first NVM transistor changes from a first value to a second value, wherein the second value can be greater than the first value.

[0047] In one implementation, I D and V T Each of the Nx levels can include a distribution, where two adjacent I D or V T The distribution can have an overlap frequency of less than 3%, and in which I D and V T The Nx levels can be linearly increasing or decreasing respectively.

[0048] According to one embodiment of a semiconductor device, the device may include: a SONOS-based NVM array comprising NVM cells arranged in rows and columns, wherein each NVM cell may include an NVM transistor and a field-effect transistor (FET), and wherein each NVM transistor may be configured to store a drain current (Id) corresponding to each NVM transistor. D ) or threshold voltage (V T The system comprises: Nx analog values ​​at a given level; a digital-to-analog converter (DAC) functional element that receives and converts digital signals from an external device, wherein the converted digital signals can be configured to read analog values ​​stored in at least one NVM cell in at least one column; a column multiplexer (mux) functional element configured to select and combine analog values ​​read from at least one NVM cell; and an analog-to-digital converter (ADC) functional element configured to convert the analog result of the column multiplexer function into a digital value and output the digital value.

[0049] In one implementation, Nx analog values ​​can be written to an NVM transistor via a series of partial programming and selective partial erasure operations, wherein the selective partial erasure operation can be configured to increase the Ig of a selected NVM transistor in the same row. D Horizontal and downward V of the selected NVM transistor in the same row T The horizontal and parallel disabling of unselected NVM transistors in the same row.

[0050] In one implementation, a read operation is performed after each of the partial programming and selective partial erase operations to verify the I0 of the selected NVM transistor. D or V T Has the level reached target I? D and V T level.

[0051] In one implementation, multiple semiconductor devices may be disposed on the same semiconductor die and coupled to each other, and each of the multiple semiconductor devices may be configured to perform a multiply-accumulate (MAC) operation based on an analog value stored in an NVM cell and a digital input from at least one other semiconductor device among the multiple semiconductor devices.

[0052] In one embodiment, a first subset of a plurality of semiconductor devices outputs a digital result of a MAC operation, and wherein the digital result of the first subset is coupled as a digital input to a second subset of the plurality of semiconductor devices.

[0053] In one implementation, multiple semiconductor devices can be configured as artificial neurons in a deep neural network (DNN) that performs neuromorphic computing in artificial intelligence (AI) applications. Detailed Implementation

[0055] Figure 1A This is a block diagram showing a cross-sectional side view of a non-volatile memory cell, and its corresponding schematic diagram is depicted in... Figure 1B In the context of non-volatile memory (NVM) arrays or devices, there may be NVM cells having non-volatile memory transistors or devices implemented using silicon (semiconductor)-silicon dioxide-silicon nitride-silicon dioxide-silicon (semiconductor) (SONOS) or floating gate technology, and conventional field-effect transistors (FETs) arranged adjacent to or coupled to each other.

[0056] In one implementation, such as Figure 1A As shown, the non-volatile memory transistor is a SONOS-type charge-trapping non-volatile memory transistor. (Refer to...) Figure 1AThe NVM cell 90 includes a control gate (CG) or memory gate (MG) stack of NV transistors 94 formed above the substrate 98. The NVM cell 90 also includes source 97 / drain 88 regions formed within a shallow positive well (SPW) 93 on either side of the NV transistor 94, formed in or optionally within the substrate 98. The SPW 93 may be at least partially encapsulated within a deep negative well (DNW) 99. In one embodiment, the source / drain regions 88 and 97 are connected via a channel region 91 beneath the NV transistor 94. The NV transistor 94 includes an oxide tunnel dielectric layer forming an ONO stack, a nitride or oxynitride charge trapping layer 92, an oxide top layer, or a barrier layer. In one embodiment, the charge trapping layer 92 may be multilayered and traps charges injected from the substrate 98 via FN tunneling. The V of the NV transistor 94... T and I D The value can change at least partially due to the amount of trapped charge. In one embodiment, the high-k dielectric layer can form at least a portion of the barrier layer. The polysilicon or metal gate layer covering the ONO layer can be used as the control gate (CG) or the memory gate (MG). Figure 1A As best illustrated, the NVM cell 90 also includes a FET 96 disposed adjacent to the NV transistor 94. In one embodiment, the FET 96 includes a metal or polysilicon select gate (SG) disposed over an oxide or high-k dielectric gate dielectric layer. The FET 96 also includes source / drain regions 86 and 97 formed on either side of the FET 96 within a well 93 formed in or optionally in the substrate 98. Figure 1A As best shown, FET 96 and NV transistor 94 share a source / drain region 97, also known as an internal node 97, located between them. SG is appropriately biased by V. SG To open or close the channel 95 below the FET 96. For example... Figure 1A As shown, the NVM unit 90 is considered to have a dual-transistor (2T) structure, wherein the NV transistor 94 and the FET 96 can be considered as a memory transistor and a selection or transmission transistor, respectively, throughout this patent document.

[0057] In one implementation method Figure 1B A dual-transistor (2T) SONOS NVM cell 90 with a non-volatile (NV) transistor 94 connected in series with a FET 96 is depicted. When V CGWhen the CG is properly biased or when a positive pulse is applied to the CG relative to the substrate 98 or the well 93, causing electrons to be injected from the inversion layer into the charge trapping layer 92 via FN tunneling, the NVM cell 90 is programmed (bit value "1"). The charge trapped in the charge trapping layer 92 causes the electrons between the drain 88 and the source 97 to be depleted, thereby increasing the threshold voltage (V) required to turn on the SONOS-based NV transistor 94. T This puts the device into a "programming" state. This is achieved by applying an opposite bias V to the CG. CG Alternatively, a negative pulse is applied to the CG relative to the substrate 98 or the well 93, causing holes FN from the accumulation channel 91 to tunnel into the ONO stack to erase the NVM cell 90. The programming threshold voltage and the erase threshold voltage are referred to as "Vtp" and "Vte," respectively. In one embodiment, the NV transistor 94 can also be in an inhibited state (bit value "0"), wherein, while the control gate (CG) is pulsed positive relative to the substrate 98 or the well 93 (as in programming conditions), programming of the previously erased cell (bit value "0") is inhibited (bit value "1") by applying positive voltages to the source and drain of the NVM cell 90. The threshold voltage of the NV transistor 94 (referred to as "Vtpi") becomes slightly more positive due to the interference vertical field, but it remains erased (or inhibited). In one embodiment, Vtpi is also determined by the ability of the charge trapping layer 92 of the ONO stack to retain the trapped charges (holes in the erased state) in the charge trapping layer 92. If the charge trap is shallow, the trapped charge tends to dissipate, and the Vtpi of the NV transistor 94 becomes more positive. In one embodiment, the Vtpi of the NV transistor 94 tends to decay or ramp up with further disable operation. It will be understood that the assignment of bit values ​​or binary values ​​“1” and “0” to the corresponding “programming” and “erasing” states of the NVM cell 90 herein is for illustrative purposes only and is not to be construed as limiting. In other embodiments, the assignment may be reversed or have other arrangements. In another embodiment, as will be described in detail in later sections, the NVM cell 90 may be configured to store one of a plurality of analog values ​​(in addition to “0” and “1”) by manipulating their threshold voltage or drain current levels.

[0058] In another embodiment, the NV transistor 94 may be a floating-gate MOS field-effect transistor (FGMOS) or a device. Typically, an FGMOS is structurally similar to the SONOS-based NV transistor 94 described above, the main difference being that the FGMOS includes a polysilicon floating gate capacitively coupled to the input of the device, instead of a nitride or oxynitride charge trapping layer 92. Therefore, reference can be made to… Figure 1A and Figure 1B Describe an FGMOS device, and explain how an FGMOS device can be operated in a similar manner.

[0059] Similar to the SONOS-based NV transistor 94, an FGMOS device can be programmed by applying an appropriate bias V between the control gate and the source and drain regions. CG This increases the threshold voltage V required to turn on the FGMOS device. T This can be achieved by applying an opposite bias V to the control gate. CG To erase the FGMOS device.

[0060] In one implementation, the source / drain region 86 can be considered the "source" of the NVM cell 90 and coupled to V. SL The source / drain region 88 can be considered as the "drain" and coupled to V. BL Optionally, SPW 93 and V SPW Coupled and DNW 99 with V DNW Coupled.

[0061] FET 96 prevents hot carrier electron injection and junction breakdown during programming or erasing operations. FET 96 also prevents large currents from flowing between the source 86 and drain 88, which could lead to high power consumption and parasitic voltage drops in the memory array. For example... Figure 1A As best illustrated, both FET 96 and NV transistor 94 can be n-type transistors or n-channel transistors, wherein the source / drain regions 86, 88, 97 and DNW 99 are doped with n-type material, while SPW 93 and / or substrate 98 are doped with p-type material. It will be understood that NVM cell 90 may also additionally or alternatively include p-type transistors or p-channel transistors, wherein the source / drain regions and wells may be doped differently or in reverse, according to the practice of those skilled in the art.

[0062] Memory arrays are constructed by fabricating a grid of memory cells, such as NVM cells 90. The memory cells are arranged in rows and columns and connected to peripheral circuitry, such as address decoders and comparators, such as analog-to-digital converter (ADC) and digital-to-analog converter (DAC) functional elements, via multiple horizontal and vertical control lines. Each memory cell includes at least one non-volatile semiconductor device (such as those described above) and may have a single-transistor (1T) architecture or, as... Figure 1A The dual-transistor (2T) architecture described in the document.

[0063] Figure 2 This is a schematic diagram illustrating an NVM array according to one embodiment of this subject matter. In one embodiment, such as Figure 2As shown, memory cell 90 has a 2T architecture and, in addition to non-volatile memory transistors, memory cell 90 also includes transfer or select transistors, such as conventional MOSFETs sharing a common substrate connection or internal node with the memory transistors. In one embodiment, NVM array 100 includes NVM cells 90 arranged in N rows or N pages (horizontal) and M columns (vertical). NVM cells 90 in the same row can be considered to be in the same page. In some embodiments, multiple rows or multiple pages can be combined to form memory sectors. It should be understood that the terms "row" and "column" in memory array are used for illustrative and not limiting purposes. In one embodiment, rows are arranged horizontally and columns are arranged vertically. In another embodiment, the terms row and column in memory array can be reversed or used in the opposite sense, or arranged in any orientation.

[0064] In one implementation, SONOS word lines (WLS) are coupled to all CGs of NVM cells 90 in the same row, and word lines (WL) are coupled to all SGs of NVM cells 90 in the same row. In one implementation, bit lines (BL) are coupled to all drain regions 88 of NVM cells 90 in the same column, while common source lines (CSL) or regions 86 are coupled between or shared among all NVM cells in the array. In an alternative implementation, CSL can be between two pairs of NVM cells in the same row—for example, as shown in the image. Figure 3A C1 and C2 are best shown in the diagram—shared between them. CSL is also coupled to the shared source pole region of all NVM pairs in the same two columns.

[0065] In flash mode, a write operation can include a batch erase operation on selected rows (pages), followed by a programmable or disable operation on individual cells within the same row. The smallest NVM cell block that can be erased at once is a single page (row). The smallest cell block that can be programmed / disabled at once can also be a single page.

[0066] Reference Figure 2 The NVM units 90 can be arranged in pairs, such as NVM unit pair 200. In one embodiment, as... Figure 3A , Figure 3B , Figure 8A and Figure 8B As best illustrated, the NVM cell pair 200 includes two NVM cells 90 with mirror orientation, such that the selection transistors of each NVM cell, such as C1 and C2, are arranged adjacent to each other. The NVM cells 90 of the same NVM cell pair 200 can also share the received voltage signal V. CSL The public source polar region.

[0067] Figure 3AA 2×2 array 300 of NVM array 100 is shown to illustrate an implementation of an erase or hard erase operation according to this disclosure. As previously described, NVM array 100 may employ a common source line (CSL) configuration. In one embodiment, a single CSL (e.g., CSL0) is shared between all NVM cells in the NVM array or at least between NVM cells in adjacent columns (e.g., C1 and C2). In one embodiment, a CSL may be provided and shared between the selection transistors of NVM cells 90 in adjacent columns. In the following description, for clarity and ease of illustration, it is assumed that all transistors in the NVM array 100 comprising the 2×2 array 300 are N-type transistors. It should be appreciated that, without loss of generality, a P-type configuration can be described by reversing the polarity of the applied voltage, and such a configuration is within the contemplated implementation of this disclosure. Additionally, the voltages and pulse durations used in the following description are chosen for ease of illustration and represent only one exemplary implementation of the subject matter. Other voltages may be used in different implementations.

[0068] Figure 3A An exemplary implementation of a segment of an NVM array 100 is shown, which may be part of a large memory array of memory cells. Figure 3A In this 2×2 memory array 300, at least four memory cells C1, C2, C3, and C4 are arranged in two rows and two columns. While NVM cells C1 to C4 can be located in two adjacent columns (common source line CSL0), they can also be located in two adjacent rows or two non-adjacent rows. Each of the NVM cells C1 to C4 can be structurally similar to the NVM cell 90 described above.

[0069] Each of the NVM cells C1 through C4 may include a SONOS-based memory transistor and a select transistor. Each memory transistor includes a drain coupled to a bit line (e.g., BL0 and BL1), a drain coupled to a select transistor, and a source coupled to a single common source line (e.g., CSL0) via the select transistor. Each memory transistor also includes a control gate coupled to a SONOS word line (e.g., WLS0). Each select transistor includes a source coupled to a common source line (e.g., CSL0) and a select gate coupled to a word line (e.g., WL0).

[0070] Reference Figure 3AFor example, in an erase operation, page 0 is selected to be erased while page 1 is not (unselected) to be erased. As previously mentioned, a single page can be the smallest block of NVM cells 90 to be erased in a single operation. Therefore, all NVM cells in a row, including C1 and C2, are erased at once by applying an appropriate voltage to the SONOS word line (WLS0), substrate connections, and all bit lines in the NVM array 100 shared by all NVM cells in the selected row (page 0). In one embodiment, a negative voltage V NEG A positive voltage V is applied to WLS0. POS A full erase voltage (V) is applied to the substrate or p-well via the SPW and deep n-well DNW of all NVM cells in page 0, all bit lines including BL0 and BL1, and the common source line including CSL. Therefore, a full erase voltage (V) is applied between the substrate / p-well of the memory transistors in CG and C1 and C2. NEG -V POS The pulse duration is approximately 10 ms (Te) to erase any previously trapped charge (if any). In one implementation, all word lines, including WL0 and WL1, are coupled to the supply voltage V. PWR .

[0071] Still refer to Figure 3A When no page (row) is selected for the erase operation, such as page 1, a positive voltage V is applied to WLS1 instead. POS This results in the CG to the substrate / P-well of the memory transistors in page 1, including C3 and C4, being approximately 0 V (V). POS -V POS Therefore, the state of the NVM cell on page 1 remains unchanged (not erased).

[0072] Table I depicts exemplary bias voltages that can be used for bulk erase operations on pages / rows 0 of a non-volatile memory, similar to the 2×2 array 300, which has a 2T architecture and includes memory cells with N-type SONOS transistors and CSLs.

[0073] <![CDATA[ node ]]> <![CDATA[ Voltage (V) ]]> <![CDATA[ Voltage range (V) ]]> WLS0 <![CDATA[V NEG For example, -3.8 V]]> -4.0 V to -3.2 V BL0 <![CDATA[V POS For example, +4.2 V]]> +3.8 V to +4.6 V WL0 <![CDATA[V PWR For example, +1.1 V]]> +1.0 V to +1.2 V SPW <![CDATA[V POS For example, +4.2 V]]> +3.8 V to +4.6 V DNW <![CDATA[V POS For example, +4.2 V]]> +3.8 V to +4.6 V CLS0 <![CDATA[V POS For example, +4.2 V]]> +3.8 V to +4.6 V WLS1 <![CDATA[V POS For example, +4.2 V]]> +3.8 V to +4.6 V BL1 <![CDATA[V POS For example, +4.2 V]]> +3.8 V to +4.6 V WL1 <![CDATA[V PWR For example, +1.1 V]]> +1.0 V to +1.2 V

[0074] Table I

[0075] Figure 3B An exemplary implementation of a segment 2×2 array 300 of the NVM array 100 during programming or hard programming operations is shown. (Refer to...) Figure 3B For example, NVM cell C1 is the target cell to be programmed or written as a logic "1" state (i.e., programmed to be in a cutoff state), and may have already been programmed as follows: Figure 3AThe NVM cell C2, which was previously erased to a logic "0" state, is maintained in a logic "0" or on state. It should be understood that although C1 and C2 are shown as two adjacent cells for illustrative purposes, C1 and C2 could also be two separate NVM cells on the same row, such as row 0. These two objectives (programming C1 and disabling C2) are achieved by applying a first or positive high voltage (V... POS The second or negative high voltage (V) is applied to WLS0 in page or row 0 of the NVM array 100. NEG A voltage (V) is applied to BL0 to bias the memory transistor C1 when programming the selected memory cell, while simultaneously inhibiting the voltage (V). INHIB The memory transistor C2 is biased when programming of unselected memory cells is disabled by applying a common voltage to BL1 and DNW, applying a common voltage to the shared substrate or p-well SPW of all NVM cells, and coupling word lines (WL1 and WL2) to a second or negative high voltage (V). NEG In one implementation, the common source line CSL0 between C1 and C2 or between all NVM cells 90 can be at a third high voltage or CSL voltage (V). CSL (), or may be allowed to float. In one implementation, the third high voltage V CSL It can have less than V POS or V NEG The voltage level or absolute amplitude. In one implementation, V CSL It can be generated by its own dedicated circuitry system (not shown), including a DAC, within the memory device. V CSL It can have a margin voltage V MARG The voltage level or absolute magnitude is roughly the same, which will be discussed in more detail later. When V POS When the memory transistor is applied to C2 via WLS0, the positive V on BL1 INHIB The voltage is transferred to the channel of the memory transistor. This voltage reduces the gate-to-drain / channel voltage bias on the memory transistor of C2, thereby reducing the programming domain and making the threshold voltage offset from Vte smaller. The charge tunneling that may still occur is called suppression interference and is quantized as (Vte - Vtpi). In one implementation, due to the programming operation, all NVM cells of page 0, including C1 and C2, can obtain a binary state "1" (programmed -Vtp) or "0" (inhibited -Vtpi) based on the bit line voltage received by the NVM cell. NVM cells in unselected pages, such as page 1, can remain in a binary state "0" (erase -Vte).

[0076] Additionally, and as described in more detail below, the voltage level or absolute amplitude is less than V.NEG Selected margin voltage (V) MARG WLS1 is applied to unselected rows or pages (e.g., page 1) to reduce or substantially eliminate programming state bitline interference in unselected NVM cells C4 due to programming of the selected C1. In one implementation, V MARG The absolute voltage level or amplitude can be related to V CSL same.

[0077] Table II depicts exemplary bias voltages that can be used to program a non-volatile memory having a 2T architecture and including memory cells with N-type SONOS transistors and CSLs.

[0078] <![CDATA[ node ]]> <![CDATA[ Voltage (V) ]]> <![CDATA[ Voltage range (V) ]]> WLS0 <![CDATA[V POS For example, +4.2 V]]> +3.8 V to +4.6 V BL0 <![CDATA[V NEG For example, -3.8 V]]> -4.0 V to -3.4 V WL0 <![CDATA[V NEG For example, -3.8 V]]> -4.0 V to -3.4 V SPW <![CDATA[V NEG For example, -3.8 V]]> -4.0 V to -3.4 V DNW <![CDATA[V INHIB For example, +1.1 V]]> +1.0 V to +1.2 V CLS0 <![CDATA[Floating / V MARG For example -2.4 V]]> -3.0 V to -2.0 V WLS1 <![CDATA[V MARG For example, -2.4 V -3.0 V to -2.0 V BL1 <![CDATA[V INHIB For example, +1.1 V]]> +1.0 V to +1.2 V WL1 <![CDATA[V NEG For example, -3.8 V]]> -4.0 V to -3.4 V

[0079] Table II

[0080] Typically, margin voltage (V) MARG ) has a second high voltage or V NEG Same polarity, but margin voltage (V) MARG ) than V NEG Higher or corrected, the higher voltage must be at least equal to the threshold voltage (V) of the memory transistor for reduced programming state bit-line interference. T ).

[0081] Figure 4 The following diagram illustrates Vtp and Vte, as well as the programmed drain current (Itp) in an exemplary SONOS-based NVM array, such as NVM array 100. DP ) and the erased drain current (I DE Distribution. Typical write operations include, for example... Figure 3A The described erase or hard erase operation and subsequent actions, such as... Figure 3B The hard-programmed / disabled operation is described. In one implementation, after a reliable read operation, it can be determined that the NVM cell is in one of two distinct binary states ("0" or "1"). Figure 3A The erase operation described can also be considered a hard erase, because the erase operation causes the V of the NVM cells (e.g., C1 and C2) to be erased to change. T / I D Move to the erased V T / I D Horizontal (complete erasure), regardless of the initial V of these cells. T / I D What is the level of skill? Similarly, such as... Figure 3B The described programming operations can be considered hard programming operations. In one implementation, there may be no verification or read operations between the hard erase operation and the hard programming / disable operation.

[0082] Figure 5 This illustrates multiple different drain currents (Id) of NVM memory cells in a SONOS-based NVM simulation device according to one embodiment of the present disclosure. D A schematic diagram of the horizontal plane. In one embodiment, the I of the NVM cell can be determined or verified by applying a predetermined voltage to the CG of the SONOS transistor via WLS and reading via BL. D In other embodiments, I can be determined by other methods known and practiced in the art. D Similar to VT, in embodiments where the NVM array 100 is used as a digital memory device such as NOR flash memory, EEPROM, etc., the ID can be used to determine the binary state of the NVM cell 90. In other embodiments, the NVM array 100 can be utilized in an analog device by storing one of a plurality of (more than two) analog values. (See also...) Figure 4 and Figure 5 , instead of using Figure 3A and Figure 3B The hard programming and erase operations described herein write one of two binary values ​​("0" and "1") to NVM cell 90 of NVM array 100. A series of partial programming and partial erase operations can be used to write multiple (more than two) I... D Horizontal or V T The level (corresponding to the trapped charge in charge trapping layer 92). In an embodiment, partial programming and erasing operations can be configured to adjust the V of the target NVM cell by manipulating the voltage difference or bias applied to the CG and the drain or substrate, as well as the pulse duration. T / I D respectively to programmed V T / I D and erased V T / I D Move horizontally (or closer). Some programming and erasing operations may include, but are not limited to, soft programming operations, refill programming operations, soft erase (row) operations, selective soft erase (cell) operations, and annealed erase (row) operations, which will be further explained below.

[0083] In one implementation, such as Figure 5 As best illustrated, in the simulation configuration / mode, the NVM unit 90 can be configured according to its I D To represent or store 2 horizontally n One of the following values ​​(4, 8, 16, ..., 128, etc.), where n is a natural number greater than 1. In another embodiment, the NVM unit 90 can be configured to represent one of any number of values ​​greater than 2. In one embodiment, I D 1 to ID 2 n They are the first I D Distributed to the 2nd n Personal I D The average I of the distribution D Value. In each I D In the distribution, there can exist I D Lower limit and I D Upper limit (see I) D 1). First I D The distribution can be similar to Figure 4 The programmed unit distribution σ3 in the second I D Distribution similar to Figure 4 The erased cell distribution σ4 is shown in the figure. In an implementation, the average I can be predetermined based on system design and requirements. D Level or average V T The level and its upper and lower limits. In one implementation, the operation I of the NVM array 100. D The range can be approximated as (I) D 2n to I D 1), and as an example (1.60 μA - 50 nA = 1550 nA). It should be understood that 1550 nA of I... D The range is merely an example and can be any other value depending on the NVM cell, operating voltage, pulse duration, and system requirements / design. In one implementation, this is achieved by writing the NVM cell 90 to operation I. D Specific I within the range (e.g., 1.60 μA to 50 nA) D Horizontally, the NVM array 100 can be used as an analog memory device. In one embodiment, those skilled in the art will understand that the same concept can be applied to writing multiple (more than two) V... T level.

[0084] In one implementation, in order to achieve limited operation I D Multiple different I within the range D Level, may require each I D The distribution has a close distribution (low sigma σ), such that adjacent I D The distributions are clearly separated, especially when n is a high number. Different levels of I D It can also increase linearly, such that ΔI D exist Figure 5 The IT value is approximately constant for accurate and efficient read / verification operations. SONOS-based units, such as the NVM unit 90, benefit from their inherently low IT value. D / V T Sigma and Low Power (V)CC =0.81 V-1.21 V) makes it a good candidate for analog memory with multiple levels. Furthermore, since FN tunneling is used to perform both programming and erasing operations (hard and soft) in SONOS-based cells, very fine I / O with very low sigma can be achieved. D / V T Horizontal tuning. Furthermore, SONOS-based units are tuned at -40°C. o C to 125 o After cycling at 100 K within the C temperature range, it exhibits high robustness and minimal degradation, meeting the needs of most consumer, industrial, and automotive applications. In one implementation, adjacent I... D I overlapping between distributions D Value 502. To reliably and accurately read the I... D Level, I D The distributed sigma σ can be reduced to approximately below 8 nA or other current values, such that the overlapping region 502 is kept below 1% to 3% of the distribution. According to I... D The sigma between levels can be higher or lower. In some cases, a sigma of 50 nA may be sufficient to keep the overlap area below 1% to 3% of the distribution.

[0085] Figure 6 This illustrates 16 (2) NVM units according to one embodiment of the present disclosure. 4 ) individual I D A horizontal diagram. For example... Figure 6 As best shown in the middle, I D The levels are distinct, well-separated (low sigma), and incrementally linear to maintain the high functionality of the multi-level NVM unit as an analog device.

[0086] As previously explained, conventional write sequences, such as hard erase and hard program sequences, may not be precise enough to handle a specific I in multiple (more than two) levels. D / V T Horizontal writing is performed to the NVM cell. In one implementation, a sequence of hard programming, hard erasing, partial programming, and partial erasing operations can be used to precisely write the I0 data to the NVM cell. D / V T Write horizontally to an NVM cell, such as NVM cell 90.

[0087] Figure 7A This is a schematic diagram illustrating the trap density distribution from the valence band to the conduction band in the charge trapping nitride layer of a SONOS transistor according to the present disclosure. Figure 7B It is shown that due to I Dand retain degradation for I in multi-level NVM cells D A graph illustrating the potential impact of the distribution. While the lifetime start (BOL) sigma of the SONOS transistor 94 may be very low, significant degradation can occur over time during storage, particularly at high temperatures. Therefore, I D Distribution (e.g., I) D 1 and I D 2) It can be distributed more widely (increased sigma), and adjacent I D Distribution can have Figure 7B More overlapping portions 710 (e.g., greater than 3%) in the layer can lead to incorrect / erroneous readings of levels or values. In one implementation, sigma degradation may be due to the loss of trapped charges in the "shallow" traps in the nitride layer 92 during retention, while trapped charges in the "deep" traps remain trapped. Loss of trapped charges during retention may also cause I D Horizontal upward offset, for example Figure 7B I in D 8 and I D 8'. Although the lifetime start-of-life (BOL) sigma of the SONOS transistor 94 may be very low, significant degradation can occur over time during storage, especially at high temperatures. (See reference...) Figure 7A For conventional write algorithms that only use hard erase and hard program operations (e.g., in NOR flash or EEPROM), charge tends to be trapped in both shallow and deep traps. In one implementation, when using a write algorithm that utilizes a series of partial erase / programming operations (e.g., soft erase, soft program, selective soft erase, annealing erase, and refill programming operations) to write the I / O of an NVM cell... D / V T When it moves to its corresponding target, it may capture more charge in the deep trap, such as Figure 9A , Figure 9B , Figure 11 as well as Figure 12 As described herein, this method can help redistribute charge from shallow traps to deep traps. In one implementation, partial erase and programming operations can clear charge from shallow traps and instead fill deep traps. Therefore, it is possible to target I D / V T Improving the I of NVM cells while maintaining the same level D / V T Sigma degradation and retention.

[0088] Retention and I can also be improved by changing the manufacturing process. D / V TSigma degradation reduces the density of shallow traps in the charge trapping layer. In one embodiment, manufacturing process improvements may include: smoothing the curvature of shallow trench isolation (STI) corners in the SONOS transistor, optimizing the dopant distribution in the channel, and improving the oxide layer, etc.

[0089] Soft erase operation:

[0090] In one implementation, the operating voltage coupled to the various nodes for the soft erase operation is similar to that previously... Figure 3A The hard erase operation is described in [the document]. Therefore, a complete erase voltage bias of 8 V is still applied between the CG and the substrate / drain. NEG -V POS Compared to hard erase operations, the duration of the WLS pulse (e.g., WLS0, WLS1) in a soft erase pulse is significantly shorter (Tse approximately 20 μs) compared to the approximately 10 ms of a hard erase operation. Although the CG-to-drain voltage bias (e.g., -8 V) is the same, the shorter soft erase pulse may only increase (e.g., at...) Figure 10 (From L4 to L2), but will not increase the I of the NVM cells (e.g., C1, C2) in the selected row 0. D Move to the erased I D Horizontal. In one implementation, a soft erase operation can be performed only on the entire selected row.

[0091] Annealing and erasing operation:

[0092] The general purpose of annealing erase operations is to trap charges in shallow traps to improve post-retention performance. Table III depicts exemplary bias voltages that can be used for annealing erase operations on page / row 0 of non-volatile memory with a 2T architecture and including memory cells with N-type SONOS transistors and CSLs. Figure 3A The 2×2 array 300 shown in the best example is similar.

[0093] <![CDATA[ node ]]> <![CDATA[ Voltage (V) ]]> <![CDATA[ Voltage range (V) ]]> WLS0 <![CDATA[V NEG For example, -3.8 V]]> -4.0 V to -2.0 V BL0 <![CDATA[V AEPOS For example, +2.2 V]]> +1.8 V to +2.4 V WL0 <![CDATA[V PWR For example, +1.1 V]]> +1.0 V to +1.2 V SPW <![CDATA[V AEPOS For example, +2.2 V]]> +1.8 V to +2.4 V DNW <![CDATA[V AEPOS For example, +2.2 V]]> +1.8 V to +2.4 V CLS0 <![CDATA[V AEPOS For example, +2.2 V]]> +1.8 V to +2.4 V WLS1 <![CDATA[V AEPOS For example, +2.2 V]]> +1.8 V to +2.4 V BL1 <![CDATA[V AEPOS For example, +2.2 V]]> +1.8 V to +2.4 V WL1 <![CDATA[V PWR For example, +1.1 V]]> +1.0 V to +1.2 V

[0094] Table III

[0095] In one implementation, unlike erase and soft erase operations, due to V AEPOS It may have a higher value than V. POS A low amplitude, applying a softer erase voltage bias (V) between the CG and the substrate / drain. NEG -V AEPOSHowever, applying a softer or lower erase voltage (e.g., 6 V vs. 8 V) to the CG results in a much longer pulse duration, approximately 50 ms for Tae. In one implementation, a longer and softer erase pulse can help remove charge closer to the conduction band in shallow traps. In one implementation, the annealing erase operation can be performed only on the entire selected row.

[0096] Selective soft erase:

[0097] Figure 8A A 2×2 array 800 of an NVM array 100, according to an embodiment of selective soft erase operation, is shown. In one embodiment, the 2×2 array 800 may be similar to... Figure 3A and Figure 3B The 2×2 array 300 is described below. For clarity and ease of explanation, it is assumed that all transistors in the 2×2 array 800 are N-type transistors. It should be understood that, without loss of generality, a P-type configuration can be described by reversing the polarity of the applied voltage, and such a configuration is within the contemplated embodiments of this disclosure. Furthermore, the voltages used in the following description are chosen for ease of explanation and represent only one exemplary embodiment of the subject matter. Other voltages may be used in different embodiments.

[0098] Reference Figure 8A The 2×2 memory array 800 includes at least four memory cells C1, C2, C3, and C4 arranged in two rows and two columns. While NVM cells C1 to C4 can be located in two adjacent columns (common source line CSL0), they can also be located in two adjacent rows or two non-adjacent rows. Each of the NVM cells C1 to C4 can be structurally similar to the NVM cell 90 described above. (Refer to...) Figure 3A , Figure 3B as well as Figure 5 , Figure 3A The hard erase operation described in [the document] can erase the I of the NVM cell. D Raise to Figure 5 Erased I D Horizontally, and similarly, hard-programming operations can transform the I of programmed NVM units. D Raise to Figure 5 In the programming I D Horizontal. In one implementation, erased and programmed I D The horizontal distribution can be located in the NVM array 100 I D 1 to I D 2 n Outside the scope of operation. In another embodiment, erased and programmed I D One of the levels can fall within the operational range.

[0099] Reference Figure 8A For example, page 0 is selected to be partially erased / disabled, while page 1 is not selected (not selected) for selective soft erase (SSE) / disable operations. Compared to the previously described hard erase operation implementation, soft erase operation implementation, and annealed erase operation implementation, in this case, a single page or row is the smallest erase block of NVM cells 90, and a single NVM cell / bit or multiple NVM cells / bits in the same row (e.g., page 0) can be selected for selective soft erase operations. Unselected NVM cells (e.g., C2) can instead be disabled. Therefore, by applying an appropriate voltage to the SONOS word line (WLS0) shared by all NVM cells in row 0, the substrate connection, and all bit lines in the NVM array 100, only the selected NVM cells including C1 in the selected row (page 0) are disabled. D The level is raised (partial erasure). In one implementation, the selective soft erase (SSE) negative voltage V... SSENEG The positive voltage V of SSE is applied to WLS0. SSEPOS BLO and DNW are applied to all NVM cells in page 0. In one implementation, with Figure 3A The V used in the hard erase operation NEG In comparison, V SSENEG It has a small absolute amplitude, and V SSEPOS Having more Figure 3A V in POS Large absolute range. V EINHIB The conditions are applied to WL0, SPW, BL1, and WL1 to disable soft erase operations on unselected NVM cells (such as C2) and prevent them from being erased. D Enhancement. CLS0 and WLS1 are coupled to ground or 0 V. In one implementation, the SG of all NVM cells C1 through C4 is at least partially off (WL = -1.4 V), and the SG is normally on for hard erase operations.

[0100] In one implementation, although V SSENEG The absolute amplitude is small, but a relatively complete erase voltage bias (V) is still applied only between the memory transistors CG and BL0 in C1. SSENEG – V SSEPOS = -7.2 V). The voltage difference between CG and BL1 in the unselected C2 is only (V). SSENEG – V EINHIB = -0.9 V). Therefore, only the selected C1 has I D It can be promoted, while the unselected C2 in the same selected row 0 is I. DNo boosting was performed. In one implementation, the pulse duration of the selected erase operation coupled to WLS0 (Tsse approximately 20 µs) is much shorter than the pulse duration of the hard erase operation (Te approximately 10 ms). The shorter SSE pulse may not have enough time to erase all previously trapped charges (if any) in the NVM cell C1. In one implementation, all word lines including WL0 and WL1, as well as SPW, are coupled to V. EINHIB This prevents unselected NVM cells C2, C3, and C4 from being partially erased as in NVM cell C1. In one embodiment, a general concept for the selected erase operation is to apply a relatively high erase voltage bias (e.g., 7.2 V) for a short period (20 µs) to reduce trapped charge in only selected NVM cells in the same row. In one embodiment, Tae > Te > Tsse and Tse. In one embodiment, more than one NVM cell (adjacent or non-adjacent) in the same row can be selected for SSE operation, while more than one NVM cell (adjacent or non-adjacent) in the same row can be disabled to allow their Ig to be removed. D The level remains relatively unchanged.

[0101] Table IV describes exemplary bias voltages that can be used for selective soft erase operations on pages / row 0 and column 0 (C1 only) of a non-volatile memory having a 2T architecture and including memory cells with N-type SONOS transistors and CSLs, similar to a 2×2 array 800.

[0102] <![CDATA[ node ]]> <![CDATA[ Voltage (V) ]]> <![CDATA[ Voltage range (V) ]]> WLS0 <![CDATA[V SSENEG For example, -2.3 V]]> -2.5 V to -1.5 V BL0 <![CDATA[V SSEPOS For example, +4.9 V]]> +3.0 V to +5.0 V WL0 <![CDATA[V EINHIB For example, -1.4 V]]> -1.6 to -0.8 SPW <![CDATA[V EINHIB For example, -1.4 V]]> -1.6 to -0.8 DNW <![CDATA[V SSEPOS For example, +4.9 V]]> +3.0 V to +5.0 V CLS0 Ground or 0V Ground or 0V WLS1 Ground or 0V Ground or 0V BL1 <![CDATA[V EINHIB For example, -1.4 V]]> -1.6 to -0.8 WL1 <![CDATA[V EINHIB For example, -1.4 V]]> -1.6 to -0.8

[0103] Table IV

[0104] Software programming operations:

[0105] In one implementation, apart from the voltage coupled to the selected WLS (e.g., WLS0), the operating voltage coupled to each node for soft programming (SP) / disable operation is similar to that previously. Figure 3B The hard-programmed / disabled operation described in [the document]. In one implementation, V SPPOS It has V in a more hard-programmed operation POS The low amplitude allows for a reduction in the programming voltage applied to the selected C1's CG. Therefore, a soft programming voltage bias of 6 V is applied between CG and BL / substrate / P-well. NEG –V SPPOSCompared to hard programming operations, the duration of the WLS pulses (e.g., WLS0, WLS1) in soft programming is significantly shorter (Tsp approximately 10 µs), compared to the approximately 5 ms Tp of hard programming operations. With a small CG-drain voltage difference (e.g., 6 V vs. 8 V) and a shorter soft programming pulse (10 µs vs. 5 ms), soft programming operations can reduce only the Ig of the selected NVM cell C1. D Instead of using the I of the selected NVM unit C1 D Move to programming I D Horizontal (e.g., in) Figure 10 (From L3 to L2). In one implementation, unselected NVM cells on the same row, such as C2, and unselected NVM cells on the same row, such as C3 and C4, can be disabled.

[0106] Then fill in the programming operations:

[0107] Figure 8B An exemplary implementation of a segment 2×2 array 800 of an NVM array 100 during refill programming (RP) / disable operation is shown. (Refer to...) Figure 8B For example, NVM unit C1 is to be partially programmed (I D Horizontal orientation Figure 5 In programming I D The target cell (reduced or moved) is disabled, while NVM cell C2 is disabled. It should be understood that although C1 and C2 are shown as two adjacent cells for illustrative purposes, C1 and C2 could also be two separate NVM cells on the same row (such as row 0). The general purpose of the refill programming operation is to fill the deep trap with charge using a high programming voltage bias (see...). Figure 7A To improve post-retention performance. Table V depicts exemplary bias voltages that can be used for refill programming operations on page / row 0 of non-volatile memory having a 2T architecture and including memory cells with N-type SONOS transistors and CSLs, and Figure 8B The 2×2 array 800 shown in the best example is similar.

[0108] In one implementation, unlike software programming operations, due to V RPPOS It may have the same characteristics as V. POS Comparable but less than V POS High amplitude and V RPNEG It may have the same characteristics as V. NEG Comparable but less than V NEG The high amplitude necessitates applying a harder programming voltage bias (V) between the CG and the substrate / drain. RPPOS –V RPNEG Therefore, the resulting programming voltage bias applied to the CG of the selected C1 is as follows: Figure 3B The programming voltage bias in the hard programming operation described in [the document] is comparable to, but slightly higher than, [the voltage bias]. Figure 3B The programming voltage bias in the hard programming operation described herein (e.g., 9 V vs. 8 V). However, the harder programming pulse is only applied to the selected CG for a very short duration, Trp approximately 5 µs. The short refill programming pulse can reduce the I of C1. D However, it cannot be fully programmed. In one implementation, Tp > Tsp > Trp. The hard-programming pulses of the refill programming operation can help fill the deep traps with charge, which have... Figure 7A The optimal energy level between the conduction band and valence band is shown in the diagram. In one embodiment, similar to hard programming and soft programming operations, unselected NVM units C2, C3, C4, etc., may be disabled. In one embodiment, a refill programming operation can be performed after or before an annealing erase operation. The refill programming operation can restore the I of the selected NVM unit by refilling the charge into the deep trap. D The charge may have been cleared from the shallow trap during a previous annealing and erasing operation.

[0109] Table V depicts an exemplary bias voltage that can be used to refill and program NVM cells C1 in a non-volatile memory having a 2T architecture and including memory cells with N-type SONOS transistors and CSL.

[0110] <![CDATA[ node ]]> <![CDATA[ Voltage (V) ]]> <![CDATA[ Voltage range (V) ]]> WLS0 <![CDATA[V RPPOS For example, +5 V]]> +3.8 V to +5.0 V BL0 <![CDATA[V RPNEG For example -4 V]]> -4.0 V to -3.4 V WL0 <![CDATA[V RPNEG For example -4 V]]> -4.0 V to -3.4 V SPW <![CDATA[V RPNEG For example -4 V]]> -4.0 V to -3.4 V DNW <![CDATA[V INHIB For example, +1.1 V]]> +1.0 V to +1.2 V CLS0 <![CDATA[Floating / V MARG For example, -2.4 V]]> -3.0 V to -2.0 V WLS1 <![CDATA[V MARG For example, -2.4 V -3.0 V to -2.0 V BL1 <![CDATA[V INHIB For example, +1.1 V]]> +1.0 V to +1.2 V WL1 <![CDATA[V RPNEG For example -4 V]]> -4.0 V to -3.4 V

[0111] Table V

[0112] It should be understood that the voltages and voltage ranges used in the foregoing descriptions of hard erase, hard program, partial erase, and partial program operations are chosen for ease of explanation and represent only one exemplary implementation of the subject matter, and should not be construed as limiting. Other voltages may be used in different implementations without losing the generality of this disclosure.

[0113] Figure 9A and Figure 9B These are representative flowcharts 900A and 900B illustrating a method 900A for writing a multi-level NVM cell according to one embodiment of this subject matter. Figure 10 This illustrates a plurality of I-cells in an analog NVM array according to one embodiment of the present disclosure. D Horizontal or V T A horizontal representation diagram. As previously explained, write methods 900A and 900B can be applied to multiple V-types of a tuned NVM cell. T Level and I DBoth are horizontal. It should be understood that, for the sake of clarity and brevity only, methods 900A and 900B will be referred to below only from the perspective of I. D This will be explained from that perspective. (Refer to...) Figure 9A and Figure 9B The main purpose of write operations 900A and 900B is to transfer the desired or predetermined I / O data through a series of partially programmed, partially erased, and verified operations. D Horizontal or V T Horizontal (or target) precise writing to one or more selected cells or bits, such as an NVM array 100 or... Figure 13 The SONOS-based NVM cell 90 in the multi-level or simulated NVM array 1302. In one embodiment, the written I D It may have to fall on a relatively narrow I D Within the distribution (low sigma), to maintain multiple I D The functionality of horizontal analog memory. (Refer to...) Figure 9A and Figure 13 Method 900A begins with a wake-up phase. In one implementation, in step 902, a process similar to [previous implementation details] can be performed throughout the entire simulated NVM array 1302. Figure 3B The hard-programming operations described in the implementation are used to reduce leakage in unselected NVM cells. It should be understood that a single row and column or multiple rows and columns of an NVM cell can be selected for write operations 900A and 900B. As an example, Figure 13 In the multi-level NVM array 1302, NVM cells in row A, column X, and column Y are selected for write operations to obtain target I. D Level 2, such as Figure 10 As shown. Subsequently, a series of hard erase operations can be performed in the selected row A in steps 904 and 906 respectively. Figure 3A ) and hard-programmed operations ( Figure 3B In one implementation, the I of the NVM cell in row A. D You can first move to the erased I D Horizontal, and then move to the programmed I D Horizontal, such as Figure 10 As shown. Steps 904 and 906 can be repeated X times, for example, 5 times (in step 908), and the wake-up phase can prepare the selected row A for the upcoming operation. After the wake-up phase, the NVM cells in the selected row A can be in fully programmed I... D Level (L1). In one implementation, there may be no verification or read operations during the wake-up phase.

[0114] Reference Figure 9A and Figure 10In step 910, a soft erase operation is performed on the selected bits in row A, causing the I of these NVM cells to... D From horizontal L1 towards the erased I D The level is raised. Subsequently, unlike write operations in binary NVM cells, a verification operation similar to a regular read operation can be performed after each partial programming and partial erase operation to check the I of the selected bits. D Horizontal. In step 912, a verification step is performed on the selected bits in columns X and Y to check that the soft erase operation in step 910 sets their respective I... D How much was improved? If the I of two bits in column X and column Y... D All are greater than target I D The lower limit, i.e., I D If 2LL, then the method can proceed to... Figure 9B The fine-tuning stage is detailed in section 914. If two bits of I are determined in step 914... D All below I D If 2LL is reached, then method 900A can return to step 910 to perform another soft erase operation to further boost or increase the two bits of I. D If we determine the I of the selected bits in columns X and Y D There is only one below I D If 2LL, then in step 916, it is possible to apply the value higher than I. D 2LL bits perform soft programming operations (to reduce its I) D ), and prohibits anything below I D 2LL bits, such that the two selected bits are in similar I positions. D Horizontal. Then, method 900A can return to step 910 to perform another soft erase operation to further erase the two bits of I. D Towards Target I D Horizontal elevation. In one implementation, steps 912, 914, and 916 may be repeated several times until all selected bits (e.g., bits in row A, column X, and column Y) reach I. D The level is improved by the soft erase operation in step 910 and subsequently verified to be greater than the target I in step 912. D The lower limit of the level (e.g., Figure 10 (L2 or L3 level in the middle). In one implementation, the aforementioned steps can be performed on all bits in the selected row A.

[0115] Reference Figure 9B In method 900B, the fine-tuning phase is initiated, where a series of soft programming operations and selective soft erase operations (each followed by a verification operation) are performed on one or more selected bits to set their I...D Each of the targets I D Level (e.g., I) D 2) Movement. In one implementation, a verification or read operation can be performed on all selected bits to determine whether any of the selected bits has exceeded the target I. D Upper limit (e.g., Figure 10 I in D 2UL) of I D If it is determined that both selected bits (e.g., column X and column Y) are less than I. D If 2UL is selected, the fine-tuning phase will proceed to step 922. If the selected bit's I... D Any one greater than I D If 2UL (e.g., L3 level) is used, then in step 920, a soft programming operation will be performed on these bits. Figure 8B ) to make it I D Slightly descend back to I D Within the allocation limit 2, other selected bits can be disabled. In one implementation, steps 918 and 920 can be repeated several times until all selected bits are determined to have a value less than 1. D 2UL of I D .

[0116] In verification step 922, all selected bits (e.g., columns X and Y) are read to determine whether the bit I is affected by the soft programming / disable operation in the previous step 920. D Any of them have been shifted to I D Below 2LL (e.g., L4 level). If it is determined that all selected bits are greater than I. D If 2LL is reached, the fine-tuning phase can proceed to step 926. If it is determined that any selected bit has been shifted to I... D For bits below 2LL, a selective soft erase operation can be performed only on these bits. Figure 8A ) to make its I D towards I D 2. Distributed Shift. As previously discussed, unlike hard or soft erase operations that can be performed on all bits in a row, a selective soft erase operation can be performed on only a single bit or multiple bits in a selected row. In one implementation, selected bits that have not undergone a selective erase operation (I...) can be disabled. D (Substantially unchanged). Steps 922 and 924 can be repeated several times until all selected bits make their I... D Move to higher than I D 2LL.

[0117] In verification step 926, all selected bits (e.g., columns X and Y) are read to determine whether the bit I was affected by the selective soft erase / disable operation in the previous step 924. D Any of them have been shifted to I D 2UL or higher (overcorrected). If it is determined that any selected bit has been shifted to I. D For 2UL and above, software programming operations can be performed only on these bits. Figure 8B ), to make their I D Move back to I D 2. Allocation. In one implementation, selected bits that have not undergone software programming can be disabled.

[0118] In one implementation, if in verification step 926 it is determined that all selected bits are less than 1 D If 2UL is reached, the fine-tuning phase can be terminated in step 930. All selected bits (e.g., row A, column X, and column Y) are determined to have a value higher than I. D Target I of 2LL and below ID2UL D Methods 900A and 900B can be written to another line, for example, for the same or different target I. D Horizontal row B. In one implementation, the write operation can be repeated until the entire simulated NVM array 1302 is programmed to target I. D level.

[0119] In another implementation, the fine-tuning phase can loop back to step 922 to check if any selected bits were overcorrected by the soft programming operation in step 928. Before the fine-tuning phase proceeds to the write end step 930, steps 922 (verification), 924 (SE), 926 (verification), and 928 (SP) can be configurably repeated a number of times according to system requirements. Repeated verification is performed in some implementations—particularly in systems with a high number of I... D Horizontal (adjacent target I) D In multi-level NVM arrays (where the layers are closely distributed horizontally), their advantages may be present.

[0120] Figure 11 This is a representative flowchart illustrating another implementation of the write algorithm according to this disclosure. In one implementation, write algorithm 1100 can be used to write from the same row (e.g., Figure 13 Two bits in row A, column X, and column Y of the array are used to achieve two different goals I. D (For example, column X-I2, column Y-I0). See reference. Figure 11 Method 1100 begins, and in step 1104 (wake-up phase), multiple cycles of hard or strong programming and erasing operations can be performed on both column X and column Y bits. Figure 3A and Figure 3B Subsequently, in step 1106, a hard erase operation can be performed on two bits, causing their I... D The level reaches I1. In another embodiment, the hard erase operation can erase more than two bits of I1. D Push to the erased I D The level is then determined. Partial programming operations, such as soft programming (in step 1108) and verification or reading (in step 1109), can then be repeated several times until at least column X bits reach I2 by comparing the column X bits with the I2 average. Subsequently, in step 1110, since column X bits have reached their target I2, they can be disabled for further programming or erasure operations. Then, in step 1112, a selective erasure operation can be performed on the undisabled bits (i.e., column Y bits) to reduce their I2 value. D The level is pushed up to I3. In one implementation, several selective erase operations may be required for column Y bits to reach I3. Then, partial programming operations such as soft programming operations (in step 1114) and verification or reading (in step 1116) can be repeated several times until column Y bits reach their target level I0. Once it is determined that column Y bits have reached their target I0 by comparing column Y bits with the average of I0, in step 1118, column Y bits can be disabled for further programming / erasing operations, just like column X bits. In one implementation, in this example, I2 < I0 < I3 < I1. To determine whether a bit has reached its target I0... D Horizontal, can be used to correlate bits with target I D The mean level is compared. In another implementation, it can be used to... Figure 9A and Figure 9B The lower and upper bound algorithms are detailed in steps such as 920, 924, and 926. In another implementation, the write algorithm can use the same steps to continue writing to other bits in the selected row or other rows.

[0121] Figure 11 The write algorithm illustrates the basic concept of writing analog values ​​to an NVM array (e.g., a multi-level NVM array 1302). In one alternative implementation, more than one bit can be written to targets I2 and I0 as soft programming, and selective soft erase operations can be performed selectively on one or more bits in the same row. In other alternative implementations, instead of using soft programming operations (in steps 1106 and 1114) to push or trim bits to their respective targets I0, the bits are pushed or trimmed. D Selective soft erasure operations can be used additionally or alternatively. Figure 11 The example in the image is an erased I DThe horizontal start (after step 1106) can also be achieved alternatively when a hard programming operation is performed in step 1106 (pushing all bits to I2 or the programmed I2). D (Level) to be programmed I D Begin at a horizontal level.

[0122] As previously explained, SONOS-based cells such as NVM cell 90 are suitable for multi-level analog memory devices due to their high endurance of 1K cycles and low power consumption. SONOS-based NVM arrays also have the advantage of low random telegraph noise (RTN) of less than 3 nA. In one embodiment, more than two adjacent V values ​​can represent more than two analog values. T / I D The close horizontal spacing allows for more stringent retention specifications in multi-level NVM devices compared to binary NVM devices (e.g., NOR flash, EEPROM). Improvements in data retention performance and V may be necessary. T / I D Sigma degradation is used to avoid incorrect or erroneous reads at multiple levels in a multi-level NVM cell. This adversely affects retention and V. T / I D One of the main contributing factors to sigma is the loss of charge (e.g., electrons and holes) from shallow traps in the charge trapping layer 92 of the SONOS transistor 94 during the hold period, as shown in Figure 1. Figure 7A and Figure 7B The best example shown is...

[0123] Figure 12 This is a representative flowchart illustrating a method for an operation refilling and annealing routine algorithm according to one embodiment of the present disclosure. (Refer to...) Figure 9B It can be considered that step 930 completes the writing of the simulated value into the target multi-level NVM cell. In the implementation, the refill and annealing algorithm 1200 can be performed on one or more bits or an entire row of programmed bits. (Used with...) Figure 9A and Figure 9B Similarly, in step 930, bits in row A, column X, and column Y can be written and target I can be stored. D 2 values. In one implementation, in order to improve performance retention and make V T / I D Minimizing sigma degradation by replacing shallow trap charges (electrons or holes) with deep trap charges may be beneficial. In one implementation, the target I can be pre-programmed. DThe horizontal bits are refilled and annealed using routine 1200. In step 1202, method 1200 performs a soft erase operation on the selected bits (e.g., row A, column X, and column Y) to reset them. D Value increased to target I D Mean + X% level (e.g., I D Start with 2 + 20% to 50%. A verification step can then be performed to ensure the selected position is at or above the target I. D The mean is +20% to 50% level. In one implementation, the soft erase operation can clear the charge mainly in the shallow traps to improve I. D Value. Subsequently, in step 1206, the selected bit can be processed as previously described and... Figure 8B The best example shown is the refill procedure operation to separate their I D Value reduced to target I D Mean - Y% level (I D (2-10% to 20%). A verification step can then be performed to ensure that the selected position is at or below the target I. D The mean is -10% to 20% level. In one implementation, a short but strong refill programming pulse (e.g., 9 V CG to the drain) can replenish some of the charge removed in the previous soft erase operation in step 1202 with charge primarily stored in the deep traps. Steps 1202 and 1206 can be repeated several times to reinforce the replacement of shallow trap charges by deep trap charges. It should be understood that I D 2-10% to 20% and I D The 2+20% to 50% values ​​are examples used for illustrative purposes. Other offset percentages can be used, as long as they affect the I of the selected bits. D Values ​​from their target I D The mean swings from one side to the other.

[0124] Then, method 1200 can continue performing the annealing erase operation as previously described on the selected bit in step 1208. In one embodiment, the annealing erase operation can clear the charge mainly in the shallow trap to I D The value of I from the result of step 1206 D A 2-10% level improvement. As previously explained, a soft (6 V CG to drain) and long (~50 ms) annealing erase pulse further allows sufficient time to clear the charge primarily in the shallow traps. A verification step can then be performed to ensure that at least one or more selected bits are at or above the target I. D Lower limit level (e.g., I) D 2LL). Then, in step 1210, method 1200 can continue to process items below I. DA selective soft erase operation is performed on the 2LL bit. Alternatively, bits with higher than I can be disabled due to a previous annealing erase operation (step 1208). D 2LL of I D The value's bits. A verification operation can be performed to ensure that all bits are partially erased to achieve a value greater than I. D 2LL of I D Horizontal. At the end of step 1210, due to a series of refill programming and annealing erase operations, all selected bits (e.g., row A, column X, and column Y) can be recovered to target I with most of the charge in the deep trap. D Level (e.g., I) D 2).

[0125] In an alternative implementation, additionally or alternatively, it may immediately follow... Figure 9B After step 918 (verification is "No") in the write algorithm 900B, steps 1202 (soft erase operation) and 1206 (refill programming operation) of the refill and annealing routine 1200 are executed.

[0126] Figure 13 This is a schematic block diagram illustrating an embodiment of a multi-level or analog NVM device 1300 according to the subject matter. In one embodiment, the analog NVM array 1302 may be similar to... Figure 2 The NVM array 100 in the diagram has multi-level NVM cells 1310 arranged in N rows and M columns. Each multi-level NVM cell 1310 may have a 2T configuration (SONOS transistors and FET transistors) and share a CSL with an adjacent cell in the same row. In one embodiment, other connections such as WLS, WL, BL, SPW, DNW, etc., may also be similar. Figure 1A , Figure 1B and Figure 2 The configuration of the NVM array 100. The multi-level NVM unit 1310 can be configured to have more than two different I... D / V T Level (see) Figure 10 ), for example 2 4 = 16 levels or 0 to 15 levels. In one embodiment, each analog NVM unit 1310 can store an analog value 0 to 15, the analog value 0 to 15 corresponding to the I value of each analog NVM unit when it is read. D / V T Horizontal. In one implementation, multiple different I can be pre-defined. D / V T Levels and their corresponding simulated values. Examples include... Figures 9A to 12The simulated value is written to the simulated NVM cell 1310 using one or more writing methods / algorithms shown and described, employing a series of partial programming / disabling operations, partial erasing / disabling operations, and verification steps. As an example, the value 10 (I) is written to the value 10 in row A, column X, bit X. D / V T (Level = 10), row A, column Y, value 5 is written, row B, column X, value 8 is written, and row C, column Z, value 2 is written. In the implementation, the multi-level NVM unit 1310 can be written with predefined I... D / V T Any simulated value within the horizontal range (e.g., for 16 I) D / V T The level is written from 0 to 15. The aforementioned stored values ​​may be used for illustrative purposes only in the examples of the operating methods below; and should not be construed as limiting.

[0127] In one implementation, the stored values ​​of multiple multi-level NVM units 1310 can be combined to store a single analog value. For example, two multi-level NVM units 1310 can be configured to have eight levels, with one unit storing values ​​0 to 7 and the other storing values ​​-8 to -1. When reading two units in one operation, the combined units can be considered to have 16 levels (-8 to 7) representing 16 analog values ​​instead of 8 analog values. In other implementations, more than two multi-level NVM units 1310 can be combined, allowing for operation I without further partitioning of the multi-level NVM units 1310. D / V T A higher number of units can be achieved within a certain range. In an implementation, the units to be combined can be arranged in adjacent columns of the same row, adjacent rows of the same column, or distributed in the analog NVM array 1302 according to some predetermined algorithms.

[0128] Reference Figure 13The analog NVM array 1302 can be coupled to the column multiplexing function 1304 via its bit lines (e.g., BL.X, BL.Y). In one embodiment, the column multiplexing function 1304 may include multiplexers, capacitors, transistors, and other semiconductor devices. During a read operation, similar to a read operation of a digital NVM array, the value 10 of bit X in row A can be read from the column multiplexing function 1304 via BL.X. In one embodiment, multiple bits in the same column (e.g., row A, column X and row B, column X) can be selected in a single read operation, such that the read value is the sum of the two selected bits (10 + 8 = 18). In another embodiment, multiple bits in the same row (e.g., row A, column X and row A, column Y) can be selected for the same read operation. The column multiplexing function 1304 can be configured to select both columns X and Y for reading and add or subtract the two values ​​(10 + 5 = 15 or 10 – 5 = 5). In another embodiment, the NVM device 1300 can be configured to perform a multiplication function. For example, row A, column X, bit X can be read 7 times to calculate (7 × 10 = 70). Multiplication (M × stored value) can be performed by using M × multiple pulses on the WL (coupled to the SG) or by extending the pulse duration of a WL pulse (M times). In one embodiment, as an example, the analog value "7" can be an input from an external device that can be coupled to the WL via a digital-to-analog converter (DAC) 1320 to a row of the SG. Figure 13 As best illustrated, each DAC 1320 to DAC 1326 can be coupled to one or more read rows (WLs). One of the functions of DACs 1320 to DAC 1326 is to configure the selected row for read operations. It will be understood that... Figure 13 The number, configuration, and coupling of the DACs shown to the NVM array 1302 are merely one example for illustrative purposes. Other configurations are possible depending on system requirements and design, without altering the general teachings of this embodiment. In various embodiments, DACs 1320 to DAC 1326, the analog NVM array 1302, and the column multiplexing function 1304 can be configured to perform simple arithmetic functions, such as summation and multiplication, as illustrated in the previous examples, with or without a CPU or GPU. In one embodiment, the analog NVM device 1300 can function as both a data storage device and an inference device.

[0129] The analog results from the column multiplexing function 1304 can then be input to an analog-to-digital converter (ADC) or comparator 1306, where the analog readout results can be converted into digital data and output. In one embodiment, all or part of the analog NVM array 1302 can be refreshed or have its analog values ​​rewritten periodically—such as every 24 hours, 48 ​​hours, or other durations. The refresh operation can be due to hold, I D / V T Downgrade (in) Figure 7B (best shown in the image) or other reasons caused by the programming of multi-level NVM units I D / V T The potential effects of horizontal offset or attenuation are minimized. In another embodiment, the analog NVM array 1302 may include a reference cell (not shown), wherein potential I values ​​can be subtracted from the multi-level NVM cells 1310. D / V T The combined effects of horizontal offset.

[0130] Figure 14 and Figure 15 These are representative block diagrams illustrating a multiply-accumulate (MAC) system and a von Neumann architecture of an artificial neuron, respectively, according to one embodiment of this disclosure. Artificial intelligence (AI) can be defined as the ability of machines to perform cognitive functions performed by the human brain—such as reasoning, perception, and learning. Machine learning can use algorithms to find patterns in data and use models that recognize these patterns to predict any new data or patterns. At the heart of AI applications or machine learning is the existence of MAC operations, or dot product operations, which may require two values ​​(input values ​​and weight values), multiply these two values, and add the result to an accumulator. Figure 15The artificial neuron 1504 in the diagram can be a component characteristic of MAC operations within a deep neural network (DNN). DNNs mimic the function of the human brain by implementing a massively parallel computing (neuronal computing) architecture that connects low-power computational elements (neurons) and adaptive memory elements (synapses). One reason for the rapid growth of machine learning is the availability of graphics processing units (GPUs). In MAC applications such as System 1402, GPUs can perform necessary computations much faster than general-purpose CPUs. One drawback of using GPUs for MAC operations is that GPUs tend to utilize floating-point operations, which can be far beyond the needs of relatively simple machine learning algorithms like MAC operations. Furthermore, AI applications—especially those running at the edge—may require MACs to operate with high power efficiency to reduce power consumption and heat generation. Existing systems based on all-digital von Neumann architectures (such as MAC System 1502) may also experience significant bottlenecks between the GPU performing computations and the memory that only stores data (weight values, input values, output values, etc.) due to frequent memory access. Therefore, the use of low-power memory elements that can be configured to function as both inference and data storage devices needs to be considered.

[0131] Figure 16 This is a representative block diagram illustrating a neural network accelerator system according to one embodiment of the present disclosure. In one embodiment, the SONOS-based simulation device can have the unique ability to store simulation weight values ​​locally and process each non-volatile memory element in parallel, which can significantly eliminate... Figure 14 The diagram illustrates the energy consumption of moving large amounts of data. Each NVM unit can have multiple levels (e.g., 4 to 8 bits) instead of binary levels (1 bit), and each I... D / V T The level can represent a multi-dimensional weight value used for inference ( Figure 15 (wi in the original text). In one implementation, a higher number of levels results in higher training accuracy and a lower inference error rate. The key performance and reliability requirements for typical analog memories used in neuromorphic computing are unit I at all levels. D / V T , retention and noise sigma. As previously explained, SONOS-based NVM devices (e.g. Figure 13 The analog NVM device 1300 in the DNN system can be a good candidate to perform the storage and inference functions of artificial neurons.

[0132] Reference Figure 16The neural network accelerator system 1600 may include multiple analog NVM devices or accelerators 1602 disposed in a single substrate, package, or die, and the multiple analog NVM devices or accelerators 1602 are coupled to each other via a bus system. Each accelerator 1602 may be similar to Figure 13 The simulated NVM device 1300 is similarly operated. In one embodiment, the NVM device 1602 can be configured to perform MAC operations. Each simulated NVM device 1602 can be used as a DNN system. Figure 15 Artificial neurons 1504 are present in the array. In one embodiment, the SONOS array 1602 may have multiple SONOS-based NVM units (…). Figure 16 (Not shown in the image), the plurality of SONOS-based NVM cells are arranged in rows and columns. In other embodiments, the SONOS array 1602 may include a plurality of SONOS NVM sections or arrays. Each NVM cell may be configured to store weight values ​​from 0 to 2. n -1 or use as... Figures 9A to 12 Other values ​​written by the write algorithms described and illustrated herein, as well as combinations thereof. In other embodiments, the simulated value of each NVM cell may be written by other write algorithms.

[0133] As part of the neuromorphic computation algorithm, each simulated NVM device 1602 (e.g., accelerator 1602a) can execute the following MAC function, where xi is the input from other simulated NVM devices 1602 or external devices, wi is the stored weight value, b is a constant, and f is the activation function:

[0134] f ( (1) ……………..

[0135] like Figure 16 As best shown, xi can be a digital input from other analog NVM devices (e.g., 1602b and 1602c or other analog NVM devices). The digital input xi can then be converted into an analog signal by DAC 1612, which can then be coupled to low-voltage driver 1614 and / or high-voltage driver 1616. In one embodiment, the low-voltage driver can generate a control signal (to control SG) corresponding to the analog signal from DAC 1612 via the WL of the NVM unit. The high-voltage column driver 1604 can generate a control signal to BL and a high-voltage driver to WLS to control the CG of the NVM unit.

[0136] It can be used Figure 13 The example in [reference] illustrates one implementation of MAC operation in an NVM device 1602, where i can be set to 3. Figure 13 The digital input xi can be coupled to DAC 1320 to DAC 1326, with x1 = 3, x2 = 5, and x3 = 1. The selected weight values ​​are stored in bits of row A, column X (w1 = 10), row B, column X (w2 = 8), and row C, column Z (w3 = 2). The weight values ​​can be selected based on addresses received from other analog NVM devices 1602 or from external devices (e.g., processors, CPUs, GPUs, etc.). A constant b can be selected to store an analog value in row A, column Y (b = 5). To calculate x1 × w1, rows A and column X (stored value = 10) can be read. For x1, the reads can be repeated 3 times to calculate x1 × w1. Similarly, for x2, rows B, column X (weight value = 8) can be read 5 times to calculate x2 × w2, and for x3, rows C, column Z (weight value = 2) can be read 1 time to calculate x3 × w3. Alternatively, both row A, column X and row B, column X can be read three times (to accumulate the combined weight values), and only row A, column X can be read an additional two times. Then, the bit (b=5) at row A, column Y can be read. As previously mentioned, column multiplexing 1304 or 1606 can be configured to sum those results together to compute the MAC result as 3 × 10 + 5 × 8 + 1 × 2 + 2 = 74. It will be understood that the above algorithm is merely an example of using SONOS-based NVM devices (e.g., inference NVM devices 1300 and 1602) to compute the MAC result; this example is for illustrative purposes and should not be construed as limiting. MAC weight values ​​(wi) can be stored, organized, and read in various ways to compute the MAC result depending on the system design and requirements. In one implementation, the activation function (f) can be an algorithm that instructs the MAC output of the simulated NVM device 1602 or prioritizes the MAC output of the simulated NVM device 1602 from the perspective of the entire neural network. For example, the MAC result from the previous example (result = 74) might be considered unimportant and assigned a low priority. In some implementations, the output signal can be de-escalated or boosted based on its priority, and this can be implemented in the column multiplexing function 1606 or the ADC 1608.

[0137] Subsequently, in one embodiment, the MAC result in analog form can be converted into a digital signal using an ADC 1306 or 1608. The digital signal can then be output to another analog NVM device 1602 as xi for its own MAC operation. In one embodiment, similar to a DNN, neuromorphic computations performed by all analog NVM devices 1602 can be executed in parallel. The digital MAC output of each analog NVM device 1602 can be transmitted as a digital input to other analog NVM devices. In some embodiments, multiple analog NVM devices 1602 can be divided into multiple subsets. The digital output of one subset of analog NVM devices 1602 can be propagated to the next subset without repetition. The digital output of the final subset can be output as a neuromorphic computation or machine learning result to an external device.

[0138] In one implementation, a command and control circuitry system including a digital data flow control block 1610 ( Figure 16 (Not shown) can be programmable and configured to guide the data flow within the analog NVM device 1602. The command and control circuitry can also provide control over the low-voltage driver 1614 and the high-voltage driver 1616, as well as the high-voltage column driver 1604, to provide various operating voltage signals to the SONOS array 1602 via SONOS word lines, word lines, bit lines, CSLs, etc., including but not limited to at least... Figure 3A , Figure 3B , Figure 8A , Figure 8B The V shown POS V SEPOS V RPPOS V NEG V SENEG V CSL V MARG V INHIB wait.

[0139] Those skilled in the art should understand that Figure 16 The neural network accelerator system 1600 and analog NVM device 1602 described herein have been simplified for illustrative purposes and are not intended to be a complete description. In particular, the analog NVM device 1602 may include processing functions, row decoders, column decoders, sense amplifiers or other comparators, and command and control circuitry that are not shown or described in detail herein.

[0140] Figure 17This is a representative flowchart illustrating an embodiment of an operation method of an NN accelerator system 1600 characterized by a SONOS-based NVM array / cell according to the present disclosure. In one embodiment, in step 1702, simulated weight values ​​(wi) and other constant values ​​(e.g., b) are written to the SONOS-based NVM array in the NN accelerator using the previously described method. In some embodiments, in optional step 1712, the NVM array may be periodically refreshed to achieve better retention and smaller Ig. D / V T Sigma. Subsequently, in step 1704, an accelerator's NVM array can be configured to perform a MAC operation based at least on digital inputs (xi) from other accelerators and their stored weight values. After completing the MAC operation, in step 1706, an accelerator can output its result and propagate the result to one or more connected accelerators as digital inputs for the MAC operations of said one or more connected accelerators themselves. In one implementation, steps 1704 and 1706 can be repeated multiple times in parallel mode. In step 1710, the output can be transmitted as the result of neuromorphic computation in machine learning for AI applications to external devices such as CPUs and GPUs.

[0141] Therefore, embodiments of SONOS-based multilevel nonvolatile memory and methods for operating it as an analog memory device and MAC device in neuromorphic computing systems such as DNNs have been described. Although this disclosure has been described with reference to specific exemplary embodiments, it will be apparent that various modifications and changes can be made to these embodiments without departing from the broader spirit and scope of this disclosure. Therefore, the specification and drawings are to be considered illustrative rather than restrictive.

[0142] An abstract of this disclosure is provided to comply with 37 C. FR § 1.72(b), which requires an abstract that allows the reader to quickly determine the nature of one or more embodiments of the technical disclosure. The abstract is submitted on the basis that it will not be used to interpret or limit the scope or meaning of the claims. Furthermore, as can be seen in the foregoing detailed description, various features are combined in a single embodiment for the purpose of simplifying the disclosure. The method of this disclosure is not to be construed as reflecting an intention that the claimed embodiment requires more features than expressly listed in each claim. Rather, as reflected in the appended claims, the subject matter of the invention lies in fewer than all features in a single disclosed embodiment. Therefore, the appended claims are thus incorporated into the detailed description, wherein each claim is considered a separate embodiment.

[0143] The phrase "one embodiment" or "implementation" in the description means that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the circuit or method. The phrase "one embodiment" appearing in various places in the specification does not necessarily refer to the same embodiment.

Claims

1. A method of operating a semiconductor device, comprising: Access the semiconductor device, the semiconductor device including multi-level memory transistors arranged in rows and columns, wherein the multi-level memory transistors include silicon-silicon dioxide-silicon nitride-silicon dioxide-silicon-based charge trapping transistors, the charge trapping transistors being configured to store one of Nx analog values ​​corresponding to N levels of threshold voltage and drain current, and wherein N is a natural number greater than 2. At least one of the multilevel memory transistors is selected for the writing process of the target value, wherein the target value is one of the Nx analog values ​​and corresponds to a target drain current range extending from the lower limit of the target drain current to the upper limit of the target drain current. A partial programming operation is performed on at least one of the multilevel memory transistors to reduce the drain current level, wherein a first verification read is performed after the partial programming operation to determine how the reduced drain current level compares to a target average drain current. A partial erase operation is performed on at least one of the multilevel memory transistors to increase the drain current level, wherein a second verification read is performed after the partial erase operation to determine how the increased drain current level compares to the target average drain current; and When the drain current level of at least one of the multilevel memory transistors falls within the target drain current range, the writing process to the target value is determined to be complete.

2. The method according to claim 1, further comprising: After the writing process to the target value is completed, further programming and erasing operations are prohibited for at least one of the multilevel memory transistors, wherein the prohibition includes reducing the gate-to-drain voltage bias of the at least one of the multilevel memory transistors.

3. The method according to claim 1, wherein, The partial programming operation includes at least one of a soft programming operation and a refill programming operation, wherein the partial programming operation is configured to reduce the drain current level of at least one multilevel memory transistor in the multilevel memory transistor and increase the threshold voltage level of at least one multilevel memory transistor in the multilevel memory transistor, and wherein multilevel memory transistors not selected for the partial programming operation are disabled.

4. The method according to claim 1, wherein, The partial programming operation is performed for a much shorter duration compared to the programming operation, wherein the programming operation is configured to reduce the drain current level of the multilevel memory transistor to the fully programmed drain current level, regardless of the initial drain current level of the multilevel memory transistor.

5. The method according to claim 3, wherein, The partial erase operation includes at least one of a soft erase operation, a selective soft erase operation, and an annealing erase operation, wherein the partial erase operation is configured to increase the drain current level of at least one multilevel memory transistor in the multilevel memory transistor and decrease the threshold voltage level of at least one multilevel memory transistor in the multilevel memory transistor, and wherein multilevel memory transistors not selected for the selective soft erase operation are disabled.

6. The method according to claim 5, wherein, The soft erase operation and the selective soft erase operation are performed in a much shorter duration than the erase operation, wherein the erase operation is configured to raise the drain current level of the multilevel memory transistor to the drain current level of a complete erase, regardless of the initial drain current level of the multilevel memory transistor.

7. The method according to claim 5, wherein, The annealing erase operation is performed for a much longer duration than the erase operation, and wherein, compared to the annealing erase operation, the gate-to-drain voltage bias of at least one of the multilevel memory transistors in the multilevel memory transistors is greater during the erase operation.

8. The method of claim 5, further comprising a refill and annealing algorithm, including: After the writing process to the target value is completed, the soft erase operation is performed on at least one of the multilevel memory transistors. Verify that the drain current level has reached at least the target drain current +X%, where X is in the range of 20 to 50. The refill programming operation is performed on at least one of the multilevel memory transistors; Verify that the drain current level has reached at most the target drain current -Y%, where Y is in the range of 10 to 20; The annealing erase operation is performed on at least one of the multilevel memory transistors; Verify the drain current level of each of the at least one multilevel memory transistor in the multilevel memory transistor; Selective soft erase operation is performed only on at least one of the multilevel memory transistors whose drain current level is less than the target lower limit of drain current, and unselected multilevel memory transistors are disabled; and Verify whether the drain current level of at least one of the multilevel memory transistors in the multilevel memory transistors has recovered back to the target drain current level range.

9. The method according to claim 8, wherein, The refill and annealing algorithm is configured to maintain the drain current level of the at least one multilevel memory transistor in the multilevel memory transistor within the target drain current range when replacing the charge in the shallow traps with the charge in the deep traps of the charge trapping layer of the at least one multilevel memory transistor in the multilevel memory transistor, wherein the refill programming operation promotes the deep trap charge by applying a high gate-to-drain voltage bias and a short programming pulse to the at least one multilevel memory transistor in the multilevel memory transistor, and wherein the annealing erase operation is configured to clear the shallow trap charge via Fowler-Nordheim tunneling by applying a low gate-to-drain voltage bias and a long erase pulse to the at least one multilevel memory transistor in the multilevel memory transistor.

10. The method of claim 1, wherein at least one of the multilevel memory transistors is arranged in the same row or the same column.

11. A method of operating a semiconductor device, comprising: A first non-volatile memory cell based on a silicon-silicon dioxide-silicon nitride-silicon dioxide-silicon non-volatile memory array is selected for a selective soft erase operation, wherein the silicon-silicon dioxide-silicon nitride-silicon dioxide-silicon non-volatile memory array comprises non-volatile memory cells arranged in rows and columns, and wherein adjacent first and second column non-volatile memory cells are coupled to a first shared source line; A first negative voltage is generated and coupled to a first silicon-silicon-nitride-silicon-silicon word line in the first row of the silicon-silicon-oxygen-nitride-silicon-silicon-based nonvolatile memory array, and a positive voltage is generated and coupled to a first bit line in the first column to apply a gate-to-drain voltage bias to a first nonvolatile memory transistor in the first nonvolatile memory cell, thereby partially erasing the first nonvolatile memory cell via Fowler-Nordheim tunneling, wherein the drain current level and threshold voltage level of the first nonvolatile memory transistor are increased and decreased, respectively; and A disable voltage is coupled to a second bit line in the second column to reduce the gate-to-drain voltage bias of a second non-volatile memory transistor in a second non-volatile memory cell in the first row that is not selected for the selective soft erase operation, wherein the disable voltage has the same polarity as the first negative voltage and a smaller magnitude than the first negative voltage, and wherein the second non-volatile memory transistor has approximately the same drain current and threshold voltage levels before and after the selective soft erase operation.

12. The method of claim 11, further comprising: The ground voltage is coupled to the second silicon-silicon-silicon-nitride-silicon-silicon word line in the second row of the silicon-silicon-oxygen-nitride-silicon-silicon-based non-volatile memory array, so that all non-volatile memory cells in the second row are not selected for the selective soft erase operation.

13. The method of claim 11, further comprising: The inhibit voltage is generated and coupled to the first word line and shallow positive well node in the first row of the silicon-silicon dioxide-silicon nitride-silicon dioxide-silicon non-volatile memory array to turn off the first field-effect transistor in the first non-volatile memory cell and the second field-effect transistor in the second non-volatile memory cell. as well as The positive voltage is coupled to the deep negative well node.

14. The method according to claim 11, wherein, Each of the non-volatile memory cells includes a non-volatile memory transistor configured to store one of Nx values ​​corresponding to N levels of drain current and threshold voltage, where N is a natural number greater than 2, and wherein the selective soft erase operation is configured to increase the drain current level of the first non-volatile memory transistor and decrease the threshold voltage level of the first non-volatile memory transistor such that the value stored in the first non-volatile memory transistor changes from a first value to a second value, and wherein the second value is greater than the first value.

15. The method according to claim 14, wherein, Each of the Nx levels of drain current and threshold voltage includes a distribution, wherein two adjacent drain current or threshold voltage distributions have an overlap frequency of less than 3%, and wherein the Nx levels of drain current and threshold voltage are linearly increasing and decreasing, respectively.

16. A semiconductor device, comprising: A non-volatile memory array based on semiconductor-silicon dioxide-silicon nitride-silicon dioxide-semiconductor, the non-volatile memory array comprising non-volatile memory cells arranged in rows and columns, wherein each non-volatile memory cell comprises a non-volatile memory transistor and a field-effect transistor, and wherein each non-volatile memory transistor is configured to store Nx analog values ​​corresponding to N levels of drain current or threshold voltage level of each non-volatile memory transistor; A digital-to-analog converter functional element that receives and converts digital signals from an external device, wherein the converted digital signals are configured such that analog values ​​stored in at least one non-volatile memory cell in at least one column are read. The multiplexer functional elements are configured to select and combine the analog values ​​read from the at least one non-volatile memory cell; and An analog-to-digital conversion function element is configured to convert the analog result of the column multiplexer function element into a digital value and output the digital value.

17. The semiconductor device according to claim 16, wherein, The Nx analog values ​​are written to the non-volatile memory transistors through a series of partial programming and selective partial erasure operations, wherein the selective partial erasure operations are configured to increase the drain current level of the selected non-volatile memory transistors in the same row and decrease the threshold voltage level of the selected non-volatile memory transistors in the same row, and in parallel disable the unselected non-volatile memory transistors in the same row.

18. The semiconductor device according to claim 17, wherein, A read operation is performed after each of the partial programming operation and the selective partial erase operation to verify whether the drain current or threshold voltage level of the selected non-volatile memory transistor has reached the target drain current and threshold voltage level.

19. The semiconductor device according to claim 16, wherein, The plurality of semiconductor devices are disposed on the same semiconductor die and communicatively coupled to each other, each of the plurality of semiconductor devices being configured to perform a multiplication-accumulation operation based on the analog value stored in the non-volatile memory cell and a digital input from at least one other semiconductor device among the plurality of semiconductor devices.

20. The semiconductor device of claim 19, wherein, A first subset of the plurality of semiconductor devices outputs a digital result of the multiplication-accumulation operation, wherein the digital result of the first subset is coupled as a digital input to a second subset of the plurality of semiconductor devices.

21. The semiconductor device according to claim 20, wherein, The semiconductor devices are configured to function as artificial neurons in deep neural networks that perform neuromorphic computations in artificial intelligence applications.

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