A computing system including a host and a storage system

Abstract

A computing system includes a storage system configured to store data, and a host configured to compress a data block of a preset size loaded to a memory, generate a merged block of the preset size by merging a compressed block corresponding to the data block, an identifier of a node block referencing the data block, and an offset indicating an index of the data block among at least one data block referenced by the node block, and provide the merged block to the storage system.

Description

[0001] Cross-references to related applications

[0002] This application is based on and claims priority to Korean Patent Application No. 10-2021-0004937, filed January 13, 2021; Korean Patent Application No. 10-2021-0078288, filed June 16, 2021; and Korean Patent Application No. 10-2021-0191117, filed December 29, 2021, the disclosures of which are incorporated herein by reference in their entirety. Technical Field

[0003] Embodiments of the present invention relate to a computing system, and more specifically, to a computing system comprising a host and a storage system. Background Technology

[0004] When random data is updated, file systems (such as Extended File System 4 (EXT4)) rewrite the new data to the original location. This is called an in-place update scheme. Log-structured file systems (LFS) use an out-of-place update scheme, which invalidates the old data and writes the new data to another location. Summary of the Invention

[0005] Embodiments of the present invention relate to a computing system that provides improved write performance by asynchronously writing compressed data blocks, node identifiers, and offsets to merged blocks.

[0006] According to one aspect of the present invention, a computing system including a storage system and a host is provided, the storage system being configured to store data, and the host being configured to compress data blocks of a preset size loaded into memory, by generating a merged block of the preset size by merging compressed blocks corresponding to the data blocks, identifiers of node blocks referencing the data blocks, and offsets indicating the indexes of at least one data block referenced by the node blocks, and providing the merged block to the storage system.

[0007] According to one aspect of the present invention, a host device for writing data to a storage system is provided, the host device including a memory for storing data to be written to or read from the storage system; a compression manager configured to compress data blocks of a preset size loaded into the memory; and a file system configured to receive compressed blocks corresponding to the data blocks from the compression manager, generate a merged block by merging the compressed blocks, an identifier of a node block referencing the data blocks, and an offset indicating an index of a data block in at least one data block referenced by the node block, and write the merged block to the storage system.

[0008] According to one aspect of the present invention, a computing system including a Universal Flash Memory (UFS) system is provided, the system including a plurality of storage regions and a UFS host, the UFS host being configured to store merged blocks in a first storage region among the plurality of storage regions, the merged blocks merging compressed data blocks into compressed blocks, identifiers of node blocks referencing the data blocks, and offsets indicating the indexes of at least one data block referenced by the node blocks, and storing node blocks indicating the addresses of the data blocks in a second storage region among the plurality of storage regions. Attached Figure Description

[0009] Embodiments of the inventive concept will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 This is a schematic diagram of a computing system according to an embodiment of the concept of the present invention;

[0011] Figure 2 This is an embodiment of the concept of the present invention. Figure 1 A block diagram of the host computer;

[0012] Figure 3 This is an embodiment of the concept of the present invention. Figure 1 A block diagram of a storage device;

[0013] Figure 4 It is stored in an embodiment of the present invention. Figure 1 A view of the structure of files in a storage device;

[0014] Figure 5 This is an embodiment of the concept of the present invention. Figure 1 A block diagram of a storage device;

[0015] Figure 6 This is a schematic diagram of a node address table according to an embodiment of the present invention.

[0016] Figure 7 This is a schematic diagram of a method for accessing data blocks according to an embodiment of the present invention;

[0017] Figure 8 This is a schematic diagram of a write operation according to an embodiment of the present invention;

[0018] Figure 9 This is a schematic diagram of the operation method of a computing system according to an embodiment of the present invention;

[0019] Figure 10 This is a flowchart of a host operation method according to an embodiment of the present invention;

[0020] Figure 11 This is a schematic diagram of a sudden power outage recovery operation according to an embodiment of the present invention.

[0021] Figure 12 This is a schematic diagram of an operation method of a computing system performing a recovery operation according to an embodiment of the present invention;

[0022] Figure 13 A computing system according to an embodiment of the concept of the present invention is shown;

[0023] Figure 14 This is a block diagram of a computing system according to an embodiment of the present invention; and

[0024] Figure 15 This is a schematic diagram of a Universal Flash Memory (UFS) system according to an embodiment of the present invention. Detailed Implementation

[0025] Embodiments of the inventive concept will now be described more fully with reference to the accompanying drawings. Throughout the drawings, the same reference numerals may refer to the same elements.

[0026] It should be understood that the terms "first," "second," "third," etc., are used herein to distinguish one element from another, and these elements are not limited by these terms. Therefore, a "first" element in one embodiment can be described as a "second" element in another embodiment.

[0027] It should be understood that the description of features or aspects within each embodiment should generally be considered to be available for other similar features or aspects in other embodiments, unless the context clearly indicates otherwise.

[0028] As used in this article, the singular forms “a,” “one,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0029] In this document, when a value is described as approximately equal to another value, or substantially the same as or equal to another value, it should be understood that these values ​​are identical, that they are equal to each other within a measurement error, or, if measurably unequal, that they are sufficiently close in value to be functionally equal to each other, as understood by one of ordinary skill in the art. For example, the term “approximately” as used herein includes the stated value and means within an acceptable range of deviation for a particular value determined by one of ordinary skill in the art considering measurement and error in relation to a problem related to the measurement of a particular quantity (i.e., limitations of the measurement system). For example, “approximately” may mean within one or more standard deviations as understood by one of ordinary skill in the art. Furthermore, it should be understood that while a parameter may be described herein as having “approximately” a certain value, according to embodiments, the parameter may be an exact value or an approximation of a value within a measurement error as understood by one of ordinary skill in the art.

[0030] Figure 1 This is a schematic diagram of a computing system according to an embodiment of the concept of the present invention.

[0031] refer to Figure 1 The computing system 10 may include a host 100 and a storage system 200.

[0032] Host 100 can provide storage system 200 with write requests, read requests, or erase requests for data. Storage system 200 can store data in a storage area in response to a write request, read data stored in the storage area and provide the read data to host 100 in response to a read request, and perform an erase operation on the data in response to an erase request. Data can be stored or retrieved in preset blocks (e.g., 4KB).

[0033] Host 100 may include file system 110. File system 110 can process data, allowing the data to be stored in a specific logical or physical location within a storage area included in storage system 200. For example, file system 110 can process data provided by a user application and store the processed data in storage system 200.

[0034] In this context, in this embodiment, the file system 110 may be a journaling file system (LFS). For example, the file system 110 may be a flash-friendly file system (F2FS), which is a file system for the Linux kernel designed based on the characteristics of flash memory, or a journaling flash file system (JFFS), which is a Linux LFS used in NOR flash devices.

[0035] However, the type of file system 110 is not limited to LFS, and when files are updated, embodiments of the inventive concept can be applied to any file system of a type where new data is written to a logical address different from the logical address where existing data is written.

[0036] Storage system 200 may include storage controller 210 and storage device 220. Storage device 220 may include at least one non-volatile memory. Storage controller 210 may translate logical addresses received from host 100 into physical addresses and control storage device 220 to store data in a storage area with physical addresses.

[0037] Storage system 200 may include a storage medium that stores data in response to a request from host 100. For example, storage system 200 may include one or more solid-state drives (SSDs). When storage system 200 includes SSDs, storage device 220 may include multiple flash memory chips (e.g., NAND memory chips) that store data in a non-volatile manner. Storage device 220 may correspond to a flash memory device, or storage device 220 may include a memory card containing one or more flash memory chips.

[0038] When the storage system 200 includes flash memory, the flash memory may include a two-dimensional (2D) NAND memory array or a three-dimensional (3D) (or vertical) NAND (VNAND) memory array. A 3D memory array may be monolithically formed as an array of memory cells having active regions disposed on a silicon substrate, or at least one physical layer of circuitry associated with the operation of the memory cells may be formed on or in the substrate. The term "monolithic" means that the layers constituting each level of the array are stacked close together on top of each lower level of the array.

[0039] In embodiments of the present invention, the 3D memory array may include vertically arranged VNAND strings, such that at least one memory cell is located on top of another memory cell. At least one memory cell may include a charge trap layer.

[0040] In another example, storage system 200 may include a variety of other types of memory. For example, storage system 200 may include non-volatile memory such as magnetic random access memory (MRAM), spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FeRAM), phase RAM (PRAM), resistive RAM, nanotube RAM, polymer RAM (PoRAM), nanofloating gate memory (NFGM), holographic memory, molecular electronic memory, insulator resistance change memory, etc.

[0041] For example, storage device 220 may include an embedded multimedia card (eMMC) or an embedded universal flash memory (UFS) storage device. In this example, storage device 220 may be an external storage device that is detachably attached to storage system 200. For example, storage device 220 may include, but is not limited to, a UFS memory card, a compact flash (CF) card, a secure digital card (SD) card, a microSD card, a miniSD card, an extreme digital (xD) card, or a memory stick.

[0042] The host 100 can communicate with the storage system 200 through various interfaces. For example, the host 100 can communicate with the storage system 200 through various interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), PCI-E, AT Accessory (ATA), Serial AT Accessory (SATA), Parallel AT Accessory (PATA), Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Enhanced Small Disk Interface (ESDI), Interchangeable Drive Electronic Device (IDE), Non-Volatile Memory Specification (NVMe), etc.

[0043] When updating the data of a random file with new data, the host 100 can send a write request (or write command) to the storage system 200 for the new data.

[0044] In this document, data provided by a user application to the file system 110 can be referred to as file data. File data can be stored in the storage system 200 in units of preset blocks (e.g., 4KB), and file data in blocks can be referred to as data blocks. File data may include multiple data blocks.

[0045] The file system 110 can generate node blocks corresponding to data blocks. Node blocks can include information about the data blocks. For example, a node block can include a filename, a node identifier, a file size, or a logical address of the data block. In an embodiment, the filename refers to the name of the file formed by the data blocks, the node identifier is a unique identifier for the node block, and the file size refers to the size of the file formed by the data blocks. A node block can reference multiple data blocks and can identify each of the multiple data blocks based on an offset.

[0046] Node blocks can be stored in storage system 200 in units of preset blocks (e.g., 4KB). For example, node blocks can be used to locate data blocks. For example, file system 110 can assign a node identifier to each node block. File system 110 can manage node identifiers and the logical addresses corresponding to those node identifiers through a Node Address Table (NAT). File system 110 can access node blocks through NAT and access data blocks by recognizing the logical addresses of the data blocks stored in the node blocks.

[0047] A host 100 according to an embodiment of the present invention may include a compression manager 120. The compression manager 120 can generate compressed blocks by compressing data blocks. The file system 110 can generate blocks in preset units (e.g., 4KB) by merging compressed blocks, node identifiers of node blocks corresponding to data blocks, and offsets of data blocks. Hereinafter, a block generated by merging compressed blocks, node identifiers, and offsets may be referred to as a merged block. A node block may reference multiple data blocks corresponding to file data. A node block may identify each of the multiple data blocks based on an offset. The offsets included in the merged block may be information used to identify data blocks among the multiple data blocks. In some embodiments of the present invention, the merged block may include bits indicating the merged block. The compression manager 120 may also be referred to as compression circuitry or compression manager circuitry.

[0048] The file system 110 can asynchronously write merged blocks and corresponding node blocks to the storage system 200. That is, the time periods during which merged blocks are sent to the storage system 200 and the time periods during which node blocks are sent to the storage system 200 can be discontinuous. For example, merged blocks can be sent to the storage system 200 at a different time than node blocks are sent to the storage system 200. For example, the file system 110 can write merged blocks to the storage system 200 in response to a user application request, and write node blocks to the storage system 200 during periods when the interface between the host 100 and the storage system 200 is idle. Therefore, the time periods during which the interface between the host 100 and the storage system 200 is occupied by node blocks and the time periods during which the interface is occupied by merged blocks can be distributed, thereby improving write performance.

[0049] Host 100 may include memory 130. File system 110 may divide file data provided by user applications into data blocks and load the data blocks into memory 130. File system 110 may generate node blocks corresponding to each data block and load the generated node blocks into memory 130. Memory 130 may be a volatile memory device. For example, memory 130 may include volatile memory such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, GRAM, etc.

[0050] When a sudden power outage (SPO) occurs, where power to host 100 is abruptly cut off, data loaded into memory 130 may be corrupted / erased. To prevent SPO, file system 110 can perform a checkpointing operation that stores all data loaded into memory 130 (e.g., NAT, data blocks, and node blocks) in storage system 200. Storage device 220 can continue to store data even when power is cut off. Checkpointing operations can be performed periodically or irregularly. For example, a checkpointing operation can be performed every 30 seconds. However, the interval for performing checkpointing operations is not limited to this.

[0051] When power is restored to host 100 after a sudden power outage (SPO), file system 110 can perform a sudden power outage recovery (SPOR) operation. In SPOR, file system 110 can load merged blocks into memory 130 and obtain data blocks from the merged blocks. File system 110 can obtain node identifiers and offsets from the merged blocks and generate node blocks corresponding to the data blocks.

[0052] According to an embodiment of the present invention, the file system 110 can asynchronously write merge blocks and node blocks to the storage device 220. Therefore, when an SPO occurs after a merge block has been written to the storage device 220, the node block corresponding to the merge block may be corrupted / erased in the memory 130 without being written to the storage device 220. Thus, the file system 110 can read the merge block already written to the storage device 220 and generate the node block corresponding to the merge block using the node identifier and offset included in the merge block.

[0053] Figure 2 This is an embodiment of the concept of the present invention. Figure 1 Block diagram of host 100.

[0054] refer to Figure 2 Host 100 may include user space 11 and kernel space 12.

[0055] Figure 2 The components shown can be software or hardware components, such as, for example, field-programmable gate arrays (FPGAs) or application-specific integrated circuits (ASICs). However, the components are not limited to these. For example, in some embodiments, the component may be configured to reside in an addressable storage medium or may be configured to run one or more processors. The functionality provided in the component may be implemented by more detailed components or may be implemented as a single component that performs a specific function by combining multiple components.

[0056] In this embodiment, user space 11 is the region where user application 13 runs, and kernel space 12 is a region reserved for kernel operation with restrictions. System calls can be used to allow user space 11 to access kernel space 12.

[0057] The kernel space 12 may include a virtual file system 14, a file system 110, a device driver 15, etc. According to embodiments, there may be one or more file systems 110. In some embodiments, the file system 110 may be F2FS.

[0058] In some embodiments, the file system 110 may divide the storage area of ​​the storage device 220 into multiple blocks, multiple sections, and multiple zones, and write logs provided by the user application 13 to each block. (See also...) Figure 5 The storage area of ​​storage device 220 is divided into multiple blocks, multiple groups, and multiple domains in detail.

[0059] Virtual file system 14 can allow one or more file systems 110 to interoperate. Virtual file system 14 enables the use of standardized system calls to perform read / write operations on different file systems 110 on different media. Therefore, for example, system calls such as open(), read(), and write() can be used regardless of the type of file system 110. That is, virtual file system 14 can be an abstraction layer existing between user space 11 and file system 110.

[0060] Device driver 15 can manage the interface between hardware and user application 13 (or operating system). Device driver 15 can be a program that enables the hardware to function properly under a specific operating system.

[0061] Figure 3 This is an embodiment of the concept of the present invention. Figure 1 Block diagram of storage device 220.

[0062] refer to Figure 3 The storage area of ​​storage device 220 can be configured to include blocks 31, segments 32, groups 33, and domains 34. The storage area of ​​storage device 220 can include multiple domains 34. A domain 34 can include multiple groups 33, a group 33 can include multiple segments 32, and a segment 32 can include multiple blocks 31. For example, a block 31 can be a storage area storing 4KB of data, and a segment 32 can be a storage area storing 2MB of data by including 512 blocks 31. Figure 3 The configuration of the storage device 220 shown can be determined at the time of formatting the storage device 220, but is not limited thereto. The file system 110 can read and write data in units of 4KB pages. That is, block 31 can store one page.

[0063] Figure 4 It is stored in an embodiment of the present invention. Figure 1 A view of the structure of the files in the storage device 220.

[0064] Files stored in storage device 220 may have an index structure. A file may include file data and node data, the file data including data to be processed by user application 13 ( Figure 2 The content of the stored file is represented by the node data, which includes the file's attributes and the location of the data blocks where the file data will be stored.

[0065] refer to Figure 4 Data blocks 41 to 44 can be storage areas for storing file data, and node blocks 51 to 57 can be storage areas for storing node data.

[0066] Node blocks 51 to 57 may include index node block 51, direct node blocks 52, 54 and 57, and indirect node blocks 53, 55 and 56.

[0067] Inode block 51 may include at least one of the following: a direct pointer to data block 41, a single indirect pointer to direct block 52, a double indirect pointer to indirect block 53, or a triple indirect pointer to indirect block 55. Inode blocks may be provided for each file. Although each of inode blocks 51 to 57 is shown as indicating a data block, the embodiment is not limited thereto. Each of inode blocks 51 to 57 may indicate multiple data blocks. In some embodiments, each of the multiple data blocks may be identified based on an offset. The offset may be an index of each of the multiple data blocks.

[0068] Indirect node blocks 52, 54, and 57 may include data pointers that directly point to data blocks 41, 43, and 44.

[0069] Indirect node blocks 53, 55, and 56 may include first indirect node blocks 53 and 56 and a second indirect node block 55. First indirect node blocks 53 and 56 may include first node pointers to direct node blocks 54 and 57. Second indirect node block 55 may include second node pointers to first indirect node block 56.

[0070] Figure 5 This is an embodiment of the concept of the present invention. Figure 1 A block diagram of a storage device. Figure 6 This is a schematic diagram of a NAT according to an embodiment of the present invention.

[0071] refer to Figure 5 The storage area of ​​storage device 220 may include a first region REGION 1 and a second region REGION 2. In file system 110, the storage area of ​​storage device 220 may be formatted as a first region REGION 1 and a second region REGION 2, but the embodiments of the present invention are not limited thereto.

[0072] In this embodiment, the first region REGION 1 is a region that stores multiple pieces of information managed by the entire system, and may include, for example, the number of currently allocated files, the number of valid pages, and their locations. In this embodiment, the second region REGION 2 is a storage area that stores multiple pieces of directory information, data, file information, etc., actually used by the user.

[0073] REGION 1 may include the first superblock SB1 61, the second superblock SB2 62, the checkpoint area (CP area) 63, the segment information table (SIT) 64, NAT 65, the segment summary area (SSA) 66, etc.

[0074] The first superblock SB1 61 and the second superblock SB2 62 can store default information about the file system 110. For example, they can store the size of the first superblock SB1 61, the number of blocks 61, and the state plugs of the file system 110 (clean, stable, active, logged, unknown). As shown in the figure, the first superblock 61 and the second superblock 62 can be two blocks in total, with each block storing the same content. Therefore, even if either of the two superblocks encounters a problem, the other superblock can be used.

[0075] CP 63 can store checkpoints. Checkpoints can be logical breakpoints, and the state of the breakpoint can be fully preserved. When an SPO occurs during the operation of computing system 10, file system 110 can recover the data using the saved checkpoints. Checkpoints can be generated periodically. However, checkpoint generation is not limited to this.

[0076] NAT 65 can include multiple node identifiers (NODE IDs) corresponding to node blocks and multiple addresses corresponding to the multiple node identifiers, such as... Figure 6 As shown. For example, the node block corresponding to node identifier N1 can correspond to address A1, the node block corresponding to node identifier N2 can correspond to address A2, and the node block corresponding to node identifier N3 can correspond to address A3.

[0077] All nodes (index nodes, direct nodes, indirect nodes, etc.) can have their unique node identifiers. NAT 65 can store the node identifiers of index nodes, direct nodes, indirect nodes, etc. The file system 110 can update the address corresponding to each node identifier.

[0078] SIT 64 can include the number of valid pages per segment and a bitmap of multiple pages. In the bitmap, whether each page is valid can be indicated by 0 or 1. SIT 64 can be used for scrubbing tasks (or garbage collection). For example, when performing a scrubbing task, the bitmap can reduce unnecessary read requests, and it can also be used when performing block allocation in an adaptive data logging log.

[0079] In an embodiment, SSA 66 is a region that aggregates summary information for each segment of the second region REGION 2. For example, SSA 66 may describe node information for multiple blocks comprising each segment of the second region REGION 2. SSA 66 can be used for cleaning tasks (or garbage collection). For example, an upper node block may have a list of node identifiers or addresses to identify the location of data blocks 41 to 44 or lower node blocks. In an embodiment, an upper node block is a node block that references a lower node block via a node pointer, and a lower node block is a node block that is referenced by an upper node block via a node pointer. SSA 66 may provide an index that allows data blocks 41 to 44 or lower node blocks to identify the location of an upper node block. SSA 66 may include multiple segment summary blocks. A segment summary block may have information about a segment located in the second region REGION 2. A segment summary block may include multiple summary pieces of information, and one summary piece of information may correspond to a data block or a node block.

[0080] Figure 7 This is a schematic diagram of a method for accessing data blocks according to an embodiment of the present invention. The following will refer to... Figure 1 describe Figure 7 .

[0081] refer to Figure 7 Data block 710 may include at least a portion of file data. Data block 710 may be stored at address A2. Node block 720 may store address A2 indicating the storage location of data block 710, and may also be stored at address A1. File system 110 may assign node identifier N1 to node block 720.

[0082] File system 110 can access the data block corresponding to node identifier N1 by referring to NAT. File system 110 can obtain address A1 from NAT. File system 110 can access node block 720 by using address A1. File system 110 can obtain address A2 from node block 720. File system 110 can access data block 710 by using address A2.

[0083] exist Figure 7 In the middle, node block 720 can correspond to Figure 4The direct node blocks 52, 54, and 57. However, embodiments of the present invention are not limited thereto. For example, in some embodiments, the file system 110 may access the data block 710 by using indirect node blocks 53, 55, and 56 or inode block 51.

[0084] Figure 8 This is a schematic diagram of a write operation according to an embodiment of the present invention. The following will refer to... Figure 1 and Figure 2 describe Figure 8 .

[0085] The file system 110 can use data loaded onto the memory 130 to provide data for use by user applications, and update the data loaded onto the memory 130 based on file data provided by user applications. The memory 130 is volatile memory, allowing the file system 110 to write data from the memory 130 to the storage system 200, which includes non-volatile memory, to protect the data. The host 100 can write data loaded onto the memory 130 to the storage system 200 through multiple operations S810 to S850.

[0086] In operation S810, the compression manager 120 included in the host 100 can generate a compressed block c_BLOCK by compressing the first data block DATABLOCK 1. The size of the first data block DATABLOCK 1 can be L1. In some embodiments of the present invention, L1 can be 4KB. The size of the compressed block c_BLOCK can be L2, which is smaller than L1. The compression manager 120 can compress the first data block DATABLOCK 1 by using a compression algorithm, such as run-length encoding schemes, Huffman coding schemes, arithmetic coding schemes, entropy coding schemes, Markov chain schemes, range coding schemes, or differential pulse code modulation schemes.

[0087] In operation S820, the file system 110 can generate a merged block m_BLOCK by merging the compressed block c_BLOCK, the node identifier N1, and the offset ofs of the first data block DATA BLOCK 1. The size of the merged block m_BLOCK can be L1. In some embodiments of the present invention, L1 can be 4KB. That is, the sum of the size L2 of the compressed block c_BLOCK, the size L3 of the node identifier N1, and the size L4 of the offset ofs can be L1. The file system 110 can generate a node block 810 corresponding to the first data block DATA BLOCK 1. The node block 810 can be a block including the node identifier N1 and the address A2. The address A2 can indicate the location where the merged block m_BLOCK is stored. The node block 810 can reference multiple data blocks including the first data block DATA BLOCK 1. The node block 810 can identify the first data block DATA BLOCK 1 based on the offset ofs among the multiple data blocks.

[0088] During operation S830, the file system 110 can write the merged block m_BLOCK to the storage system 200. The merged block m_BLOCK can be written to the data log included in the storage device 220. In the data log, data blocks can be written sequentially. Therefore, the merged block m_BLOCK can be written sequentially from the location immediately adjacent to where the second data block DATA BLOCK 2 (which is an existing data block) is stored. The first data block DATA BLOCK 1 and the second data block DATA BLOCK 2 can be data about the same file, where the first data block DATA BLOCK 1 can be the latest data block, and the second data block DATA BLOCK 2 can be an existing data block. In the embodiment, the data log means corresponding to Figure 5 The storage area for the data segment. The first data block, DATA BLOCK 1, can be a merged block.

[0089] In operation S840, the file system 110 can write node block 810 corresponding to the merge block m_BLOCK to the storage system 200. Node block 810 can be written to the node log included in the storage device 220. Node blocks can be written sequentially in the node log. Therefore, node block 810 can be written sequentially from the location immediately adjacent to where the second node block 820 (which is an existing data block) is stored. The second node block 820 can store the address A4 of the second data block DATA BLOCK 2, which is an existing data block. Operation S840 can be performed during the idle time when the interface between the host 100 and the storage system 200 is not occupied by data. That is, the time period for writing the merge block m_BLOCK. The time period for writing node block 810 can be discontinuous. For example, the time when the interface between the host 100 and the storage system 200 is occupied by the merge block m_BLOCK and the time when the interface is occupied by node blocks can be distributed to improve write performance.

[0090] In operation S850, the file system 110 can perform an update operation on the NAT by executing a write operation that changes the address of node identifier N1 to A1. Before the update operation, address A3 can correspond to node identifier N1 on the NAT of storage system 200. After the update operation, address A1 can correspond to node identifier N1.

[0091] After operating S850, even when SPO occurs, the file system 110 can read the address A1 corresponding to the node identifier N1 by referring to the NAT stored in the storage system 200, access the node block 810 by using the address A1, and access the merge block m_BLOCK by using the address A2 stored in the node block 810.

[0092] The file system 110 according to an embodiment of the present invention can access the merged block m_BLOCK, update the node block 810 indicating the merged block m_BLOCK, and update the NAT to indicate the node block 810, even when an SPO occurs after operation S830.

[0093] Figure 9 This is a schematic diagram of the operation method of a computing system according to an embodiment of the present invention.

[0094] refer to Figure 9 The operation method of the computing system may include multiple operations S910 to S960.

[0095] In operation of S910, user applications can send write requests w_REQ to file system 110. A write request w_REQ can be a system call. For example, a write request w_REQ can be written().

[0096] In operation S920, the file system 110 can generate a data block corresponding to the write request and send the data block to the compression manager 120. The file system 110 can generate at least one node block corresponding to the data block. The at least one node block can include at least one of an inode block, a direct block, or an indirect block. The data block and the node block can have a preset size L1 (e.g., 4KB).

[0097] In operation S930, compression manager 120 can generate a compressed block c_BLOCK. For example, compression manager 120 can stop the compression operation based on whether the size of the data block has decreased by a reference size. The reference size can be determined based on the sum of the size of the node identifier and the size of the data block offset. In some embodiments of the inventive concept, the reference size can be determined based on the size of the node identifier, the size of the offset, and the size of the compression mark. In embodiments, the compression mark means at least one bit indicating that the data block is being compressed. In operation S930, when the size of the data block has not decreased by the reference size, compression manager 120 can provide a compression failure signal to file system 110.

[0098] In operation S940, the compression manager 120 can provide a compressed block c_BLOCK to the file system 110. The size of the compressed block c_BLOCK may be L2, which is smaller than L1.

[0099] In operation S950, file system 110 can generate a merge block m_BLOCK. For example, file system 110 can generate a merge block m_BLOCK by merging compressed block c_BLOCK, data block offsets, and node identifiers. The size of the merge block m_BLOCK can be equal to the size of the data blocks. For example, the size of the merge block m_BLOCK can be 4KB.

[0100] In operation S960, the file system 110 can send a write command w_CMD and a merge block m_BLOCK to the storage system 200. When the storage system 200 has idle time after the file system 110 sends the merge block m_BLOCK, a node block can be sent to the storage system 200. That is, the storage system 200 can asynchronously write the merge block m_BLOCK and the node block. In operation S930, when no compressed block c_BLOCK is generated, the file system 110 can send a write command w_CMD, a data block, and a node block to the storage system 200. That is, the storage system 200 can synchronously write the data block and the node block.

[0101] Figure 10 This is a flowchart of a host operation method according to an embodiment of the present invention.

[0102] refer to Figure 10 The host's operation methods may include multiple operations S1010 to S1060.

[0103] In operation S1010, the compression manager 120 can perform a compression operation on the first part of the data block. The first part can be a portion with a preset size of the data block. The compression size can vary depending on the data state of the portion with the preset size and the compression algorithm.

[0104] In operation S1020, the compression manager 120 can compare the compressed size with a reference size. In some embodiments of the inventive concept, the compression manager 120 can compare the size reduced by the compression of the first portion with the reference size. The reference size may correspond to the sum of the size of the node identifier and the size of the offset of the data block. In some embodiments of the inventive concept, the reference size may correspond to the size of the node identifier, the size of the offset, and the size of the merge tag. When the compressed size is less than the reference size, operation S1040 can be performed, and when the compressed size is equal to or greater than the reference size, operation S1030 can be performed.

[0105] In operation S1030, the file system 110 can generate a merged block and send it to the storage system 200. The file system 110 can also send the merged block along with a write command to the storage system 200 to perform a write operation on the merged block. The file system 110 can provide the storage system 200 with node blocks corresponding to the merged block at a time period different from the time the merged block is sent, thereby improving write performance.

[0106] In operation S1040, the compression manager 120 can determine whether maximum compression has been performed on the data block. When maximum compression is performed, operation S1060 can be executed, while when maximum compression is not performed, operation S1050 can be executed.

[0107] In operation S1050, compression manager 120 can compress the next portion of the data block. The next portion of the data block can have a size equal to or different from the size of the first portion. After compressing the next portion, operation S1020 can be performed again. Because compression manager 120 compresses the data block in a stepwise manner, the compression time used to generate the merged block can be reduced.

[0108] In operation S1060, the file system 110 can send data blocks and node blocks to the storage system 200, so that the data blocks and node blocks are written to the storage system 200 in a continuous time period.

[0109] Figure 11 This is a schematic diagram of the SPOR operation according to an embodiment of the present invention.

[0110] refer to Figure 8 After operating S830, an SPO (Special Purpose Error) may occur. Therefore, if node block 810 is not written to the node log, the data in memory 130 may be corrupted / eraseed. That is, as... Figure 11 As shown, an SPO may occur when the merged block m_BLOCK is written to the data log and the first node block 810 corresponding to the merged block m_BLOCK is not written. Therefore, the existing second node block 820 written to the node log may indicate the address A4 of the second data block DATA BLOCK 2, which is an existing data block, instead of the address A2 of the merged block m_BLOCK. The SPR operation may include multiple operations S1110 to S1150.

[0111] In operation S1110, file system 110 can load NAT into storage 130. Although in Figure 11 The illustration shows existing data being written to the NAT, but embodiments of the present invention are not limited thereto. For example, in some embodiments, the NAT loaded into memory 130 may store address A3 corresponding to node identifier N1 and address A2 corresponding to node identifier N1.

[0112] In operation S1120, file system 110 can load merged blocks m_BLOCK that have been written to the data log into memory 130. When blocks are written sequentially to the data log, file system 110 can load blocks sequentially into memory 130 starting with the most recently written block. Figure 11 The diagram shows the merge block m_BLOCK being loaded, but the data block that replaces the merge block can be loaded into memory 130. File system 110 can load the second node block 820, which is written to the node log, into memory 130.

[0113] In operation S1130, the file system 110 can search for the merged block m_BLOCK among the loaded blocks. The file system 110 can search for the merged block m_BLOCK by recognizing the merge marker e_m among the loaded blocks.

[0114] In operation S1140, the file system 110 can generate the first node block 810 by updating the second node block 820, such that the second node block 820 corresponds to the merged block m_BLOCK. For example, the file system 110 can update the second node block 820 based on the node identifier N1 included in the merged block m_BLOCK and the offset ofs of the data blocks. As multiple data blocks are sequentially written to the data log and the sizes of the multiple data blocks are determined, the file system 110 can obtain the address of the merged block m_BLOCK. Furthermore, the file system 110 can connect the first node block 810 to the first data block DATA BLOCK 1 based on the offset ofs. Specifically, the file system 110 can set the data block corresponding to the offset ofs among the multiple data blocks referenced by the first node block 810 as the first data block DATA BLOCK 1. Therefore, since the second node block 820 can be updated to the first node block 810 based on the node identifier N1 and the offset ofs, even when no execution is performed... Figure 8 When operating S840, the first node block 810 can also be restored.

[0115] During operation S1150, file system 110 can update NAT. For example, file system 110 can update the address corresponding to node identifier N1 from A3 to A1.

[0116] Figure 12 This is a schematic diagram of an operation method of a computing system performing a recovery operation according to an embodiment of the present invention.

[0117] refer to Figure 12 The operation method of the computing system may include multiple operations S1210 to S1240.

[0118] In operation S1210, the file system 110 can send a read command r_CMD to the storage system 200. The file system 110 can send the address of a recently written data log block along with the read command r_CMD to the storage system 200. The address of the recently written block can be obtained through CP. The recently written block can be the most recently written block (e.g., the most recently written block).

[0119] In operation S1220, storage system 200 can send the merge block m_BLOCK to file system 110. Storage system 200 can send data blocks, node blocks, and the merge block m_BLOCK.

[0120] In operation S1230, the file system 110 can search for a merged block m_BLOCK among the blocks received from the storage system 200, and send the compressed block c_BLOCK, which is included in the found merged block m_BLOCK, to the compression manager 120.

[0121] In operation S1240, the compression manager 120 can generate data blocks by decompressing the compressed block c_BLOCK and send the data blocks to the file system 110. The data blocks can be stored in the memory 130.

[0122] In operation S1250, the file system 110 can generate node blocks corresponding to data blocks based on the node identifiers and addresses included in the merge block m_BLOCK. The node blocks can be stored in the memory 130.

[0123] Figure 13 This is a schematic diagram of a computing system 1000 that utilizes a storage device according to an embodiment of the present invention. Figure 13 System 1000 can be, for example, a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet PC, a wearable device, a healthcare device, or an Internet of Things (IoT) device. However, Figure 13 System 1000 is not necessarily limited to this type of mobile system and can be, for example, a personal computer, laptop computer, server, media player, or automotive equipment (e.g., a navigation device). System 1000 may include Figure 1 The computing system 10.

[0124] refer to Figure 13 The computing system 1000 may include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage system (e.g., 1300a and 1300b). Furthermore, the computing system 1000 may include at least one of an image capture device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480.

[0125] The main processor 1100 can control all operations of the computing system 1000, including, for example, the operations of components included in the computing system 1000. The main processor 1100 can be implemented as, for example, a general-purpose processor, a special-purpose processor, or an application processor.

[0126] The main processor 1100 may include at least one CPU core 1110 and may further include a controller 1120 configured to control memories 1200a and 1200b and / or storage systems 1300a and 1300b. In some embodiments, the main processor 1100 may also include an accelerator 1130, which is dedicated circuitry for high-speed data operations, such as artificial intelligence (AI) data operations. The accelerator 1130 may include, for example, a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and is implemented as a chip physically separate from other components of the main processor 1100.

[0127] Memory 1200a and 1200b can be used as the main memory device of computing system 1000. Although each of memory 1200a and 1200b may include volatile memory, such as static random access memory (SRAM) and / or dynamic RAM (DRAM), in some embodiments, each of memory 1200a and 1200b may include non-volatile memory, such as flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM). Memory 1200a and 1200b may be implemented in the same package as main processor 1100. Figure 1 The host 100 can be generated by Figure 13 The main processor 1100 and memory 1200a and 1200b are implemented.

[0128] Storage systems 1300a and 1300b can be used as non-volatile storage devices configured to store data, regardless of whether they are powered, and have a larger storage capacity than memories 1200a and 1200b. Storage systems 1300a and 1300b may each include storage controllers 1310a and 1310b and NVMs 1320a and 1320b configured to store data via the control of storage controllers 1310a and 1310b. While NVMs 1320a and 1320b may include flash memory with a two-dimensional (2D) or three-dimensional (3D) NAND structure, in some embodiments, NVMs 1320a and 1320b may include other types of NVMs, such as PRAM and / or RRAM.

[0129] Storage systems 1300a and 1300b may be physically separate from the main processor 1100 and included in the computing system 1000, or implemented in the same package as the main processor 1100. Storage systems 1300a and 1300b may be solid-state devices (SSDs) or memory cards and may be removably combined with other components of the system 1000 via interfaces such as connection interface 1480, which will be further described below. Storage systems 1300a and 1300b may be devices applying standard protocols, such as, for example, Universal Flash Memory (UFS), embedded multimedia card (eMMC), or Non-Volatile Memory Specification (NVMe), but are not limited thereto. Figure 1 The storage system 200 may be included in at least one of the storage systems 1300a and 1300b.

[0130] Image capture device 1410 can capture still images or moving images. Image capture device 1410 may include, for example, a camera, video camera, and / or webcam.

[0131] User input device 1420 can receive various types of data input by the user of system 1000, and includes, for example, a touchpad, keypad, keyboard, mouse and / or microphone.

[0132] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the computing system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include, for example, temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0133] Communication device 1440 can send and receive signals between other devices outside system 1000 according to various communication protocols. Communication device 1440 may include, for example, an antenna, a transceiver, and / or a modem.

[0134] The display 1450 and the speaker 1460 can be used as output devices and are configured to output visual and auditory information to the user of the system 1000, respectively.

[0135] The power supply device 1470 can appropriately convert power supplied from a battery and / or an external power source embedded in the computing system 1000 and supply the converted power to each of the components of the computing system 1000.

[0136] The connection interface 1480 provides a connection between the computing system 1000 and an external device that connects to the computing system 1000 and can send and receive data from the computing system 1000. The connection interface 1480 can be implemented using various interface schemes, such as Advanced Technology Attachment (ATA), Serial ATA (SATA), External SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral Component Interconnect (PCI), PCIe, NVMe, IEEE 1394, Universal Serial Bus (USB) interface, Secure Digital (SD) card interface, Multimedia Card (MMC) interface, eMMC interface, UFS interface, Embedded UFS (eUFS) interface, and Compact Flash (CF) card interface, etc.

[0137] Figure 14 This is a block diagram of a computing system 2000 according to an embodiment of the present invention.

[0138] Computing system 2000 may include host 2100 and storage system 2200. Storage system 2200 may include storage controller 2210 and NVM 2220. According to an embodiment, host 2100 may include host controller 2110 and host memory 2120. Host memory 2120 may be used as buffer memory and is configured to temporarily store data to be sent to or received from storage system 2200. Host 2100 is... Figure 1 Example of host 100.

[0139] Storage system 2200 may include storage media configured to store data in response to a request from host 2100. As an example, storage system 2200 may include at least one of SSD, embedded memory, and removable external memory. When storage system 2200 is an SSD, it may be an NVMe-compliant device. When storage system 2200 is embedded memory or external memory, it may be a UFS-compliant or eMMC-compliant device. Each of host 2100 and storage system 2200 may generate and send a packet according to a standard protocol adopted.

[0140] When the NVM 2220 of the storage system 2200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage system 2200 may include a variety of other types of NVM. For example, the storage system 2200 may include magnetic RAM (MRAM), spin-torque MRAM, conductive bridged RAM (CBRAM), ferroelectric RAM (FRAM), PRAM, RRAM, and a variety of other types of memory.

[0141] According to embodiments, the host controller 2110 and host memory 2120 can be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 2110 and host memory 2120 can be integrated into the same semiconductor chip. As an example, the host controller 2110 can be any of a plurality of modules included in an application processor (AP). The AP can be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 2120 can be embedded memory included in the AP or in an NVM or memory module external to the AP.

[0142] The host controller 2110 can manage operations that store data (e.g., write data) in the buffer area of ​​the host memory 2120 in the NVM 2220 or operations that store data (e.g., read data) in the buffer area of ​​the NVM 2220.

[0143] Storage controller 2210 may include host interface 2211, memory interface 2212, and CPU 2213. Storage controller 2210 may also include flash translation layer (FTL) 2214, packet manager 2215, buffer memory 2216, error correction code (ECC) engine 2217, and Advanced Encryption Standard (AES) engine 2218. Storage controller 2210 may also include working memory in which FTL 2214 is loaded. CPU 2213 can run FTL 2214 to control data write and read operations on NVM 2220.

[0144] Host interface 2211 can send packets to and receive packets from host 2100. Packets sent from host 2100 to host interface 2211 may include commands or data to be written to NVM 2220. Packets sent from host interface 2211 to host 2100 may include responses to commands or data read from NVM 2220. Memory interface 2212 can send data to be written to NVM 2220 or receive data read from NVM 2220. Memory interface 2212 can be configured to conform to standard protocols, such as, for example, Toggle or Open NAND Flash Interface (ONFI).

[0145] The FTL2214 can perform various functions, such as address mapping, wear-leveling, and garbage collection. Address mapping can be the process of translating logical addresses received from host 2100 into physical addresses used for actual data storage in the NVM 2220. Wear-leveling can be a technique to prevent or reduce excessive degradation of specific blocks by allowing for even use of blocks in the NVM 2220. As an example, wear-leveling can be implemented using firmware techniques that balance the erase counts of physical blocks. Garbage collection can be a technique for obtaining available capacity in the NVM 2220 by erasing existing blocks after copying valid data from existing blocks to new blocks.

[0146] Packet manager 2215 can generate packets according to the protocol of the interface connected to host 2100, or parse various types of information from packets received from host 2100. Furthermore, buffer memory 2216 can temporarily store data to be written to NVM 2220 or data to be read from NVM 2220. Although buffer memory 2216 is included... Figure 14 The components are in the storage controller 2210, but in some embodiments, the buffer memory 2216 may be placed outside the storage controller 2210.

[0147] The ECC engine 2217 can perform error detection and correction operations on read data read from the NVM 2220. For example, the ECC engine 2217 can generate parity bits for write data to be written to the NVM 2220, and the generated parity bits can be stored in the NVM 2220 along with the write data. During the reading of data from the NVM 2220, the ECC engine 2217 can correct errors in the read data by using the parity bits read from the NVM 2220 along with the read data, and output the error-corrected read data.

[0148] The AES engine 2218 can perform at least one of encryption and decryption operations on the data input to the storage controller 2210 using a symmetric key algorithm.

[0149] Figure 15 This is a schematic diagram of a UFS system 3000 according to an embodiment of the present invention. The UFS system 3000 may be a system conforming to the UFS standard of the Joint Electronic Equipment Committee (JEDEC) and includes a UFS host 3100, a UFS device 3200 and a UFS interface 3300. Figure 1 The aspects of the computing system 10 described above can also be applied to Figure 15The UFS system 3000, unless the context otherwise indicates. Host 3100 may include... Figure 1 The host 100 may contain at least some elements, and the UFS device 3200 may include... Figure 1 The storage system 200 contains at least some elements.

[0150] refer to Figure 15 The UFS host 3100 can be connected to the UFS device 3200 through the UFS interface 3300.

[0151] UFS host 3100 may include UFS host controller 3110, application 3120, UFS driver 3130, host memory 3140, and UFS interconnect (UIC) layer 3150. UFS device 3200 may include UFS device controller 3210, NVM 3220, storage interface 3230, device memory 3240, UIC layer 3250, and regulator 3260. NVM 3220 may include multiple memory elements 3221. Although each memory element 3221 may include V-NAND flash memory with a 2D or 3D structure, in some embodiments, each memory element 3221 may include another NVM, such as, for example, PRAM and / or RRAM. UFS device controller 3210 can be connected to NVM 3220 via storage interface 3230. Storage interface 3230 may be configured to comply with standard protocols, such as, for example, Toggle or ONFI.

[0152] Application 3120 can refer to a program that communicates with UFS device 3200 to use the functions of UFS device 3200. Application 3120 can send input-output requests (IORs) to UFS drive 3130 for input / output (I / O) operations on UFS device 3200. IORs can refer to, for example, data read requests, data storage (or write) requests, and / or data erase (or discard) requests, but are not limited to these.

[0153] UFS drive 3130 can manage UFS host controller 3110 via UFS-HCI (UFS-Host Controller Interface). UFS drive 3130 can translate IOR generated by application 3120 into UFS commands defined by the UFS standard and send these UFS commands to UFS host controller 3110. One IOR can be translated into multiple UFS commands. Although UFS commands can be defined by the SCSI standard, they can also be commands specific to the UFS standard.

[0154] The UFS host controller 3110 can send UFS commands translated by the UFS driver 3130 to the UIC layer 3250 of the UFS device 3200 via the UIC layer 3150 and the UFS interface 3300. During the transmission of UFS commands, the UFS host register 3111 of the UFS host controller 3110 can be used as a command queue (CQ).

[0155] The UIC layer 3150 on the UFS host 3100 side may include the Mobile Industrial Processor Interface (MIPI) M-PHY 3151 and MIPI UniPro 3152, and the UIC layer 3250 on the UFS device 3200 side may also include MIPI M-PHY 3251 and MIPI UniPro 3252.

[0156] The UFS interface 3300 may include a line configured to transmit a reference clock signal REF_CLK, a line configured to transmit a hardware reset signal RESET_n of the UFS device 3200, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C, and a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C.

[0157] In some embodiments, the frequency of the reference clock signal REF_CLK provided from the UFS host 3100 to the UFS device 3200 can be one of approximately 19.2 MHz, approximately 26 MHz, approximately 38.4 MHz, and approximately 52 MHz, but is not limited thereto. The UFS host 3100 can change the frequency of the reference clock signal REF_CLK during operation, i.e., during data transmission / reception operations between the UFS host 3100 and the UFS device 3200. The UFS device 3200 can generate clock signals with multiple frequencies from the reference clock provided by the UFS host 3100 using a phase-locked loop (PLL). Furthermore, the UFS host 3100 can set the data rate between the UFS host 3100 and the UFS device 3200 by using the frequency of the reference clock signal REF_CLK. That is, the data rate can be determined based on the frequency of the reference clock signal REF_CLK.

[0158] The UFS interface 3300 can support multiple channels, each of which can be implemented as a pair of differential lines. For example, the UFS interface 3300 may include at least one receive channel and at least one transmit channel. Figure 15 In this configuration, a pair of lines configured to transmit a pair of differential input signals DIN_T and DIN_C can form a receiving channel, and a pair of lines configured to transmit a pair of differential output signals DOUT_T and DOUT_C ​​can form a transmitting channel. Although in Figure 5The diagram shows one transmit channel and one receive channel, but the number of transmit channels and receive channels is not limited to this.

[0159] The receive and transmit channels can transmit data based on a serial communication scheme. Due to the separate structure of the receive and transmit channels, full-duplex communication between the UFS host 3100 and the UFS device 3200 is enabled. That is, while receiving data from the UFS host 3100 via the receive channel, the UFS device 3200 can transmit data to the UFS host 3100 via the transmit channel. Furthermore, control data (e.g., commands) from the UFS host 3100 to the UFS device 3200 and user data to be stored by the UFS host 3100 in or read from the NVM 3220 of the UFS device 3200 can be transmitted through the same channel. Therefore, in some embodiments, no separate channel for data transmission is used between the UFS host 3100 and the UFS device 3200, in addition to a pair of receive channels and a pair of transmit channels.

[0160] The UFS device controller 3210 of the UFS device 3200 can control all operations of the UFS device 3200. The UFS device controller 3210 can manage the NVM 3220 using logical elements (LUs) 3211 as logical data storage elements. The number of LUs 3211 can be eight, but is not limited to this. In some embodiments, the above references... Figure 8 and Figure 10 The described data log and node log may include at least one of logical elements (LUs) 3211. For example, a first logical element (LU) may be included in the data log, and a second logical element (LU) may be included in the node log. Logical element (LU) 3211 may be referred to as a storage area. The UFS device controller 3210 may include an FTL and, by using the address mapping information of the FTL, translates logical data addresses (e.g., logical block addresses (LBAs)) received from the UFS host 3100 into physical data addresses (e.g., physical block addresses (PBAs)). Logical blocks configured to store user data in the UFS system 3000 may have sizes within a predetermined range. For example, the minimum size of a logical block may be set to 4KB.

[0161] When a command from the UFS host 3100 is applied to the UFS device 3200 through the UIC layer 3250, the UFS device controller 3210 can respond to the command to perform an operation and send a completion response to the UFS host 3100 when the operation is completed.

[0162] As an example, when UFS host 3100 intends to store user data in UFS device 3200, UFS host 3100 can send a data storage command to UFS device 3200. When it receives a response from UFS device 3200 instructing UFS host 3100 to be ready to receive user data (ready-to-transfer) ("ready-to-transfer" response), UFS host 3100 can send the user data to UFS device 3200. UFS device controller 3210 can temporarily store the received user data in device memory 3240, and store the user data temporarily stored in device memory 3240 in a selected location of NVM 3220 based on FTL address mapping information.

[0163] As another example, when UFS host 3100 intends to read user data stored in UFS device 3200, UFS host 3100 can send a data read command to UFS device 3200. UFS device controller 3210, having received the command, can read the user data from NVM 3220 based on the data read command and temporarily store the read user data in device memory 3240. During the read operation, UFS device controller 3210 can detect and correct errors in the read user data using an embedded ECC engine. For example, the ECC engine can generate parity bits for the write data to be written to NVM 3220, and the generated parity bits can be stored in NVM 3220 along with the write data. During the reading of data from NVM 3220, the ECC engine can correct errors in the read data by using the parity bits read from NVM 3220 and the read data, and output the error-corrected read data.

[0164] Furthermore, the UFS device controller 3210 can send user data temporarily stored in the device memory 3240 to the UFS host 3100. Additionally, the UFS device controller 3210 may include an AES engine. The AES engine can perform at least one of encryption and decryption operations on the data sent to the UFS device controller 3210 using a symmetric key algorithm.

[0165] The UFS host 3100 can sequentially store commands to be sent to the UFS device 3200 in the UFS host register 3111, which can be used as a common queue, and send the commands to the UFS device 3200 sequentially. In this case, even while a previously sent command is still being processed by the UFS device 3200, that is, even before receiving notification that a previously sent command has been processed by the UFS device 3200, the UFS host 3100 can send the next command waiting in the CQ to the UFS device 3200. Therefore, the UFS device 3200 can also receive the next command from the UFS host 3100 during the processing of a previously sent command. The maximum number of commands (or queue depth) that can be stored in the CQ can be, for example, 32. Furthermore, the CQ can be implemented as a circular queue, where the start and end of the command lines stored in the queue are indicated by head pointers and tail pointers.

[0166] Each of the plurality of memory elements 3221 may include a memory cell array and control circuitry configured to control the operation of the memory cell array. The memory cell array may include a 2D memory cell array or a 3D memory cell array. The memory cell array may include a plurality of memory cells. Although in some embodiments each memory cell is configured to store 1 bit of information as a single-level cell (SLC), in other embodiments each memory cell may be a cell configured to store 2 or more bits of information, such as, for example, a multi-level cell (MLC), a three-level cell (TLC), and a four-level cell (QLC). A 3D memory cell array may include vertical NAND strings, wherein at least one memory cell is vertically oriented and situated on top of another memory cell.

[0167] Voltages VCC, VCCQ1, and VCCQ2 can be applied as power supply voltages to the UFS device 3200. Voltage VCC can be the main power supply voltage for the UFS device 3200, and is in the range of approximately 2.4V to approximately 3.6V. Voltage VCCQ1 can be a power supply voltage primarily used to supply a low voltage to the UFS device controller 3210, and is in the range of approximately 1.14V to approximately 1.26V. Voltage VCCQ2 can be a power supply voltage, lower than voltage VCC and higher than voltage VCCQ1, primarily for I / O interfaces such as the MIPI M-PHY 3251, and is in the range of approximately 1.7V to approximately 1.95V. Regulator 3260 can be implemented as a set of component regulators, each connected to one of the aforementioned different power supply voltages.

[0168] As is customary in the field of the present invention, embodiments are described in terms of functional blocks, elements, and / or modules, and are illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, elements, and / or modules are physically implemented by electronic (or optical) circuitry, such as logic circuits, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connections, etc. They can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, elements, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and / or software. Alternatively, each block, element, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry).

[0169] In embodiments of the inventive concept, a three-dimensional (3D) memory array is provided. The 3D memory array is monolithically formed in one or more physical levels of an array of memory cells having active regions disposed above a silicon substrate and circuitry associated with the operation of these memory cells, whether such associated circuitry is above or within the substrate. The term "monolithic" means that the layers of each level of the array are deposited directly on the layers of each lower level of the array. In embodiments of the inventive concept, the 3D memory array includes vertically oriented vertical NAND strings such that at least one memory cell is situated above another memory cell. At least one memory cell may include a charge trapping layer. The following patent documents are incorporated herein by reference: U.S. Patent Nos. 7,679,133; 8,553,466; 8,654,587; 8,559,235; and U.S. Patent Publication No. 2011 / 0233648, which describes a suitable configuration of a three-dimensional memory array wherein the three-dimensional memory array is configured to have multiple stages having word lines and / or bit lines shared between stages.

[0170] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it should be understood that various changes in form and detail may be made without departing from the spirit and scope of the inventive concept as defined by the appended claims.

Claims

1. A computing system, comprising: The storage system is configured to store data; as well as The host is configured to compress data blocks of a preset size loaded into memory, generate a merged block of the preset size by merging compressed blocks corresponding to the data blocks, identifiers of node blocks referencing the data blocks, and offsets indicating the indexes of data blocks in at least one data block referenced by the node blocks, and provide the merged block to the storage system.

2. The computing system according to claim 1, wherein, The host is also configured to send a node block indicating the address of the data block to the storage system after the merged block is sent to the storage system.

3. The computing system according to claim 2, wherein, The host is also configured to send node blocks to the storage system when the interface between the storage system and the host is idle.

4. The computing system according to claim 2, wherein, The time periods during which merged blocks are sent to the storage system and node blocks are sent to the storage system are not consecutive.

5. The computing system according to claim 1, wherein, The host is also configured as a first part of the compressed data block, and a second part of the compressed data block, different from the first part, is configured based on a comparison of the compressed size of the first part with a reference size.

6. The computing system according to claim 5, wherein, The reference size is equal to the sum of the size of the identifier corresponding to the data block, the size of the offset of the data block, and the size of the bit indicating the merged block.

7. The computing system according to claim 1, wherein, The host is also configured to, during a sudden power outage recovery operation, read merged blocks stored in the storage system and obtain data blocks, identifiers corresponding to the data blocks, and offsets of the data blocks from the read merged blocks.

8. The computing system according to claim 7, wherein, The host is also configured to update the node blocks corresponding to the data blocks based on the identifiers and offsets obtained from the merged blocks.

9. The computing system according to claim 7, wherein, The merge block includes bits indicating the merge block, and The host is also configured to read multiple blocks from the data logs of the storage system and search for a merged block among the multiple blocks based on the bit.

10. A host device, comprising: Memory, which stores data to be written to or read from a storage system; The compression manager circuit is configured to compress data blocks of a preset size loaded into memory; as well as The file system is configured to receive compressed blocks corresponding to data blocks from the compression manager circuit, generate merged blocks by merging compressed blocks, identifiers of node blocks referencing data blocks, and offsets indicating the indexes of data blocks in at least one data block referenced by the node blocks, and write the merged blocks to the storage system.

11. The host device of claim 10, wherein the size of the data block and the size of the merged block are equal to each other.

12. The host device according to claim 10, wherein, The file system is also configured to generate node blocks that indicate the addresses of merged blocks, and to send node blocks to the storage system during time periods that are not contiguous with the time periods during which data blocks are sent to the storage system.

13. The host device according to claim 10, wherein, The compression manager circuit is also configured to: The first part of the compressed data block, Based on the comparison between the compressed size of the first part and the reference size, the second part of the compressed data block differs from the first part, and Based on the comparison between the compressed size and the reference size in the first part, compressed blocks or compression failure signals are selectively provided to the file system. The file system is further configured as follows: After receiving the compressed block, the compressed block and the write command for the compressed block are sent to the storage system; and After receiving the compression failure signal, the data block, the node block indicating the address of the data block, and the write command for the data block and the node block are sent to the storage system.

14. The host device according to claim 10, wherein, The file system is configured to generate merge blocks by further merging bits that indicate the merge blocks.

15. The host device according to claim 14, wherein, The file system is also configured to, during a sudden power outage recovery operation, read merged blocks stored in the storage system and generate data blocks and node blocks indicating the addresses of the data blocks from the read merged blocks.

16. The host device according to claim 15, wherein, The file system is also configured to read multiple blocks from the data log of the storage system and search for a merge block among the multiple blocks based on the bit.

17. A computing system, comprising: Universal flash storage (UFS) systems include multiple storage areas; as well as A UFS host is configured to store merged blocks in a first storage area among the plurality of storage areas, wherein a compressed block into which data blocks are compressed, an identifier of a node block referencing the data blocks, and an offset indicating the index of a data block in at least one data block referenced by the node block are merged into the merged block, and a node block indicating the address of the data blocks is stored in a second storage area among the plurality of storage areas.

18. The computing system according to claim 17, wherein, The time period during which merged blocks are sent to the UFS system and the time period during which node blocks are sent to the UFS system are not consecutive.

19. The computing system according to claim 17, wherein, The size of the data block and the size of the merged block are equal.

20. The computing system according to claim 17, wherein, The UFS host is also configured to generate merge blocks by further merging bits indicating merge blocks, and in a sudden power outage recovery operation, read merge blocks stored in a first storage area and generate data blocks and node blocks indicating the addresses of the data blocks from the read merge blocks.

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