Address remapping system, method and electronic device

Abstract

The present invention discloses an address remapping system, method, and electronic device. The system includes: a master device, an address remapping module corresponding to the master device, and a slave device; the master device is configured to send a first access request to access a slave device and receive data fed back by the slave device; the address remapping module is configured to receive the first access request, remap the address in the first access request to obtain a second access request, such that the address in the second access request is the address of the slave device to be accessed by the master device; and the slave device is configured to receive the second access request and feed back data corresponding to the second access request. The present invention solves the technical problem of difficulty in mapping the access address of the master device to the address space of the slave device to be accessed.

Description

Technical Field

[0001] The present invention relates to the technical field of system on chip, and in particular to an address remapping system, method and electronic equipment. Background Art

[0002] In a system-on-chip (SoC), all master devices access different slave devices through an internetwork. Each slave device has its own address space in a global address mapping table. This global address mapping table exists only once for the entire SoC, and all master devices see the same address. The internetwork routes the master's access request to the appropriate slave device based on the address in the request, completing the entire transmission process.

[0003] For a system on a chip, the address in the access request issued by the master device may not correspond to the address of the slave device to be accessed, making it difficult for the master device's access address to be completely mapped to the entire address space of the slave device to be accessed or failing to access the corresponding slave address. Summary of the Invention

[0004] The present invention provides an address remapping system, method and electronic device to solve the technical problem that the access address of a master device is difficult to map to the address space of a slave device to be accessed.

[0005] According to one aspect of the present invention, there is provided an address remapping system, comprising:

[0006] A master device, an address remapping module corresponding to the master device, and a slave device;

[0007] The master device is used to send a first access request to access the slave device and receive data fed back by the slave device;

[0008] The address remapping module is configured to receive the first access request, and remap the address in the first access request to obtain a second access request, so that the address in the second access request is the address of the slave device accessed by the master device;

[0009] The slave device is configured to receive the second access request and feed back data corresponding to the second access request.

[0010] Optionally, it further includes a first control module;

[0011] The first control module is used to control the address remapping module corresponding to the master device so that the address in the first access request is remapped.

[0012] Optionally, it also includes the Internet;

[0013] The interconnection network is used to receive the second access request from the address remapping module, identify the address in the second access request, and send the second access request to the corresponding slave device; receive data fed back by the slave device, and send the fed back data to the master device.

[0014] Optionally, the address remapping module includes:

[0015] an address expansion module, configured to, upon receiving an expansion enable signal, select to expand the first address in the first access request, so that the expanded first address is mapped to a slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address;

[0016] or / and,

[0017] an address shift module, configured to, upon receiving a shift enable signal, select to shift the second address in the first access request so that the shifted second address is mapped to the slave device address accessed by the master device, and an address space of the second address does not correspond to an address space of the slave device address;

[0018] or / and,

[0019] An address shift module is used to select, when receiving a shift enable signal, to shift the third address in the first access request so that the shifted third address is mapped to the slave device address accessed by the master device, and the number of bytes represented by each bit in the third address is inconsistent with the number of bytes represented by each bit in the slave device address.

[0020] Optionally, when the address remapping module includes the address expansion module, the address offset module and the address shift module, the address expansion module, the address offset module and the address shift module are connected in series in sequence.

[0021] Optionally, the address expansion module includes a first selector and an address expansion unit; the first selector is used to select whether to input the first access request into the address expansion unit; the address expansion unit is used to, when the first access request is input, perform address expansion on the first address in the first access request, so that the expanded first address is mapped to the slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address;

[0022] The address shift module includes a second selector and an address shift unit; the second selector is used to select whether to input the first access request into the address shift unit; the address shift unit is used to, when the first access request is input, perform an address shift on the first address in the first access request, so that the offset second address is mapped to the slave device address accessed by the master device, and the address space of the second address does not correspond to the address space of the slave device address;

[0023] The address shift module includes a third selector and an address shift unit; the third selector is used to select whether to input the first access request into the address shift unit; the address shift unit is used to shift the first address in the first access request when the first access request is input, so that the shifted third address is mapped to the slave device address accessed by the master device, and the number of bytes represented by each bit in the third address is inconsistent with the number of bytes represented by each bit in the slave device address.

[0024] Optionally, the first control module further includes a second control module and a third control module;

[0025] The second control module is used to control the first selector, the second selector and the third selector, so as to select whether to pass through the corresponding address expansion unit, address offset unit and address shift unit;

[0026] The third control module is used to control the address extension unit, the address offset unit and the address shift unit, so that the address in the first access request is extended, offset and shifted.

[0027] According to another aspect of the present invention, there is provided an address remapping method, comprising:

[0028] The master device sends a first access request to access the slave device;

[0029] The address remapping module receives the first access request, and remaps the address in the first access request to obtain a second access request, so that the address in the second access request is the address of the slave device accessed by the master device;

[0030] The slave device receives the second access request and feeds back data corresponding to the second access request.

[0031] Optionally, remapping the address in the first access request to obtain the second access request, so that the address in the first access request is mapped to the address of the slave device accessed by the master device, specifically includes:

[0032] When an extension enable signal is received, the first address in the first access request is selected to be extended, so that the extended first address is mapped to a slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address;

[0033] or / and,

[0034] When an offset enable signal is received, selecting to offset the second address in the first access request so that the offset second address is mapped to the slave device address accessed by the master device, and an address space of the second address does not correspond to an address space of the slave device address;

[0035] and / or,

[0036] When a shift enable signal is received, the third address in the first access request is selected to be shifted so that the shifted third address is mapped to the slave device address accessed by the master device, and the number of bytes represented by each bit in the third address is inconsistent with the number of bytes represented by each bit in the slave device address.

[0037] According to another aspect of the present invention, an electronic device is provided, comprising:

[0038] at least one processor; and

[0039] a memory communicatively connected to the at least one processor; wherein,

[0040] The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform the address remapping method described in any embodiment of the present invention.

[0041] The technical solution of the embodiment of the present invention is to remap the address in the access request sent by each master device through the address remapping module of the on-chip system, under the premise that the address space and address format of the master device and the slave device are known. The address in the remapped access request is consistent with the address of the slave device to be accessed, so that the master device can access all address spaces of the corresponding slave device.

[0042] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 This is a system architecture diagram of an address remapping system provided according to the first embodiment of the present invention;

[0045] Figure 2 This is a system architecture diagram of an address remapping system applicable to the second embodiment of the present invention;

[0046] Figure 3 A schematic structural diagram of an address remapping module in an address remapping system applicable to the second embodiment of the present invention;

[0047] Figure 4 is a schematic diagram of the specific structure of the address remapping module in the address remapping system applicable to the third embodiment of the present invention;

[0048] Figure 5 Schematic diagram of address allocation of slave devices and reserved areas in an address remapping system applicable to embodiment 3 of the present invention;

[0049] Figure 6 This is a flow chart of an address remapping method provided according to a fourth embodiment of the present invention;

[0050] Figure 7 This is a structural diagram of an electronic device provided in Example 5. DETAILED DESCRIPTION

[0051] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0052] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] Example 1

[0054] Figure 1 The first embodiment of the present invention provides a system architecture for an address remapping system. This embodiment is applicable to the case where the address spaces and address formats of the master device and the slave device are known, and the address mapping of the access request sent by the master device is modified to achieve access to the corresponding slave device. Figure 1 As shown, the system includes:

[0055] A master device 1, an address remapping module 2 corresponding to the master device 1, and a slave device 3;

[0056] The master device 1 is used to send a first access request to access the slave device 3 and receive data fed back by the slave device 3;

[0057] The address remapping module 2 is configured to receive a first access request, and remap the address in the first access request to obtain a second access request, so that the address in the second access request is the address of the slave device 3 accessed by the master device 1;

[0058] The slave device 3 is configured to receive the second access request and feed back data corresponding to the second access request.

[0059] Among them, the master device 1 can be any device that sends requests and receives data; the slave device 3 can be a device with data storage function, which is used to feed back corresponding data to the master device after the master device 1 sends request information to the slave device 3; the address remapping module 2 can be integrated by the on-chip system, and the corresponding remapping method is set according to the known address format and address space of the master device 1 and the slave device 3, so that the address remapping module 2 after setting can map the address in the first access request sent by the master device 1 to the corresponding address of the slave device 3.

[0060] It should be noted that, when the address spaces and address formats of the master device 1 and the slave device 3 are known, the address remapping module 2 can be configured so that it has an address remapping function. When a first access request sent by the master device 1 passes through the corresponding address remapping module 2, the address information in the first access request is remapped by the address remapping module 2 to the address of the slave device 3 to be accessed by the master device 1, thereby obtaining a second access request capable of accessing the corresponding slave device 3. After receiving the corresponding second access request, the slave device 3 can feedback the data required by the corresponding master device 1 based on the information in the second access request.

[0061] In this embodiment, the master device 1 can correspond to the address remapping module 2 on a one-to-one basis, that is, each address remapping module 2 can correspond to one master device 1, so that each address remapping module 2 can remap the address in the first access request sent by the corresponding master device 1. Therefore, each address remapping module 2 can be configured as needed so that the first access request sent by each master device 1 can access the entire address space of the corresponding slave device 3 after being mapped by the corresponding slave device 3.

[0062] Of course, the master device 1 can also correspond to multiple address remapping modules 2. When the master device 1 sends a first access request containing different address information to different address remapping modules 2, the address in the input first access request is remapped by the address remapping module 2, so that the address information in different first access requests is remapped to the addresses of different slave devices 3, thereby accessing different slave devices 3.

[0063] The technical solution of the first embodiment of the present invention, under the premise that the address space and address format of the master device and the slave device are known, remaps the address in the access request sent by each master device through the address remapping module corresponding to each master device in the on-chip system. The address in the remapped access request is consistent with the address of the slave device to be accessed, so that the master device can access all address spaces of the corresponding slave device.

[0064] Example 2

[0065] A system architecture of an address remapping system is provided for the second embodiment of the present invention. Figure 2 As shown, the system includes:

[0066] There are multiple master devices 1 , each of which corresponds to an address remapping module 2 , a first control module 4 , an interconnection network 5 and multiple slave devices 3 .

[0067] Specifically, the master device 1 is used to send a first access request to access the slave device 3 and receive data fed back by the slave device 3 .

[0068] It should be noted that, in the present application, each master device 1 can be connected to a corresponding address remapping module 2. When the master device 1 needs to access the slave device 3, the master device 3 can send a first access request to the corresponding slave device 3 to the corresponding address remapping module 2. The master device 1 can also be used to receive data fed back from the slave device 3 after the slave device feeds back the data corresponding to the first access request.

[0069] The address remapping module 2 is used to receive a first access request sent by the corresponding master device 1, and remap the address in the first access request to obtain a second access request, so that the address in the second access request is the address of the slave device 3 accessed by the master device 1.

[0070] It should be noted that, after the address remapping module 2 receives the first access request sent by the master device 1, the address remapping module 2 can modify the address in the first access request according to a preset address remapping method to obtain a second access request, so that the address in the second access request is the address of the slave device 3 to be accessed by the master device 1. The address remapping methods include address extension, address offset, and address shift.

[0071] Specifically, the address remapping module 2 may include:

[0072] The address expansion module 21 is configured to, upon receiving an expansion enable signal, select to expand the first address in the first access request so that the expanded first address is mapped to the address of the slave device 3 accessed by the master device 1, and the bit width of the first address is smaller than the address space size of the address of the slave device 3;

[0073] or / and,

[0074] An address shift module 22 is configured to, upon receiving a shift enable signal, select to shift the second address in the first access request so that the shifted second address is mapped to the address of the slave device 3 accessed by the master device 1, and the address space of the second address does not correspond to the address space of the address of the slave device 3;

[0075] or / and,

[0076] The address shift module 23 is used to select to shift the third address in the first access request when receiving the shift enable signal, so that the shifted third address is mapped to the address of the slave device 3 accessed by the master device 1, and the number of bytes represented by each address in the third address is inconsistent with the number of bytes represented by each address in the address of the slave device 3.

[0077] It should be noted that the address remapping module 2 can modify the address in the first access request sent by the master device 1 according to a pre-set address remapping method, and can input the first access request sent by the master device 1 into the address expansion module 21, or / and, the address offset module 22, or / and, the address shift module 23 for corresponding address expansion, or / and, address offset, or / and, address shift. For example, if the address bit width of the master device 1 is smaller than the address space size of the address of the slave device 3, the first address in the first access request sent by the master device 1 can be address expanded so that the address in the expanded second access request can include the entire address space of the corresponding slave device 3. If the address space originally accessed by the master device 1 is prohibited, that is, when the system startup is completed, for security reasons, it is necessary to close the master device 1's access to the corresponding slave device 3, the second address in the first access request sent by the master device 1 can be offset to a reserved area or other slave device 3; or, when the second address in the first access request sent by the master device 1 does not correspond to the address space of the address of the slave device 3 to be accessed, the second address in the first access request of the master device 1 can be address-offset so that the second address corresponding to the master device 1 can be mapped to the address of the slave device 3 to be accessed; if the number of bytes represented by each bit of the address in the master device 1 is inconsistent with the number of bytes represented by each bit in the address of the slave device 3, the address in the master device 1 can be address-shifted so that the number of bytes of each bit in the third address in the first access request is consistent with the number of bytes of each bit in the address of the slave device 3.

[0078] In a specific implementation, when the address remapping module 2 includes the address expansion module 21 , the address offset module 22 and the address shift module 23 , the address expansion module 21 , the address offset module 22 and the address shift module 23 are sequentially connected in series.

[0079] It should be noted that the structural diagram of the address remapping module in this embodiment is as follows Figure 3 As shown in the figure, the address expansion module 21, the address offset module 22 and the address shift module 23 are connected in series in sequence, so that the first access request input can be input into the address expansion module 21, the address offset module 22 and the address shift module 23 in sequence, and whether to perform address expansion, address offset and address shift is selected in sequence, so as to achieve the selection of one or more corresponding address remapping methods for the address access requirements of each master device 1, so that the master device 1 can access the entire address space of the corresponding slave device 3.

[0080] The address remapping system further includes a first control module 4 , which is configured to control the address remapping module 2 corresponding to the master device 1 so that the address in the first access request is remapped.

[0081] It should be noted that the first control module 4 can set up each address remapping module 2 in advance, thereby controlling the address remapping method of each address remapping module 2, so that each address remapping module 2 can implement corresponding remapping for the corresponding address, and the master device 1 corresponding to the address remapping module 2 can also access the corresponding slave device 3. In this application, under the premise of knowing the requirements of the master device 1, the address remapping module 2 corresponding to the master device 3 can be configured through the first control module 4, so that the master device 1 can access the address space of the corresponding slave device 3.

[0082] The address remapping system also includes an internet network 5 and a slave device 3. The internet network 5 is used to receive a second access request from the address remapping module 2, identify the address in the second access request, and send the second access request to the corresponding slave device 3; receive data fed back from the slave device 3, and send the fed back data to the master device 1.

[0083] The slave device 3 is configured to receive the second access request and feed back data corresponding to the second access request to the internet 5 .

[0084] It should be noted that after the Internet network 5 receives the second access request sent by the address remapping module 2, it can identify the address of the second access request, and thus send the request information to the slave device 3 corresponding to the address. After the slave device 3 feeds back the data corresponding to the second access request to the Internet network 5, the Internet network 5 can directly feed back the data to the corresponding master device 1.

[0085] The technical solution of this embodiment can expand the address bit width in the access request of the master device 1 when the address bit width of the master device 1 is smaller than the address space size of the address of the slave device 3, so that the master device 1 can access the entire address space of the corresponding slave device 3; it can also perform address offset on the address space accessed by the master device 1, so as to realize the setting of access permissions to the address space of the slave device 3, thereby achieving the purpose of secure access; it can also perform address shift on the address in the access request sent by the master device 1 when the address calculation methods of the master device 1 and the slave device 3 are inconsistent, so as to realize adaptation with the address interface of the slave device 3.

[0086] Example 3

[0087] A system architecture of an address remapping system is provided for the third embodiment of the present invention. Figure 4 As shown, in addition to the structure included in the second embodiment, the address remapping module of the system also includes:

[0088] The address expansion module 21 includes a first selector 211 and an address expansion unit 212; the first selector 211 is used to select whether to input the first access request into the address expansion unit 212; the address expansion unit 212 is used to, when the first access request is input, expand the first address in the first access request so that the expanded first address is mapped to the address of the slave device 3 accessed by the master device 1, and the bit width of the first address is smaller than the address space size of the address of the slave device 3;

[0089] The address shift module 22 includes a second selector 221 and an address shift unit 222. The second selector 221 is used to select whether to input the first access request into the address shift unit 222. The address shift unit 222 is used to, when the first access request is input, perform an address shift on the first address in the first access request so that the offset second address is mapped to the address of the slave device 3 accessed by the master device 1, and the address space of the second address does not correspond to the address space of the address of the slave device 3.

[0090] The address shift module 23 includes a third selector 231 and an address shift unit 232; the third selector 231 is used to select whether to input the first access request into the address shift unit 232; the address shift unit 232 is used to shift the first address in the first access request when the first access request is input, so that the shifted third address is mapped to the address of the slave device 3 accessed by the master device 1, and the number of bytes represented by each bit in the third address is inconsistent with the bytes represented by each bit in the address of the slave device 3.

[0091] It should be noted that the first selector 211 can be controlled to select whether to input the first access request into the address expansion unit 212, that is, it can control the address in the first access request to undergo address expansion or be directly output through the selector; similarly, the second selector 221 can be controlled to select whether to input the first access request into the address offset unit 222, that is, it can control the address in the first access request to undergo address offset or be directly output through the selector; the third selector 231 can be controlled to select whether to input the first access request into the address shift unit 232, that is, it can control the address in the first access request to undergo address shift or be directly output through the selector.

[0092] In a specific embodiment, the first control module 4 also includes a second control module 41 and a third control module 42; the second control module 41 is used to control the first selector 211, the second selector 221 and the third selector 231, so as to select whether to pass through the corresponding address expansion unit 212, the address offset unit 222 and the address shift unit 232; the third control module 42 is used to control the address expansion unit 212, the address offset unit 222 and the address shift unit 232, so that the address in the first access request is expanded, offset and shifted.

[0093] Among them, the first control module 4 can be specifically a CPU, which is used to control the entire address remapping module 2, so as to achieve remapping of the addresses corresponding to all master devices 1, so that the master device 1 can access the entire address space of the corresponding slave device 3. The first control module 4 can also include a second control module 41 and a third control module 42, wherein the second control module 41 is used to control the first selector 211, the second selector 212 and the third selector 213, and the second control module 41 can be specifically the address expansion control register corresponding to the first selector 211, the address offset control register corresponding to the second selector 221 and the address shift control register corresponding to the third selector 231. The third control module 42 is used to control the address expansion unit, the address offset unit and the address shift unit, and can be specifically the address expansion configuration register corresponding to the address expansion unit 212, the address offset configuration register corresponding to the address offset unit 222 and the address shift configuration register corresponding to the address shift unit 232. For details, please refer to Figure 4 , Figure 4 The address extension control register controls the first selector 211, the address offset control register controls the second selector 221, and the address shift control register controls the third selector 231. The address extension configuration register is used to control the address extension unit 212, the address offset configuration register 222 is used to control the address offset unit, and the address shift configuration register is used to control the address shift unit 232.

[0094] Specifically, when the address extension control register is set to 1, it indicates that the end connecting the first selector 211 to the address extension unit 212 is conductive. In this case, the address extension configuration register should be enabled so that the address extension unit 212 performs address extension. When the address extension control register is set to 0, it indicates that the first selector 211 is conductive with the first selector 211. Similarly, when the address offset control register is set to 1, it indicates that the end connecting the second selector 221 to the address offset unit 222 is conductive. In this case, the address offset configuration register should be enabled so that the address offset unit 222 performs address offset. When the address offset control register is set to 0, it indicates that the second selector 221 is conductive with the second selector 221. When the address shift control register is set to 1, it indicates that one end of the third selector 231 connected to the address shift unit 232 is turned on. At this time, the address shift configuration register should be controlled to be enabled so that the address shift unit 232 performs the address shift; when the address shift control register is set to 0, it indicates that the third selector 231 is turned on.

[0095] Specifically, the address space of the access address of the master device 1 is expanded by using the address expansion module 21. For example, when the address width of the master device 1 is 32 bits, it can access a maximum of 4GB of address space. If the master device 1 needs to access the 16GB address space of the slave device 3, it is necessary to configure the address expansion control register to 1 to enable the address expansion register; in addition, the value of the 2-bit address expansion configuration register is configured so that the address expansion configuration register can supplement the value corresponding to the address space of the master device 1 exceeding 4GB after configuration, thereby expanding the access address space of the master device 1. For example, when the address width of the master device 1 is 32 bits, it can access an address space of 4GB (0x0000_0000-0xFFFF_FFFF). If it is now necessary to access an address space of 4GB to 8GB (0x1_0000_0000-0x1_FFFF_FFFF), the address expansion configuration register can be configured to 0x1. That is, when the address in the first access request sent by the master device 1 is ADDR, the address becomes {1, ADDR} after passing through the remapping module.

[0096] A method for offsetting the address space of the master device access address using the address offset module 22. For example, if master device a originally could only access the 4GB address space (0x0-0xFFFF_FFFF) of slave device a, and now needs to access the 0 to 4GB address space (0x8_0000_0000 to 0x8_FFFF_FFFF) of slave device b, then it is necessary to configure the address offset control register to 1 and enable the address offset register. At the same time, the address offset configuration register is configured to 0x8_0000_0000, so that the original access to the first 4GB space of device 0 is changed to accessing the first 4GB address space of slave device b. If the address space before mapping is ADDR, the address after mapping becomes ADDR+0x8_0000_0000. Alternatively, the address offset configuration register can be configured to 0x4_0000_0000, so that accessing the first 4GB address space of slave device a becomes accessing the first 4GB address space of reserved area 0. However, since there is no real slave device mounted in reserved area 0, an error signal will be returned if a request is received, so that the master device a can be shielded from accessing the slave device a. The address allocation diagram of slave device a and the reserved area is shown in the figure below. Figure 5 As shown, (0x0-0x4FFFF_FFFF) represents the address space of slave device a, (0x4_0000_0000 to 0x8_FFFF_FFFF) is the address space of reserved area 0, and (0x8_0000_0000 to 0xC_FFFF_FFFF) is the address space of slave device b.

[0097] The method for adjusting the address format of the master device access address by shifting the address format using the address shift module 23 specifically includes the following steps: When the address corresponding to master device b is designed as a byte address, that is, the 1-bit address of master device b is set in a 1-byte format, while the address of slave device 1 is designed as a word address, that is, the 1-bit address represents a 2-byte number. Therefore, it is difficult for the address in the master device's access request to correspond to the address of the slave device. In this case, the address shift control register can be set to 1, and the address shift configuration register can be configured to 1. This means that the address sent by master device b is shifted right by 1 bit, i.e., the least significant address bit is truncated. This converts the address after passing through the address shift unit 232 into an address in a word format, allowing slave device b to recognize the address after the address shift. Conversely, if the 1-bit address of the master device represents a 2-byte number and the 1-bit address of the slave device represents a 1-byte number, the address shift module 23 needs to shift the address left by 1 bit. This can be achieved by using more configuration signals in the address shift configuration register. For example, if the address shift configuration register is 32 bits, bit

[31] can be used to indicate left or right shift. Assume that bit

[31] is defined as 1 for right shift and bit

[31] is 0 for left shift. Bit[30:0] can indicate the number of bits to shift. For example, if bit[30:0] is 1, the address shifts by 1 bit. The above is just an example; you can set it as needed.

[0098] The technical solution of this embodiment can expand the address bit width in the access request of the master device 1 when the address bit width of the master device 1 is smaller than the address space size of the address of the slave device 3, so that the master device 1 can access the entire address space of the corresponding slave device 3; it can also perform address offset on the address space accessed by the master device 1, so as to realize the setting of access permissions to the address space of the slave device 3, thereby achieving the purpose of secure access; it can also perform address shift on the address in the access request sent by the master device 1 when the address calculation methods of the master device 1 and the slave device 3 are inconsistent, so as to realize adaptation with the address interface of the slave device 3.

[0099] Example 4

[0100] Figure 6 This is a flowchart of an address remapping method provided by the fourth embodiment of the present invention. This embodiment is a detailed description of the address remapping method of an address remapping system in the first embodiment above. Figure 6 As shown, the method includes:

[0101] 601. The master device sends a first access request to access the slave device.

[0102] 602. The address remapping module receives a first access request and remaps the address in the first access request to obtain a second access request, so that the address in the second access request is the address of the slave device accessed by the master device;

[0103] 603. Receive a second access request from the device and feed back data corresponding to the second access request.

[0104] In a specific embodiment, remapping the address in the first access request to obtain the second access request so that the address in the first access request is mapped to the address of the slave device accessed by the master device specifically includes:

[0105] When an extension enable signal is received, the first address in the first access request is extended so that the extended first address is mapped to a slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address;

[0106] or / and,

[0107] When an offset enable signal is received, the second address in the first access request is offset so that the offset second address is mapped to a slave device address accessed by the master device, and an address space of the second address does not correspond to an address space of the slave device address;

[0108] and / or,

[0109] When a shift enable signal is received, the third address in the first access request is shifted so that the shifted third address is mapped to the slave device address accessed by the master device, and the number of bytes per bit in the third address is inconsistent with the number of bytes per bit in the slave device address.

[0110] The technical solution of this embodiment can expand the address bit width in the master device access request when the address bit width of the master device is smaller than the address space size of the slave device address, so that the master device can access the entire address space of the corresponding slave device; it can also perform address offset on the address space accessed by the master device, thereby realizing the setting of access permissions for the slave device address space, thereby achieving the purpose of secure access; it can also perform address shift on the address in the access request sent by the master device when the address calculation methods of the master device and the slave device are inconsistent, thereby realizing adaptation to the slave device address interface.

[0111] Example 5

[0112] Figure 7A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0113] like Figure 6 As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0114] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0115] The processor 11 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as an address remapping method.

[0116] In some embodiments, the address remapping method may be implemented as a computer program that is written to a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the address remapping method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the address remapping method in any other appropriate manner (e.g., by means of firmware).

[0117] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0118] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0119] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0120] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0121] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0122] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0123] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0124] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. An address remapping system, characterized in that: include: A master device, an address remapping module corresponding to the master device, and a slave device; The master device is used to send a first access request to access the slave device and receive data fed back by the slave device; The address remapping module is configured to receive the first access request, and remap the address in the first access request to obtain a second access request, so that the address in the second access request is the address of the slave device accessed by the master device; The slave device is configured to receive the second access request and feed back data corresponding to the second access request; The address remapping module includes: an address shift module, configured to, upon receiving a shift enable signal, select to shift the second address in the first access request so that the shifted second address is mapped to the slave device address accessed by the master device, and an address space of the second address does not correspond to an address space of the slave device address; or / and, An address shift module is used to select, when receiving a shift enable signal, to shift the third address in the first access request so that the shifted third address is mapped to the slave device address accessed by the master device, and the number of bytes represented by each bit in the third address is inconsistent with the number of bytes represented by each bit in the slave device address.

2. The address remapping system according to claim 1, wherein: Also included is a first control module; The first control module is used to control the address remapping module corresponding to the master device so that the address in the first access request is remapped.

3. The address remapping system according to claim 1, wherein: It also includes the Internet; The interconnection network is used to receive the second access request from the address remapping module, identify the address in the second access request, and send the second access request to the corresponding slave device; receive data fed back by the slave device, and send the fed back data to the master device.

4. The address remapping system according to claim 2, wherein: The address remapping module includes: The address expansion module is used to select to expand the first address in the first access request when receiving the expansion enable signal, so that the expanded first address is mapped to the slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address.

5. The address remapping system according to claim 4, wherein: When the address remapping module includes the address expansion module, the address offset module and the address shift module, the address expansion module, the address offset module and the address shift module are sequentially connected in series.

6. The address remapping system according to claim 4, wherein: The address expansion module includes a first selector and an address expansion unit; the first selector is used to select whether to input the first access request into the address expansion unit; the address expansion unit is used to, when the first access request is input, perform address expansion on the first address in the first access request, so that the expanded first address is mapped to the slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address; The address offset module includes a second selector and an address offset unit; the second selector is used to select whether to input the first access request into the address offset unit; The address shifting unit is configured to, when the first access request is input, perform an address shift on the first address in the first access request, so that the shifted second address is mapped to the slave device address accessed by the master device, and an address space of the second address does not correspond to an address space of the slave device address; The address shift module includes a third selector and an address shift unit; the third selector is used to select whether to input the first access request into the address shift unit; the address shift unit is used to shift the first address in the first access request when the first access request is input, so that the shifted third address is mapped to the slave device address accessed by the master device, and the number of bytes represented by each bit in the third address is inconsistent with the number of bytes represented by each bit in the slave device address.

7. The address remapping system according to claim 6, wherein: The first control module also includes a second control module and a third control module; The second control module is used to control the first selector, the second selector and the third selector, so as to select whether to pass through the corresponding address expansion unit, address offset unit and address shift unit; The third control module is used to control the address extension unit, the address offset unit and the address shift unit, so that the address in the first access request is extended, offset and shifted.

8. An address remapping method, characterized in that: include: The master device sends a first access request to access the slave device; The address remapping module receives the first access request, and remaps the address in the first access request to obtain a second access request, so that the address in the second access request is the address of the slave device accessed by the master device; receiving the second access request from the device, and feeding back data corresponding to the second access request; The step of remapping the address in the first access request to obtain the second access request, so that the address in the first access request is mapped to the address of the slave device accessed by the master device, specifically includes: When an extension enable signal is received, the first address in the first access request is selected to be extended, so that the extended first address is mapped to a slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address; or / and, When an offset enable signal is received, the second address in the first access request is selected to be offset so that the offset second address is mapped to the slave device address accessed by the master device, and the address space of the second address does not correspond to the address space of the slave device address.

9. The address remapping method according to claim 8, wherein: Remapping the address in the first access request to obtain the second access request, so that the address in the first access request is mapped to the address of the slave device accessed by the master device, specifically includes: When an expansion enable signal is received, the first address in the first access request is selected to be expanded so that the expanded first address is mapped to the slave device address accessed by the master device, and the first address bit width is smaller than the address space size of the slave device address.

10. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor to enable the at least one processor to perform the address remapping method according to any one of claims 8 to 9.

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