Light emitting diode display device and method of manufacturing light emitting diode display device

Abstract

This application relates to an LED display device, and more specifically, to an LED display device having high resolution and increased light-emitting unit area. The invention configures a first light-emitting region and a second light-emitting region such that the first and third light-emitting regions overlap and are arranged identically, thereby enabling all R, G, and B colors to be realized in a single pixel, allowing the pixel size to be smaller than the pixel size of conventional display devices that require R, G, and B subpixels.

Description

Technical Field

[0001] This disclosure relates to light-emitting diode display devices, and more specifically, to light-emitting diode display devices that achieve high resolution and increase the area of ​​the light-emitting region. Background Technology

[0002] In recent years, with the expansion of display devices, the requirements for flat panel display devices with small footprints have become increasingly higher, and the technology of liquid crystal display (LCD) devices or organic light-emitting diode (OLED) devices has developed rapidly.

[0003] Here, in an LCD device, the backlight unit is positioned below the liquid crystal panel, and polarizers are present on the front and rear surfaces of the liquid crystal panel. Therefore, less than 5% of the light from the backlight unit passes through the liquid crystal panel, resulting in a deficiency in the luminous efficiency of the LCD device.

[0004] Although OLED devices have improved luminous efficiency compared to LCD devices, OLED devices still have limitations in terms of luminous efficiency and are at a disadvantage in terms of display device durability and / or lifespan.

[0005] Therefore, in order to solve the above-mentioned problems of LCD devices and / or OLED devices, light-emitting diode (LED) display devices have recently been proposed.

[0006] LED display devices that incorporate micro-LEDs with dimensions of hundreds of micrometers or tens of micrometers (μLEDs) in each sub-pixel used to display images have advantages such as low power consumption and small size.

[0007] In LED display devices, in order to obtain full color (red, green, and blue), i.e., multicolor, LEDs emitting red, green, and blue light are respectively arranged in sub-pixels, and the sub-pixels corresponding to red, green, and blue constitute a single unit pixel.

[0008] When the minimum size of a single LED is 10μm, there is a limitation that the size of a single pixel, including the three sub-pixels corresponding to red, green, and blue, is greater than 30μm.

[0009] As a result, it is difficult to obtain high-resolution LED display devices with increased pixel density per unit area.

[0010] In addition, since LEDs that emit red light have relatively low luminous efficiency compared to LEDs that emit green light and LEDs that emit blue light, it is impossible to obtain high-brightness red light compared to green and blue light.

[0011] Although the area of ​​LEDs emitting red light has been increased to improve their luminous efficiency, limitations exist due to their high resolution.

[0012] Specifically, the substrate used to form an LED that emits red light is different from the substrate used to form an LED that emits green or blue light. For example, the substrate used to form an LED that emits red light may include gallium arsenide (GaAs), while the substrate used to form an LED that emits green or blue light may include sapphire (Al2O3).

[0013] As a result, LEDs emitting red light and LEDs emitting green or blue light are formed on substrates containing different materials.

[0014] Furthermore, because the material of the active layer used for LEDs that emit red light is different from the material of the active layer used for LEDs that emit green or blue light, the manufacturing process becomes more complex and the manufacturing cost increases. Summary of the Invention

[0015] Technical issues

[0016] Therefore, this disclosure relates to a light-emitting diode (LED) display device that substantially eliminates one or more problems caused by the limitations and defects of the prior art. A primary objective of this disclosure is to provide a light-emitting diode (LED) display device with high resolution.

[0017] A second objective of this disclosure is to provide a micro LED display device that improves luminous efficiency by increasing the light-emitting area of ​​the LED.

[0018] A third objective of this disclosure is to provide an LED display device that reduces manufacturing costs and simplifies the manufacturing process.

[0019] Additional features and advantages of this disclosure will be set forth in the description which follows, and will be apparent in part from that description, or may be learned by practice of this disclosure. The purposes and other advantages of this disclosure will be realized and obtained by means of the structures particularly pointed out in the written description and claims and the accompanying drawings.

[0020] Problem-solving methods

[0021] This disclosure provides an LED display device, comprising: a substrate; an LED, the LED comprising: a first semiconductor layer, a first active layer, and a second semiconductor layer sequentially disposed and corresponding to a first light-emitting region; a second active layer disposed on the second semiconductor layer and corresponding to a second light-emitting region overlapping a portion of the first light-emitting region; a third semiconductor layer disposed on the second active layer; a third active layer disposed on the second semiconductor layer and corresponding to a third light-emitting region overlapping another portion of the first light-emitting region; and a fourth semiconductor layer disposed on the third active layer; a first transistor located on a portion of the substrate for driving the first active layer; a second transistor located on another portion of the substrate for driving the second active layer; and a third transistor located on the first transistor above a portion of the substrate for driving the third active layer.

[0022] Here, the first pad electrode is disposed below the first semiconductor layer, the third pad electrode and the fourth pad electrode are disposed on the third semiconductor layer and the fourth semiconductor layer, respectively, and the second pad electrode is disposed along the edge of the second semiconductor layer and contacts the side surface of the second semiconductor layer. An insulating layer is disposed along the edge of the first pad electrode, the first semiconductor layer and the first active layer.

[0023] Furthermore, the first, third, and fourth semiconductor layers comprise semiconductor materials of the negative gallium nitride (n-GaN) group, and the second semiconductor layer comprises semiconductor materials of the positive gallium nitride (p-GaN) group.

[0024] Furthermore, the first active layer is doped with europium (Eu). The first pad electrode is electrically connected to the first driving drain of the first driving transistor of the first transistor, the second pad electrode is electrically connected to the common line, the third pad electrode is electrically connected to the second driving drain of the second driving transistor of the second transistor, and the fourth pad electrode is electrically connected to the third driving drain of the third driving transistor of the third transistor. The first to third driving gate electrodes of the first to third driving transistors are respectively electrically connected to the first to third switching sources of the first to third switching transistors, the first to third switching gate electrodes of the first to third switching transistors are electrically connected to the gate line, the first to third driving sources of the first to third driving transistors are electrically connected to the power line, and the first to third switching sources of the first to third switching transistors are electrically connected to the data line.

[0025] Furthermore, the first pad electrode is electrically connected to the first driving drain of the first driving transistor of the first transistor, the second pad electrode is electrically connected to the power line, the third pad electrode is electrically connected to the second driving drain of the second driving transistor of the second transistor, and the fourth pad electrode is electrically connected to the third driving drain of the third driving transistor of the third transistor. The first to third driving gate electrodes of the first to third driving transistors are respectively electrically connected to the first to third switching drains of the first to third switching transistors, the first to third switching gate electrodes of the first to third switching transistors are electrically connected to the gate line, the first to third driving sources of the first to third driving transistors are electrically connected to the common line, and the first to third switching sources of the first to third switching transistors are electrically connected to the data line.

[0026] In addition, the first to third driving transistors include first to third driving gates, first to third driving semi-insulating patterns, first to third driving active layers having first to third driving source and drain regions, and first to third driving source and drain; the first to third switching transistors include first to third switching gates, first to third switching semi-insulating patterns, first to third switching active layers having first to third switching source and drain regions, and first to third switching source and drain.

[0027] In addition, this disclosure provides a method for manufacturing an LED display device, the method comprising the following steps: a) sequentially forming an undoped semiconductor material layer, a first semiconductor material layer, an active material layer, and a second semiconductor material layer on a growth substrate; b) forming a first insulating layer having a first recess on the second semiconductor material layer; c) sequentially forming a second active layer and a third semiconductor layer in the first recess on the second semiconductor material layer; d) after forming a second recess in the first insulating layer, sequentially forming a second active layer and a third semiconductor layer in the second recess on the second semiconductor material layer; e) forming the first semiconductor layer, the first active layer, and the second semiconductor layer by patterning the first semiconductor material layer, the active material layer, and the second semiconductor material layer; f) forming an insulating layer along the edges of the first active layer and the first semiconductor layer; g) forming a second pad electrode along the edge of the second semiconductor layer, forming a third pad electrode on the third semiconductor layer above the insulating layer, and forming a fourth pad electrode on the fourth semiconductor layer; h) removing the growth substrate and the undoped semiconductor material layer; and i) forming a first pad electrode under the first semiconductor layer.

[0028] Here, step d) includes forming a second insulating layer on the third semiconductor layer, and the method further includes removing the first insulating layer before step c).

[0029] Invention Effects

[0030] In the LED display device according to this disclosure, a first light-emitting region and a second light-emitting region are configured to overlap each other, and a first light-emitting region and a third light-emitting region are configured to overlap each other. An LED including a first active layer is configured corresponding to the first light-emitting region, a second active layer of the LED is configured corresponding to the second light-emitting region, and a third active layer of the LED is configured corresponding to the third light-emitting region. A first switching transistor and a first driving transistor for driving the first active layer are disposed in the first transistor region, a second switching transistor and a second driving transistor for driving the second active layer are disposed in the second transistor region, and a third switching transistor and a third driving transistor for driving the third active layer are disposed in the third transistor region. Because red, green, and blue are obtained in a single pixel, the pixel size is reduced and the pixel density per unit area is increased compared to a pixel including red, green, and blue sub-pixels. As a result, a high resolution greater than 300 ppi (pixels per inch) and an ultra-high resolution greater than 500 ppi are obtained.

[0031] In addition, by increasing the area of ​​the first to third active layers, the luminous efficiency of each active layer is improved, and a high-brightness image is obtained.

[0032] Furthermore, by omitting the LED transfer process, manufacturing time and costs are reduced, and manufacturing efficiency is improved. Additionally, since the first to third active layers are formed on the same substrate through epitaxial growth, manufacturing costs are lowered and the manufacturing process is simplified. As a result, product reliability is improved. Attached Figure Description

[0033] Figure 1 This is a schematic cross-sectional view showing the pixels of a light-emitting diode display device according to an embodiment of the present disclosure.

[0034] Figures 2 to 13 This is a schematic cross-sectional view showing a method for manufacturing a light-emitting diode according to a first embodiment of the present disclosure.

[0035] Figure 14 This is a schematic plan view showing the first light-emitting region and the first transistor region of a pixel of a light-emitting diode display device according to a first embodiment of the present disclosure.

[0036] Figure 15 This is a schematic plan view showing the second and third light-emitting regions and the second and third transistor regions according to the first embodiment of the present disclosure.

[0037] Figure 16 This is a schematic circuit diagram showing the circuit structure of a light-emitting diode display device according to a first embodiment of the present disclosure.

[0038] Figure 17 This is a schematic cross-sectional view showing the pixels of a light-emitting diode display device according to a first embodiment of the present disclosure.

[0039] Figure 18 This is a schematic cross-sectional view showing the pixels of a light-emitting diode display device according to a second embodiment of the present disclosure.

[0040] Figure 19 This is a schematic circuit diagram showing the circuit structure of a light-emitting diode display device according to a second embodiment of the present disclosure. Detailed Implementation

[0041] The advantages and features of this disclosure and its implementation methods will be illustrated by the following exemplary embodiments described with reference to the accompanying drawings. However, this disclosure may be implemented in various forms and should not be construed as limiting itself to the exemplary embodiments described herein. Rather, these exemplary embodiments are provided to make this disclosure thorough and complete enough to assist those skilled in the art in fully understanding its scope. Furthermore, this disclosure is limited only by the scope of the claims.

[0042] The shapes, dimensions, ratios, angles, and quantities disclosed in the accompanying drawings to describe embodiments of this disclosure are merely examples. Therefore, this disclosure is not limited to the details shown. The same reference numerals denote the same elements throughout the specification. In the following description, a detailed description of a known function or configuration may be omitted where such a description unnecessarily obscures the essential points of this disclosure. Where the terms “comprising,” “having,” and “including” are used as described in this specification, an additional part may be added unless a more restrictive term, such as “only,” is used. Unless otherwise stated, singular terms may include plural forms. When interpreting an element, that element is interpreted as including a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided.

[0043] When describing positional relationships, if the positional relationship between two components is described as, for example, "above," "over," "below," or "near," then one or more other components may be positioned between the two components unless more restrictive terms such as "only" or "directly" are used. The use of "on" another device or layer to specify a device or layer includes cases where the other layer or device is directly inserted into or in between another device. When an element is described as "connected to," "joined to," or "in contact" with another element, it should be understood that the element may be directly connected to or joined to the other element, the other element may be "intercalated" between the elements, or the elements may be "connected to," "joined to," or "in contact" with each other through the other element.

[0044] It should be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0045] For ease of illustration, the dimensions and thickness of each element in the accompanying drawings are shown, and this disclosure is not limited to the dimensions and thickness of the elements shown. Various embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0046] Figure 1 This is a schematic cross-sectional view showing the pixels of a light-emitting diode display device according to an embodiment of the present disclosure.

[0047] As shown in the figure, pixel P is defined on substrate 101. Pixel P includes first to third light-emitting regions EA1, EA and EA3 that substantially display an image, and a non-light-emitting region NEA is provided along the edge of the first light-emitting region EA1.

[0048] A light-shielding pattern 160 is set along the edge of pixel P. The light-shielding pattern 160 is set at the boundary of pixel P to prevent the mixing of light emitted from adjacent pixels.

[0049] Although the light-blocking pattern 160 may include materials for a black background or reflective materials, it is not limited to these.

[0050] Pixel P includes a first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 corresponding to the first active layer 205a, the second active layer 205b, and the third active layer 205c, respectively, and a non-light-emitting region NEA is set along the edge of the first light-emitting region EA1.

[0051] The non-light-emitting region NEA defines a first transistor region TrA1, a second transistor region TrA2, and a third transistor region TrA3, wherein the first to third transistors DRT1, DRT2, DRT3, STW1, STW2, and STW3 are electrically connected to the first to third active layers 205a, 205b, and 205c, respectively.

[0052] A first light-emitting region EA1, a second light-emitting region EA2, and a third light-emitting region EA3 are defined on a substrate 101 and overlap each other. The first light-emitting region EA1 and the second light-emitting region EA2 are defined to overlap each other, and the first light-emitting region EA1 and the third light-emitting region EA3 are defined to overlap each other.

[0053] The second luminous region EA2 and the third luminous region EA3 do not overlap.

[0054] The light-emitting diode (ELD) 200 is disposed in the first light-emitting region EA1 and includes first to fourth semiconductor layers 203a, 207, 203b and 203c and first to third active layers 205a, 205b and 205c.

[0055] The first transistors DRT1 and STW1 are disposed in the first transistor region TrA1 of the non-light-emitting region NEA on the substrate 101, and the first interlayer insulating layer 140a and the second interlayer insulating layer 140b are disposed on the entire substrate 101 having the first transistors DRT1 and STW1.

[0056] A recess 143 is provided in the second interlayer insulating layer 140b to correspond to the first light-emitting region EA1, and an LED 200 is provided in the recess 143.

[0057] LED 200 includes a first semiconductor layer 203a, a first active layer 205a, and a second semiconductor layer 207 stacked sequentially. A second active layer 205b and a third semiconductor layer 203b are stacked sequentially on a portion of the second semiconductor layer 207, and a third active layer 205c and a fourth semiconductor layer 203c are stacked on another portion of the second semiconductor layer 207.

[0058] The first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c provide holes to the first active layer 205a, the second active layer 205b, and the third active layer 205c, respectively. The first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c may comprise positive gallium nitride (p-GaN) group semiconductor materials, and the p-GaN group semiconductor materials may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Magnesium (Mg), zinc (Zn), or beryllium (Be) may be used as impurities to dope the first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c.

[0059] The first active layer 205a, the second active layer 205b, and the third active layer 205c adjacent to the first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c can have a multiple quantum well (MQW) structure, which includes a well layer and a barrier layer having a band gap larger than that of the well layer.

[0060] The first active layer 205a emits red light, the second active layer 205b emits blue light, and the third active layer 205c emits green light.

[0061] The first active layer 205a, the second active layer 205b, and the third active layer 205c can have an indium gallium nitride (InGaN) / gallium nitride (GaN) MQW structure, and the first active layer 205a can be doped with europium (Eu).

[0062] As a result, the first active layer 205a may include europium (Eu)-doped III-V or II-VI group semiconductors. For example, the first active layer 205a may include compound semiconductor materials such as europium (Eu)-doped gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN).

[0063] Europium (Eu) doped into the first active layer 205a has an ionic state. As a result, electrons and holes injected from the first semiconductor layer 203a and the second semiconductor layer 207 recombine with each other in the first active layer 205a, and in the europium (Eu) 3+ The transition in the first active layer 205a causes it to emit red light (590nm to 670nm).

[0064] Each of the second active layer 205b emitting blue light and the third active layer 205c emitting green light may comprise a compound semiconductor material, such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN) doped with indium (In). The second active layer 205b and the third active layer 205c may have different doping concentrations.

[0065] As the indium concentration increases, the wavelength of light emitted from the second active layer 205b and the third active layer 205c shifts from short wavelengths to long wavelengths. As a result, the third active layer 205c, with a relatively high indium concentration, can emit green light (490 nm to 560 nm), while the second active layer 205b, with a relatively low indium concentration, can emit blue light (440 nm to 480 nm).

[0066] The indium concentration doped into the second active layer 205b and the third active layer 205c can be easily adjusted, and the color purity of blue and green can be adjusted by changing the indium concentration.

[0067] The second semiconductor layer 207 provides electrons to the first active layer 205a, the second active layer 205b, and the third active layer 205c. The second semiconductor layer 207 may include a negative gallium nitride (n-GaN) group semiconductor material, and the negative gallium nitride (n-GaN) group semiconductor material may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), or carbon (C) may be used as impurities to dope the second semiconductor layer 207.

[0068] The first pad electrode 201a is disposed below the first semiconductor layer 203a of the LED 200, and the first connection electrode 127 is disposed below the first pad electrode 201a. The first connection electrode 127 is electrically connected to the first transistors DRT1 and STW1 in the first transistor region TrA1 defined in a portion of the non-light-emitting region NEA, and the first pad electrode 201a is electrically connected to the first transistors DRT1 and STW1.

[0069] The second semiconductor layer 207 on the first active layer 205a is configured to be exposed on the second interlayer insulating layer 140b, and the second pad electrode 209 is disposed along the edge of the second semiconductor layer 207 on the second interlayer insulating layer 140b.

[0070] The second pad electrode 209 contacts the side surface of the second semiconductor layer 207.

[0071] An insulating layer 211 is disposed along the edge of the first semiconductor layer 203a, the first active layer 205a and the first pad electrode 201a, so that the first pad electrode 201a, the first active layer 205a and the first semiconductor layer 203a are insulated from the second pad electrode 209.

[0072] The second pad electrode 209 is electrically connected to the common line Vcom on the second interlayer insulation layer 140b.

[0073] The third pad electrode 201b and the fourth pad electrode 201c are respectively disposed on the third semiconductor layer 203b and the fourth semiconductor layer 203c, and the third interlayer insulating layer 140c is disposed on the entire substrate 101 having the third pad electrode 201b and the fourth pad electrode 201c, the second pad electrode 209 and the common line Vcom.

[0074] The second transistors DRT2 and STW2 are disposed in the second transistor region TrA2 of the non-light-emitting region NEA on a part of the third interlayer insulating layer 140c, and the third transistors DRT3 and STW3 are disposed in the third transistor region TrA3 of the non-light-emitting region NEA on another part of the third interlayer insulating layer 140c.

[0075] The second transistors DRT2 and STW2 are electrically connected to the third pad electrode 201b through the second driving drain 114b, and the third transistors DRT3 and STW3 are electrically connected to the fourth pad electrode 201c through the third driving drain 114c.

[0076] The third pad electrode 201b and the fourth pad electrode 201c, as well as the second driving drain 114b and the third driving drain 114c, may include transparent conductive oxide materials with relatively high transmittance, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin oxide (TO).

[0077] The fourth interlayer insulating layer 140d and the fifth interlayer insulating layer 140e are disposed on the entire substrate 101 having the second and third transistors DRT2, STW2, DRT3 and STW3 to protect the second and third transistors DRT2, STW2, DRT3 and STW3 and the LED 200 from external oxides and external moisture.

[0078] In the LED display device 100 according to an embodiment of the present disclosure, since the first to third transistors DRT1, STW1, DRT2, STW2, DRT3 and STW3 and the LED 200 including the first to third active layers 205a, 205b and 205c are disposed in a single pixel P, the single pixel P displays each of the colors red, green and blue or a mixture of at least two of the colors red, green and blue.

[0079] The first active layer 205a, the second active layer 205b, and the third active layer 205c are electrically connected to the first to third transistors DRT1, STW1, DRT2, STW2, DRT3, and STW3, respectively, and can be driven individually by the first to third transistors DRT1, STW1, DRT2, STW2, DRT3, and STW3.

[0080] As a result, only the third active layer 205c can emit light through the third transistor DRT3 and STW3, allowing pixel P to emit only green light. Optionally, both the second active layer 205b and the third active layer 205c can emit light through the second and third transistors DRT2, STW2, DRT3, and STW3, allowing pixel P to emit both blue and green light.

[0081] Furthermore, only the first active layer 205a can emit light through the first transistors DRT1 and STW1. Since the second active layer 205b and the third active layer 205c include nitride semiconductor materials with relatively high transmittance, and the third pad electrode 201b and the fourth pad electrode 201c include transparent conductive oxide materials with high transmittance, the red light emitted from the first active layer 205a passes through the second active layer 205b and the third active layer 205c, as well as the third pad electrode 201b and the fourth pad electrode 201c, allowing pixel P to emit red light.

[0082] In the LED display device 100 according to an embodiment of the present disclosure, since a single pixel P can display red, green and blue, the size of a single unit pixel P is reduced compared to a unit pixel including red sub-pixels, green sub-pixels and blue sub-pixels.

[0083] As a result, the pixel density per unit area increased, and both high resolution (greater than 300 ppi) and ultra-high resolution (greater than 500 ppi) were achieved.

[0084] Furthermore, by increasing the area of ​​the first active layer 205a, the second active layer 205b, and the third active layer 205c, the luminous efficiency of each of the first active layer 205a, the second active layer 205b, and the third active layer 205c is improved, and a relatively high brightness image is obtained.

[0085] Table 1 below shows a comparison of the active layers 205a, 205b, and 205c with the pixel P of an LED display device according to a comparative example and an LED display device according to an embodiment of the present disclosure. Sample 1 represents the LED display device according to the comparative example, and sample 2 represents the LED display device 100 according to an embodiment of the present disclosure.

[0086] Table 1

[0087]

[0088] In Samples 1 and 2, for pixels with the same area, transistors DRT1, STW1, DRT2, STW2, DRT3, and STW3, as well as storage capacitors Cst1, Cst2, and Cst3, have the same area. In Table 1, the LED display device of Sample 1 includes R sub-pixels, G sub-pixels, and B sub-pixels, each with a size of 40 x 55.5 μm, and the size of a single sub-pixel can be defined as 100%. In the LED display device 100 according to an embodiment of this disclosure, since each of the R sub-pixels, G sub-pixels, and B sub-pixels has a minimum size of 64 x 58 μm, the size of a single sub-pixel increases by 167% to 560% compared to the size of the sub-pixels in the LED display device according to the comparative example. Furthermore, Sample 1 includes R active layers, G active layers, and B active layers, each with a maximum size of 34 x 34.5 μm, and the size of a single active layer can be defined as 100%. In the LED display device 100 according to the embodiment of the present disclosure of sample 2, the dimensions of the first active layer 205a, the second active layer 205b and the third active layer 205c are increased by a minimum of 316% to a maximum of 1060%.

[0089] In the LED display device 100 according to an embodiment of the present disclosure, the first active layer 205a emitting red light in the first light-emitting region EA1 may have a size that is 1060% larger than the R active layer of the LED display device according to the comparative example, and the second active layer 205b and the third active layer 205c may have a size that is 316% larger than the G active layer and the B active layer of the LED display device according to the comparative example.

[0090] As the size of each of the first active layer 205a, the second active layer 205b, and the third active layer 205c increases, the luminous efficiency of each of the first active layer 205a, the second active layer 205b, and the third active layer 205c is improved and relatively high brightness is obtained.

[0091] Figures 2 to 13 This is a schematic cross-sectional view illustrating a method for manufacturing a light-emitting diode according to an embodiment of the present disclosure.

[0092] exist Figure 2 In the growth substrate 301, a space is defined with ( Figure 1 The first region A corresponding to the first luminescent region EA1, overlaps with the first region A and is ( Figure 1 The second region B, corresponding to the second luminescent region EA2, and the region overlapping with and (the first region A) Figure 1The third region C corresponds to the third light-emitting region EA3. An undoped semiconductor material layer 315, a first semiconductor material layer 303, an active material layer 305, and a second semiconductor material layer 307 are sequentially formed on the growth substrate 301.

[0093] The growth substrate 301 can be a sapphire (Al2O3) substrate, a silicon carbide substrate, or a silicon substrate, wherein the semiconductor material layers 303 and 307 (specifically, group II nitrides) are in an epitaxial growth state. Preferably, the growth substrate 301 can be a sapphire substrate.

[0094] The undoped semiconductor material layer 315 may include undoped micro gallium nitride (μ-GaN).

[0095] The undoped semiconductor material layer 315 can be referred to as a buffer layer and can be grown on the growth substrate 301 to mitigate lattice mismatch and differences in thermal expansion coefficients.

[0096] Each of the first semiconductor material layer 303, the second semiconductor material layer 307, and the active material layer 305 may include a nitride semiconductor material.

[0097] The first semiconductor material layer 303 may include a positive gallium nitride (p-GaN) group semiconductor material, and the p-GaN group semiconductor material may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Magnesium (Mg), zinc (Zn), or beryllium (Be) may be used as impurities to dope the first semiconductor material layer 303.

[0098] The second semiconductor material layer 307 may include a negative gallium nitride (n-GaN) group semiconductor material, and the n-GaN group semiconductor material may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), or carbon (C) may be used as impurities to dope the second semiconductor material layer 307.

[0099] The active material layer 305 may include europium (Eu) doped III-V or II-VI group semiconductors. For example, the active material layer 305 may include compound semiconductor materials such as europium (Eu) doped gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN).

[0100] The undoped semiconductor material layer 315, the first semiconductor material layer 303, the second semiconductor material layer 307, and the active material layer 305 can be formed on the growth substrate 301 by epitaxial growth to have excellent crystallinity.

[0101] Although an undoped semiconductor material layer 315, a first semiconductor material layer 303, a second semiconductor material layer 307, and an active material layer 305 can be formed on the growth substrate 301 using a metal-organic chemical vapor deposition (MOCVD) method, this method is not limited to this. For example, the undoped semiconductor material layer 315, the first semiconductor material layer 303, the second semiconductor material layer 307, and the active material layer 305 can be formed using a molecular beam epitaxy (MBE) method, a plasma-enhanced chemical vapor deposition (PECVD) method, or a vapor phase epitaxy (VPE) method. The MOCVD method can be performed at a temperature of about 900°C to about 1300°C.

[0102] exist Figure 3 In the process, after the first insulating layer 311 is completely deposited on the second semiconductor material layer 307, a first recess 311a corresponding to the second region B is formed.

[0103] exist Figure 4 In the first recess 311a, a second active layer 205b and a third semiconductor layer 203b are sequentially formed.

[0104] exist Figure 5 In this process, a second insulating layer 313 is formed on the third semiconductor layer 203b. Figure 6 In the first insulating layer 311, a second recess 311b corresponding to the third region C is formed.

[0105] exist Figure 7 In the second recess 311b, a third active layer 205c and a fourth semiconductor layer 203c are formed sequentially.

[0106] The second active layer 205b and the third active layer 205c may have an indium gallium nitride (InGaN) / gallium nitride (GaN) MQW structure, and each of the second active layer 205b and the third active layer 205c may include a compound semiconductor material such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN) doped with different concentrations of indium (In).

[0107] The third semiconductor layer 203b and the fourth semiconductor layer 203c may include positive gallium nitride (p-GaN) group semiconductor materials, and the p-GaN group semiconductor materials may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Magnesium (Mg), zinc (Zn), or beryllium (Be) may be used as impurities to dope the third semiconductor layer 203b and the fourth semiconductor layer 203c.

[0108] The first recess 311a and the second recess 311b can be formed by an etching process using a mask.

[0109] exist Figure 8 In this process, the first insulating layer 311 and the second insulating layer 313 are removed by an etching method such as wet etching. Figure 9 In this process, the first semiconductor layer 203a, the first active layer 205a, and the second semiconductor layer 207 are formed by patterning the first semiconductor material layer 303, the active material layer 305, and the second semiconductor material layer 307 to correspond to the first region A.

[0110] Patterning can be performed using an etching process that employs a mask.

[0111] exist Figure 10 In the middle, the insulating layer 211 is formed along the edge of the first semiconductor layer 203a and the first active layer 205a.

[0112] exist Figure 11 In the process, a second pad electrode 209 is formed on the insulating layer 211 along the edge of the second semiconductor layer 207 to contact the side surface of the second semiconductor layer 207, and a third pad electrode 201b and a fourth pad electrode 201c are formed on the third semiconductor layer 203b and the fourth semiconductor layer 203c.

[0113] The second pad electrode 209 may include indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). Optionally, the second pad electrode 209 may include silver (Ag), aluminum (Al), gold (Au), chromium (Cr), iridium (Ir), magnesium (Mg), neodymium (Nd), nickel (Ni), palladium (Pd), platinum (Pt), rhodium (Rh), titanium (Ti), or tungsten (W), or an alloy of at least two of them, or a laminated structure of different metals.

[0114] The third pad electrode 201b and the fourth pad electrode 201c may include transparent conductive oxide materials, such as indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), and tin oxide (TO).

[0115] exist Figure 12 In this process, the growth substrate 301 can be removed by laser lift-off (LLO) process. In the LLO process, an excimer laser beam is focused and irradiated onto the growth substrate 301, and the thermal energy is focused on the boundary surface between the growth substrate 301 and the undoped semiconductor material layer 315 on the growth substrate 301.

[0116] As a result, the interface between the growth substrate 301 and the undoped semiconductor material layer 315 is separated into gallium molecules and nitrogen molecules, and the growth substrate 301 is instantaneously separated from the undoped semiconductor material layer 315 at the part where the excimer laser beam passes.

[0117] exist Figure 13 In this process, after removing the undoped semiconductor material layer 315, a first pad electrode 201a is formed below the first semiconductor layer 203a. As a result, an LED 200 according to an embodiment of the present disclosure is completed.

[0118] The completed LED 200 was transferred to a device with ( Figure 1 The transistors DRT1, STW1, DRT2, STW2, DRT3, and STW3 ( Figure 1 After the substrate 101 is connected, the LED 200 is electrically connected to transistors DRT1, STW1, DRT2, STW2, DRT3, and STW3 on the substrate 101. As a result, the present disclosure is completed. Figure 1 LED display device 100.

[0119] Although the LED transfer process is performed three times per unit pixel in the LED display device according to the comparative example, in the LED display device 100 according to the embodiment of the present disclosure, the LED transfer process can be performed once per unit pixel P. As a result, manufacturing time and manufacturing costs are reduced, and manufacturing efficiency is improved.

[0120] Specifically, in the LED display device 100 according to the embodiments of the present disclosure, since the first active layer 205a emitting red light is formed on the growth substrate 301 together with the second active layer 205b and the third active layer 205c through epitaxial growth, the manufacturing cost is reduced and the manufacturing process is simplified.

[0121] In the LED display device according to the comparative example, an LED emitting red light is formed on a growth substrate including gallium arsenide (GaAs). The active layer emitting red light includes a material such as gallium phosphide (GaP), and the active layers emitting green and blue light include compound semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN) doped with indium (In).

[0122] As a result, LEDs emitting red light and LEDs emitting green and blue light were not formed on the same growth substrate using the same process, which increased manufacturing costs and complicated the manufacturing process.

[0123] In the LED display device 100 according to an embodiment of the present disclosure, since the active layer 205a emitting red light includes gallium nitride (GaN) doped with europium (Eu), the first active layer 205a emitting red light is formed together with the second active layer 205b and the third active layer 205c emitting blue and green light on the sapphire crystal. Figure 12 On the growth substrate 301.

[0124] As a result, manufacturing costs were reduced and the manufacturing process was simplified.

[0125] Specifically, since all the first to third active layers 205a, 205b, and 205c are formed from compound semiconductor materials such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN), the first to third active layers 205a, 205b, and 205c are formed using the same manufacturing process, and the conditions for injecting current to drive the active layers 205a, 205b, and 205c are identical. As a result, the reliability of the product is also improved.

[0126] Furthermore, in the LED display device according to the comparative example, since the growth substrate of gallium arsenide (GaAs) for the active layer used to emit red light is opaque, additional techniques for dividing the growth substrate are required. In the LED display device according to the embodiments of this disclosure, since the sapphire growth substrate 301 is transparent, the growth substrate can be easily divided by a laser lift-off (LLO) method. As a result, manufacturing time and manufacturing costs are reduced, and manufacturing efficiency is improved.

[0127] In the LED display device 100 according to an embodiment of the present disclosure, since red, green and blue are obtained in a single pixel P, the pixel size is reduced compared to LED display devices that require red sub-pixels, green sub-pixels and blue sub-pixels to be separated from each other.

[0128] Because of the increased density of pixels P per unit area, high resolutions of more than 300 ppi (pixels per inch) and ultra-high resolutions of more than 500 ppi are achieved.

[0129] Furthermore, since the areas of the first active layer 205a, the second active layer 205b, and the third active layer 205c are enlarged, the luminous efficiency of each of the active layers 205a, 205b, and 205c is improved, and a relatively high-brightness image is obtained.

[0130] Furthermore, by omitting the LED 200 transfer process, manufacturing time and costs are reduced, and manufacturing efficiency is improved. Since the first active layer 205a, the second active layer 205b, and the third active layer 205c are formed on the same growth substrate 301 through epitaxial growth, manufacturing costs are reduced, the manufacturing process is simplified, and product reliability is improved.

[0131] In the following description, the connection structure of the first to third active layers 205a, 205b and 205c and the first to third transistors DRT1, STW1, DRT2, STW2, DRT3 and STW3 in the LED display device 100 will be described according to the embodiments.

[0132] -First Implementation Method-

[0133] Figure 14 This is a schematic plan view showing the first light-emitting region and the first transistor region in a pixel of a light-emitting diode display device according to a first embodiment of the present disclosure. Figure 15 This is a schematic plan view showing the second and third light-emitting regions, as well as the second and third transistor regions, in a pixel of a light-emitting diode display device according to a first embodiment of the present disclosure.

[0134] Figure 16 This is a schematic circuit diagram showing the circuit structure of a light-emitting diode display device according to a first embodiment of the present disclosure.

[0135] Here, the front surface is defined as a surface that emits light from pixel P, and the rear surface is defined as another surface opposite to the front surface.

[0136] exist Figure 14 In the first embodiment of the present disclosure, when the rear surface of the light-emitting diode (LED) display device 100 is observed, the first gating line GL1 and the data line DL are arranged along the edge of a single unit pixel P, the common line Vcom is arranged facing the data line DL, and the first power line Vdd1 is arranged facing the first gating line GL1.

[0137] Although a single unit pixel P is defined by the intersection structure of the data line DL and the first gate line GL1, it is not limited thereto.

[0138] Pixel P includes a first luminescent region EA1 that substantially displays an image, and a non-luminescent region NEA is set along the edge of the first luminescent region EA1.

[0139] ( Figure 13A light-emitting diode (LED) 200 is disposed in a first light-emitting region EA1, and a first transistor DRT1 and STW1 are disposed in a first transistor region TrA1 in a non-light-emitting region NEA on one side of the first light-emitting region EA1.

[0140] When pixel P is viewed from the rear surface, only the first active layer 205a is disposed in the first light-emitting region EA1, and red light is emitted from the first active layer 205a in the first light-emitting region EA1 to the front surface.

[0141] ( Figure 13 The first semiconductor layer 203a and the second semiconductor layer 207, as well as the first active layer 205a between the first semiconductor layer 203a and the second semiconductor layer 207, are stacked and disposed in the first light-emitting region EA1. Figure 13 The first pad electrode 201a is disposed below the first semiconductor layer 203a, and the second pad electrode 209 is disposed along the edge of the first active layer 205a.

[0142] First transistors DRT1 and STW1, connected to the first gating line GL1, data line DL, common line Vcom, and first power line Vdd1, are disposed in the first transistor region TrA1 of the non-light-emitting region NEA. First switching transistor STW1 is disposed in the region where the first gating line GL1 and data line DL intersect, and first driving transistor DRT1 is disposed between the first switching transistor STW1 and the first power line Vdd1.

[0143] The first switching transistor STW1 selects each pixel P and includes a first switching gate 103a, ( Figure 17 The first switch active layer S-ACT1 and the first switch source 116a and drain 117a.

[0144] The first driving transistor DRT1 drives the LED 200 of the pixel P selected by the first switching transistor STW1. The first driving transistor DRT1 includes a first driving gate 102a, ( Figure 17 The first driving active layer D-ACT1, the first driving source 115a, and the first driving drain 114a.

[0145] The first-first storage electrode 121a connected to the first driving source 115a of the first driving transistor DRT1 and the first-second storage electrode 125a connected to the first switching source 116a of the first switching transistor STW1 overlap each other, and the first dielectric layer 123a is located between the first-first storage electrode 121a and the first-second storage electrode 125a to form the first storage capacitor Cst1.

[0146] The first storage capacitor Cst1 stores the data voltage Vdata to maintain the same state of the first active layer 205a until the next gate voltage Vgate is applied.

[0147] The first driving gate 102a of the first driving transistor DRT1 is connected to the first switching source 116a of the first switching transistor STW1.

[0148] The first switching gate 103a of the first switching transistor STW1 is connected to the first gate line GL1, the first driving source 115a of the first driving transistor DRT1 is connected to the first power supply line Vdd1, and the first switching drain 117a of the first switching transistor STW1 is connected to the data line DL.

[0149] In the first luminescent region EA1 ( Figure 13 The first pad electrode 201a is connected to the first drive drain 114a of the first drive transistor DRT1, and the second pad electrode 209 is connected to the common line Vcom.

[0150] As a result, the first switching transistor STW1 is switched according to the gate voltage Vgate provided to the first gate line GL1, so as to provide the data voltage Vdata provided to the data line DL to the first driving transistor DRT1.

[0151] The first driving transistor DRT1 is switched according to the data voltage Vdata provided from the first switching transistor STW1 to regulate the data current flowing from the power supply voltage provided through the first pad electrode 201a of the LED 200 to the first active layer 205a.

[0152] The first storage capacitor Cst1 is connected between the first driving gate 102a and the first driving source 115a of the first driving transistor DRT1 to store a voltage corresponding to the data voltage Vdata supplied to the first driving gate 102a of the first driving transistor DRT1, and to turn on the first driving transistor DRT1 using the stored voltage.

[0153] As a result, the first active layer 205a is electrically connected between the power supply voltage provided through the first pad electrode 201a and the common voltage provided through the second pad electrode 209, and emits light due to the data voltage Vdata provided from the first driving transistor DRT1.

[0154] exist Figure 15 In the image, when viewed from the front surface, the data line DL and the common line Vcom are arranged along the edge of a single pixel P facing each other, and the first power line Vdd1 and the second power line Vdd2 are arranged perpendicular to the data line DL and the common line Vcom and facing each other.

[0155] The second gate line GL2 is set to intersect the central portion of pixel P.

[0156] Pixel P overlaps with the first light-emitting area EA1 to include the second light-emitting area EA2 and the third light-emitting area EA3, and the non-light-emitting area NEA is set along the edges of the second light-emitting area EA2 and the third light-emitting area EA3.

[0157] The second active layer 205b, the third semiconductor layer 203b, and the third pad electrode 201b of the LED 200 are disposed in the second light-emitting region EA2, and the second transistors DRT2 and STW2 are disposed in the second transistor region TrA2 of the non-light-emitting region NEA on one side of the second light-emitting region EA2.

[0158] The third active layer 205c, the fourth semiconductor layer 203c, and the fourth pad electrode 201c of the LED 200 are disposed in the third light-emitting region EA3, and the third transistors DRT3 and STW3 are disposed in the third transistor region TrA3 of the non-light-emitting region NEA on one side of the third light-emitting region EA3.

[0159] When pixel P is viewed from the front surface, blue light is emitted in the second light-emitting region EA2 due to the second active layer 205b, and green light is emitted in the third light-emitting region EA3 due to the third active layer 205c.

[0160] The second transistors DRT2 and STW2, connected to the second gate line GL2, data line DL, common line Vcom, and first power line Vdd1, are disposed in the second transistor region TrA2 of the non-light-emitting region NEA. The second switching transistor STW2 is disposed in the region where the second gate line GL2 and data line DL intersect each other, and the second driving transistor DRT2 is disposed between the second switching transistor STW2 and the first power line Vdd1.

[0161] The third transistors DRT3 and STW3, connected to the second gate line GL2, the data line DL, the common line Vcom, and the second power line Vdd2, are located in the third transistor region TrA3. The third switching transistor STW3 is located in the region where the second gate line GL2 and the data line DL intersect, and the third driving transistor DRT3 is located between the third switching transistor STW3 and the second power line Vdd2.

[0162] The second switching transistor STW2 and the third switching transistor STW3 select each pixel P and include a second switching gate 103b and a third switching gate 103c. Figure 17 The second active switch layer S-ACT2 and the third active switch layer S-ACT3, as well as the second and third source and drain electrodes 116b, 116c, 117b and 117c.

[0163] The second driving transistor DRT2 and the third driving transistor DRT3 drive the LED 200 of the pixel P selected by the second switching transistor STW2 and the third switching transistor STW3. The second driving transistor DRT2 and the third driving transistor DRT3 include a second driving gate 102b and a third driving gate 102c, (…). Figure 17 The second driving active layer D-ACT2 and the third driving active layer D-ACT3, as well as the second and third driving source and drain electrodes 115b, 114b, 115c and 114c.

[0164] The second-first storage electrode 121b and the third-first storage electrode 121c, which are connected to the second driving source 115b and the third driving source 115c of the second driving transistor DRT2 and the third driving transistor DRT3, and the second-second storage electrode 125b and the third-second storage electrode 125c, which are connected to the second switching source 116b and the third switching source 116c of the second switching transistor STW2 and the third switching transistor STW3, overlap each other. The second dielectric layer 123b and the third dielectric layer 123c are inserted between the second-first storage electrode 121b and the third-first storage electrode 121c and the second-second storage electrode 125b and the third-second storage electrode 125c to form the second storage capacitor Cst2 and the third storage capacitor Cst3.

[0165] The second driving gate 102b and the third driving gate 102c of the second driving transistor DRT2 and the third driving transistor DRT3 are respectively connected to the second switching source 116b and the third switching source 116c of the second switching transistor STW2 and the third switching source 116c of the third switching transistor STW3.

[0166] The second gate 103b and the third gate 103c of the second switching transistor STW2 and the third switching transistor STW3 are connected to the second gate line GL2, and the second driving source 115b and the third driving source 115c of the second driving transistor DRT2 and the third driving transistor DRT3 are connected to the first power line Vdd1 and the second power line Vdd2, respectively.

[0167] The second switch drain 117b and the third switch drain 117c of the second switch transistor STW2 and the third switch transistor STW3 are connected to the data line DL.

[0168] In the second luminescent region EA2 ( Figure 13 The third pad electrode 201b is connected to the second driving drain 114b of the second driving transistor DRT2, and the third light-emitting region EA3 is ( Figure 13The fourth pad electrode 201c is connected to the third drive drain 114c of the third drive transistor DRT3.

[0169] As a result, the second switching transistor STW2 and the third switching transistor STW3 are switched according to the gate voltage Vgate provided to the second gate line GL2, so as to provide the data voltage Vdata provided to the data line DL to the second driving transistor DRT2 and the third driving transistor DRT3.

[0170] The second drive transistor DRT2 and the third drive transistor DRT3 are switched according to the data voltage Vdata provided by the second switch transistor STW2 and the third switch transistor STW3 to regulate the flow from ( Figure 13 The power supply voltage provided by the third pad electrode 201b and the fourth pad electrode 201c of the LED 200 flows into the second active layer 205b and the third active layer 205c, providing data current.

[0171] As a result, the second active layer 205b and the third active layer 205c are electrically connected between the power supply voltage provided through the third pad electrode 201b and the fourth pad electrode 201c and the common voltage provided through the second pad electrode 209, and emit light due to the data current provided from the second driving transistor DRT2 and the third driving transistor DRT3.

[0172] In the LED display device 100 according to the first embodiment of the present disclosure, when viewing pixel P from the front surface and the rear surface, the light-emitting regions EA1, EA2, and EA3 are defined to be different from each other. When viewing pixel P from the rear surface, a first light-emitting region EA1 and a first transistor region TrA1 located on one side of the first light-emitting region EA1 are defined. When viewing pixel P from the front surface, a second light-emitting region EA2 and a third light-emitting region EA3, as well as a second transistor region TrA2 and a third transistor region TrA3 located on one side of the second light-emitting region EA2 and the third light-emitting region EA3 are defined.

[0173] As a result, the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3 are defined to overlap with each other. The first transistor region TrA1, the second transistor region TrA2, and the third transistor region TrA3 are defined to overlap with each other.

[0174] In the LED display device 100 according to the first embodiment of the present disclosure, an LED 200 including a first active layer 205a is configured to correspond to a first light-emitting region EA1, a second active layer 205b of only the LED 200 is configured to correspond to a second light-emitting region EA2, and a third active layer 205c of only the LED 200 is configured to correspond to a third light-emitting region EA3. A first switching transistor STW1 and a first driving transistor DRT1 for driving the first active layer 205a are disposed in the first transistor region TrA1, a second switching transistor STW2 and a second driving transistor DRT2 for driving the second active layer 205b are disposed in the second transistor region TrA2, and a third switching transistor STW3 and a third driving transistor DRT3 for driving the third active layer 205c are disposed in the third transistor region TrA3.

[0175] Since the first active layer 205a, the second active layer 205b, and the third active layer 205c obtain all the red, green, and blue in a single pixel P, the pixel size is reduced compared to the LED display device according to the comparative example.

[0176] Because of the increased density of pixels P per unit area, high resolutions of more than 300 ppi (pixels per inch) and ultra-high resolutions of more than 500 ppi are achieved.

[0177] Furthermore, since the areas of the first active layer 205a, the second active layer 205b, and the third active layer 205c are enlarged, the luminous efficiency of each of the active layers 205a, 205b, and 205c is improved, and a relatively high-brightness image is obtained.

[0178] Furthermore, by omitting the LED 200 transfer process, manufacturing time and costs are reduced, and manufacturing efficiency is improved. Since the first active layer 205a, the second active layer 205b, and the third active layer 205c are formed on the same growth substrate 301 through epitaxial growth, manufacturing costs are reduced, the manufacturing process is simplified, and product reliability is improved.

[0179] Figure 17 This is a schematic cross-sectional view showing the pixels of a light-emitting diode display device according to a first embodiment of the present disclosure.

[0180] For ease of explanation, Figure 17 The diagram shows a first light-emitting region EA1, a second light-emitting region EA2 and a third light-emitting region EA3, a first transistor region TrA1, a second transistor region TrA2 and a third transistor region TrA3, and a non-light-emitting region NEA.

[0181] As shown in the figure, a single unit pixel P is defined on the substrate 101 to include a first light-emitting region to a third light-emitting region and a non-light-emitting region NEA along the edge of a first light-emitting region EA1. The image is substantially shown in the first light-emitting region EA1, the second light-emitting region EA2, and the third light-emitting region EA3. The first light-emitting region EA1 and the second light-emitting region EA2 are defined to overlap each other, and the first light-emitting region EA1 and the third light-emitting region EA3 are defined to overlap each other.

[0182] The edge of the first luminescent region EA1 constitutes the non-luminescent region NEA.

[0183] The first transistor region TrA1, the second transistor region TrA2, and the third transistor region TrA3 are defined within the non-light-emitting region NEA. The first transistor region TrA1, the second transistor region TrA2, and the third transistor region TrA3 are defined by the first switching regions STrA1, STrA2, and STrA3 where the first switching transistor STW1, the second switching transistor STW2, and the third switching transistor STW3 are located; the first driving regions DTrA1, DTr2, and DTr3 where the first driving transistor DRT1, the second driving transistor DRT2, and the third driving transistor DRT3 are located; and the first storage regions StgA1, StgA2, and StgA3 where the first storage capacitor Cst1, the second storage capacitor Cst2, and the third storage capacitor Cst3 are located.

[0184] In the first transistor region TrA1 of the non-light-emitting region NEA on the substrate 101, the first switching gate 103a is configured to correspond to the first switching region STrA1, and the first driving gate 102a is configured to correspond to the first driving region DTrA1. A first gate insulating pattern 112a is disposed on the first switching gate 103a and the first driving gate 102a to cover the first switching gate 103a and the first driving gate 102a.

[0185] The first active switching layer S-ACT1 is disposed on the first gate insulating pattern 112a corresponding to the first switching region STrA1. The first active switching layer S-ACT1 includes a first switching semi-insulating pattern 105a corresponding to the first switching gate 103a and forming a channel, and a first switching source region 108a and a drain region 109a located on both sides of the first switching semi-insulating pattern 105a and doped with relatively high concentrations of impurities.

[0186] The first driving active layer D-ACT1 is disposed on the first gate insulating pattern 112a corresponding to the first driving region DTrA1. The first driving active layer D-ACT1 includes a first driving semi-insulating pattern 104a corresponding to the first driving gate 102a and forming a channel, and a first driving source region 106a and a drain region 107a on both sides of the first driving semi-insulating pattern 104a and doped with relatively high concentrations of impurities.

[0187] A first interlayer insulating layer 140a is disposed on the entire substrate 101 having a first switching active layer S-ACT1 and a first driving active layer D-ACT1. A first interlayer contact hole 141a and a second interlayer contact hole 141b are formed in the first interlayer insulating layer 140a, respectively exposing a first driving drain region 107a and a first driving source region 106a, to correspond to the first driving region DTrA1. A third interlayer contact hole 141c and a fourth interlayer contact hole 141d are formed in the first interlayer insulating layer 140a, respectively exposing a first switching source region 108a and a first switching drain region 109a, to correspond to the first switching region STrA1.

[0188] On the first interlayer insulating layer 140a, a first driving drain 114a is provided that is electrically connected to the first driving drain region 107a of the first driving active layer D-ACT1 exposed through the first interlayer contact hole 141a, and a first driving source 115a is provided that is electrically connected to the first driving source region 106a of the first driving active layer D-ACT1 exposed through the second interlayer contact hole 141b.

[0189] In addition, a first switch source 116a is provided that is electrically connected to the first switch source region 108a of the first switch active layer S-ACT1 exposed through the third interlayer contact hole 141c, and a first switch drain 117a is provided that is electrically connected to the first switch drain region 109a of the first switch active layer S-ACT1 exposed through the fourth interlayer contact hole 141d.

[0190] The first switch gate 103a, the first switch active layer S-ACT1, the first switch source 116a and the first switch drain 117a constitute the first switch transistor STW1, and the first drive gate 102a, the first drive active layer D-ACT1, the first drive source 115a and the first drive drain 114a constitute the first drive transistor DRT1.

[0191] The first-first storage electrode 121 is disposed in the first storage region StgA1 and is electrically connected to the first driving source electrode 115a through the fifth interlayer contact hole 141e in the first interlayer insulating layer 140a.

[0192] The first switch source 116a extends to the first storage region StgA1 to form the first-second storage electrode 125a, and the first-second storage electrode 125a overlaps with the first-first storage electrode 121. The first dielectric layer 123a is inserted between the first-second storage electrode 125a and the first-first storage electrode 121 to form the first storage capacitor Cst1.

[0193] The first driving drain 114a of the first driving region DTrA1 extends to the first light-emitting region EA1 to form the first connecting electrode 127.

[0194] The second interlayer insulating layer 140b is disposed on the entire substrate 101 having the first connecting electrode 127, and the recess 143 is disposed in the second interlayer insulating layer 140b to correspond to the first light-emitting region EA1.

[0195] LED 200 is disposed in recess 143.

[0196] The LED 200 in the recess 143 of the second interlayer insulating layer 140b corresponding to the first light-emitting region EA1 includes a first pad electrode 201a connected to the first connection electrode 127, a first semiconductor layer 203a, a first active layer 205a, and a second semiconductor layer 207 sequentially disposed on the first pad electrode 201a. The second active layer 205b, the third semiconductor layer 203b, and the third pad electrode 201b are sequentially disposed on the second semiconductor layer 207 to correspond to the second light-emitting region EA2, and the third active layer 205c, the fourth semiconductor layer 203c, and the fourth pad electrode 201c are sequentially disposed on another portion of the second semiconductor layer 207 to correspond to the third light-emitting region EA3.

[0197] The first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c provide holes to the first active layer 205a, the second active layer 205b, and the third active layer 205c, respectively. The first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c may comprise positive gallium nitride (p-GaN) group semiconductor materials, and the p-GaN group semiconductor materials may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Magnesium (Mg), zinc (Zn), or beryllium (Be) may be used as impurities to dope the first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c.

[0198] The first active layer 205a, the second active layer 205b, and the third active layer 205c adjacent to the first semiconductor layer 203a, the third semiconductor layer 203b, and the fourth semiconductor layer 203c can have a multiple quantum well (MQW) structure, which includes a well layer and a barrier layer having a band gap larger than that of the well layer.

[0199] The first active layer 205a emits red light, the second active layer 205b emits blue light, and the third active layer 205c emits green light.

[0200] The first active layer 205a, the second active layer 205b, and the third active layer 205c can have an indium gallium nitride (InGaN) / gallium nitride (GaN) MQW structure, and the first active layer 205a can be doped with europium (Eu).

[0201] As a result, the first active layer 205a may include europium (Eu)-doped III-V or II-VI group semiconductors. For example, the first active layer 205a may include compound semiconductor materials such as europium (Eu)-doped gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN).

[0202] Europium (Eu) doped into the first active layer 205a has an ionic state. As a result, electrons and holes injected from the first semiconductor layer 203a and the second semiconductor layer 207 recombine with each other in the first active layer 205a, and in the europium (Eu) 3+ The transition in the first active layer 205a causes it to emit red light (590nm to 670nm).

[0203] Each of the second active layer 205b emitting blue light and the third active layer 205c emitting green light may comprise a compound semiconductor material, such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN) doped with indium (In). The second active layer 205b and the third active layer 205c may have different doping concentrations.

[0204] As the indium concentration increases, the wavelength of light emitted from the second active layer 205b and the third active layer 205c shifts from short wavelengths to long wavelengths. As a result, the third active layer 205c, with a relatively high indium concentration, can emit green light (490 nm to 560 nm), while the second active layer 205b, with a relatively low indium concentration, can emit blue light (440 nm to 480 nm).

[0205] The indium concentration doped into the second active layer 205b and the third active layer 205c can be easily adjusted, and the color purity of blue and green can be adjusted by changing the indium concentration.

[0206] The second semiconductor layer 207 provides electrons to the first active layer 205a, the second active layer 205b, and the third active layer 205c. The second semiconductor layer 207 may include a negative gallium nitride (n-GaN) group semiconductor material, and the negative gallium nitride (n-GaN) group semiconductor material may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), or carbon (C) may be used as impurities to dope the second semiconductor layer 207.

[0207] The second semiconductor layer 207 on the first active layer 205a is configured to be exposed on the second interlayer insulating layer 140b, and the second pad electrode 209 is disposed along the edge of the second semiconductor layer 207 on the second interlayer insulating layer 140b.

[0208] The second pad electrode 209 contacts the side surface of the second semiconductor layer 207.

[0209] Since the second pad electrode 209 does not affect the light emitted from the first active layer 205a, the second pad electrode 209 can be formed of a conductive material and a transparent material.

[0210] For example, the second pad electrode 209 may include indium tin oxide (ITO), indium zinc oxide (IZO), indium tin zinc oxide (ITZO), zinc oxide (ZnO), or tin oxide (TO) for transmitting light emitted from the first active layer 205a. Optionally, the second pad electrode 209 may include silver (Ag), aluminum (Al), gold (Au), chromium (Cr), iridium (Ir), magnesium (Mg), neodymium (Nd), nickel (Ni), palladium (Pd), platinum (Pt), rhodium (Rh), titanium (Ti), or tungsten (W), or alloys of at least two of them, or laminates of different metals.

[0211] An insulating layer 211 is disposed along the edge of the first semiconductor layer 203a, the first active layer 205a and the first pad electrode 201a, so that the first pad electrode 201a, the first active layer 205a and the first semiconductor layer 203a are insulated from the second pad electrode 209.

[0212] The data line DL and the common line Vcom are disposed on the second interlayer insulation layer 140b. The data line DL is electrically connected to the first switch drain 117a through the sixth interlayer contact hole 141f in the second interlayer insulation layer 140b.

[0213] The second pad electrode 209 is electrically connected to the common line Vcom on the second interlayer insulation layer 140b.

[0214] As a result, the first active layer 205a receives the power supply voltage from the first driving transistor DRT1 connected to the first pad electrode 201a and the common voltage through the second pad electrode 209 connected to the common line Vcom, thereby emitting light.

[0215] The third interlayer insulating layer 140c is disposed on the entire substrate 101 having LED 200, a common line Vcom corresponding to the first light-emitting region EA1 and a data line DL, and the second transistor region TrA2 is defined on one side of the non-light-emitting region NEA on the third interlayer insulating layer 140c.

[0216] In the second transistor region TrA2, the second switching gate 103b is configured to correspond to the second switching region STrA2, and the second driving gate 102b is configured to correspond to the second driving region DTrA2.

[0217] The second gate insulating pattern 112b is disposed on the second switching gate 103b and the second driving gate 102b to cover the second switching gate 103b and the second driving gate 102b.

[0218] The second active switching layer S-ACT2 is disposed on the second gate insulating pattern 112b corresponding to the second switching region STrA2. The second active switching layer S-ACT2 includes a second semi-insulating pattern 105b corresponding to the second switching gate 103b and forming a channel, and a second source region 108b and a drain region 109b located on both sides of the second semi-insulating pattern 105b and doped with a relatively high concentration of impurities.

[0219] The second driving active layer D-ACT2 is disposed on the second gate insulating pattern 112b corresponding to the second driving region DTrA2. The second driving active layer D-ACT2 includes a second driving semi-insulating pattern 104b corresponding to the second driving gate 102b and forming a channel, and a second driving source region 106b and a drain region 107b on both sides of the second driving semi-insulating pattern 104b and doped with a relatively high concentration of impurities.

[0220] The third transistor region TrA3 is defined on the third interlayer insulating layer 140c on the other side of the non-light-emitting region NEA. In the third transistor region TrA3, the third switching gate 103c is configured to correspond to the third switching region STrA3, and the third driving gate 102c is configured to correspond to the third driving region DTrA3.

[0221] The third gate insulating pattern 112c is disposed on the third switch gate 103c and the third drive gate 102c to cover the third switch gate 103c and the third drive gate 102c.

[0222] The third active switching layer S-ACT3 is disposed on the third gate insulating pattern 112c corresponding to the third switching region STrA3. The third active switching layer S-ACT3 includes a third semi-insulating pattern 105c corresponding to the third switching gate 103c and forming a channel, and a third source region 108c and a drain region 109c on both sides of the third semi-insulating pattern 105c and doped with a relatively high concentration of impurities.

[0223] The third driving active layer D-ACT3 is disposed on the third gate insulating pattern 112c corresponding to the third driving region DTrA3. The third driving active layer D-ACT3 includes a third driving semi-insulating pattern 104c corresponding to the third driving gate 102c and forming a channel, and a third driving source region 106c and a drain region 107c on both sides of the third driving semi-insulating pattern 104c and doped with relatively high concentrations of impurities.

[0224] A fourth interlayer insulating layer 140d is disposed on the entire substrate 101 having a second switching active layer S-ACT2, a third switching active layer S-ACT3, a second driving active layer D-ACT2, and a third driving active layer D-ACT3. A seventh interlayer contact hole 141g and an eighth interlayer contact hole 141h are formed in the fourth interlayer insulating layer 140d, respectively exposing the second driving drain region 107b and the second driving source region 106b, to correspond to the second driving region DTrA2. A ninth interlayer contact hole 141i and a tenth interlayer contact hole 141j are formed in the fourth interlayer insulating layer 140d, respectively exposing the second switching source region 108b and the second switching drain region 109b, to correspond to the second switching region STrA2.

[0225] Thirteenth interlayer contact holes 141m and fourteenth interlayer contact holes 141n are formed in the fourth interlayer insulating layer 140d, respectively exposing the third driving drain region 107c and the third driving source region 106c, to correspond to the third driving region DTrA3. Fifteenth interlayer contact holes 141o and sixteenth interlayer contact holes 141p are formed in the fourth interlayer insulating layer 140d, respectively exposing the third switching source region 108c and the third switching drain region 109c, to correspond to the third switching region STrA3.

[0226] Additionally, the fourth interlayer insulating layer 140d has an eleventh interlayer contact hole 141k that exposes the third pad electrode 201b and a twelfth interlayer contact hole 141l that exposes the fourth pad electrode 201c having the third interlayer insulating layer 140c.

[0227] The fourth interlayer insulation layer 140d has an eighteenth interlayer contact hole 141r and a nineteenth interlayer contact hole 141s that expose the data line DL having the third interlayer insulation layer 140c.

[0228] On the fourth interlayer insulating layer 140d, a second driving drain 114b is provided, which is electrically connected to the second driving drain region 107b of the second driving active layer D-ACT2 exposed through the seventh interlayer contact hole 141g, and a second driving source 115b is provided, which is electrically connected to the second driving source region 106b of the second driving active layer D-ACT2 exposed through the eighth interlayer contact hole 141h.

[0229] In addition, a second switch source 116b is provided that is electrically connected to the second switch source region 108b of the second switch active layer S-ACT2 exposed through the ninth interlayer contact hole 141i, and a second switch drain 117b is provided that is electrically connected to the second switch drain region 109b of the second switch active layer S-ACT2 exposed through the tenth interlayer contact hole 141j.

[0230] On the fourth interlayer insulating layer 140d, a third driving drain 114c is provided, which is electrically connected to the third driving drain region 107c of the third driving active layer D-ACT3 exposed through the thirteenth interlayer contact hole 141m, and a third driving source 115c is provided, which is electrically connected to the third driving source region 106c of the third driving active layer D-ACT3 exposed through the fourteenth interlayer contact hole 141n.

[0231] In addition, a third switch source 116c is provided that is electrically connected to the third switch source region 108c of the third switch active layer S-ACT3 exposed through the fifteenth interlayer contact hole 141o, and a third switch drain 117c is provided that is electrically connected to the third switch drain region 109c of the third switch active layer S-ACT3 exposed through the sixteenth interlayer contact hole 141p.

[0232] The second driving drain 114b is electrically connected to the third pad electrode 201b through the eleventh interlayer contact hole 141k, and the third driving drain 114c is electrically connected to the fourth pad electrode 201c through the twelfth interlayer contact hole 141l.

[0233] The drain of the third switch 117c is electrically connected to the data line DL through the seventeenth interlayer contact hole 141q, and the drain of the second switch 117b is electrically connected to the data line DL through the eighteenth interlayer contact hole 141r.

[0234] As a result, the second active layer 205b receives a common voltage through the second pad electrode 209 connected to the common line Vcom, and receives a power supply voltage from the second driving transistor DRT2 through the third pad electrode 201b, thereby emitting light. The third active layer 205c receives a common voltage through the second pad electrode 209 connected to the common line Vcom, and receives a power supply voltage from the third driving transistor DRT3 through the fourth pad electrode 201c, thereby emitting light.

[0235] The second switch gate 103b, the second switch active layer S-ACT2, the second switch source 116b, and the second switch drain 117b constitute the second switch transistor STW2. The second drive gate 102b, the second drive active layer D-ACT2, the second drive source 115b, and the second drive drain 114b constitute the second drive transistor DRT2. The third switch gate 103c, the third switch active layer S-ACT3, the third switch source 116c, and the third switch drain 117c constitute the third switch transistor STW3. The third drive gate 102c, the third drive active layer D-ACT3, the third drive drain 114c, and the third drive source 115c constitute the third drive transistor DRT3.

[0236] The second-first storage electrode 121b is disposed in the second storage region StgA2 and is electrically connected to the second driving source electrode 115b through the nineteenth interlayer contact hole 141s in the fourth interlayer insulating layer 140d. The second switching source electrode 116b extends into the second storage region StgA2 to form the second-second storage electrode 125b, and the second-second storage electrode 125b overlaps with the second-first storage electrode 121b. The second dielectric layer 123b is located between the second-second storage electrode 125b and the second-first storage electrode 121b to form the second storage capacitor Cst2.

[0237] The third-first storage electrode 121c, electrically connected to the third driving source electrode 115c via the twentieth interlayer contact hole 141t of the fourth interlayer insulating layer 140d, is disposed in the third storage region StgA3, and the third switching source electrode 116c extends into the third storage region StgA3 to form the third-second storage electrode 125c. The third-first storage electrode 121c and the third-second storage electrode 125c overlap each other, and the third dielectric layer 123c is disposed between the third-first storage electrode 121c and the third-second storage electrode 125c to form the third storage capacitor Cst3.

[0238] The fifth interlayer insulation layer 140e is disposed on the fourth interlayer insulation layer 140d, the second and third drive source drains 115b, 114b, 115c and 114c, the second and third switch source drains 116b, 117b, 116c and 117c, the second-second storage electrode 125b and the third-second storage electrode 125c.

[0239] The fifth interlayer insulation layer 140e protects the LED 200 and the first to third driving transistors and switching transistors DRT1, DRT2, DRT3, STW1, STW2 and STW3, and prevents external oxygen and moisture from penetrating the LED display device 100.

[0240] -Second Implementation Method–

[0241] Figure 18 This is a schematic cross-sectional view showing the pixels of a light-emitting diode display device according to a second embodiment of the present disclosure. Figure 19 This is a schematic circuit diagram showing the circuit structure of a light-emitting diode display device according to a second embodiment of the present disclosure.

[0242] To avoid repetitive descriptions, parts having the same function as in the first embodiment will be indicated by the same reference numerals, and the characteristic parts of the second embodiment will be described.

[0243] For ease of explanation, Figure 18 The diagram shows a first light-emitting region EA1, a second light-emitting region EA2 and a third light-emitting region EA3, a first transistor region TrA1, a second transistor region TrA2 and a third transistor region TrA3, and a non-light-emitting region NEA.

[0244] As shown in the figure, in the first transistor region TrA1 of the non-light-emitting region NEA on the substrate 101, the first switching gate 103a is configured to correspond to the first switching region STrA1, and the first driving gate 102a is configured to correspond to the first driving region DTrA1. A first gate insulating pattern 112a is disposed on the first switching gate 103a and the first driving gate 102a to cover the first switching gate 103a and the first driving gate 102a.

[0245] The first active switching layer S-ACT1 is disposed on the first gate insulating pattern 112a corresponding to the first switching region STrA1. The first active switching layer S-ACT1 includes a first switching semi-insulating pattern 105a corresponding to the first switching gate 103a and forming a channel, and a first switching source region 108a and a drain region 109a located on both sides of the first switching semi-insulating pattern 105a and doped with relatively high concentrations of impurities.

[0246] The first driving active layer D-ACT1 is disposed on the first gate insulating pattern 112a corresponding to the first driving region DTrA1. The first driving active layer D-ACT1 includes a first driving semi-insulating pattern 104a corresponding to the first driving gate 102a and forming a channel, and a first driving source region 106a and a drain region 107a on both sides of the first driving semi-insulating pattern 104a and doped with relatively high concentrations of impurities.

[0247] A first interlayer insulating layer 140a is disposed on the entire substrate 101 having a first switching active layer S-ACT1 and a first driving active layer D-ACT1. A first interlayer contact hole 141a and a second interlayer contact hole 141b are formed in the first interlayer insulating layer 140a, respectively exposing a first driving drain region 107a and a first driving source region 106a, to correspond to the first driving region DTrA1. A third interlayer contact hole 141c and a fourth interlayer contact hole 141d are formed in the first interlayer insulating layer 140a, respectively exposing a first switching drain region 109a and a first switching source region 108a, to correspond to the first switching region STrA1.

[0248] On the first interlayer insulating layer 140a, a first driving drain 114a is provided that is electrically connected to the first driving drain region 107a of the first driving active layer D-ACT1 exposed through the first interlayer contact hole 141a, and a first driving source 115a is provided that is electrically connected to the first driving source region 106a of the first driving active layer D-ACT1 exposed through the second interlayer contact hole 141b.

[0249] In addition, a first switch drain 117a is provided that is electrically connected to the first switch drain region 109a of the first switch active layer S-ACT1 exposed through the third interlayer contact hole 141c, and a first switch source 116a is provided that is electrically connected to the first switch source region 108a of the first switch active layer S-ACT1 exposed through the fourth interlayer contact hole 141d.

[0250] The first switch gate 103a, the first switch active layer S-ACT1, the first switch source 116a and the first switch drain 117a constitute the first switch transistor STW1, and the first drive gate 102a, the first drive active layer D-ACT1, the first drive drain 114a and the first drive source 115a constitute the first drive transistor DRT1.

[0251] The first driving drain 114a of the first driving region DTrA1 extends to the first light-emitting region EA1 to form the first connecting electrode 127.

[0252] The second interlayer insulating layer 140b is disposed on the entire substrate 101 having the first connecting electrode 127, and the recess 143 is disposed in the second interlayer insulating layer 140b to correspond to the first light-emitting region EA1.

[0253] A light-emitting diode (LED) 200 is disposed in the recess 143.

[0254] The LED 200 in the recess 143 of the second interlayer insulating layer 140b corresponding to the first light-emitting region EA1 includes a first pad electrode 201a connected to the first connection electrode 127, a first semiconductor layer 207a, a first active layer 205a, and a second semiconductor layer 203 sequentially disposed on the first pad electrode 201a. The second active layer 205b, the third semiconductor layer 207b, and the third pad electrode 201b are sequentially disposed on the second semiconductor layer 203 to correspond to the second light-emitting region EA2, and the third active layer 205c, the fourth semiconductor layer 207c, and the fourth pad electrode 201c are sequentially disposed on the second semiconductor layer 203 to correspond to the third light-emitting region EA3.

[0255] The first semiconductor layer 207a, the third semiconductor layer 207b, and the fourth semiconductor layer 207c provide electrons to the first active layer 205a, the second active layer 205b, and the third active layer 205c, respectively. The first semiconductor layer 207a, the third semiconductor layer 207b, and the fourth semiconductor layer 207c may comprise a negative-mode gallium nitride (n-GaN) group semiconductor material, and the n-GaN group semiconductor material may comprise gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Silicon (Si), germanium (Ge), selenium (Se), tellurium (Te), or carbon (C) may be used as impurities to dope the first semiconductor layer 207a, the third semiconductor layer 207b, and the fourth semiconductor layer 207c.

[0256] The first active layer 205a, the second active layer 205b, and the third active layer 205c adjacent to the first semiconductor layer 207a, the third semiconductor layer 207b, and the fourth semiconductor layer 207c can have a multiple quantum well (MQW) structure, which includes a well layer and a barrier layer having a band gap larger than that of the well layer.

[0257] The first active layer 205a emits red light, the second active layer 205b emits blue light, and the third active layer 205c emits green light.

[0258] The first active layer 205a, the second active layer 205b, and the third active layer 205c can have an indium gallium nitride (InGaN) / gallium nitride (GaN) MQW structure, and the first active layer 205a can be doped with europium (Eu).

[0259] As a result, the first active layer 205a may include europium (Eu)-doped III-V or II-VI group semiconductors. For example, the first active layer 205a may include compound semiconductor materials such as europium (Eu)-doped gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN).

[0260] Europium (Eu) doped into the first active layer 205a has an ionic state. As a result, electrons and holes injected from the first semiconductor layer 207a and the second semiconductor layer 203 recombine with each other in the first active layer 205a, and in the europium (Eu) 3+ The transition in the first active layer 205a causes it to emit red light (590nm to 670nm).

[0261] Each of the second active layer 205b emitting blue light and the third active layer 205c emitting green light may comprise a compound semiconductor material, such as gallium nitride (GaN), indium gallium nitride (InGaN), aluminum gallium nitride (AlGaN), and indium aluminum gallium nitride (InAlGaN) doped with indium (In). The second active layer 205b and the third active layer 205c may have different doping concentrations.

[0262] As the indium concentration increases, the wavelength of light emitted from the second active layer 205b and the third active layer 205c shifts from short wavelengths to long wavelengths. As a result, the third active layer 205c, with a relatively high indium concentration, can emit green light (490 nm to 560 nm), while the second active layer 205b, with a relatively low indium concentration, can emit blue light (440 nm to 480 nm).

[0263] The indium concentration doped into the second active layer 205b and the third active layer 205c can be easily adjusted, and the color purity of blue and green can be adjusted by changing the indium concentration.

[0264] The second semiconductor layer 203 provides holes to the first active layer 205a, the second active layer 205b, and the third active layer 205c. The second semiconductor layer 203 may include a positive gallium nitride (p-GaN) group semiconductor material, and the positive gallium nitride (p-GaN) group semiconductor material may include gallium nitride (GaN), aluminum gallium nitride (AlGaN), indium gallium nitride (InGaN), or aluminum indium gallium nitride (AlInGaN). Magnesium (Mg), zinc (Zn), or beryllium (Be) may be used as impurities to dope the second semiconductor layer 203.

[0265] The second semiconductor layer 203 on the first active layer 205a is configured to be exposed on the second interlayer insulating layer 140b, and the second pad electrode 209 is disposed along the edge of the second semiconductor layer 203 on the second interlayer insulating layer 140b.

[0266] The second pad electrode 209 contacts the side surface of the second semiconductor layer 203.

[0267] An insulating layer 211 is disposed along the edge of the first semiconductor layer 207a, the first active layer 205a and the first pad electrode 201a, so that the first pad electrode 201a, the first active layer 205a and the first semiconductor layer 207a are insulated from the second pad electrode 209.

[0268] The data line DL and the common line Vcom are disposed on the second interlayer insulation layer 140b. The data line DL is electrically connected to the first switch source 116a through the sixth interlayer contact hole 141f in the second interlayer insulation layer 140b.

[0269] The second pad electrode 209 is electrically connected to the common line Vcom on the second interlayer insulation layer 140b.

[0270] A sixth interlayer contact hole 141f is formed in the second interlayer insulating layer 140b to expose the first switch drain 117a, and a first-second storage electrode 125a connected to the first switch drain 117a through the sixth interlayer contact hole 141f is disposed on the second interlayer insulating layer 140b to correspond to the first storage region StgA1.

[0271] The first driving source 115a extends to the first storage region StgA1 to form the first-first storage electrode 121a, and the first-first storage electrode 121a overlaps with the first-second storage electrode 125a. The first dielectric layer 123a is located between the first-first storage electrode 121a and the first-second storage electrode 125a to form the first storage capacitor Cst1.

[0272] The third interlayer insulating layer 140c is disposed on the entire substrate 101 having LED 200, source line Vdd corresponding to the first light-emitting region EA1 and data line DL, and the second transistor region TrA2 is defined on one side of the non-light-emitting region NEA on the third interlayer insulating layer 140c.

[0273] In the second transistor region TrA2, the second switching gate 103b is configured to correspond to the second switching region STrA2, and the second driving gate 102b is configured to correspond to the second driving region DTrA2.

[0274] The second gate insulating pattern 112b is disposed on the second switching gate 103b and the second driving gate 102b to cover the second switching gate 103b and the second driving gate 102b.

[0275] The second active switching layer S-ACT2 is disposed on the second gate insulating pattern 112b corresponding to the second switching region STrA2. The second active switching layer S-ACT2 includes a second semi-insulating pattern 105b corresponding to the second switching gate 103b and forming a channel, and a second source region 108b and a drain region 109b located on both sides of the second semi-insulating pattern 105b and doped with a relatively high concentration of impurities.

[0276] The second driving active layer D-ACT2 is disposed on the second gate insulating pattern 112b corresponding to the second driving region DTrA2. The second driving active layer D-ACT2 includes a second driving semi-insulating pattern 104b corresponding to the second driving gate 102b and forming a channel, and a second driving source region 106b and a drain region 107b on both sides of the second driving semi-insulating pattern 104b and doped with a relatively high concentration of impurities.

[0277] The third transistor region TrA3 is defined on the third interlayer insulating layer 140c on the other side of the non-light-emitting region NEA. In the third transistor region TrA3, the third switching gate 103c is configured to correspond to the third switching region STrA3, and the third driving gate 102c is configured to correspond to the third driving region DTrA3.

[0278] The third gate insulating pattern 112c is disposed on the third switch gate 103c and the third drive gate 102c to cover the third switch gate 103c and the third drive gate 102c.

[0279] The third active switching layer S-ACT3 is disposed on the third gate insulating pattern 112c corresponding to the third switching region STrA3. The third active switching layer S-ACT3 includes a third semi-insulating pattern 105c corresponding to the third switching gate 103c and forming a channel, and a third source region 108c and a drain region 109c on both sides of the third semi-insulating pattern 105c and doped with a relatively high concentration of impurities.

[0280] The third driving active layer D-ACT3 is disposed on the third gate insulating pattern 112c corresponding to the third driving region DTrA3. The third driving active layer D-ACT3 includes a third driving semi-insulating pattern 104c corresponding to the third driving gate 102c and forming a channel, and a third driving source region 106c and a drain region 107c on both sides of the third driving semi-insulating pattern 104c and doped with relatively high concentrations of impurities.

[0281] A fourth interlayer insulating layer 140d is disposed on the entire substrate 101 having a second switching active layer S-ACT2, a third switching active layer S-ACT3, a second driving active layer D-ACT2, and a third driving active layer D-ACT3. A seventh interlayer contact hole 141g and an eighth interlayer contact hole 141h are formed in the fourth interlayer insulating layer 140d, respectively exposing the second driving drain region 107b and the second driving source region 106b, to correspond to the second driving region DTrA2. A ninth interlayer contact hole 141i and a tenth interlayer contact hole 141j are formed in the fourth interlayer insulating layer 140d, respectively exposing the second switching drain region 109b and the second switching source region 108b, to correspond to the second switching region STrA2.

[0282] Thirteenth interlayer contact holes 141m and fourteenth interlayer contact holes 141n are formed in the fourth interlayer insulating layer 140d, respectively exposing the third driving drain region 107c and the third driving source region 106c, to correspond to the third driving region DTrA3. Fifteenth interlayer contact holes 141o and sixteenth interlayer contact holes 141p are formed in the fourth interlayer insulating layer 140d, respectively exposing the third switch drain region 109c and the third switch source region 108c, to correspond to the third switching region STrA3.

[0283] Additionally, the fourth interlayer insulating layer 140d has an eleventh interlayer contact hole 141k that exposes the third pad electrode 201b and a twelfth interlayer contact hole 141l that exposes the fourth pad electrode 201c having the third interlayer insulating layer 140c.

[0284] The fourth interlayer insulation layer 140d has an eighteenth interlayer contact hole 141r and a nineteenth interlayer contact hole 141s that expose the data line DL having the third interlayer insulation layer 140c.

[0285] On the fourth interlayer insulating layer 140d, a second driving drain 114b is provided, which is electrically connected to the second driving drain region 107b of the second driving active layer D-ACT2 exposed through the seventh interlayer contact hole 141g, and a second driving source 115b is provided, which is electrically connected to the second driving source region 106b of the second driving active layer D-ACT2 exposed through the eighth interlayer contact hole 141h.

[0286] In addition, a second switch drain 117b is provided that is electrically connected to the second switch drain region 109b of the second switch active layer S-ACT2 exposed through the ninth interlayer contact hole 141i, and a second switch source 116b is provided that is electrically connected to the second switch source region 108b of the second switch active layer S-ACT2 exposed through the tenth interlayer contact hole 141j.

[0287] On the fourth interlayer insulating layer 140d, a third driving drain 114c is provided, which is electrically connected to the third driving drain region 107c of the third driving active layer D-ACT3 exposed through the thirteenth interlayer contact hole 141m, and a third driving source 115c is provided, which is electrically connected to the third driving source region 106c of the third driving active layer D-ACT3 exposed through the fourteenth interlayer contact hole 141n.

[0288] In addition, a third switch drain 117c is provided that is electrically connected to the third switch drain region 109c of the third switch active layer S-ACT3 exposed through the fifteenth interlayer contact hole 141o, and a third switch source 116c is provided that is electrically connected to the third switch source region 108c of the third switch active layer S-ACT3 exposed through the sixteenth interlayer contact hole 141p.

[0289] The second driving drain 114b is electrically connected to the third pad electrode 201b through the eleventh interlayer contact hole 141k, and the third driving drain 114c is electrically connected to the fourth pad electrode 201c through the twelfth interlayer contact hole 141l.

[0290] The third switch source 116c is electrically connected to the data line DL through the seventeenth interlayer contact hole 141q, and the second switch source 116b is electrically connected to the data line DL through the eighteenth interlayer contact hole 141r.

[0291] The second switch gate 103b, the second switch active layer S-ACT2, the second switch source 116b, and the second switch drain 117b constitute the second switch transistor STW2. The second drive gate 102b, the second drive active layer D-ACT2, the second drive source 115b, and the second drive drain 114b constitute the second drive transistor DRT2. The third switch gate 103c, the third switch active layer S-ACT3, the third switch source 116c, and the third switch drain 117c constitute the third switch transistor STW3. The third drive gate 102c, the third drive active layer D-ACT3, the third drive source 115c, and the third drive drain 114c constitute the third drive transistor DRT3.

[0292] The second-first storage electrode 121b is disposed in the second storage region StgA2 and is electrically connected to the second driving source electrode 115b through the nineteenth interlayer contact hole 141s in the fourth interlayer insulating layer 140d. The second switch drain electrode 117b extends to the second storage region StgA2 to form the second-second storage electrode 125b, and the second-second storage electrode 125b overlaps with the second-first storage electrode 121b. The second dielectric layer 123b is located between the second-second storage electrode 125b and the second-first storage electrode 121b to form the second storage capacitor Cst2.

[0293] The third-first storage electrode 121c, electrically connected to the third driving source electrode 115c via the twentieth interlayer contact hole 141t of the fourth interlayer insulating layer 140d, is disposed in the third storage region StgA3, and the third switch drain electrode 117c extends into the third storage region StgA3 to form the third-second storage electrode 125c. The third-first storage electrode 121c and the third-second storage electrode 125c overlap each other, and the third dielectric layer 123c is disposed between the third-first storage electrode 121c and the third-second storage electrode 125c to form the third storage capacitor Cst3.

[0294] The fifth interlayer insulation layer 140e is disposed on the fourth interlayer insulation layer 140d, the second and third drive source drains 115b, 114b, 115c and 114c, the second-second storage electrode 125b, the second and third switch source drains 116b, 117b, 116c and 117c, and the third-second storage electrode 125c.

[0295] The fifth interlayer insulation layer 140e protects the LED 200 and the first to third driving transistors and switching transistors DRT1, DRT2, DRT3, STW1, STW2 and STW3, and prevents external oxygen and moisture from penetrating the LED display device 100.

[0296] In the LED display device 100 according to the second embodiment of the present disclosure, the first light-emitting region EA1 and the second light-emitting region EA2 overlap each other, and the first light-emitting region EA1 and the third light-emitting region EA3 overlap each other. An LED 200 including a first active layer 205a is configured to correspond to the first light-emitting region EA1, a second active layer 205b of only the LED 200 is configured to correspond to the second light-emitting region EA2, and a third active layer 205c of only the LED 200 is configured to correspond to the third light-emitting region EA3. A first switching transistor STW1 and a first driving transistor DRT1 for driving the first active layer 205a are disposed in the first transistor region TrA1, a second switching transistor STW2 and a second driving transistor DRT2 for driving the second active layer 205b are disposed in the second transistor region TrA2, and a third switching transistor STW3 and a third driving transistor DRT3 for driving the third active layer 205c are disposed in the third transistor region TrA3.

[0297] Since the first active layer 205a, the second active layer 205b, and the third active layer 205c obtain all the red, green, and blue in a single pixel P, the pixel size is reduced compared to the LED display device according to the comparative example.

[0298] Because of the increased density of pixels P per unit area, high resolutions of more than 300 ppi (pixels per inch) and ultra-high resolutions of more than 500 ppi are achieved.

[0299] Furthermore, since the areas of the first active layer 205a, the second active layer 205b, and the third active layer 205c are enlarged, the luminous efficiency of each of the active layers 205a, 205b, and 205c is improved, and a relatively high-brightness image is obtained.

[0300] Furthermore, by omitting the LED 200 transfer process, manufacturing time and costs are reduced, and manufacturing efficiency is improved. This is because the LEDs are grown epitaxially in (… Figure 12 The first active layer 205a, the second active layer 205b and the third active layer 205c are formed on the same growth substrate 301, thereby reducing manufacturing costs, simplifying the manufacturing process and improving product reliability.

[0301] While this disclosure has been described with reference to exemplary embodiments and examples, these embodiments and examples are not intended to limit the scope of this disclosure. Rather, various modifications and variations can be made to this disclosure without departing from the spirit or scope of the invention, as will be apparent to those skilled in the art. Therefore, this disclosure is intended to cover modifications and variations thereof, provided they fall within the scope of the appended claims and their equivalents. The various embodiments described above can be combined to provide further embodiments. If desired, aspects of the embodiments can be modified to employ concepts from various patents, applications, and disclosures to provide further embodiments. These and other changes can be made to the embodiments based on the detailed description above. Generally, the terminology used in the appended claims should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed as including all possible embodiments and the full scope of equivalents conferred by those claims. Therefore, the claims are not limited to this disclosure.

[0302] Cross-references to related applications

[0303] This application claims priority to Korean Patent Application No. 10-2019-0174025, filed in Korea on December 24, 2019, the entire contents of which are incorporated herein by reference.

Claims

1. A light-emitting diode (LED) display device, comprising: substrate; The LED includes: a first semiconductor layer, a first active layer and a second semiconductor layer disposed sequentially and corresponding to a first light-emitting region; a second active layer located on the second semiconductor layer and corresponding to a second light-emitting region overlapping a portion of the first light-emitting region; a third semiconductor layer located on the second active layer; a third active layer located on the second semiconductor layer and corresponding to a third light-emitting region overlapping another portion of the first light-emitting region; and a fourth semiconductor layer located on the third active layer. A first transistor, located on a portion of the substrate, is used to drive the first active layer; A second transistor, located on another portion of the substrate, is used to drive the second active layer; and A third transistor, located above the first transistor on the portion of the substrate, is used to drive the third active layer.

2. The LED display device according to claim 1, wherein, The first pad electrode is disposed below the first semiconductor layer, and the third and fourth pad electrodes are disposed on the third and fourth semiconductor layers, respectively. The second pad electrode is disposed along the edge of the second semiconductor layer and contacts the side surface of the second semiconductor layer.

3. The LED display device according to claim 2, wherein, An insulating layer is disposed along the edge of the first pad electrode, the first semiconductor layer, and the first active layer.

4. The LED display device according to claim 1, wherein, The first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer comprise negative gallium nitride (n-GaN) group semiconductor materials, and the second semiconductor layer comprises positive gallium nitride (p-GaN) group semiconductor materials.

5. The LED display device according to claim 1, wherein, The first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer comprise positive gallium nitride p-GaN group semiconductor materials, and the second semiconductor layer comprises negative gallium nitride n-GaN group semiconductor materials.

6. The LED display device according to claim 1, wherein, The first active layer is doped with europium (Eu).

7. The LED display device according to claim 2, wherein, The first pad electrode is electrically connected to the first driving drain of the first driving transistor of the first transistor. The second pad electrode is electrically connected to the common line. The third pad electrode is electrically connected to the second driving drain of the second driving transistor of the second transistor, and The fourth pad electrode is electrically connected to the third driving drain of the third driving transistor of the third transistor.

8. The LED display device according to claim 7, wherein, The first driving gate of the first driving transistor to the third driving gate of the third driving transistor are respectively electrically connected to the first switching source of the first switching transistor to the third switching source of the third switching transistor. Wherein, the first gate of the first switching transistor and the third gate of the third switching transistor are electrically connected to the gate line. Wherein, the first driving source of the first driving transistor to the third driving source of the third driving transistor are electrically connected to the power supply line, and The first switching source of the first switching transistor and the third switching source of the third switching transistor are electrically connected to the data line.

9. The LED display device according to claim 2, wherein, The first pad electrode is electrically connected to the first driving drain of the first driving transistor of the first transistor. The second pad electrode is electrically connected to the power supply line. The third pad electrode is electrically connected to the second driving drain of the second driving transistor of the second transistor, and The fourth pad electrode is electrically connected to the third driving drain of the third driving transistor of the third transistor.

10. The LED display device according to claim 9, wherein, The first driving gate of the first driving transistor to the third driving gate of the third driving transistor are respectively electrically connected to the first switching drain of the first switching transistor to the third switching drain of the third switching transistor. Wherein, the first gate of the first switching transistor and the third gate of the third switching transistor are electrically connected to the gate line. Wherein, the first driving source of the first driving transistor and the third driving source of the third driving transistor are electrically connected to a common line, and The first switching source of the first switching transistor and the third switching source of the third switching transistor are electrically connected to the data line.

11. The LED display device according to any one of claims 8 and 10, wherein, The first driving transistor to the third driving transistor includes: a first driving gate to a third driving gate, a first driving semi-insulating pattern to a third driving semi-insulating pattern, a first driving active layer to a third driving active layer having a first driving source region and a drain region to a third driving source region and a drain region, and a first driving source and a drain to a third driving source and a drain. The first to third switching transistors include a first to third switching gate, a first to third switching semi-insulating pattern, a first to third switching active layer having a first to third switching source and drain region, and a first to third switching active layer having a first to third switching source and drain region, and a first to third switching source and drain.

12. The LED display device according to claim 8, wherein, The first driving transistor to the third driving transistor includes: a first driving gate to a third driving gate, a first driving source region and a drain region to a third driving source region and a drain region, and a first driving source and a drain to a third driving source and a drain. Wherein, the first switching transistor to the third switching transistor includes the first switching gate to the third switching gate, the first switching semi-insulating pattern to the third switching semi-insulating pattern, the first switching active layer to the third switching active layer having the first switching source region and the drain region to the third switching source region and the drain region, and the first switching source and the drain to the third switching source and the drain.

13. A method for manufacturing a light-emitting diode (LED) display device, the method comprising the following steps: a) An undoped semiconductor material layer, a first semiconductor material layer, an active material layer, and a second semiconductor material layer are sequentially formed on a growth substrate; b) Forming a first insulating layer having a first recess on the second semiconductor material layer; c) A second active layer and a third semiconductor layer are sequentially formed in the first recess on the second semiconductor material layer; d) After forming the second recess in the first insulating layer, a second active layer and a third semiconductor layer are sequentially formed in the second recess on the second semiconductor material layer; e) Forming the first semiconductor layer, the first active layer, and the second semiconductor layer by patterning the first semiconductor material layer, the active material layer, and the second semiconductor material layer; f) An insulating layer is formed along the edge of the first active layer and the first semiconductor layer; g) A second pad electrode is formed along the edge of the second semiconductor layer, a third pad electrode is formed on the third semiconductor layer above the insulating layer, and a fourth pad electrode is formed on the fourth semiconductor layer; h) Remove the growth substrate and the undoped semiconductor material layer; as well as i) A first pad electrode is formed below the first semiconductor layer.

14. The method according to claim 13, wherein, Step d) includes forming a second insulating layer on the third semiconductor layer.

15. The method of claim 13, further comprising removing the first insulating layer prior to step c).

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