An operating method of a memory device, a memory device, and a memory system
By providing a low bias voltage to the gate of the select transistor during the pre-charge phase of the memory device, the programming interference problem caused by the threshold voltage drift of the select transistor in the three-dimensional memory device is solved, and more efficient programming operation is achieved.
CN114863963BActive Publication Date: 2026-06-19YANGTZE MEMORY TECH CO LTD
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- YANGTZE MEMORY TECH CO LTD
- Filing Date
- 2022-04-18
- Publication Date
- 2026-06-19
AI Technical Summary
Technical Problem
In three-dimensional memory devices, programming interference is a serious problem, especially when using gate-induced drain leakage (GIDL) precharge, where the threshold voltage drift of the select transistor for unselected memory cell strings affects programming interference.
Method used
During precharge, a low bias voltage is provided to the gate of the select transistor of the memory cell string for a duration shorter than the precharge bias rise time. After precharge ends, the low bias voltage is released or a small bias voltage is applied to reduce the threshold voltage drift of the select transistor.
Benefits of technology
It effectively reduces programming interference and improves the programming efficiency and reliability of storage devices.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN114863963B_ABST
Abstract
This invention discloses an operation method for a memory device, a memory device, and a memory system. The method includes: during a pre-charge period of a programming operation, providing a first pre-charge bias to a bit line connected to a string of memory cells, and providing a first low bias to the gate of a first select transistor included in the string of memory cells; and / or, providing a second pre-charge bias to a source line connected to the string of memory cells, and providing a second low bias to the gate of a second select transistor included in the string of memory cells; wherein the duration of the first low bias is less than the rise time of the first pre-charge bias; the duration of the second low bias is less than the rise time of the second pre-charge bias; and during the programming operation, programming the memory cells included in the string of memory cells according to a predetermined programming sequence.
Need to check novelty before this filing date? Find Prior Art