Dual-port SRAM cell and SRAM memory

Abstract

A dual-port SRAM cell and an SRAM memory, comprising a first inverter, a second inverter, a first write transfer transistor, a second write transfer transistor, a first read transfer transistor and a second read transfer transistor; the first inverter comprises a first pull-up transistor and a first pull-down transistor, the second inverter comprises a second pull-up transistor and a second pull-down transistor, the first write transfer transistor and the first read transfer transistor are both connected to the first inverter, and the second write transfer transistor and the second read transfer transistor are both connected to the second inverter; wherein the on-current of the first write transfer transistor and the on-current of the second write transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters; and the data writing capability is improved without changing the inherent process of the wafer factory.

Description

Technical Field

[0001] The present application belongs to the field of memory, and in particular to a dual-port SRAM unit and an SRAM memory. Background Art

[0002] In the related dual-port SRAM cells, each transistor adopts the same semiconductor process. The write data capability of the related dual-port SRAM cells is determined during the layout design. However, the layout design is limited by the inherent process of the wafer fab, which leads to the problem of difficulty in improving the write data capability. Summary of the invention

[0003] The purpose of the present application is to provide a dual-port SRAM cell and an SRAM memory, aiming to solve the problem that it is difficult to improve the data writing capability of the traditional dual-port SRAM cell.

[0004] An embodiment of the present application provides a dual-port SRAM cell, comprising:

[0005] including a first inverter, a second inverter, a first write pass transistor, a second write pass transistor, a first read pass transistor, and a second read pass transistor;

[0006] The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor and a second pull-down transistor, the first write transfer transistor and the first read transfer transistor are both connected to the first inverter, and the second write transfer transistor and the second read transfer transistor are both connected to the second inverter;

[0007] The on-current of the first write-transfer transistor and the on-current of the second write-transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters.

[0008] In one embodiment, the on-current of the first write-transfer transistor and the on-current of the second write-transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically:

[0009] The work function of the gate of the first write transfer transistor and the work function of the gate of the second write transfer transistor are increased through a gate work function modulation process so that the work function of the gate of the first write transfer transistor and the work function of the gate of the second write transfer transistor are both greater than the work function of the gate of the first pull-up transistor and the work function of the gate of the second pull-up transistor.

[0010] In one embodiment, the on-current of the first write-transfer transistor and the on-current of the second write-transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically:

[0011] The doping concentration of the channel of the first write-transfer transistor and the doping concentration of the channel of the second write-transfer transistor are increased by an ion implantation process so that the doping concentration of the channel of the first write-transfer transistor and the doping concentration of the channel of the second write-transfer transistor are both greater than the doping concentration of the channel of the first pull-up transistor and the doping concentration of the channel of the second pull-up transistor.

[0012] In one embodiment, the on-current of the first write-transfer transistor and the on-current of the second write-transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically:

[0013] By increasing the width-to-length ratio of the channel of the first write pass transistor and the width-to-length ratio of the channel of the second write pass transistor, the on-current of the first write pass transistor and the on-current of the second write pass transistor are both greater than the on-current of the first pull-up transistor and the on-current of the second pull-up transistor.

[0014] In one of the embodiments, the on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters.

[0015] In one embodiment, the on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically:

[0016] The work function of the gate of the first read pass transistor and the work function of the gate of the second read pass transistor are reduced by a gate work function modulation process so that the work function of the gate of the first read pass transistor and the work function of the gate of the second read pass transistor are both smaller than the work function of the gate of the first pull-down transistor and the work function of the gate of the second pull-down transistor.

[0017] In one embodiment, the on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically:

[0018] The doping concentration of the channel of the first read pass transistor and the doping concentration of the channel of the second read pass transistor are reduced by an ion implantation process so that the doping concentration of the channel of the first read pass transistor and the doping concentration of the channel of the second read pass transistor are both less than the doping concentration of the channel of the first pull-down transistor and the doping concentration of the channel of the second pull-down transistor.

[0019] In one embodiment, the on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically:

[0020] By reducing the width-to-length ratio of the channel of the first read pass transistor and the width-to-length ratio of the channel of the second read pass transistor, the on-current of the first read pass transistor and the on-current of the second read pass transistor are made smaller than the on-current of the first pull-down transistor and the on-current of the second pull-down transistor.

[0021] An embodiment of the present invention further provides an SRAM memory, comprising the above-mentioned dual-port SRAM unit.

[0022] Compared with the prior art, the embodiments of the present invention have the following beneficial effects: since the on-current of the first write transfer transistor and the on-current of the second write transfer transistor are increased by adjusting the device size parameters, the channel characteristic parameters and / or the gate characteristic parameters, while the on-current of the first pull-up transistor and the on-current of the second pull-up transistor remain unchanged, the alpha ratio of the SRAM (the ratio of the on-current of the pull-up transistor to the on-current of the write transfer transistor) is reduced, and the data writing capability is improved without changing the inherent process of the wafer fab. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0024] Figure 1 A schematic diagram of the structure of a dual-port SRAM unit provided in one embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0026] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0027] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0028] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0029] Figure 1 The structure diagram of the dual-port SRAM unit provided by the preferred embodiment of the present application is shown. For the convenience of explanation, only the part related to the present embodiment is shown, which is described in detail as follows:

[0030] The dual-port SRAM cell includes a first inverter 11, a second inverter 12, a first write pass transistor PG1-1, a second write pass transistor PG1-2, a first read pass transistor PG2-1 and a second read pass transistor PG2-2.

[0031] The first inverter 11 includes a first pull-up transistor PU1 and a first pull-down transistor PD1, the second inverter 12 includes a second pull-up transistor PU2 and a second pull-down transistor PD2, the first write transfer transistor PG1-1 and the first read transfer transistor PG2-1 are both connected to the first inverter 11, and the second write transfer transistor PG1-2 and the second read transfer transistor PG2-2 are both connected to the second inverter 12.

[0032] The on-current of the first write pass transistor PG1 - 1 and the on-current of the second write pass transistor PG1 - 2 are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters.

[0033] Among them, the on-current of the first write transfer transistor PG1-1 and the on-current of the second write transfer transistor PG1-2 are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically, there are the following three situations.

[0034] In the first case, the work function of the gate of the first write transfer transistor PG1-1 and the work function of the gate of the second write transfer transistor PG1-2 are increased through the gate work function modulation process, so that the work function of the gate of the first write transfer transistor PG1-1 and the work function of the gate of the second write transfer transistor PG1-2 are both greater than the work function of the gate of the first pull-up transistor PU1 and the work function of the gate of the second pull-up transistor PU2.

[0035] In a specific implementation, various dopant types and concentrations are used to change the work function of the gate of the first write pass transistor PG1-1 and the work function of the gate of the second write pass transistor PG1-2. For example, the dopant atoms may include arsenic atoms. In addition, different silicide phases may be selected for the gate (by changing the ratio of semiconductor to metal material) to change the work function of the gate. In addition, the work function of the gate may also be changed by changing the metal used to form the silicide.

[0036] By increasing the work function of the gate of the first write transfer transistor PG1-1 and the work function of the gate of the second write transfer transistor PG1-2, the threshold voltage of the first write transfer transistor PG1-1 and the threshold voltage of the second write transfer transistor PG1-2 are reduced, so that the on-current of the first write transfer transistor PG1-1 and the on-current of the second write transfer transistor PG1-2 are increased.

[0037] In the second case, the doping concentration of the channel of the first write transfer transistor PG1-1 and the doping concentration of the channel of the second write transfer transistor PG1-2 are increased by an ion implantation process so that the doping concentration of the channel of the first write transfer transistor PG1-1 and the doping concentration of the channel of the second write transfer transistor PG1-2 are both greater than the doping concentration of the channel of the first pull-up transistor PU1 and the doping concentration of the channel of the second pull-up transistor PU2.

[0038] In a specific implementation, when the first write transfer transistor PG1-1 and the second write transfer transistor PG1-2 are p-type transistors, the doping concentration of the Group IIIA element in the channel of the first write transfer transistor PG1-1 and the doping concentration of the Group IIIA element in the channel of the second write transfer transistor PG1-2 are increased by an ion implantation process; when the first write transfer transistor PG1-1 and the second write transfer transistor PG1-2 are N-type transistors, the doping concentration of the Group VA element in the channel of the first write transfer transistor PG1-1 and the doping concentration of the Group VA element in the channel of the second write transfer transistor PG1-2 are increased by an ion implantation process.

[0039] By increasing the doping concentration of the channel of the first write transfer transistor PG1-1 and the doping concentration of the channel of the second write transfer transistor PG1-2, the threshold voltage of the first write transfer transistor PG1-1 and the threshold voltage of the second write transfer transistor PG1-2 are reduced, so that the on-current of the first write transfer transistor PG1-1 and the on-current of the second write transfer transistor PG1-2 are both increased.

[0040] In the third case, by increasing the width-to-length ratio of the channel of the first write transfer transistor PG1-1 and the width-to-length ratio of the channel of the second write transfer transistor PG1-2, the on-current of the first write transfer transistor PG1-1 and the on-current of the second write transfer transistor PG1-2 are both greater than the on-current of the first pull-up transistor PU1 and the on-current of the second pull-up transistor PU2.

[0041] Since the width-to-length ratio of the transistor channel is proportional to the on-current, when the width-to-length ratio of the channel of the first write transfer transistor PG1-1 and the width-to-length ratio of the channel of the second write transfer transistor PG1-2 increase, the on-current of the first write transfer transistor PG1-1 and the on-current of the second write transfer transistor PG1-2 are increased.

[0042] It should be noted that in the above-mentioned dual-port SRAM cell, the on-current of the first read pass transistor PG2-1 and the on-current of the second read pass transistor PG2-2 can also be reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters.

[0043] Since the on-current of the first read transfer transistor PG2-1 and the on-current of the second read transfer transistor PG2-2 are also reduced through the semiconductor process, and the on-current of the first pull-down transistor PD1 and the on-current of the second pull-down transistor PD2 remain unchanged, the beta ratio of the SRAM (the ratio of the on-current of the pull-down transistor to the on-current of the read transfer transistor) is improved, and the data reading capability is improved without changing the inherent process of the wafer factory.

[0044] Since the on-current of the read transfer transistor and the on-current of the write transfer transistor in the dual-port SRAM cell can be adjusted separately by adding steps in the semiconductor process without increasing the layout area or additional read and write circuits, the power supply voltage of the dual-port SRAM cell can be reduced, thereby further reducing power consumption. At the same time, the minimum voltage test pass rate of the read and write operations is improved, and the process yield will also be greatly improved.

[0045] Among them, the on-current of the first read pass transistor PG2-1 and the on-current of the second read pass transistor PG2-2 are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically, there are the following three situations.

[0046] In the first case, the work function of the gate of the first read transfer transistor PG2-1 and the work function of the gate of the second read transfer transistor PG2-2 are reduced through the gate work function modulation process, so that the work function of the gate of the first read transfer transistor PG2-1 and the work function of the gate of the second read transfer transistor PG2-2 are both smaller than the work function of the gate of the first pull-down transistor PD1 and the work function of the gate of the second pull-down transistor PD2.

[0047] In a specific implementation, various dopant types and concentrations are used to change the work function of the gate of the first read pass transistor PG2 - 1 and the work function of the gate of the second read pass transistor PG2 - 2 . For example, the dopant atoms may include arsenic atoms.

[0048] By reducing the work function of the gate of the first read transfer transistor PG2-1 and the work function of the gate of the second read transfer transistor PG2-2, the threshold voltage of the first read transfer transistor PG2-1 and the threshold voltage of the second read transfer transistor PG2-2 are increased, so that the on-current of the first read transfer transistor PG2-1 and the on-current of the second read transfer transistor PG2-2 are reduced.

[0049] In the second case, the doping concentration of the channel of the first read transfer transistor PG2-1 and the doping concentration of the channel of the second read transfer transistor PG2-2 are reduced by an ion implantation process so that the doping concentration of the channel of the first read transfer transistor PG2-1 and the doping concentration of the channel of the second read transfer transistor PG2-2 are both smaller than the doping concentration of the channel of the first pull-down transistor PD1 and the doping concentration of the channel of the second pull-down transistor PD2.

[0050] In a specific implementation, when the first read transfer transistor PG2-1 and the second read transfer transistor PG2-2 are p-type transistors, the doping concentration of the Group IIIA element in the channel of the first read transfer transistor PG2-1 and the doping concentration of the Group IIIA element in the channel of the second read transfer transistor PG2-2 are reduced by an ion implantation process; when the first read transfer transistor PG2-1 and the second read transfer transistor PG2-2 are N-type transistors, the doping concentration of the Group VA element in the channel of the first read transfer transistor PG2-1 and the doping concentration of the Group VA element in the channel of the second read transfer transistor PG2-2 are reduced by an ion implantation process.

[0051] By reducing the doping concentration of the channel of the first read transfer transistor PG2-1 and the doping concentration of the channel of the second read transfer transistor PG2-2, the threshold voltage of the first read transfer transistor PG2-1 and the threshold voltage of the second read transfer transistor PG2-2 are increased, so that the on-current of the first read transfer transistor PG2-1 and the on-current of the second read transfer transistor PG2-2 are reduced.

[0052] In the third case, by reducing the width-to-length ratio of the channel of the first read pass transistor PG2-1 and the width-to-length ratio of the channel of the second read pass transistor PG2-2, the on-current of the first read pass transistor PG2-1 and the on-current of the second read pass transistor PG2-2 are made smaller than the on-current of the first pull-down transistor PD1 and the on-current of the second pull-down transistor PD2.

[0053] Since the width-to-length ratio of the transistor's channel is proportional to the on-current, when the width-to-length ratio of the channel of the first read pass transistor PG2-1 and the width-to-length ratio of the channel of the second read pass transistor PG2-2 decrease, the on-current of the first read pass transistor PG2-1 and the on-current of the second read pass transistor PG2-2 are reduced.

[0054] An embodiment of the present invention further provides an SRAM memory, comprising the dual-port SRAM unit as described above.

[0055] The embodiment of the present invention includes a first inverter, a second inverter, a first write transfer transistor, a second write transfer transistor, a first read transfer transistor and a second read transfer transistor; the first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor and a second pull-down transistor, the first write transfer transistor and the first read transfer transistor are both connected to the first inverter, and the second write transfer transistor and the second read transfer transistor are both connected to the second inverter; wherein the on-current of the first write transfer transistor and the on-current of the second write transfer transistor are both increased by adjusting the device size parameters, the channel characteristic parameters and / or the gate characteristic parameters; since the on-current of the first write transfer transistor and the on-current of the second write transfer transistor are both increased by adjusting the device size parameters, the channel characteristic parameters and / or the gate characteristic parameters, while the on-current of the first pull-up transistor and the on-current of the second pull-up transistor remain unchanged, the alpha ratio of the SRAM (the ratio of the on-current of the pull-up transistor to the on-current of the write transfer transistor) is reduced, and the data writing capability is improved without changing the inherent process of the wafer factory.

[0056] It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

[0057] The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A dual-port SRAM cell, characterized in that: including a first inverter, a second inverter, a first write pass transistor, a second write pass transistor, a first read pass transistor, and a second read pass transistor; The first inverter includes a first pull-up transistor and a first pull-down transistor, the second inverter includes a second pull-up transistor and a second pull-down transistor, the first write transfer transistor and the first read transfer transistor are both connected to the first inverter, and the second write transfer transistor and the second read transfer transistor are both connected to the second inverter; Among them, the on-current of the first write transfer transistor and the on-current of the second write transfer transistor are increased by adjusting the device size parameters, the channel characteristic parameters and / or the gate characteristic parameters, and the on-current of the first pull-up transistor and the on-current of the second pull-up transistor remain unchanged, thereby reducing the alpha ratio of the SRAM.

2. The dual-port SRAM cell according to claim 1, wherein: The on-current of the first write-transfer transistor and the on-current of the second write-transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically: The work function of the gate of the first write transfer transistor and the work function of the gate of the second write transfer transistor are increased through a gate work function modulation process so that the work function of the gate of the first write transfer transistor and the work function of the gate of the second write transfer transistor are both greater than the work function of the gate of the first pull-up transistor and the work function of the gate of the second pull-up transistor.

3. The dual-port SRAM cell according to claim 1, wherein: The on-current of the first write-transfer transistor and the on-current of the second write-transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically: The doping concentration of the channel of the first write-transfer transistor and the doping concentration of the channel of the second write-transfer transistor are increased by an ion implantation process so that the doping concentration of the channel of the first write-transfer transistor and the doping concentration of the channel of the second write-transfer transistor are both greater than the doping concentration of the channel of the first pull-up transistor and the doping concentration of the channel of the second pull-up transistor.

4. The dual-port SRAM cell according to claim 1, wherein: The on-current of the first write-transfer transistor and the on-current of the second write-transfer transistor are both increased by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically: By increasing the width-to-length ratio of the channel of the first write pass transistor and the width-to-length ratio of the channel of the second write pass transistor, the on-current of the first write pass transistor and the on-current of the second write pass transistor are both greater than the on-current of the first pull-up transistor and the on-current of the second pull-up transistor.

5. The dual-port SRAM cell according to claim 1, wherein: The on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters.

6. The dual-port SRAM cell according to claim 5, wherein: The on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically: The work function of the gate of the first read pass transistor and the work function of the gate of the second read pass transistor are reduced by a gate work function modulation process so that the work function of the gate of the first read pass transistor and the work function of the gate of the second read pass transistor are both smaller than the work function of the gate of the first pull-down transistor and the work function of the gate of the second pull-down transistor.

7. The dual-port SRAM cell according to claim 5, wherein: The on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically: The doping concentration of the channel of the first read pass transistor and the doping concentration of the channel of the second read pass transistor are reduced by an ion implantation process so that the doping concentration of the channel of the first read pass transistor and the doping concentration of the channel of the second read pass transistor are both less than the doping concentration of the channel of the first pull-down transistor and the doping concentration of the channel of the second pull-down transistor.

8. The dual-port SRAM cell according to claim 5, wherein: The on-current of the first read pass transistor and the on-current of the second read pass transistor are both reduced by adjusting device size parameters, channel characteristic parameters and / or gate characteristic parameters. Specifically: By reducing the width-to-length ratio of the channel of the first read pass transistor and the width-to-length ratio of the channel of the second read pass transistor, the on-current of the first read pass transistor and the on-current of the second read pass transistor are made smaller than the on-current of the first pull-down transistor and the on-current of the second pull-down transistor.

9. A SRAM memory, characterized in that: The method comprises a dual-port SRAM cell as claimed in any one of claims 1 to 8.

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