Semiconductor device for selectively performing isolation function and layout replacement method thereof

Abstract

A semiconductor device includes: a substrate including a first active region and a second active region extending along a first direction, the first active region and the second active region being arranged along a second direction perpendicular to the first direction; a first gate electrode extending along the second direction over the first active region and the second active region; a second gate electrode extending along the second direction over the first active region; a third gate electrode extending along the second direction over the second active region; a first source region and a first drain region located on the first active region and on both sides of the first gate electrode; a second source region and a second drain region located on the first active region and on both sides of the second gate electrode; and a third source electrode. A first active region and a third drain region, which are located on the second active region and on both sides of the first gate electrode; a fourth source region and a fourth drain region, which are located on the second active region and on both sides of the third gate electrode; a first wire electrically connected to the first gate electrode; a second wire electrically connected to the second gate electrode, the first source region and the second source region; a third wire electrically connected to the third gate electrode, the third source region and the fourth source region; and a fourth wire electrically connected to the first drain region, the second drain region, the third drain region and the fourth drain region, wherein a first voltage is provided to the second wire, and wherein a second voltage is provided to the third wire.

Description

[0001] This case is a divisional application of the invention patent application filed on January 25, 2017, with application number 201710061158.3 and titled "Semiconductor Device for Selectively Performing Isolation Functions and Layout Alternative Method Thereof".

[0002] Cross-references to related applications

[0003] This application claims priority to U.S. Provisional Patent Application No. 62 / 288,750, filed January 29, 2016 with the U.S. Patent and Trademark Office and Korean Patent Application No. 10-2016-0058860, filed May 13, 2016 with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0004] The apparatus consistent with the exemplary embodiments relates to a semiconductor device, and more specifically to the layout of a semiconductor device that operates selectively as an insulating circuit or a driving circuit. Background Technology

[0005] The size of semiconductor devices is gradually shrinking as they become more integrated and their storage capacity increases. Correspondingly, the resolution of semiconductor manufacturing processes is increasing. However, this increased resolution leads to a reduction in the distance between the gate electrodes of semiconductor devices. In this situation, unintended short circuits or product defects also increase. Consequently, electrical insulation problems are beginning to emerge.

[0006] Typically, insulating films produced by individual processes such as shallow trench isolation (STI) can be used for insulation in semiconductor devices. Alternatively, increasing the distance between gate electrodes or inserting dummy gates can be used for insulation in semiconductor devices. However, this approach is inefficient due to the increased chip size of semiconductor devices and the implementation of additional / further processes. Summary of the Invention

[0007] According to an exemplary embodiment, a system-on-a-chip (SoC) includes: a first semiconductor device including a first transistor and a second transistor, the first transistor and the second transistor respectively including a first gate electrode and a second gate electrode; the first semiconductor device being disposed on an active region disposed on a substrate; the active region extending in a first direction; and the first gate electrode and the second gate electrode extending in a second direction different from the first direction and disposed along the first direction. The SoC further includes a second semiconductor device including a third transistor and a fourth transistor, the third transistor and the fourth transistor respectively including a third gate electrode and a fourth gate electrode; the second semiconductor device being disposed on the active region; and the third gate electrode and the fourth gate electrode extending in the second direction and disposed along the first direction. The second transistor is configured to turn off in response to turning on the first transistor, the third transistor, and the fourth transistor, such that the first transistor is electrically insulated from devices adjacent to the first transistor.

[0008] According to an exemplary embodiment, a semiconductor device includes: an active region disposed on a substrate and extending in a first direction; and a first transistor including a first gate electrode and first source and drain regions disposed on the active region, the first source and drain regions being disposed on opposite sides of the first gate electrode. The semiconductor device further includes a second transistor including a second gate electrode and second source and drain regions disposed on the active region, the second source and drain regions being disposed on opposite sides of the second gate electrode; and a third transistor including a third gate electrode and third source and drain regions disposed on the active region, the third source and drain regions being disposed on opposite sides of the third gate electrode, and the first gate electrode, the second gate electrode, and the third gate electrode extending in a second direction different from the first direction and disposed along the first direction. The second transistor is configured to be turned on and off based on an operating mode of the semiconductor device.

[0009] According to an exemplary embodiment, a semiconductor device includes a first active region and a second active region, the first active region and the second active region extending in a first direction and disposed on a substrate along a second direction different from the first direction; and a first transistor, the first transistor including a first gate electrode and first source and drain regions, the first gate electrode being disposed on the first active region and the second active region and extending in the second direction, and the first source and drain regions being disposed on the first active region and disposed on opposite sides of the first gate electrode. The semiconductor device further includes a second transistor, the second transistor including a second gate electrode and second source and drain regions, the second gate electrode being disposed on the first active region and extending in the second direction, and the second source and drain regions being disposed on the first active region and disposed on opposite sides of the second gate electrode; and a third transistor, the third transistor including a first gate electrode and third source and drain regions, the third source and drain regions being disposed on the second active region and disposed on opposite sides of the first gate electrode. The semiconductor device further includes a fourth transistor, the fourth transistor including a third gate electrode and fourth source and drain regions, the third gate electrode being disposed on the second active region and extending in the second direction, and the fourth source and drain regions being disposed on the second active region and disposed on opposite sides of the third gate electrode. A source or drain region shared by the first and second transistors in the first and second source and drain regions is connected to a source or drain region shared by the third and fourth transistors in the third and fourth source and drain regions, and the second and fourth transistors are configured to be on and off.

[0010] According to an exemplary embodiment, a semiconductor device includes a first active region and a second active region, the first active region and the second active region extending in a first direction and disposed on a substrate along a second direction different from the first direction; and a first transistor, the first transistor including a first gate electrode and first source and drain regions, the first gate electrode being disposed on the first active region and the second active region and extending in the second direction, and the first source and drain regions being disposed on the first active region and disposed on opposite sides of the first gate electrode. The semiconductor device further includes a second transistor, the second transistor including a second gate electrode and second source and drain regions, the second gate electrode being disposed on the first active region and extending in the second direction, and the second source and drain regions being disposed on the first active region and disposed on opposite sides of the second gate electrode; and a third transistor, the third transistor including a first gate electrode and third source and drain regions, the third source and drain regions being disposed on the second active region and disposed on opposite sides of the first gate electrode. The semiconductor device further includes a fourth transistor, the fourth transistor including a second gate electrode and a fourth source and drain region, the fourth source and drain region being disposed on the second active region and disposed on the opposite side of the second gate electrode. A source or drain region shared by the first and second transistors in the first and second source and drain regions is connected to a source or drain region shared by the third and fourth transistors in the third and fourth source and drain regions.

[0011] According to an exemplary embodiment, a semiconductor device includes: a substrate including a first active region and a second active region extending along a first direction, the first active region and the second active region being arranged along a second direction perpendicular to the first direction; a first gate electrode extending over the first active region and the second active region along the second direction; a second gate electrode extending over the first active region along the second direction; a third gate electrode extending over the second active region along the second direction; a first source region and a first drain region located on the first active region and on both sides of the first gate electrode; a second source region and a second drain region located on the first active region and on both sides of the second gate electrode. A third source region and a third drain region are located on the second active region and on both sides of the first gate electrode; a fourth source region and a fourth drain region are located on the second active region and on both sides of the third gate electrode; a first wire electrically connected to the first gate electrode; a second wire electrically connected to the second gate electrode, the first source region, and the second source region; a third wire electrically connected to the third gate electrode, the third source region, and the fourth source region; and a fourth wire electrically connected to the first drain region, the second drain region, the third drain region, and the fourth drain region, wherein a first voltage is provided to the second wire, and wherein a second voltage is provided to the third wire.

[0012] According to an exemplary embodiment, a semiconductor device includes: a substrate including a first active region and a second active region extending along a first direction, the first active region and the second active region being arranged along a second direction perpendicular to the first direction; a first gate electrode extending along the second direction over the first active region and the second active region; a second gate electrode extending along the second direction over the first active region; a third gate electrode extending along the second direction over the second active region; a first source region and a first drain region located on the first active region and on both sides of the first gate electrode; a second source region and a second drain region located on the first active region and on both sides of the second gate electrode; a third source region and a third drain region... A third gate electrode is formed by: a first source region located on the second active region and on both sides of the first gate electrode; a fourth source region and a fourth drain region located on the second active region and on both sides of the third gate electrode; a first wire electrically connected to the first gate electrode; a second wire electrically connected to the second gate electrode; a third wire electrically connected to the first source region and the second source region; a fourth wire electrically connected to the third source region and the fourth source region; a fifth wire electrically connected to the first drain region, the second drain region, the third drain region and the fourth drain region; and a sixth wire electrically connected to the third gate electrode, wherein a first voltage is provided to the third wire, and wherein a second voltage is provided to the fourth wire. Attached Figure Description

[0013] Figure 1 It is a plan view showing the layout of a semiconductor device according to an exemplary embodiment.

[0014] Figure 2 This is a circuit diagram of a semiconductor device in a first operating mode according to an exemplary embodiment.

[0015] Figure 3 This is a circuit diagram of a semiconductor device in a second operating mode according to an exemplary embodiment.

[0016] Figure 4 This is a block diagram illustrating a system-on-a-chip (SOC) according to an exemplary embodiment.

[0017] Figure 5 It is a demonstration Figure 4 A block diagram of one of the first and second static random access memories (SRAMs) shown in the figure.

[0018] Figure 6 It is shown in Figure 4 The image shows a view of the waveforms of the signals during a read operation on the first SRAM.

[0019] Figure 7 It is shown in Figure 4 The image shows a view of the waveforms of the signals during a read operation on the first SRAM.

[0020] Figure 8 yes Figure 5 Detailed circuit diagram of the delay chain circuit.

[0021] Figure 9 It is a demonstration Figure 8 A partial plan view of the layout of the delay chain circuit shown in the figure.

[0022] Figure 10 yes Figure 5 Detailed circuit diagram of the delay chain circuit.

[0023] Figure 11 It is a demonstration Figure 10 A partial plan view of the layout of the delay chain circuit shown in the figure.

[0024] Figure 12 yes Figure 5 Detailed circuit diagram of the delay chain circuit.

[0025] Figure 13 yes Figure 12 The circuit diagram of the delay chain circuit in the first operating mode is shown in the figure.

[0026] Figure 14 yes Figure 12The circuit diagram of the delay chain circuit in the second operating mode is shown in the figure.

[0027] Figure 15 It is a demonstration Figure 12 A partial plan view of the layout of the delay chain circuit shown in the figure.

[0028] Figure 16 yes Figure 5 The detailed circuit diagram of the input / output circuit is shown in the image.

[0029] Figure 17 It is a demonstration Figure 16 A partial plan view of the layout of the drive circuit shown in the figure.

[0030] Figure 18 yes Figure 5 The detailed circuit diagram of the input / output circuit is shown in the image.

[0031] Figure 19 It is a demonstration Figure 18 A partial plan view of the layout of the drive circuit shown in the figure.

[0032] Figure 20 yes Figure 5 Detailed circuit diagram of the input / output circuit.

[0033] Figure 21 It is a demonstration Figure 20 A partial plan view of the layout of the drive circuit shown in the figure. Detailed Implementation

[0034] Figure 1 It is a plan view showing the layout of a semiconductor device according to an exemplary embodiment. Figure 2 This is a circuit diagram of a semiconductor device in a first operating mode according to an exemplary embodiment. Figure 3 This is a circuit diagram of a semiconductor device in a second operating mode according to an exemplary embodiment.

[0035] Reference Figure 1 An active region AR can be formed on a substrate Sub. The active region AR can include the source and drain regions that constitute the transistor, as well as the channel region. For example, the substrate Sub can be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0036] First to third transistors TR1 to TR3 can be formed on the active region AR. For example, the active region AR can be formed to extend in a first direction D1. For example, each of the first to third transistors TR1 to TR3 can be a PMOS or NMOS field-effect transistor (FET). Figure 1For ease of description, it is assumed that the active region AR is an NMOS region, and each of the first to third transistors TR1 to TR3 is an NMOS FET.

[0037] The first to third transistors TR1 to TR3 may include corresponding gate electrodes G1 to G3 formed to extend in the second direction D2, and each of the first to third transistors TR1 to TR3 may include source and drain regions formed on the active region AR and arranged on opposite sides of each gate electrode, as well as a channel region. Figure 1 As shown, the first to third transistors TR1 to TR3 can be connected in series with each other. That is, the first and second transistors TR1 and TR2 can share the source or drain region, and the second and third transistors TR2 and TR3 can share the source or drain region.

[0038] A first input voltage IN1 can be provided to the first gate electrode G1. The first input voltage IN1 or ground voltage VSS can be selectively provided to the second gate electrode G2. For example, the first input voltage IN1 or ground voltage VSS can be provided through the first wire M1. SS Furthermore, a second input voltage IN2 can be applied to the third gate electrode G3. For example, the first and second input voltages IN1 and IN2 can be voltages used to turn on each of the first and third transistors TR1 and TR3. For example, the ground voltage V... SS The voltage may be insufficient to turn on the second transistor TR2. Although the explanation states that ground voltage V is used... SS However, it can use voltages other than ground voltage V. SS The voltage other than that is insufficient to turn on the second transistor TR2.

[0039] As in Figure 1 and Figure 2 As shown, a ground voltage V can be applied to the source or drain region of the first transistor TR1. SS Furthermore, a ground voltage V can be applied to the source or drain region shared by the second and third transistors TR2 and TR3. SS In order to apply ground voltage V SS The second conductor M2 can be arranged as follows: Figure 1 The method shown in the document. However, it is used to provide the ground voltage V. SS The wires are not limited to this.

[0040] Output OUT1, originating from the source or drain region shared by the first and second transistors TR1 and TR2, can be output via the third wire M3. Furthermore, output OUT2, originating from another source or drain region of the third transistor TR3, can be output via the fourth wire M4.

[0041] Because the second transistor TR2 is selectively turned on or off based on the voltage (or signal) input to the second gate electrode G2, the function of the second transistor TR2 can be altered. For example, by applying a ground voltage V to the second gate electrode G2... SS When the second transistor TR2 is turned off, it can act as an isolator, in which the first and third transistors TR1 and TR3 are electrically insulated from each other. Conversely, when the second transistor TR2 is turned on by applying the first input voltage IN1 to the second gate electrode G2, it can act as a driver to increase the driving force of the semiconductor device.

[0042] For example, Figure 2 and Figure 3 The multiplexer MUX shown can be selectively used as both an insulator and a driver. (See reference...) Figure 1 and Figure 2 During the first operating mode, the multiplexer MUX can select the ground voltage V. SS This is the voltage applied to the second gate electrode G2. Therefore, because the second transistor TR2 is disconnected, it can act as an isolator to electrically isolate the first and second transistors TR1 and TR2 from each other. For example, a multiplexer MUX can be controlled by a separate control signal.

[0043] In addition, refer to Figure 1 and Figure 3 During the second operating mode, the multiplexer MUX can select a first input voltage IN1 (e.g., the power supply voltage) as the voltage applied to the second gate electrode G2. Therefore, the second transistor TR2 is turned on, and thus the second transistor TR2 can act as a driver to increase the driving force of the semiconductor device. Figure 1 , Figure 2 and Figure 3 In an exemplary embodiment, a first operating mode and a second operating mode are selectively executed via a multiplexer (MUX). However, according to an exemplary embodiment, in a semiconductor device, circuitry for executing the first operating mode and circuitry for executing the second operating mode can be implemented simultaneously. (Refer to...) Figure 4 And to describe this.

[0044] Figure 4 This is a block diagram illustrating a System-on-a-Chip (SOC) according to an exemplary embodiment. (Refer to...) Figure 4 The SOC 100 may include a first static random access memory (SRAM) 110 and a second SRAM 120.

[0045] The first SRAM 110 and the second SRAM 120 can perform substantially the same function as each other. However, the first SRAM 110 is larger in size than the second SRAM 120. More specifically, the number of bit lines connected to the sense amplifier circuit of the first SRAM 110 is greater than the number of bit lines connected to the sense amplifier circuit of the second SRAM 120.

[0046] For example, as described above, the first SRAM 110 may be included in reference Figure 1 and Figure 2 The semiconductor device that performs a function (e.g., insulating layer function) in the first operating mode described herein. Conversely, the second SRAM 120 may be included in reference... Figure 1 and Figure 3 The semiconductor device described performs a function (e.g., a driver function) in the second operating mode.

[0047] Thus, although the first SRAM 110 performs the same function as the second SRAM 120, the first and second SRAMs 110 and 120 can perform different operating modes based on their size and purpose, thereby improving the insulation and driving force of the SRAM.

[0048] Figure 5 It is a demonstration Figure 4 A block diagram of one of the first SRAM 110 and the second SRAM 120 is shown. (Refer to...) Figure 5 The SRAM 200 may include an SRAM cell array 210, a sense amplifier circuit 220, an address (ADDR) decoder 230, control logic 240, and input / output (I / O) circuitry 250.

[0049] SRAM cell array 210 may include SRAM cells connected to multiple bit lines BL and multiple word lines WL. Each SRAM cell in the SRAM array can be accessed via word lines and bit lines. Each SRAM cell in the SRAM array may be connected to bit line pairs BL and / BL based on word line voltage. Each SRAM cell may include latching circuitry and a turn-on transistor that receives the word line voltage as a gate voltage. During sensing operation, the voltage of the bit line pairs BL and / BL, which are pre-charged according to data stored in the latching circuitry, may change. Data can be sensed by sensing the changing voltage.

[0050] The sense amplifier circuit 220 may include a plurality of sense amplifiers (S / A) 221 to 22n. Bit line pairs BL and / BL may be connected to each of the sense amplifiers. During sensing operation, each of the sense amplifiers can sense data by sensing voltage fluctuations in the bit line pairs BL and / BL.

[0051] Address decoder 230 can decode address ADDR received from an external device in order to select any one bit line or any combination thereof from multiple bit lines WL.

[0052] Control logic 240 can control the overall operation of SRAM 200. For example, control logic 240 can send a sense amplifier enable signal SAE received from input / output circuit 250 to sense amplifier circuit 220. For example, control logic 240 may include a delay chain circuit 242 that delays the sense amplifier enable signal IN_SAE received from input / output circuit 250 so as to output a delayed sense amplifier enable signal OUT_SAE.

[0053] Input / output circuitry 250 can exchange input / output (I / O) data (e.g., write or read data) with external devices (e.g., controllers). Input / output circuitry 250 can send the address received from the external device to address decoder 230. Input / output circuitry 250 can send the sense amplifier enable signal (SAE) received from the external device to control logic 240.

[0054] Reference Figure 5 During a read operation on SRAM 200, the word line WL of SRAM cell array 210 can be activated by address decoder 230, and one of the bit line pairs BL and / BL can be discharged based on the data stored in the SRAM cell. Subsequently, when sense amplifier circuit 220 is activated by sense amplifier enable signal SAE, the voltage difference between bit line pairs BL and / BL can be amplified by sense amplifier circuit 220. That is, there is a sufficient interval between the time when the word line WL of SRAM cell array 210 is activated and the time when sense amplifier circuit 220 is activated by sense amplifier enable signal SAE. This interval can hereafter be referred to as the "WL-SAE interval".

[0055] Figure 6 It is shown in Figure 4 The image shows a view of the waveforms of the signals during a read operation of the first SRAM 110. Figure 7 It is shown in Figure 4 The image shows a waveform view of the signals during a read operation of the second SRAM 120. (Refer to...) Figure 6 and Figure 7 The discharge of bit line BL begins at time point t1 when activation of word line WL begins. Furthermore, the sense amplifier enable signal SAE is activated at the end of activation of word line WL. That is, the sense amplifier enable signal SAE is activated at time point t2 when bit line BL is fully discharged.

[0056] Reference Figure 4 , Figure 5 and Figure 6 The description pertains to the read operation on the first SRAM 110. In the relatively large first SRAM 110, the WL to SAE intervals t1 to t3 can be relatively long. More specifically, the WL to SAE interval can become longer as the number of SRAM cells connected to the bit line pairs BL and / or BL (which are connected to each of the sense amplifiers in the sense amplifiers S / A of the sense amplifier circuit 220) increases. This is because a relatively long time is used to discharge the SRAM cells during the read operation on the SRAM 200. To perform this function, a delay chain circuit 242 is used to increase the delay of the sense amplifier enable signal SAE.

[0057] Reference Figure 4 , Figure 5 and Figure 7 The description pertains to the read operation on the second SRAM 120. In the relatively small second SRAM 120, the WL to SAE intervals t1 to t3 can be relatively short. More specifically, the WL to SAE interval can become shorter as the number of SRAM cells connected to the bit line pairs BL and / or BL (which are connected to each of the sense amplifiers in the sense amplifiers S / A of the sense amplifier circuit 220) decreases. This is because a relatively short time is used to discharge the SRAM cells during the read operation on the SRAM 200. To perform this function, a delay chain circuit 242 is used to reduce the delay of the sense amplifier enable signal SAE.

[0058] As described above, the WL to SAE interval may vary depending on the SRAM configuration (e.g., the number of SRAM cells connected to the bit lines). Accordingly, refer to Figures 1 to 3 The described semiconductor device can be used to implement a delay chain circuit 242 that adjusts the WL to SAE interval taking into account the configuration of the SRAM. (See also...) Figures 8 to 15 To describe this in more detail.

[0059] Figure 8 yes Figure 5 Detailed circuit diagram of the delay chain circuit 242. For example, in Figure 8 The delay chain circuit 300 shown in the figure can be Figure 4 The first SRAM 110 shown here has a relatively large size. For aiding understanding, reference will be made to... Figure 5 , Figure 6 and Figure 8 The exemplary embodiments are described.

[0060] The delay chain circuit 300 may include a delay chain block 310 and an isolation circuit 320. The delay chain block 310 may include a plurality of inverters 311 to 314 connected in series with each other. In an exemplary embodiment, the delay chain block 310 includes four inverters. However, the exemplary embodiment is not limited to this. The isolation circuit 320 may include a plurality of isolators 321 to 324. Again, in an exemplary embodiment, the isolation circuit 320 includes four isolators. However, the exemplary embodiment is not limited to this.

[0061] Delay chain block 310 can receive an input signal for outputting a delayed input signal. For example, delay chain block 310 can receive a sense amplifier enable signal IN_SAE from input / output circuit 250 to output a delayed sense amplifier enable signal OUT_SAE. For example, the sense amplifier enable signal IN_SAE can be delayed by t2–t1 using delay chain block 310. For example, each inverter in the inverter constituting delay chain block 310 can be implemented using PMOS transistors and NMOS transistors. However, the configuration of delay chain block 310 is not limited to this.

[0062] Each isolator in the isolator constituting the isolation circuit 320 can be implemented using PMOS and NMOS transistors. For example, the isolators can be connected to inverters respectively. For example, the output terminal of the first isolator 321 can be connected to the output terminal of the first inverter 311. The output terminal of the second isolator 322 can be connected to the output terminal of the second inverter 312. The output terminals of the third and fourth isolators 323 and 324 can also be connected in a similar manner to the output terminals of the first and second isolators.

[0063] A power supply voltage V can be applied to one end of each of the PMOS transistors constituting the isolation circuit 320. DD Furthermore, a ground voltage V can be applied to one end of each of the NMOS transistors constituting the isolation circuit 320. SS Furthermore, a power supply voltage V can be applied to the gate terminal of each of the PMOS transistors constituting the isolation circuit 320. DD Furthermore, a ground voltage V can be applied to the gate terminal of each of the NMOS transistors constituting the isolation circuit 320. SS Therefore, the PMOS and NMOS transistors constituting the isolation circuit 320 can be disconnected, and the isolation circuit 320 can thus electrically insulate the delay chain block 310 from other circuits adjacent to the delay chain block 310.

[0064] Figure 9 It is a demonstration Figure 8 This is a plan view of a portion of the layout of the delay chain circuit 300 shown. In an exemplary embodiment, Figure 9 The layout of the first inverter 311 and the first isolator 321 of the delay chain circuit 300 is shown.

[0065] To aid understanding, refer to Figure 8 and Figure 9 A first active region AR1 and a second active region AR2 can be formed on a substrate. For example, the first active region AR1 and the second active region AR2 can extend in a first direction D1 and can be arranged along a second direction D2 perpendicular to the first direction D1. Each of the first and second active regions AR1 and AR2 can include source and drain regions and a channel region for forming the corresponding transistor. For example, the substrate Sub can be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0066] First and second transistors TR1 and TR2 can be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 can be a PMOS FET.

[0067] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in a second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on a first active region AR1 and arranged on opposite sides of each of the gate electrodes G1 and G2, as well as a channel region. Figure 9 As shown, the first and second transistors TR1 and TR2 can be connected in series with each other. That is, the first and second transistors TR1 and TR2 can share the source or drain region.

[0068] The third and fourth transistors TR3 and TR4 can be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 can be an NMOS FET.

[0069] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions, as well as channel regions, formed on the second active region AR2 and arranged on opposite sides of each gate electrode in gate electrodes G1 and G3. That is, the second and fourth transistors TR2 and TR4 may not share a gate electrode (e.g., the second gate electrode G2). Figure 9 As shown, the third and fourth transistors TR3 to TR4 can be connected in series. That is, the third and fourth transistors TR3 and TR4 can share the source or drain regions.

[0070] A sense amplifier enable signal IN_SAE can be applied to the first gate electrode G1. A power supply voltage V can be applied to the second gate electrode G2. DD In addition, a ground voltage V can be applied to the third gate electrode G3. SS For example, a sense amplifier enable signal IN_SAE can be applied to the first gate electrode G1 via the first wire M1. For example, a power supply voltage V can be applied to the second gate electrode G2 via the second wire M2. DD For example, a ground voltage V can be applied to the third gate electrode G3 through the third conductor M3. SS For example, the grounding voltage V SS The voltage may be insufficient to turn on the third transistor TR3. However, a voltage other than ground V can be used. SS The voltage other than that is insufficient to turn on a certain voltage of the third transistor TR3.

[0071] A power supply voltage V can be applied to the source or drain region of the first transistor TR1. DD Furthermore, a power supply voltage V can be applied to the source or drain region of the second transistor TR2. DD A ground voltage V can be applied to the source or drain region of the third transistor TR3. SS Furthermore, a ground voltage V can be applied to the source or drain region of the fourth transistor TR4. SS .

[0072] For example, a power supply voltage V can be applied to the first and second transistors TR1 and TR2 via the second wire M2. DD For example, a ground voltage V can be applied to the third and fourth transistors TR3 and TR4 through the third wire M3. SS However, the voltage V applied to the power supply... DD and ground voltage V SS The configuration is not limited to this.

[0073] The output signal OUT_SAE from the source or drain region shared by the first and second transistors TR1 and TR2 can be output via the fourth wire M4. The output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 can also be output via the fourth wire M4. However, in an exemplary embodiment, the first isolator 321, including the second and fourth transistors TR2 and TR4, can be kept in an off state. Accordingly, the signal output via the fourth wire M4 can be the signal output from the first inverter 311, including the first and third transistors TR1 and TR3.

[0074] According to reference Figure 9The described layout and bias conditions, including the first isolator 321 of the second and fourth transistors TR2 and TR4, can electrically isolate the first inverter 311 from another device. For example, the first isolator 321 can electrically isolate the first inverter 311 from a transistor including a fourth gate electrode G4.

[0075] By placing it properly Figure 9 The layout shown in the figure can be used to implement the delay chain circuit 300 as follows: Figure 8 As shown in the diagram. Since the outputs of the first inverter 311 and the first isolator 321 are used as the inputs of the second inverter 312, suitable wiring for this configuration can be used, and its detailed description will not be repeated here.

[0076] According to the use of Figure 9 The delay chain circuit 300 implemented using the layout shown does not require a separate device for electrical isolation, nor does it require increasing the distance between the gate electrodes. Insulating devices can be implemented by using layout placement and adjusting bias conditions, thereby improving regional efficiency and insulation performance.

[0077] Figure 10 yes Figure 5 Detailed circuit diagram of the delay chain circuit 242. For example, in Figure 10 The delay chain circuit 400 shown in the figure can be Figure 4 The second SRAM 120 shown here has a relatively small size. For aiding understanding, reference will be made to... Figure 5 , Figure 7 and Figure 10 To describe an exemplary embodiment.

[0078] The delay chain circuit 400 may include a delay chain block 410 and a driver circuit 420. The delay chain block 410 may include a plurality of inverters 411 to 414 connected in series with each other. In an exemplary embodiment, the delay chain block 410 includes four inverters. However, the exemplary embodiment is not limited thereto. The driver circuit 420 may include a plurality of drivers 421 to 424. Again, in an exemplary embodiment, the driver circuit 420 includes four drivers. However, the exemplary embodiment is not limited thereto.

[0079] Delay chain block 410 can receive an input signal for outputting a delayed input signal. For example, delay chain block 410 can receive a sense amplifier enable signal IN_SAE to output a delayed sense amplifier enable signal OUT_SAE. For example, the sense amplifier enable signal IN_SAE can be delayed by (t2–t1) using delay chain block 410. However, the delay time of delay chain block 410 can be shorter than the delay time of delay chain block 310 (see reference). Figure 8For example, PMOS transistors and NMOS transistors can be used to implement each inverter in the inverters that make up the delay chain block 410.

[0080] Each driver in the driver constituting the drive circuit 420 can be implemented using PMOS and NMOS transistors. For example, the drivers can be connected in parallel to the inverters. For example, the input and output terminals of the first driver 421 can be connected to the input and output terminals of the first inverter 411, respectively. The input and output terminals of the second to fourth drivers 422 to 424 can also be connected in a similar manner to those of the first driver 421.

[0081] A power supply voltage V can be applied to the input terminal of the inverter constituting the drive circuit 420. DD Therefore, the drive circuit 420 can improve the driving capability of the delay chain block 410. That is, the delay time of the delay chain block 410 can become relatively short.

[0082] Figure 11 It is a demonstration Figure 10 This is a plan view of a portion of the layout of the delay chain circuit 400 shown. In an exemplary embodiment, Figure 11 The layout of the first inverter 411 and the first driver 421 of the delay chain circuit 400 is shown in the figure.

[0083] To aid understanding, refer to Figure 10 and Figure 11 First and second active regions AR1 and AR2 can be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0084] First and second transistors TR1 and TR2 can be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 can be a PMOS FET.

[0085] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in a second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on a first active region AR1 and arranged on opposite sides of each of the gate electrodes G1 and G2, as well as a channel region. Figure 11 As shown, the first and second transistors TR1 and TR2 can be connected in series with each other. That is, the first and second transistors TR1 and TR2 can share the source or drain region.

[0086] The third and fourth transistors TR3 and TR4 can be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 can be an NMOS FET.

[0087] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions, and a channel region, formed on the second active region AR2 and arranged on opposite sides of each gate electrode in gate electrodes G1 and G2. Figure 11 As shown, the third and fourth transistors TR3 to TR4 can be connected in series with each other. That is, the third transistor TR3 can share the gate electrode G1 with the first transistor TR1, and the fourth transistor TR4 can share the gate electrode G2 with the second transistor TR2. In addition, the third and fourth transistors TR3 and TR4 can share the source or drain regions.

[0088] A sense amplifier enable signal IN_SAE can be applied to the first and second gate electrodes G1 and G2. For example, the sense amplifier enable signal IN_SAE can be applied to the first and second gate electrodes G1 and G2 through the first wire M1.

[0089] A power supply voltage V can be applied to the source or drain region of the first transistor TR1. DD Furthermore, a power supply voltage V can be applied to the source or drain region of the second transistor TR2. DD A ground voltage V can be applied to the source or drain region of the third transistor TR3. SS Furthermore, a ground voltage V can be applied to the source or drain region of the fourth transistor TR4. SS .

[0090] For example, a power supply voltage V can be applied to the first and second transistors TR1 and TR2 via the second wire M2. DD For example, a ground voltage V can be applied to the third and fourth transistors TR3 and TR4 through the third wire M3. SS However, the voltage V applied to the power supply... DD and ground voltage V SS The configuration is not limited to this.

[0091] The output signal OUT_SAE from the source or drain region shared by the first and second transistors TR1 and TR2 can be output via the fourth wire M4. The output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 can also be output via the fourth wire M4.

[0092] According to reference Figure 11 The described layout and bias conditions, including the first driver 421 for the second and fourth transistors TR2 and TR4, can improve the driving capability of the first inverter 411. That is, the delay time of delay chain block 410 can be shorter than the delay time of delay chain block 310 (see reference). Figure 8 ).

[0093] By placing it properly Figure 11 The layout shown in the figure can implement the delay chain circuit 400 as follows: Figure 10 As shown in the diagram. Because the outputs of the first inverter 411 and the first driver 421 are used as the inputs of the second inverter 412, suitable wiring for this configuration can be used. Therefore, its detailed description will not be repeated here.

[0094] As mentioned above, from Figure 9 and Figure 11 The understanding is that the aforementioned semiconductor devices performing different functions have similar layouts. That is to say, Figure 9 The isolation circuit 320 can electrically isolate the delay chain block 310 from another device, and Figure 11 The drive circuit 420 can reduce the delay time of the delay chain block 410 (i.e., the WL to SAE interval). This can be determined based on the bias conditions and whether the second and fourth transistors TR2 and TR4 share a gate electrode. Figure 9 isolator 320 and Figure 11 The differences between the drive circuits 420.

[0095] According to reference Figures 8 to 11 In the exemplary embodiment described, the devices that differentially affect delay chain blocks 310 and 410 can be implemented by using substantially the same layout but only by differentially adjusting the bias conditions. Therefore, devices that improve regional efficiency, insulation performance, or drive capability can be selectively used depending on the SRAM configuration.

[0096] Figure 12 yes Figure 5 Detailed circuit diagram of the delay chain circuit 242. For example, in Figure 12 The delay chain circuit 500 shown in the diagram can be Figure 4 One of the first and second SRAMs, 110 and 120, is shown in the image. For aiding understanding, reference will be made to... Figure 5 , Figure 6 , Figure 7 and Figure 12 To describe an exemplary embodiment.

[0097] The delay chain circuit 500 may include a delay chain block 510, an auxiliary block 520, and a multiplexing circuit 530. The delay chain block 510 may include a plurality of inverters 511 to 514 connected in series with each other. In an exemplary embodiment, the delay chain block 510 includes four inverters. However, the exemplary embodiment is not limited thereto. The auxiliary block 520 may include first to fourth auxiliary blocks 521 to 524. Similarly, in an exemplary embodiment, the delay chain circuit 500 includes four auxiliary blocks. However, the exemplary embodiment is not limited thereto.

[0098] Delay chain block 510 can receive an input signal for outputting a delayed input signal. For example, delay chain block 510 can receive a sense amplifier enable signal IN_SAE to output a delayed sense amplifier enable signal OUT_SAE. For example, the sense amplifier enable signal IN_SAE can be delayed by (t2–t1) using delay chain block 510. For example, each inverter in the inverter constituting delay chain block 510 can be implemented using PMOS transistors and NMOS transistors.

[0099] Each of the first to fourth auxiliary blocks 521 to 524 may include a PMOS transistor and an NMOS transistor connected in series with each other. A power supply voltage V can be applied to one end of the PMOS transistor. DD Furthermore, a ground voltage V can be applied to one end of the NMOS transistor. SS Furthermore, the output terminal between the PMOS transistor and the NMOS transistor can be connected to the output terminal of the first inverter 511 corresponding to it.

[0100] The first multiplexer MUX1 can be connected to the gate electrode of the PMOS transistors constituting the first to fourth auxiliary blocks 521 to 524. Furthermore, the second multiplexer MUX2 can be connected to the gate electrode of the NMOS transistors constituting the first to fourth auxiliary blocks 521 to 524. The first multiplexer MUX1 can select the sense amplifier enable signal IN_SAE and the power supply voltage V under the control of an external device. DD One of them. Furthermore, the second multiplexer MUX2 can select the sense amplifier enable signal IN_SAE and the ground voltage V under the control of an external device. SS one.

[0101] Figure 13 yes Figure 12 The circuit diagram of the delay chain circuit 500 in the first operating mode is shown. During the first operating mode, the first multiplexer MUX1 can be controlled based on the control signal CTRL, the sense amplifier enable signal IN_SAE, and the power supply voltage V. DD Select power supply voltage V DDFurthermore, during the first operating mode, the second multiplexer MUX2 can be controlled based on the control signal CTRL, the sense amplifier enable signal IN_SAE, and the ground voltage V. SS Select grounding voltage V SS In this case, the transistor constituting auxiliary block 520 can be disconnected, and thus auxiliary block 520 can electrically insulate delay chain block 510 from another device. This electrical insulation function can be similar to that described in the reference. Figure 8 The descriptions that have been described and therefore repeated will not be repeated here.

[0102] Figure 14 yes Figure 12 The circuit diagram of the delay chain circuit 500 in the second operating mode is shown in the figure. During the second operating mode, the first multiplexer MUX1 can be controlled based on the control signal CTRL, the sense amplifier enable signal IN_SAE, and the power supply voltage V. DD The sense amplifier enable signal IN_SAE is selected during this process. Furthermore, during the second operating mode, the second multiplexer MUX2 can select the sense amplifier enable signal IN_SAE and the ground voltage V based on the control signal CTRL. SS When the sense amplifier enable signal IN_SAE is selected, the transistors constituting auxiliary block 520 can be turned on, and thus auxiliary block 520 can act as a driver to enhance the driving capability of delay chain block 510. This driver function can be similar to that of reference [reference missing]. Figure 10 The descriptions that have been described and therefore repeated will not be repeated here.

[0103] Based on the above, the operating mode can be selected according to the control signal from the external device. For example, to maintain a longer WL to SAE interval for the SRAM, the delay chain circuit 500 can enter the first operating mode based on the control signal CTRL. In this case, the auxiliary block 520 can operate as an isolation circuit; the WL to SAE interval of the SRAM may be affected by the delay chain block 510. Conversely, to maintain a shorter WL to SAE interval for the SRAM, the delay chain circuit 500 can enter the first operating mode based on the control signal CTRL. In this case, because the auxiliary block 520 operates as an isolation circuit, the WL to SAE interval of the SRAM may be reduced due to the increased drive capability through the auxiliary block 520.

[0104] Figure 15 It is a demonstration Figure 12 This is a plan view of a portion of the layout of the delay chain circuit 500 shown. In an exemplary embodiment, Figure 15 The layout of the first inverter 511 and the first auxiliary block 521 of the delay chain circuit 500 is shown in the figure.

[0105] To aid understanding, refer to Figure 12 and Figure 15 First and second active regions AR1 and AR2 can be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0106] First and second transistors TR1 and TR2 can be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 can be a PMOS FET.

[0107] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in a second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on a first active region AR1 and arranged on opposite sides of each of the gate electrodes G1 and G2, as well as a channel region. Figure 15 As shown, the first and second transistors TR1 and TR2 can be connected in series. That is, the first and second transistors TR1 and TR2 can share the source or drain region.

[0108] The third and fourth transistors TR3 and TR4 can be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 can be an NMOS FET.

[0109] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions, as well as channel regions, formed on the second active region AR2 and arranged on opposite sides of each gate electrode in gate electrodes G1 and G3. Figure 15 As shown, the third and fourth transistors TR3 to TR4 can be connected in series. That is, the fourth transistor TR4 can be independent of the gate electrode of the second transistor TR2. Furthermore, the third and fourth transistors TR3 and TR4 can share the source or drain regions.

[0110] A sense amplifier enable signal IN_SAE can be applied to the first gate electrode G1. For example, the sense amplifier enable signal IN_SAE can be applied to the first gate electrode G1 through the first wire M1.

[0111] The sense amplifier enable signal IN_SAE or the power supply voltage V can be selectively applied to the second gate electrode G2. DDFor example, the first multiplexer MUX1 can selectively apply a power supply voltage V to the second gate electrode G2 based on a control signal from an external device. DD For example, a sense amplifier enable signal IN_SAE or a power supply voltage V can be applied to the second gate electrode G2 via the second wire M2. DD .

[0112] A power supply voltage V can be applied to the source or drain region of the first transistor TR1. DD Furthermore, a power supply voltage V can be applied to the source or drain region of the second transistor TR2. DD A ground voltage V can be applied to the source or drain region of the third transistor TR3. SS Furthermore, a ground voltage V can be applied to the source or drain region of the fourth transistor TR4. SS .

[0113] For example, a power supply voltage V can be applied to the first and second transistors TR1 and TR2 via the third wire M3. DD For example, a ground voltage V can be applied to the third and fourth transistors TR3 and TR4 via the fourth wire M4. SS However, the voltage V applied to the power supply... DD and ground voltage V SS The configuration is not limited to this.

[0114] The output signal OUT_SAE from the source or drain region shared by the first and second transistors TR1 and TR2 can be output via the fifth wire M5. Furthermore, the output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 can also be output via the fifth wire M5. However, when the delay chain circuit 500 operates in the first operating mode, the auxiliary block 520 can operate as an isolation circuit. Therefore, the output from the second and fourth transistors TR2 and TR4 may be missing.

[0115] According to the reference Figure 13 The described layout and bias conditions select the function of auxiliary block 520. For example, when delay chain circuit 500 operates in the first operating mode, a power supply voltage V can be applied to the second conductor M2. DD And a grounding voltage V can be applied to the sixth conductor M6. SS Therefore, the auxiliary block 521, which includes the second transistor TR2 and the fourth transistor TR4, can electrically isolate the first inverter 311, which includes the first transistor TR1 and the third transistor TR3, from another device.

[0116] In contrast, when the delay chain circuit 500 operates in the second operating mode, a sense amplifier enable signal IN_SAE can be applied to the second conductor M2, and a sense amplifier enable signal IN_SAE can also be applied to the sixth conductor M6. Therefore, the auxiliary block 521, including the second and fourth transistors TR2 and TR4, can operate electrically as a driver that enhances the driving capability of the first inverter 511, including the first and third transistors TR1 and TR3.

[0117] The operating mode of the delay chain circuit 500 can be selected based on the SRAM configuration (e.g., the number of SRAMs connected to bit line pairs BL and / or BL), thereby improving the SRAM's regional efficiency, insulation performance, or drive capability. Furthermore, the reliability of the SRAM can be enhanced.

[0118] As described above, the layout of a semiconductor device that adjusts the WL-SAE interval of SRAM based on the operating mode has been presented. However, semiconductor devices that perform different functions based on the operating mode can also be used as drive circuits for driving loads. For example, Figure 5 The input / output circuit 250 shown can be a driver circuit, see reference. Figures 16 to 21 To describe it in more detail.

[0119] Figure 16 It is a display Figure 5 The circuit diagram of the input / output circuit 250 is shown in the image. For example, in... Figure 16 The input / output circuit 600 shown in the diagram can be Figure 4 The input / output circuitry for the second SRAM 120 is shown in the diagram. That is, it can be used when the load quantity is relatively small (i.e., when the SRAM size is relatively small). Figure 16 The input / output circuit 600 shown in the figure.

[0120] The input / output circuit 600 may include a driver circuit 610 and a load circuit 620. The driver circuit 610 may include an inverter 611 and an isolator 613. The load circuit 620 may include multiple loads 621 to 62n. For example, the driver circuit 610, which receives the input signal IN, may output an output signal OUT. Furthermore, each of the loads connected to the load circuit 620 may be driven by the output signal OUT to output data.

[0121] The isolator 613 may include a PMOS transistor and an NMOS transistor. A power supply voltage V can be applied to one end of the PMOS transistor. DD Furthermore, a ground voltage V can be applied to one end of the NMOS transistor. SS A power supply voltage V can be applied to the gate terminal of the PMOS transistor. DDFurthermore, a ground voltage V can be applied to the gate terminal of the NMOS transistor. SS Therefore, the transistors constituting the isolation circuit 613 can be disconnected, and thus the isolation circuit 613 can electrically insulate the inverter 611 from other circuits adjacent to the inverter 611.

[0122] Figure 17 It is a demonstration Figure 16 The diagram shows a partial layout of the delay chain circuit 610. For aiding understanding, refer to... Figure 16 and Figure 17 First and second active regions AR1 and AR2 can be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0123] First and second transistors TR1 and TR2 can be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 can be a PMOS FET.

[0124] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in a second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged on opposite sides of each gate electrode, as well as a channel region. Figure 17 As shown, the first and second transistors TR1 and TR2 can be connected in series. That is, the first and second transistors TR1 and TR2 can share the source or drain region.

[0125] The third and fourth transistors TR3 and TR4 can be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 can be an NMOS FET.

[0126] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions, as well as channel regions, formed on the second active region AR2 and arranged on opposite sides of each gate electrode in gate electrodes G1 and G3. That is, the second and fourth transistors TR2 and TR4 may not share a gate electrode. Figure 17As shown, the third and fourth transistors TR3 to TR4 can be connected in series. That is, the third and fourth transistors TR3 and TR4 can share the source or drain regions.

[0127] An input voltage IN can be provided to the first gate electrode G1. A power supply voltage V can be applied to the second gate electrode G2. DD In addition, a ground voltage V can be applied to the third gate electrode G3. SS For example, an input signal IN can be applied to the first gate electrode G1 via the first wire M1. For example, a power supply voltage VDD can be applied to the second gate electrode G2 via the second wire M2. For example, a ground voltage V can be applied to the third gate electrode G3 via the third wire M3. SS .

[0128] A power supply voltage V can be applied to the source or drain region of the first transistor TR1. DD Furthermore, a power supply voltage V can be applied to the source or drain region of the second transistor TR2. DD A ground voltage V can be applied to the source or drain region of the third transistor TR3. SS Furthermore, a ground voltage V can be applied to the source or drain region of the fourth transistor TR4. SS .

[0129] For example, a power supply voltage V can be applied to the first and second transistors TR1 and TR2 via the second wire M2. DD For example, a ground voltage V can be applied to the third and fourth transistors TR3 and TR4 through the third wire M3. SS However, the voltage V applied to the power supply... DD and ground voltage V SS The configuration is not limited to this.

[0130] The output signal OUT from the source or drain region shared by the first and second transistors TR1 and TR2 can be output via the fourth wire M4. Furthermore, the output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 can be output via the fourth wire M4. However, in an exemplary embodiment, the isolator 613, including the second transistor TR2 and the fourth transistor TR4, can be kept in the off state. Accordingly, the signal output via the fourth wire M4 can be the signal output from the inverter 611, including the first transistor TR1 and the third transistor TR3.

[0131] According to reference Figure 17The described layout and bias conditions, including isolator 613 for the second transistor TR2 and the fourth transistor TR4, can electrically isolate inverter 611 from another device. For example, isolator 613 can electrically isolate inverter 611 from a transistor including a fourth gate electrode G4.

[0132] Figure 18 It is a display Figure 5 The circuit diagram of the input / output circuit 250 is shown in the image. For example, in... Figure 18 The input / output circuit 700 shown in the diagram can be Figure 4 The input / output circuitry of the first SRAM 110 is shown in the diagram. That is, it can be used when the load quantity is relatively large (i.e., when the SRAM size is relatively large). Figure 18 The input / output circuit 700 shown in the figure.

[0133] The input / output circuit 700 may include a drive circuit 710 and a load circuit 720. The drive circuit 710 may include an inverter 711 and a driver 713. The load circuit 720 may include multiple loads 721 to 72n. For example, Figure 18 The number of loads 721 to 72n shown in the diagram can be greater than [a certain number]. Figure 16 The number of loads 621 to 62n shown in the figure.

[0134] The driver 713 may include a PMOS transistor and an NMOS transistor. A power supply voltage V can be applied to one end of the PMOS transistor. DD Furthermore, a ground voltage V can be applied to one end of the NMOS transistor. SS An input signal IN can be applied to the gate terminals of both the PMOS and NMOS transistors. Therefore, the driver 713 can improve the driving capability of the driving circuit 710. On the other hand, even if the number of loads 721 to 72n is relatively large, it is still possible to ensure that the driving capability is sufficient to drive the loads 721 to 72n.

[0135] Figure 19 It is a demonstration Figure 18 The diagram shows a partial layout of the delay chain circuit 710. For aiding understanding, refer to... Figure 18 and Figure 19 First and second active regions AR1 and AR2 can be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0136] First and second transistors TR1 and TR2 can be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 can be a PMOS FET.

[0137] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in a second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on a first active region AR1 and arranged on opposite sides of each of the gate electrodes G1 and G2, as well as a channel region. Figure 17 As shown, the first and second transistors TR1 and TR2 can be connected in series. That is, the first and second transistors TR1 and TR2 can share the source or drain region.

[0138] The third and fourth transistors TR3 and TR4 can be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 can be an NMOS FET.

[0139] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G2 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions, and a channel region, formed on the second active region AR2 and arranged on opposite sides of each gate electrode in gate electrodes G1 and G2. Figure 19 As shown, the third and fourth transistors TR3 to TR4 can be connected in series. That is, the third and fourth transistors TR3 and TR4 can share the source or drain regions.

[0140] Input signals IN can be applied to the first and second gate electrodes G1 and G2. A power supply voltage V can be applied to the second gate electrode G2. DD For example, an input signal IN can be applied to the first and second gate electrodes G1 and G2 via the first wire M1.

[0141] A power supply voltage V can be applied to the source or drain region of the first transistor TR1. DD Furthermore, a power supply voltage V can be applied to the source or drain region of the second transistor TR2. DD A ground voltage V can be applied to the source or drain region of the third transistor TR3. SS Furthermore, a ground voltage V can be applied to the source or drain region of the fourth transistor TR4. SS .

[0142] For example, a power supply voltage V can be applied to the first and second transistors TR1 and TR2 via the second wire M2.DD For example, a ground voltage V can be applied to the third and fourth transistors TR3 and TR4 through the third wire M3. SS However, the voltage V applied to the power supply... DD and ground voltage V SS The configuration is not limited to this.

[0143] The output signal OUT from the source or drain region shared by the first and second transistors TR1 and TR2 can be output via the fourth wire M4. Furthermore, the output signal OUT_SAE from the source or drain region shared by the third and fourth transistors TR3 and TR4 can be output via the fourth wire M4.

[0144] According to reference Figure 19 The described layout and bias conditions, including the driver 713 for the second and fourth transistors TR2 and TR4, can improve the driving capability of the drive circuit 710.

[0145] As mentioned above, refer to Figure 17 and Figure 19 Semiconductor devices performing different functions are described, but it should be understood that their layouts are similar to each other. That is to say, Figure 17 The isolator 613 can electrically isolate the inverter 711 from another device, and Figure 19 The driver 713 can improve the driving capability of the drive circuit 710. Figure 17 isolator 613 and Figure 19 The differences between the drivers 713 can be in the bias conditions and whether the second and fourth transistors TR2 and TR4 share a gate electrode.

[0146] According to reference Figures 16 to 19 In the exemplary embodiment shown, devices that have different effects on the drive circuit 710 can be implemented by using substantially the same layout but only by adjusting the bias conditions. Therefore, devices that improve regional efficiency, insulation performance, or drive capability can be selectively used depending on the configuration of the SRAM.

[0147] Figure 20 yes Figure 5 Detailed circuit diagram of the input / output circuit 250. For example, in Figure 20 The input / output circuit 800 shown in the diagram can be Figure 4 One of the first SRAM 110 and the second SRAM 120 shown. The input / output circuit 800 may include a driver circuit 810, a load circuit 820, and a multiplexing circuit 830.

[0148] The drive circuit 810 may include an inverter 811 and an auxiliary circuit 813. The load circuit 820 may include multiple loads 821 to 82n. The drive circuit 810 may receive an input signal IN to output an output signal OUT. The inverter 811 and the auxiliary circuit 813 of the drive circuit 810 may have output terminals that are connected to each other.

[0149] A power supply voltage V can be applied to one end of the PMOS transistor. DD Furthermore, a ground voltage V can be applied to one end of the NMOS transistor. SS The gate terminal of the PMOS transistor in the auxiliary circuit 813 can be connected to the output terminal of the first multiplexer MUX1, and the gate terminal of the NMOS transistor in the auxiliary circuit 813 can be connected to the output terminal of the second multiplexer MUX2.

[0150] The first multiplexer MUX1 can select the input signal IN and the power supply voltage V based on the control signal CTRL from the external device. DD One of them. Furthermore, the second multiplexer MUX2 can select the input signal IN and the ground voltage V based on the control signal CTRL from an external device. SS one.

[0151] For example, during the first operating mode, the first multiplexer MUX1 can select the power supply voltage V under the control of the control signal CTRL. DD Furthermore, the second multiplexer MUX2 can select the ground voltage V under the control of the control signal CTRL. SS Therefore, the auxiliary circuit 813 can operate as an isolator electrically isolating the inverter 811 from another device. Because the auxiliary circuit 813 operates as an isolator, the initial drive capability of the drive circuit 810 can be maintained as intended. Accordingly, the operation of the input / output circuit 800 in the first operating mode can be relatively adapted to the second SRAM 120 (see reference). Figure 4 ).

[0152] In contrast, during the second operating mode, the first and second multiplexers MUX1 and MUX2 can select the input signal IN under the control signal CTRL. Therefore, the auxiliary circuit 813 can operate as a driver to enhance the driving capability of the driving circuit 810. Because the auxiliary circuit 813 operates as a driver, the initial driving capability of the driving circuit 810 can be enhanced. Accordingly, the operation of the input / output circuit 800 in the second operating mode can be relatively adapted to the first SRAM 110 (see reference). Figure 4 ).

[0153] Figure 21 It is a demonstration Figure 20This is a plan view of a portion of the layout of the input / output circuitry 800 shown. In an exemplary embodiment, Figure 21 The layout of the inverter 811 and auxiliary circuit 813 of the input / output circuit 800 is shown in the figure.

[0154] To aid understanding, refer to Figure 20 and Figure 21 First and second active regions AR1 and AR2 can be formed on a substrate. Each of the first and second active regions AR1 and AR2 may include source and drain regions and a channel region for forming a transistor. For example, the substrate Sub may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate.

[0155] First and second transistors TR1 and TR2 can be formed on the first active region AR1. For example, each of the first and second transistors TR1 and TR2 can be a PMOS FET.

[0156] The first and second transistors TR1 and TR2 may include corresponding gate electrodes G1 and G2 formed to extend in a second direction D2, and each of the first and second transistors TR1 and TR2 may include source and drain regions formed on the first active region AR1 and arranged on opposite sides of each gate electrode, as well as a channel region. Figure 21 As shown, the first and second transistors TR1 and TR2 can be connected in series. That is, the first and second transistors TR1 and TR2 can share the source or drain region.

[0157] The third and fourth transistors TR3 and TR4 can be formed on the second active region AR2. For example, each of the third and fourth transistors TR3 and TR4 can be an NMOS FET.

[0158] The third and fourth transistors TR3 and TR4 may include corresponding gate electrodes G1 and G3 formed to extend in the second direction D2, and each of the third and fourth transistors TR3 and TR4 may include source and drain regions, as well as channel regions, formed on the second active region AR2 and arranged on opposite sides of each gate electrode. Figure 21 As shown, the third and fourth transistors TR3 to TR4 can be connected in series. That is, the fourth transistor TR4 can be independent of the gate electrode of the second transistor TR2. Furthermore, the third and fourth transistors TR3 and TR4 can share the source or drain regions.

[0159] An input voltage IN can be provided to the first gate electrode G1. For example, an input signal IN can be applied to the first gate electrode G1 through the first wire M1.

[0160] An input signal IN or a power supply voltage V can be selectively applied to the second gate electrode G2. DD For example, the first multiplexer MUX1 can selectively apply a power supply voltage V to the second gate electrode G2 based on the control signal CTRL from an external device. DD For example, an input signal IN or a power supply voltage V can be applied to the second gate electrode G2 via the second wire M2. DD .

[0161] A power supply voltage V can be applied to the source or drain region of the first transistor TR1. DD Furthermore, a power supply voltage V can be applied to the source or drain region of the second transistor TR2. DD A ground voltage V can be applied to the source or drain region of the third transistor TR3. SS Furthermore, a ground voltage V can be applied to the source or drain region of the fourth transistor TR4. SS .

[0162] For example, a power supply voltage V can be applied to the first and second transistors TR1 and TR2 via the third wire M3. DD For example, a ground voltage V can be applied to the third and fourth transistors TR3 and TR4 via the fourth wire M4. SS However, the voltage V applied to the power supply... DD and ground voltage V SS The configuration is not limited to this.

[0163] The output signal OUT from the source or drain region shared by the first and second transistors TR1 and TR2 can be output via the fifth wire M5. Similarly, the output signal OUT from the source or drain region shared by the third and fourth transistors TR3 and TR4 can be output via the fifth wire M5. However, when the input / output circuit 800 operates in the first operating mode, the auxiliary circuit 813 can operate as an isolator. Therefore, the output from the second and fourth transistors TR2 and TR4 may be missing.

[0164] Can be based on reference Figure 21 The described layout and bias conditions select the function of the auxiliary circuit 813. For example, when the input / output circuit 800 operates in the first operating mode, a power supply voltage V can be applied to the second conductor M2. DD And a grounding voltage V can be applied to the sixth conductor M6. SSTherefore, the auxiliary circuit 813, which includes the second and fourth transistors TR2 and TR4, can electrically isolate the inverter 811, which includes the first and third transistors TR1 and TR3, from another device.

[0165] In contrast, when the input / output circuit 800 operates in the second operating mode, an input signal IN can be applied to the second wire M2 and an input signal IN can be applied to the sixth wire M6. Therefore, the auxiliary circuit 813, including the second and fourth transistors TR2 and TR4, can operate electrically as a driver that improves the driving capability of the inverter 811, including the first and third transistors TR1 and TR3.

[0166] As mentioned above, in reference Figures 17 to 21 In the exemplary embodiments described, the configuration and operation of the SRAM input / output circuitry can be described. However, referring to... Figures 17 to 21 The exemplary embodiments described are not limited thereto and can be used as drive circuits configured to drive multiple loads. For example, the exemplary embodiments can also be used as input / output circuits for flash memory devices, input / output circuits for display panels, and so on.

[0167] The operating mode of the input / output circuit 800 can be selected based on the SRAM configuration (e.g., the number of loads), thereby improving the SRAM's area efficiency, insulation performance, or drive capability. Furthermore, the reliability of the SRAM can be enhanced.

[0168] Exemplary embodiments provide layouts for semiconductor devices that selectively operate as insulating circuits or driving circuits.

[0169] According to an exemplary embodiment, the regional efficiency, insulation performance, or driving capability of a semiconductor device can be improved.

[0170] As is customary in the field of inventive conception, exemplary embodiments are described and illustrated in the accompanying drawings in the form of functional blocks, units, and / or modules. Those skilled in the art will recognize that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry (e.g., logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc.), which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or the like, they can be programmed using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. Alternatively, each block, unit, and / or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing certain functions and a processor (e.g., one or more programmable microprocessors and associated circuitry) for performing other functions. Furthermore, without departing from the scope of the inventive conception, each block, unit, and / or module of the exemplary embodiments may be physically separated into two or more interacting and discrete blocks, units, and / or modules. Furthermore, without departing from the scope of the inventive concept, the blocks, units, and / or modules of the exemplary embodiments can be physically combined into more complex blocks, units, and / or modules.

[0171] Those skilled in the art will recognize that various changes and modifications can be made to the exemplary embodiments described herein without departing from the scope and spirit of the inventive concept. The inventive concept is considered to include such modifications and variations of the exemplary embodiments if such modifications fall within the scope of the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: The substrate includes a first active region and a second active region extending along a first direction, the first active region and the second active region being arranged along a second direction perpendicular to the first direction. The first gate electrode extends along a second direction over the first active region and the second active region; The second gate electrode extends over the first active region along a second direction; The third gate electrode extends along the second direction over the second active region; The first source region and the first drain region are located on the first active region and on both sides of the first gate electrode. The second source region and the second drain region are located on the first active region and on both sides of the second gate electrode. The third source region and the third drain region are located on the second active region and on both sides of the first gate electrode. The fourth source region and the fourth drain region are located on the second active region and on both sides of the third gate electrode. A first wire is electrically connected to a first gate electrode; The second wire is electrically connected to the second gate electrode, the first source region, and the second source region; The third wire is electrically connected to the third gate electrode, the third source region, and the fourth source region; and The fourth wire is electrically connected to the first drain region, the second drain region, the third drain region, and the fourth drain region. The first voltage is supplied to the second wire, and The second voltage is supplied to the third conductor.

2. The semiconductor device according to claim 1, wherein, An input signal is provided to the first conductor.

3. The semiconductor device according to claim 2, wherein, The semiconductor device is SRAM, and The input signal is the enable signal for the inductive amplifier.

4. The semiconductor device according to claim 1, wherein, The first active region is a PMOS region, and The second active region is an NMOS region.

5. The semiconductor device according to claim 1, wherein, The first gate electrode, the first source region, and the first drain region include a first transistor. The second gate electrode, the second source region, and the second drain region include a second transistor. The first gate electrode, the third source region, and the third drain region include a third transistor. The third gate electrode, the fourth source region, and the fourth drain region include a fourth transistor. Wherein, the first drain region and the second drain region are shared by the first transistor and the second transistor, and The third drain region and the fourth drain region are shared by the third transistor and the fourth transistor.

6. The semiconductor device according to claim 1, wherein, The first wire is electrically connected to the first gate electrode through the first through-hole. The second wire is electrically connected to each of the second gate electrode, the first source region, and the second source region through the second via. The third conductor is electrically connected to each of the third gate electrode, the third source region, and the fourth source region through a third via. The fourth wire is electrically connected to the first drain region, the second drain region, the third drain region and the fourth drain region through the fourth through hole.

7. The semiconductor device according to claim 1, wherein, The substrate includes at least one of a silicon substrate, a germanium substrate, and a silicon-on-insulator (SOI) substrate.

8. A semiconductor device, comprising: The substrate includes a first active region and a second active region extending along a first direction, the first active region and the second active region being arranged along a second direction perpendicular to the first direction. The first gate electrode extends along a second direction over the first active region and the second active region; The second gate electrode extends over the first active region along a second direction; The third gate electrode extends along the second direction over the second active region; The first source region and the first drain region are located on the first active region and on both sides of the first gate electrode. The second source region and the second drain region are located on the first active region and on both sides of the second gate electrode. The third source region and the third drain region are located on the second active region and on both sides of the first gate electrode. The fourth source region and the fourth drain region are located on the second active region and on both sides of the third gate electrode. A first wire is electrically connected to a first gate electrode; The second wire is electrically connected to the second gate electrode; The third conductor is electrically connected to the first source region and the second source region; The fourth wire is electrically connected to the third source region and the fourth source region; The fifth wire is electrically connected to the first drain region, the second drain region, the third drain region, and the fourth drain region; The sixth wire is electrically connected to the third gate electrode. The first voltage is supplied to the third wire, and The second voltage is supplied to the fourth wire.

9. The semiconductor device according to claim 8, wherein, An input signal is provided to the first wire. In the first operating mode, a first voltage is supplied to the second wire and a second voltage is supplied to the sixth wire. In the second operating mode, the input signal is provided to the second wire and the sixth wire.

10. The semiconductor device according to claim 9, wherein, The semiconductor device is SRAM, and The input signal is the enable signal for the inductive amplifier.

11. The semiconductor device according to claim 8, wherein, The first active region is a PMOS region, and The second active region is an NMOS region.

12. The semiconductor device according to claim 8, wherein, The first gate electrode, the first source region, and the first drain region include a first transistor. The second gate electrode, the second source region, and the second drain region include a second transistor. The first gate electrode, the third source region, and the third drain region include a third transistor. The third gate electrode, the fourth source region, and the fourth drain region include a fourth transistor. Wherein, the first drain region and the second drain region are shared by the first transistor and the second transistor, and The third drain region and the fourth drain region are shared by the third transistor and the fourth transistor.

13. The semiconductor device according to claim 8, wherein, The first wire is electrically connected to the first gate electrode through the first through-hole. The second wire is electrically connected to the second gate electrode through the second through-hole; The third conductor is electrically connected to each of the first source region and the second source region through a third through-hole; The fourth wire is electrically connected to each of the third source region and the fourth source region through the fourth through hole; The fifth conductor is electrically connected to the first drain region, the second drain region, the third drain region, and the fourth drain region through a fifth through-hole. The sixth wire is electrically connected to the third gate electrode through the sixth through-hole.

14. The semiconductor device according to claim 8, wherein, The substrate includes at least one of a silicon substrate, a germanium substrate, and a silicon-on-insulator (SOI) substrate.

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