Preparation method of radio frequency chip and structure thereof
By fabricating a protective layer and a sputtering layer on the wafer, and electroplating metal bumps of different sizes in stages to achieve the same height, the problems of poor soldering and chip cracking caused by differences in the size and height of the metal bumps are solved, and the thinning of radio frequency chips is realized.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NINGBO CHIPEX SEMICON
- Filing Date
- 2022-05-17
- Publication Date
- 2026-07-07
Smart Images
Figure CN114937613B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of chip fabrication technology, and in particular to a method for fabricating a radio frequency chip and its structure. Background Technology
[0002] Wafer bumping is a key technology in wafer-level packaging. The prototype of bumping was the solder balls required for flip chips. Flip chips, to a certain extent, replaced wire bonding packaging, laying the foundation for various subsequent packaging forms. Compared to traditional wire bonding packaging, flip chips have the following advantages: 1. They can reduce parasitic capacitance caused by wires, which is beneficial for increasing frequency and improving thermal effects; 2. The process is relatively simple and the cost is relatively low; 3. Flip chips can reduce package size, achieving chip-scale packaging. The height uniformity of the metal bumps within the chip is particularly important for flip chip quality. Poor height uniformity can lead to soldering defects such as cold solder joints, directly affecting chip performance and causing product scrap. The height uniformity of the metal bumps between different chips within the wafer also has a significant impact on the subsequent polishing process. Large height differences will affect the polishing effect.
[0003] With the development of wafer manufacturing processes, chip sizes are becoming smaller and smaller, and with the increasing demands for product functionality, the density of input / output (I / O) on the chip surface is becoming higher and higher. Due to multiple considerations regarding chip space and product electrical performance, designs for metal bumps of different sizes, based on the different functions of pins within a single chip, are increasingly being used and developed. However, in actual production, due to the different sizes of the metal bumps, the greater the difference in the size of the electroplated metal bumps, the greater the difference in the height of the metal bumps. When the height difference of the metal bumps exceeds the process capability of flip-chip technology, it will cause solder joint defects, rendering the chip unusable. Furthermore, in the development of new products, it is often necessary to design multiple new products on a single wafer for verification to shorten the development cycle. However, if multiple chips on a single wafer require different metal bump sizes, the height of the metal bumps between the chips will differ after reflow. For chips distributed in different areas, if the metal bumps in one area are lower than those in another area, this will affect the bonding effect. Vacuum leaks are common at lower positions of the metal bumps, causing the wafer attached to the grinding film to fail to adhere to the platform, or resulting in poor adhesion and movement during grinding, leading to wafer cracking. Furthermore, lower metal bumps are essentially suspended during grinding, failing to provide effective support. This uneven stress will affect the grinding effect on the back side and the uniformity of the grinding thickness, and the suspended areas are at risk of cracking under pressure.
[0004] To address the aforementioned issues, existing solutions propose reducing the size of large metal bumps while increasing the size of small metal bumps to narrow the size difference and thus reduce the height difference. However, this approach reduces chip performance; for example, reducing the size of large metal bumps requiring high current will weaken their current-carrying capacity. Existing solutions also propose increasing the height of the metal bumps to reduce the relative height difference. However, this approach has drawbacks: increasing the height increases the final chip package thickness, which does not meet the growing demand for lighter, thinner, shorter, and smaller chips. Furthermore, excessive solder can easily overflow onto the copper pillars during flip-chip bonding, potentially causing short circuits. Summary of the Invention
[0005] This application provides a method for fabricating an RF chip and its structure, which can reduce the height difference of metal bumps, reduce the possibility of chip cracking caused by large height differences between metal bumps during polishing, reduce the possibility of poor soldering during flip chip fabrication, and reduce chip thickness.
[0006] This application provides a method for fabricating an radio frequency chip, including:
[0007] Obtain the wafer to be prepared; the wafer to be prepared includes the area to be prepared and the area to be electroplated; the area to be electroplated includes pads of different sizes;
[0008] A protective layer is prepared in the area to be prepared on the wafer to be prepared;
[0009] A sputtering layer is prepared on the wafer to be prepared, such that the sputtering layer covers the protective layer and the area to be electroplated;
[0010] A photoresist layer is prepared on the sputtered layer;
[0011] The photoresist layer is electroplated based on the target height to obtain the metal bumps corresponding to the current electroplating process; the target height characterizes the height of the metal bumps pre-plated on the wafer to be prepared.
[0012] Multiple metal bumps corresponding to multiple electroplating processes are reflowed to obtain an RF chip; the RF chip includes multiple metal bumps of different sizes but the same height.
[0013] Further, a protective layer is prepared in the region to be prepared on the wafer, including:
[0014] The area to be fabricated on the wafer is coated with adhesive, exposed, developed, and cured to form a protective layer.
[0015] Further, a sputtering layer is prepared on the wafer to be prepared, such that the sputtering layer covers the protective layer and the area to be electroplated, including:
[0016] A first metal layer is prepared on the wafer to be prepared, such that the first metal layer covers the protective layer and the area to be electroplated;
[0017] A second metal layer is prepared on the first metal layer to obtain a sputtered layer.
[0018] Furthermore, the first metal layer is made of titanium, and the second metal layer is made of copper.
[0019] Further, a photoresist layer is fabricated on the sputtered layer, including:
[0020] The sputtered layer is coated with adhesive, exposed, and developed to form a photoresist layer on the sputtered layer.
[0021] Furthermore, the photoresist layer is electroplated based on the target height to obtain the metal bumps corresponding to the current electroplating process, including:
[0022] Electroplating is performed on the photoresist layer to obtain the copper pillar corresponding to the current electroplating process.
[0023] The copper pillar is electroplated to form a tin cap, resulting in a metal bump corresponding to the current electroplating process; the difference between the height of the copper pillar and the total height of the tin cap and the target height is within a preset difference range.
[0024] Furthermore, the area to be electroplated includes a first area to be electroplated and a second area to be electroplated, wherein the size of the pads in the first area to be electroplated is larger than the size of the pads in the second area to be electroplated.
[0025] A sputtering layer is fabricated on the wafer to be prepared, such that the sputtering layer covers the protective layer and the area to be electroplated, including:
[0026] A sputtering layer is prepared on the wafer to be prepared, such that the sputtering layer covers the protective layer, the first electroplating area and the second electroplating area;
[0027] Fabricating a photoresist layer on a sputtered layer includes:
[0028] A first photoresist layer is prepared on the sputtered layer corresponding to the first area to be electroplated;
[0029] Based on the target height, the photoresist layer is electroplated to obtain the metal bumps corresponding to the current electroplating process, including:
[0030] The first photoresist layer is electroplated based on the target height to obtain the first metal bump corresponding to the current electroplating process.
[0031] Furthermore, after electroplating the photoresist layer based on the target height to obtain the metal bump corresponding to the current electroplating process, the process also includes:
[0032] A second photoresist layer is prepared on the sputtered layer corresponding to the second area to be electroplated;
[0033] The second photoresist layer is electroplated based on the target height to obtain the second metal bump; the height of the first metal bump is equal to the height of the second metal bump.
[0034] Accordingly, embodiments of this application provide a structure for a radio frequency chip, including:
[0035] The wafer to be prepared includes the area to be prepared and the area to be electroplated; the area to be electroplated includes pads of different sizes.
[0036] Multiple metal bumps are set on the wafer to be prepared corresponding to the pads; the metal bumps have different sizes but the same height.
[0037] Furthermore, each metal bump includes a copper pillar and a tin cap disposed on the copper pillar;
[0038] The copper pillars in each metal bump are of equal height, and the tin caps in each metal bump are of equal height.
[0039] The embodiments of this application have the following beneficial effects:
[0040] This application discloses a method and structure for fabricating an RF chip, including obtaining a wafer to be fabricated; the wafer to be fabricated includes a region to be fabricated and a region to be electroplated; the region to be electroplated includes pads of different sizes; a protective layer is fabricated on the region to be fabricated of the wafer; a sputtering layer is fabricated on the wafer to be fabricated, such that the sputtering layer covers the protective layer and the region to be electroplated; a photoresist layer is fabricated on the sputtering layer; the photoresist layer is electroplated based on a target height to obtain metal bumps corresponding to the current electroplating process; the target height characterizes the height of the pre-plated metal bumps on the wafer to be fabricated; multiple metal bumps corresponding to multiple electroplating processes are reflowed to obtain an RF chip; the RF chip includes multiple metal bumps of different sizes but the same height. Based on this application, by electroplating metal bumps stepwise according to the size of the pads, the height difference of the metal bumps can be reduced, thereby reducing the possibility of chip cracking and poor soldering during flip-chip fabrication caused by large height differences between metal bumps during polishing, as well as reducing the chip thickness. Attached Figure Description
[0041] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0042] Figure 1 This is a schematic flowchart of a method for fabricating an radio frequency chip according to an embodiment of this application;
[0043] Figure 2 This is a schematic diagram of the fabrication process of an radio frequency chip provided in an embodiment of this application;
[0044] Figure 3 This is a schematic diagram of the structure of a wafer to be prepared according to an embodiment of this application;
[0045] Figure 4 This is a schematic diagram of the structure of an radio frequency chip provided in an embodiment of this application. Detailed Implementation
[0046] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely one embodiment of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0047] The term "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of the embodiments of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data used can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "comprising," "having," and "being," and any variations thereof, are intended to cover non-exclusive inclusion.
[0048] The following describes a specific embodiment of a method for fabricating an radio frequency chip according to this application. Figure 1 This is a schematic flowchart illustrating a method for fabricating an radio frequency chip according to an embodiment of this application. Figure 2 This is a schematic diagram of the fabrication process of an RF chip provided in an embodiment of this application. This specification provides the method operation steps as shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one of many execution orders and does not represent the only execution order. In actual execution, the methods shown in the embodiments or drawings can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment).
[0049] Specifically, such asFigure 1 As shown, the fabrication method of this radio frequency chip may include:
[0050] S101: Obtain the wafer to be prepared; the wafer to be prepared includes the area to be prepared and the area to be electroplated; the area to be electroplated includes pads of different sizes.
[0051] In this embodiment of the application, before fabricating the radio frequency chip, multiple test wafers can be taken and metal bumps can be electroplated on different test wafers using different photomasks. The electroplating time and current density required to electroplat metal bumps of target height on pads of different sizes can be obtained to establish the electroplating process required for metal bumps of different sizes to reach the target height.
[0052] In this embodiment, the wafer to be fabricated may contain one type of single chip or multiple single chips. The dimensions of the pads on the chips within the wafer may be partially identical, with the remaining dimensions differing. Alternatively, the dimensions of all the pads on the chips within the wafer may be different. The shape of the pads on the chips within the wafer may be rectangular, circular, or elliptical. The formation of the pads on the chips within the wafer may be partially identical, with the remaining dimensions differing. Alternatively, the formation of all the pads on the chips within the wafer may be identical. Alternatively, the shapes of all the pads on the chips within the wafer may be different. Figure 3 This is a schematic diagram of a wafer to be fabricated according to an embodiment of this application. The area to be electroplated may include a first area to be electroplated and a second area to be electroplated. The size of the pads in the first area to be electroplated is larger than the size of the pads in the second area to be electroplated. The shape of the pads in the first area to be electroplated can be the same as the shape of the pads in the second area to be electroplated, both being rectangular.
[0053] S103: Prepare a protective layer in the area to be prepared on the wafer to be prepared.
[0054] In this embodiment, the area to be fabricated on the wafer to be fabricated can be coated with adhesive, exposed, developed, and cured to form a protective layer on the area. Optionally, a PI protective layer can be formed on the area to be fabricated on the wafer. This PI protective layer has openings that expose the pads of the area to be electroplated, so as to ensure that individual chips in the wafer can be electrically connected.
[0055] S105: Prepare a sputtering layer on the wafer to be prepared, such that the sputtering layer covers the protective layer and the area to be electroplated.
[0056] In this embodiment, a sputtering layer can be fabricated on the wafer to be prepared after the protective layer is prepared, such that the sputtering layer covers both the protective layer and the area to be electroplated. For example, the sputtering layer can cover... Figure 3 The protective layer, the first electroplating area, and the second electroplating area on the wafer to be prepared are shown.
[0057] In one optional embodiment, a first metal layer can be fabricated on the wafer to be prepared, such that the first metal layer covers the protective layer and the area to be electroplated. Then, a second metal layer can be fabricated on the first metal layer to obtain the sputtered layer. The material of the first metal layer can be titanium (Ti), and the material of the second metal layer can be copper (Cu). The material of the sputtered layer can also be other commonly used sputtering layer materials such as gold or tungsten; this embodiment does not specifically limit the materials used.
[0058] S107: Prepare a photoresist layer on the sputtered layer.
[0059] In this embodiment, the wafer to be fabricated after the sputtering layer is completed can be coated with adhesive, exposed, and developed to form a photoresist layer on the sputtering layer. Optionally, a first photoresist layer can be fabricated on the sputtering layer corresponding to the first area to be electroplated.
[0060] In one alternative embodiment, the first photoresist layer has an opening at the sputtering layer corresponding to the small-sized pad, the size of which is equal to the size of the small-sized pad, and the first photoresist layer can cover the sputtering layer corresponding to the large-sized pad.
[0061] S109: Electroplating is performed on the photoresist layer based on the target height to obtain the metal bumps corresponding to the current electroplating process; the target height characterizes the height of the metal bumps pre-plated on the wafer to be prepared.
[0062] In this embodiment, after fabricating the photoresist layer, the photoresist layer can be electroplated based on an electroplating procedure established on a test wafer to obtain a copper pillar corresponding to the current electroplating process. Then, the copper pillar can be electroplated to form a tin cap, resulting in a metal bump corresponding to the current electroplating process. The difference between the height of the copper pillar and the total height of the tin cap and the target height can be within a preset range.
[0063] In one optional implementation, the first photoresist layer can be electroplated based on a target height to obtain a first metal bump corresponding to the current electroplating process. Then, the resist and the first photoresist layer can be removed. Next, a second photoresist layer can be prepared on the sputtered layer corresponding to the second area to be electroplated by applying resist, exposure, and development. This second photoresist layer may have an opening at the sputtered layer corresponding to the large-size pad, the size of which is equal to the size of the large-size pad. The second photoresist layer can cover the sputtered layer corresponding to the small-size pad. Then, the second photoresist layer can be electroplated based on a target height to obtain a second metal bump. The height of the first metal bump can be equal to the height of the second metal bump. Next, the resist and the second photoresist layer can be removed, and the sputtered layer can be etched.
[0064] S111: Reflow processing is performed on multiple metal bumps corresponding to multiple electroplating processes to obtain an RF chip; the RF chip includes multiple metal bumps of different sizes but the same height.
[0065] In this embodiment, the tin caps of multiple metal bumps corresponding to multiple electroplating processes can be reflowed to form a spherical shape, thus obtaining an RF chip.
[0066] The radio frequency chip fabrication method provided in this application can reduce the height difference of the metal bumps by electroplating metal bumps in steps according to the size of the pads. This reduces the possibility of chip cracking caused by large height differences between metal bumps during polishing, as well as the possibility of poor soldering during flip chip fabrication and chip thickness.
[0067] This application also provides a structure for an radio frequency chip. Figure 4 This is a schematic diagram of the structure of a radio frequency chip provided in an embodiment of this application, as shown below. Figure 4 As shown, the structure of the RF chip may include a wafer 401 to be fabricated and multiple metal bumps 403. The wafer 401 may include a fabrication area and a plating area, the plating area including pads 405 of different sizes. Each of the multiple metal bumps may be disposed on the plating area corresponding to the pad; the metal bumps have different sizes but the same height.
[0068] In this embodiment, each metal bump includes a copper pillar 407 and a tin cap 409 disposed on the copper pillar 407. The copper pillars 407 in each metal bump have the same height, and the tin caps 409 in each metal bump have the same height.
[0069] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, while this specification describes specific embodiments, other embodiments are also within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in the order shown in different embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific order or sequence of connections to achieve the desired results; in some implementations, parallel processing of multiple tasks is possible or may be advantageous.
[0070] The various embodiments in this specification are described in a progressive manner. The same or similar parts between the various embodiments can be referred to each other. The focus of each embodiment is to describe the differences from other embodiments.
[0071] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.
Claims
1. A method for fabricating a radio frequency chip, characterized in that, include: Obtain a wafer to be prepared; the wafer to be prepared includes a region to be prepared and a region to be electroplated; the region to be electroplated includes pads of different sizes; A protective layer is prepared in the region to be prepared on the wafer to be prepared; A sputtering layer is formed on the wafer to be prepared, such that the sputtering layer covers the protective layer and the area to be electroplated; A photoresist layer is prepared on the sputtered layer; The photoresist layer is electroplated based on the target height to obtain the metal bumps corresponding to the current electroplating process; the target height represents the height of the metal bumps pre-plated on the wafer to be prepared. Multiple metal bumps corresponding to multiple electroplating processes are reflowed to obtain an RF chip; the RF chip includes multiple metal bumps of different sizes but the same height; The area to be electroplated includes a first area to be electroplated and a second area to be electroplated, wherein the pads in the first area to be electroplated and the pads in the second area to be electroplated have different sizes. Accordingly, the step of fabricating a photoresist layer on the sputtered layer and electroplating the photoresist layer based on a target height to obtain a metal bump corresponding to the current electroplating process includes: fabricating a first photoresist layer on the sputtered layer corresponding to the first area to be electroplated; electroplating the first photoresist layer based on the target height to obtain a first metal bump corresponding to the current electroplating process; fabricating a second photoresist layer on the sputtered layer corresponding to the second area to be electroplated; electroplating the second photoresist layer based on the target height to obtain a second metal bump; the height of the first metal bump is equal to the height of the second metal bump.
2. The preparation method according to claim 1, characterized in that, The step of preparing a protective layer in the region to be prepared on the wafer to be prepared includes: The area to be prepared on the wafer to be prepared is subjected to coating, exposure, development and curing processes to form a protective layer on the area to be prepared on the wafer to be prepared.
3. The preparation method according to claim 1, characterized in that, The step of fabricating a sputtering layer on the wafer to be prepared, such that the sputtering layer covers the protective layer and the area to be electroplated, includes: A first metal layer is formed on the wafer to be prepared, such that the first metal layer covers the protective layer and the area to be electroplated; A second metal layer is prepared on the first metal layer to obtain the sputtered layer.
4. The preparation method according to claim 3, characterized in that, The first metal layer is made of titanium, and the second metal layer is made of copper.
5. The preparation method according to claim 1, characterized in that, The process of fabricating a photoresist layer on the sputtered layer includes: The sputtered layer is coated with adhesive, exposed, and developed to form the photoresist layer on the sputtered layer.
6. The preparation method according to claim 1, characterized in that, The electroplating process of the photoresist layer based on the target height to obtain the metal bump corresponding to the current electroplating process includes: The photoresist layer is electroplated to obtain the copper pillar corresponding to the current electroplating process; The copper pillar is electroplated to form a tin cap, resulting in a metal bump corresponding to the current electroplating process; the difference between the height of the copper pillar and the total height of the tin cap and the target height is within a preset difference range.
7. The preparation method according to claim 1, characterized in that, The size of the pads in the first area to be electroplated is larger than the size of the pads in the second area to be electroplated. The step of fabricating a sputtering layer on the wafer to be prepared, such that the sputtering layer covers the protective layer and the area to be electroplated, includes: A sputtering layer is prepared on the wafer to be prepared, such that the sputtering layer covers the protective layer, the first area to be electroplated, and the second area to be electroplated.
8. A structure for a radio frequency chip, characterized in that, The structure of the radio frequency chip is obtained based on the fabrication method of the radio frequency chip according to any one of claims 1-7, and the structure includes: A wafer to be prepared; the wafer to be prepared includes a region to be prepared and a region to be electroplated; the region to be electroplated includes pads of different sizes; Multiple metal bumps are disposed on the wafer to be prepared corresponding to the pads; the multiple metal bumps have different sizes but the same height. Each of the metal bumps includes a copper pillar and a tin cap disposed on the copper pillar; the copper pillars in each of the metal bumps are of equal height, and the tin caps in each of the metal bumps are of equal height.