Methods of fabricating reconstituted wafers, large size reconstituted wafers, bonded package structures, and optoelectronic devices

Abstract

The present application belongs to the field of semiconductor material processing and manufacturing, and provides a manufacturing method of reconstituted wafer, a large-size reconstituted wafer, a bonding packaging structure and an optoelectronic device. The manufacturing method comprises the following steps: ion implantation is performed on a small-size functional material, and then the functional material is divided into a plurality of sub-pieces; the sub-pieces are bonded to a target substrate of large size; after unified wafer splitting annealing, an initial thin film layer of the functional material is formed; after trimming processing of the initial thin film layer, a trimmed thin film layer with a globally flat surface is formed, and a reconstituted wafer is obtained. The large-size reconstituted wafer has the same characteristics as the whole bonding wafer, can be directly used for packaging bonding, and the other functional layers under the thin film layer of the functional material are not damaged, and the characteristics of the reconstituted wafer are not affected. The manufacturing method is very suitable for the reconstitution preparation of 8-inch to 12-inch optoelectronic wafers.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device processing and manufacturing technology, and relates to a method for manufacturing a reconstructed wafer, a large-size reconstructed wafer, a bonding and packaging structure, and optoelectronic devices. Background Technology

[0002] Currently, the global semiconductor industry has entered a stage of large-scale development, with large-size wafers becoming the core direction for future industry development due to their higher integration and lower unit manufacturing costs. However, due to the inherent properties of different materials, some materials can be fabricated into large sizes, such as 12-inch silicon wafers, silicon oxide wafers, and silicon photonics wafers. But materials such as lithium niobate, indium phosphide, and gallium arsenide are difficult to fabricate into large sizes. Therefore, the size of composite wafers involving these materials is limited, and large-size fabrication is not possible. Summary of the Invention

[0003] In view of the problems existing in the prior art, the purpose of the present invention is to provide a method for manufacturing a reconstructed wafer, a large-size reconstructed wafer, a bonding and packaging structure and an optoelectronic device. The manufacturing method can be used to prepare a large-size reconstructed wafer, and the large-size reconstructed wafer has the same characteristics as the whole bonding wafer. The surface flatness of the film layer is high, and it can be directly used for packaging and bonding. Other functional layers under the film layer, such as the silicon oxide layer under the film, are not damaged and do not affect the characteristics of the reconstructed wafer.

[0004] To achieve this objective, the present invention adopts the following technical solution:

[0005] In a first aspect, in some embodiments of the present invention, a method for manufacturing a large-size reconstructed wafer is provided, comprising:

[0006] A functional material is provided, with one side surface being a first bonding surface; the functional material is ion implanted to form an ion implantation layer; then the functional material is cut into several sub-pieces;

[0007] A target substrate having a second bonding surface is provided, the dimensions of which are larger than those of the functional material; the sub-piece is bonded to the target substrate by bonding the first bonding surface and the second bonding surface to obtain a bonded body;

[0008] The bond is subjected to cleaving annealing, which causes the sub-sheet to cleave along the ion implantation layer, forming an initial thin film layer of functional material on the target substrate.

[0009] The initial thin film layer is trimmed to form a trimmed thin film layer with a globally smooth surface, thus obtaining a reconstructed wafer.

[0010] The functional material described in the manufacturing method of this invention can be a wafer formed from the functional material. To achieve high-quality production of functional materials, it is often necessary to control their dimensions. Typically, wafers with large thicknesses need to be fabricated within a small size range (e.g., 6 inches and below) to better control crystal quality and uniformity, thereby ensuring the functional material can exhibit excellent optoelectronic properties. Therefore, due to the intrinsic properties of the material itself, it is difficult to directly fabricate large-size (e.g., 8 inches and above) high-quality single-crystal functional materials. Furthermore, when directly bonding large-size functional materials to a target substrate, their thin and brittle nature can easily lead to damage, breakage, or interface voids, affecting the bonding quality.

[0011] To address this, the manufacturing method provided by this invention involves pre-implanting and dicing the functional material into sub-wafers to overcome the size limitations of the functional material. The functional material can be fabricated at a smaller size, ensuring its crystal quality and optoelectronic performance. Then, multiple small-sized functional materials are diced into a sufficient number of sub-wafers, and each sub-wafer is bonded to a large-sized target substrate to cover the substrate's dimensions. This allows for splicing (with gaps) on the target substrate to form a larger, complete new functional material layer. After bonding, dicing annealing can be used to form the initial thin film layer of the functional material. Since there are numerous sub-wafers, all of which are diced, the flatness of the resulting initial thin film layer needs strict optimization. This invention, through a trimming process, significantly improves the overall surface flatness of the initial thin film layer, enabling it to be directly bonded and packaged with other wafer structures or devices after trimming. Therefore, the manufacturing method of the reconstructed wafer provided by the present invention can efficiently and conveniently realize the preparation of high-quality large-size reconstructed wafers, and the resulting large-size reconstructed wafers have excellent performance and surface flatness, which is beneficial for the implementation and matching of subsequent bonding and packaging.

[0012] In some specific embodiments, the trimming process includes superatom beam trimming.

[0013] In some specific embodiments, the superatom beam trimming process results in a surface coplanarity of the trimmed thin film layer of <10 nm, for example, 9.8 nm, 9 nm, 8 nm, 7 nm, 6 nm, 5 nm, 4 nm, 3 nm, 2 nm, 1 nm, or 0.5 nm. This surface coplanarity can be measured and calculated by the maximum vertical height difference between the highest and lowest points of the trimmed thin film layer formed on each sub-wafer on the target substrate of the obtained reconstructed wafer, relative to the fitting reference plane. Specific testing can be performed using a white light interferometer.

[0014] In some specific embodiments, the superatom beam trimming process makes the global surface roughness Ra of the trimmed thin film layer < 0.5 nm. By reducing the surface coplanarity and global surface roughness Ra on one side of the thin film layer through superatom beam trimming, it is beneficial to the interface flatness, which can be directly bonded and packaged with large-size wafers or devices. The bonding interface will not introduce bonding voids due to poor coplanarity or unevenness on one side of the thin film layer, thus preventing functional failure.

[0015] In some specific embodiments, in the superatomic beam trimming process, the proportion of superatoms in the superatomic beam is >90%, and each superatom is composed of ≥50 elementary particles; the elementary particles include atoms and / or molecules; and non-compliant low-mass superatoms and monatomic ions can be removed by magnetic sieving.

[0016] Superatoms are nanoscale particles composed of hundreds to thousands of gas molecules / atoms (such as Ar, He, Kr, NF3, etc.) bound together by van der Waals forces. In ionization collisions and electromagnetic field motion, they can be considered as single "atoms," with masses and collision cross-sections several to thousands of times larger than those of a single atom. When superatomic beams bombard material surfaces, they produce lateral sputtering and localized thermal annealing effects, and can also generate localized pulsed high temperatures. Furthermore, the processing is gentle and does not cause overall damage to the substrate and / or film layers. Therefore, this invention employs superatomic beam trimming to solve the problems of lattice damage and poor surface smoothness of the substrate (target substrate) and / or film layers (thin films of functional materials) caused by single-atom ion bombardment in semiconductor processing.

[0017] In some specific embodiments, the manufacturing method further includes providing a protective layer in the inter-layer gap between each of the initial thin film layers before performing the finishing process.

[0018] Preferably, the manufacturing method further includes removing the protective layer between each of the trimmed film layers after the trimming process.

[0019] Preferably, the protective layer comprises photoresist.

[0020] In the manufacturing method provided by this invention, a protective layer can be applied before trimming to cover the inter-wafer gaps (i.e., areas not bonded by the sub-wafers) between the initial thin film layers formed by each sub-wafer, thereby protecting the layer structure (e.g., silicon oxide layer) in the underlying target substrate and ensuring that the structure, properties, and performance of the resulting reconstructed wafer are not damaged. The protective layer is preferably a photoresist to facilitate application and removal; other materials can be selected as needed. When the protective layer covers the surface to be processed of the initial thin film layer, it should be appropriately removed to improve the trimming effect. In some possible embodiments, after trimming, the protective layer may not be removed and can continue to be used for bonding the reconstructed wafer to other wafers or structures.

[0021] In some specific embodiments, the functional material includes at least one selected from lithium niobate (LiNbO3, abbreviated as LN), lithium tantalate, indium phosphide (InP), gallium arsenide (GaAs), gallium nitride, silicon carbide, zinc oxide, zinc selenide, aluminum nitride, gallium oxide, diamond, barium titanate, yttrium aluminum garnet, silicon germanium, vanadium oxide, and sapphire. The functional material is preferably a photoelectric material, such as LN, InP, or GaAs, and the reconstructed wafer containing the thin film layer of the photoelectric material can be called a photoelectric wafer or a photoelectric reconstruction wafer.

[0022] In some specific embodiments, the size of the functional material is 4 inches to 8 inches; for example, it can be 4 inches, 6 inches or 8 inches, etc.

[0023] In some specific embodiments, both the target substrate and the reconstructed wafer are 8 inches to 12 inches in size. Exemplarily, they can be 8 inches, 10 inches, or 12 inches, etc. This invention is particularly suitable for the fabrication of large-size (8 inches and above) reconstructed wafers.

[0024] In some specific embodiments, the target substrate includes a stacked silicon layer and a silicon oxide layer, with the side of the silicon oxide layer away from the silicon layer serving as the second bonding surface. The silicon layer includes a patterned silicon layer or a bare silicon layer. The patterned silicon layer refers to a precisely controllable micro / nano structure formed on the surface through processes such as photolithography, etching, and deposition, including lines, gates, dots, alignment marks, test keys, and analog device patterns. This invention preferably utilizes the contact between the silicon oxide layer and the functional material for bonding. Hydrophilic bonding between the silicon oxide layer and the functional material can be selectively performed, eliminating the need for damaging processes such as high-energy ion beam bombardment of the interface, thus helping to avoid damage to the thin film lattice.

[0025] In some specific embodiments, in the bonding body, the sub-pieces are arranged either closely or spaced apart on the surface of the target substrate; in the closely arranged arrangement, the spacing between adjacent sub-pieces is less than 50 μm, for example, it can be 49 μm, 45 μm, 40 μm, 35 μm, 30 μm, 25 μm, 20 μm, 15 μm, 10 μm or 5 μm, etc.; in the spaced arrangement, the spacing between adjacent sub-pieces is greater than or equal to 50 μm, for example, it can be 50 μm, 51 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm or 90 μm, etc.

[0026] In this invention, the size, shape, and quantity of the cut sub-wafers can be referenced from the layout design of the back-end product, or based on the size of the target substrate and the overall design of the new thin film layer on it, or can be flexibly adjusted based on MPW (Multi Project Wafer). Under the premise of ensuring process cleanliness and production efficiency, it ensures that the size and position of the small-sized sub-wafers can be accurately bonded and combined with the back-end product.

[0027] In some specific embodiments, the bonding process includes hydrophilic bonding. For example, hydrophilic bonding of a thicker functional material (such as a lithium niobate wafer) to a layer in the target substrate, such as a silicon oxide layer, can avoid damage to the surface of the functional material and has a high-quality bonding surface and bonding strength.

[0028] In some specific embodiments, the manufacturing method further includes an annealing process after the bonding treatment. Annealing helps to further enhance the bonding strength between the sub-wafer and the target substrate.

[0029] Secondly, in some embodiments of the present invention, a large-size reconstructed wafer is provided, obtained according to the manufacturing method described in the first aspect; the size of the large-size reconstructed wafer is 8 inches to 12 inches.

[0030] In some specific embodiments, the large-size reconstructed wafer includes stacked silicon layers, silicon oxide layers, and thin film layers of functional materials; the functional materials include optoelectronic materials.

[0031] Preferably, the global surface roughness Ra of the thin film layer of the functional material is <0.5 nm and / or the surface coplanarity is <10 nm.

[0032] Thirdly, in some embodiments of the present invention, a bonding packaging structure is provided, comprising the large-size reconstructed wafer described in the second aspect, and a functional wafer bonded to a thin film layer of the functional material in the large-size reconstructed wafer.

[0033] Preferably, the functional wafer includes a silicon photonic wafer, which comprises a silicon-silicon oxide-silicon stacked structure.

[0034] Fourthly, in some embodiments of the present invention, an optoelectronic device is provided, comprising a large-size reconstructed wafer as described in the second aspect, or comprising the bonding and packaging structure as described in the third aspect.

[0035] It should be noted that, due to space limitations and to avoid redundancy, this invention does not exhaustively list all point values ​​within the above numerical range, but it is not limited to the listed values ​​either; other unlisted values ​​within the above numerical range are also applicable.

[0036] Compared with existing technical solutions, the present invention has at least the following beneficial effects:

[0037] The method for manufacturing reconstructed wafers provided by this invention involves slicing fragile functional materials into small-sized sub-wafers after ion implantation, and then bonding these sub-wafers to a large-sized target substrate. After slicing and annealing, these sub-wafers are retained and spliced ​​together to form the initial thin film layer of the new functional material. This effectively avoids the difficulties in preparing large-sized whole-sheet functional materials, which can affect film uniformity and crystal quality. It also effectively avoids warping, stress, damage, breakage, or bonding interface bubbles that can occur when directly applying large-sized whole-sheet functional materials for bonding. This slicing method allows for the early removal and replacement of defective sub-wafers, thereby improving and ensuring overall yield. Simultaneously, this invention performs a trimming process on the initial thin film layer, effectively achieving atomic-level flatness and repair of the functional material's thin film layer. The resulting globally flat trimmed thin film layer allows the obtained large-sized reconstructed wafer to be directly used for subsequent packaging and bonding. Therefore, the manufacturing method provided by this invention can efficiently produce high-quality large-sized reconstructed wafers, especially suitable for the reconstruction of 8-inch to 12-inch optoelectronic wafers. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of steps S1 to S3 in one or more embodiments of the present invention for manufacturing a large-size reconstructed wafer.

[0039] Figure 2 This is a schematic diagram of steps S4 to S5 in one or more embodiments of the present invention for manufacturing a large-size reconstructed wafer.

[0040] In the figure: 10-functional material, 11-sub-wafer, 12-ion implantation layer, 13-initial thin film layer, 14-trimmed thin film layer, 20-target substrate, 21-silicon layer, 22-silicon oxide layer, 30-bonding body, 40-protective layer, 50-large-size reconstructed wafer. Detailed Implementation

[0041] The scope of this invention can be defined by lower and upper limits. The selected lower and upper limits define the boundaries of a specific range. The range defined in this way can be defined by the inclusion or exclusion of endpoints. Any endpoint can be independently selected for inclusion or exclusion, and all lower and upper limits can be arbitrarily combined to form new ranges. That is, any lower limit can be combined with any upper limit to form an effective range. For example, if the ranges of 60~120 and 80~110 are listed for specific parameters, it should be understood that the ranges of 60~110 and 80~120 also fall within the scope of this invention. In addition, if the minimum range values ​​1 and 2 are listed, and the maximum range values ​​3, 4 and 5 are also listed, then all ranges of 1~3, 1~4, 1~5, 2~3, 2~4 and 2~5 fall within the scope of this invention. In this invention, the numerical range "a~b" represents a shortened representation of any combination of real numbers between a and b, where a and b are both real numbers. For example, the numerical range "0~5" means that all real numbers between 0 and 5 have been fully listed in this document, and "0~5" is only a shortened representation of this set of numerical combinations. When a parameter is expressed as an integer ≥2, it is equivalent to listing positive integers that meet the requirements, such as 2, 3, 4, 5, 6, 7, 8, 9, 10, etc. When a parameter is expressed as an integer selected from "2~10", it is equivalent to listing any integer among 2, 3, 4, 5, 6, 7, 8, 9, and 10.

[0042] In this invention, "a combination of at least two" refers to a quantity greater than or equal to 2 unless otherwise specified. For example, "any one or a combination of at least two" means that any one of the listed items can be selected, or a combination of at least two of the listed items formed in a manner that does not conflict and enables the implementation of this invention. In this invention, unless otherwise specified, the features or solutions corresponding to "and / or" cover any one of two or more related listed items, as well as any and all combinations of the related listed items. The arbitrary and all combinations include any two related listed items, any more related listed items, or a combination of all related listed items. For example, "A and / or B" means a set consisting of A, B, and combinations of A and B, where "containing A and / or B" can be understood, depending on the context of the statement, as containing A, containing B, or simultaneously containing both A and B. In this invention, "optional" means that the corresponding feature, component, step or solution is not necessary, that is, it is selected from either "with" or "without". If there are multiple "optional" limitations in a technical solution, unless otherwise specified and there is no technical conflict or mutual constraint, each "optional" limitation is independent and does not affect the others.

[0043] In this invention, technical features or solutions described using open-ended terms such as "comprising" or "including" do not exclude additional non-conflicting elements beyond the listed elements unless otherwise specified. They are considered to disclose both closed-ended features or solutions consisting solely of the listed elements and open-ended features or solutions that may include additional non-conflicting elements beyond the listed elements. For example, if A includes a1, a2, and a3, unless otherwise specified, this means that A can consist only of a1, a2, and a3, or it can include other non-conflicting elements based on a1, a2, and a3. This corresponds to the disclosure of technical solutions such as "A consists of a1, a2, and a3," "A is selected from a1, a2, and a3," and "A not only includes a1, a2, and a3, but may also include other non-conflicting elements." All embodiments and optional embodiments of this invention, unless otherwise specified and without technical conflict, can be combined to form new technical solutions, and such combinations fall within the scope of this invention. The term "embodiment" as used in this invention means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment or implementation of the invention. The appearance of this phrase in various locations throughout the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will understand, explicitly and implicitly, that the embodiments described in this invention can be combined with other embodiments that do not conflict with the technology. The ordinal numbers "first," "second," "third," and "fourth," etc., used in the expressions "first aspect," "second aspect," "third aspect," and "fourth aspect" in this invention are for descriptive purposes only and should not be construed as indicating or implying relative importance or quantity, nor should they be construed as implicitly specifying the importance or quantity of the indicated technical features. They serve only as a non-exhaustive enumeration and do not constitute a closed limitation on quantity.

[0044] In this invention, the order in which the steps are written in the methods described in the various embodiments does not imply a strict execution order. The actual execution order of each step should be determined based on its function and possible internal logic. Unless otherwise specified, all steps of this invention can be executed in the order they are written, or in any order without technical conflict. For example, if the method includes steps (a) and (b), it means that the method may include steps (a) and (b) executed sequentially, or it may include steps (b) and (a) executed sequentially. If the method also includes step (c), then step (c) can be added to the method in any conflict-free order, including but not limited to the execution order of steps (a), (b), and (c), steps (a), (c), and (b), steps (c), (a), and (b), etc.

[0045] Example 1

[0046] This embodiment provides a method for manufacturing a large-size reconstructed wafer, including the following steps:

[0047] S1, such as Figure 1 As shown, an 8-inch functional material 10 is provided. The functional material 10 is a lithium niobate wafer, and one side surface is the first bonding surface.

[0048] S2, such as Figure 1 As shown, the functional material 10 is ion implanted to form an ion implantation layer 12; then the functional material 10 is cut into several sub-pieces 11.

[0049] S3, such as Figure 1 As shown, a 12-inch target substrate 20 is provided. The target substrate 20 consists of a stacked silicon layer 21 and a silicon oxide layer 22. The surface of the silicon oxide layer 22 away from the silicon layer 21 is the second bonding surface.

[0050] By bonding the first bonding surface and the second bonding surface, the bonding process is hydrophilic bonding, and after bonding, annealing is performed to bond multiple sub-pieces 11 to the target substrate 20 to obtain a bonded body 30.

[0051] S4, such as Figure 2 As shown, the bond body 30 is subjected to splitting annealing, which causes the sub-piece 11 to split along the ion implantation layer 12, forming an initial thin film layer 13 of the functional material 10 on the target substrate 20.

[0052] S5, such as Figure 2 As shown, a protective layer 40 is provided on the side of the initial thin film layer 13 away from the target substrate 20. The protective layer 40 is a photoresist formed by coating. The protective layer 40 covers the inter-wafer gap between each initial thin film layer 13. The excess protective layer 40 covering the surface of the initial thin film layer 13 is removed to expose the surface. Then, the exposed surface of the initial thin film layer 13 is subjected to superatom beam trimming. The initial thin film layer 13 is trimmed with low damage to obtain trimmed thin film layer 14. After testing, the surface coplanarity of trimmed thin film layer 14 is <1nm and the global surface roughness Ra is <0.2nm. After removing the protective layer 40 in the inter-wafer gap, a large-size reconstructed wafer 50 is obtained.

[0053] Example 2

[0054] This embodiment provides a method for manufacturing a large-size reconstructed wafer. In step S1, the functional material 10 is replaced with a 4-inch gallium arsenide wafer instead of an 8-inch lithium niobate wafer. In step S3, the size of the target substrate 20 is adjusted from 12 inches to 8 inches. In step S5, the surface coplanarity of the trimmed thin film layer 14 is <5nm and the global surface roughness Ra is <0.5nm through superatom beam trimming. Except for the above, the other conditions are exactly the same as in Embodiment 1.

[0055] Example 3

[0056] This embodiment provides a method for manufacturing a large-size reconstructed wafer. In step S1, the functional material 10 is replaced from an 8-inch lithium niobate wafer to a 6-inch indium phosphide wafer; in step S3, the size of the target substrate 20 is adjusted from 12 inches to 10 inches; in step S5, the surface coplanarity of the trimmed thin film layer 14 is <2nm and the global surface roughness Ra is <0.3nm through superatom beam trimming. Except for the above, other conditions are exactly the same as in Embodiment 1.

[0057] As can be seen from the above, the manufacturing method for large-size reconstructed wafers provided in this embodiment of the invention involves pre-cutting fragile functional materials into several small-sized sub-wafers after ion implantation, bonding multiple sub-wafers to a large-size target substrate, and then splicing the functional materials retained from the ion implantation layer along each sub-wafer to form an initial thin film layer of large-size functional material. After protection with a protective layer, a finishing process is performed, particularly using superatom beam finishing, to obtain a high-quality large-size reconstructed wafer. This method ensures the quality and properties of the large-size reconstructed wafer and the optoelectronic thin film layer, solves bonding warpage, stress, and bonding interface bubble problems, and further facilitates atomic-level planarization and repair by superatom beam finishing, which is more conducive to supporting subsequent direct bonding with other wafers to manufacture high-performance large-size devices. Furthermore, the protective layer prevents damage to the structure and properties of the resulting reconstructed wafer, allowing it to better perform its functions.

[0058] The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the specific details in the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

[0059] It should also be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

[0060] Furthermore, various different embodiments of the present invention can be combined in any way, as long as they do not violate the spirit of the present invention, they should also be regarded as the content disclosed by the present invention.

Claims

1. A method for manufacturing a reconstructed wafer, characterized in that, include: A functional material is provided, with one side surface serving as the first bonding surface; The functional material is ion implanted to form an ion implantation layer; Then the functional material is cut into several sub-pieces; A target substrate having a second bonding surface is provided, the dimensions of which are larger than those of the functional material; the sub-piece is bonded to the target substrate by bonding the first bonding surface and the second bonding surface to obtain a bonded body; The bond is subjected to cleaving annealing, which causes the sub-sheet to cleave along the ion implantation layer, forming an initial thin film layer of functional material on the target substrate. The initial thin film layer is trimmed to form a trimmed thin film layer with a globally smooth surface, thus obtaining a reconstructed wafer.

2. The method for manufacturing a reconstructed wafer according to claim 1, characterized in that, The trimming process includes superatom beam trimming; Preferably, the superatom beam trimming process results in a surface coplanarity of the trimmed thin film layer of <10 nm, and / or the superatom beam trimming process results in a global surface roughness Ra of the trimmed thin film layer of <0.5 nm.

3. The method for manufacturing a reconstructed wafer according to claim 1 or 2, characterized in that, The manufacturing method further includes, before performing the finishing process, providing a protective layer in the inter-layer gap between each of the initial thin film layers; Preferably, the manufacturing method further includes removing the protective layer between each of the trimmed film layers after the trimming process; Preferably, the protective layer comprises photoresist.

4. The method for manufacturing a reconstructed wafer according to any one of claims 1-3, characterized in that, The dimensions of the functional materials are all 4 inches to 8 inches; Preferably, the target substrate and the reconstructed wafer are both ≥8 inches in size.

5. The method for manufacturing a reconstructed wafer according to any one of claims 1-4, characterized in that, The target substrate includes a stacked silicon layer and a silicon oxide layer, wherein the side of the silicon oxide layer away from the silicon layer is the second bonding surface.

6. The method for manufacturing a reconstructed wafer according to any one of claims 1-5, characterized in that, In the bonded body, the sub-pieces are arranged closely or spaced apart on the surface of the target substrate; The spacing between adjacent sub-pieces in the tightly packed arrangement is less than 50 μm; The spacing between adjacent sub-pieces in the spacing arrangement is greater than or equal to 50 μm.

7. The method for manufacturing a reconstructed wafer according to any one of claims 1-6, characterized in that, The bonding process includes hydrophilic bonding; Preferably, the manufacturing method further includes annealing after the bonding process.

8. A large-size reconstructed wafer, characterized in that, The large-size reconstructed wafer is obtained by the manufacturing method according to any one of claims 1-7, and the size specification of the wafer is 8 inches to 12 inches.

9. The large-size reconstructed wafer according to claim 8, characterized in that, The large-size reconstructed wafer comprises stacked silicon layers, silicon oxide layers, and thin film layers of functional materials; the functional materials include optoelectronic materials. Preferably, the global surface roughness Ra of the thin film layer of the functional material is <0.5 nm and / or the surface coplanarity is <10 nm.

10. A bonding packaging structure, characterized in that, The invention includes the large-size reconstructed wafer as described in claim 8 or 9, and a functional wafer bonded to a thin film layer of the functional material in the large-size reconstructed wafer; the functional wafer includes a silicon photonic wafer, which includes a silicon-silicon oxide-silicon stacked structure.

11. An optoelectronic device, characterized in that, It contains the large-size reconstructed wafer as described in claim 8 or 9, or the bonding package structure as described in claim 10.

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