System, method and apparatus for high speed data modulation

Abstract

A data modulator for a transmitter includes a multiplexer configured to receive a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols at a first rate. The multiplexer is configured to selectively output the plurality of first symbols and the plurality of second symbols based on a first clock signal to form a third data stream, the third data stream achieving a second rate greater than the first rate for transmission of the third data stream by the transmitter.

Description

Technical Field

[0001] The present disclosure generally relates to systems, methods, and apparatus for high-speed data modulation. Background Art

[0002] Data transmission equipment may include digital-to-analog converters (DACs) and data modulators to help convert digital data into analog data for transmission over a network. The type of DAC and / or data modulator used in a data transmission equipment is a factor that affects the performance of the data transmission equipment (e.g., transmission rate capability, reliability of transmitted data, etc.). Summary of the invention

[0003] In an exemplary embodiment, a data modulator for a transmitter includes a multiplexer configured to receive a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols at a first rate, and based on a first clock signal, selectively output the plurality of first symbols and the plurality of second symbols to form a third data stream, wherein the third data stream implements a second rate greater than the first rate for transmission of the third data stream by the transmitter.

[0004] In an exemplary embodiment, a digital-to-analog converter (DAC) includes a first amplifier block configured to receive a first bit and a second bit of a first data stream at a first rate and output a first signal and a second signal based on values ​​of the first bit and the second bit, a second amplifier block configured to receive a third bit and a fourth bit of a second data stream at the first rate and output a third signal and a fourth signal based on values ​​of the third bit and the fourth bit, a modulator configured to receive the first signal, the second signal, the third signal, and the fourth signal and selectively output signs of the first signal, the second signal, the third signal, and the fourth signal based on a first clock signal to form a third data stream having a second rate greater than the first rate, and a conversion circuit configured to receive the signs of the third data stream and output analog signals representing the first data stream and the second data stream.

[0005] In an exemplary embodiment, a transmitter includes a parallel-input serial-output (PISO) device configured to receive parallel input data and output serialized data at a first rate, and a digital-to-analog (DAC) converter. The DAC includes a first amplifier block configured to receive a first bit and a second bit of a first data stream of the serialized data at the first rate, and output a first signal and a second signal based on the values ​​of the first bit and the second bit, a second amplifier block configured to receive a third bit and a fourth bit of a second data stream of the serialized data at the first rate, and output a third signal and a fourth signal based on the values ​​of the third bit and the fourth bit, a modulator configured to receive the first signal, the second signal, the third signal, and the fourth signal, and selectively output the symbols of the first signal, the second signal, the third signal, and the fourth signal based on a first clock signal to form a third data stream having a second rate greater than the first rate, and a conversion circuit configured to receive the symbols of the third data stream from the modulator and output an analog signal representing the third data stream.

[0006] Additional features and advantages are described herein, and will become apparent from the following description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure is described in conjunction with the accompanying drawings, which are not necessarily drawn to scale:

[0008] Figure 1 A system according to at least one example embodiment is shown;

[0009] Figure 2 According to at least one example embodiment, Figure 1 Additional details of the transmitter in;

[0010] Figure 3A A general schematic diagram and timing diagram of a dual input data modulator implemented with voltage control according to at least one example embodiment are shown;

[0011] Figure 3B A general schematic diagram and timing diagram of a four-input data modulator implemented using voltage control according to at least one example embodiment are shown;

[0012] Figure 4 In more detail, according to at least one example embodiment, Figure 3A A data modulator;

[0013] Figure 5 In more detail, according to at least one example embodiment, Figure 2 DAC;

[0014] Fig. 6AA two-bit DAC implemented with current control is shown according to at least one example embodiment; and

[0015] Figure 6B An N-bit DAC implemented with current control according to at least one example embodiment is shown. DETAILED DESCRIPTION

[0016] The following description only provides embodiments and is not intended to limit the scope, applicability or configuration of the claims. Instead, the following description will provide a feasible description for implementing the described embodiments to those skilled in the art. It should be understood that various changes may be made to the functions and arrangements of the elements without departing from the spirit and scope of the appended claims.

[0017] As will be appreciated from the following description, and for reasons of computing efficiency, the components of the system may be arranged at any suitable locations within a distributed network of components without affecting the operation of the system.

[0018] In addition, it should be understood that the various links of the connecting elements can be wired, trace or wireless links, or any suitable combination thereof, or can provide data to the connecting elements and / or communicate data to and from the connecting elements. For example, the transmission medium used as a link can be any suitable electrical signal carrier, including coaxial cable, copper wire and optical fiber, electrical traces on a PCB, etc.

[0019] As used herein, the phrases "at least one," "one or more," "or," and "and / or" are open-ended expressions that are both conjunctive and disjunctive in operation. For example, each of the expressions "at least one of A, B, and C," "at least one of A, B, or C," "one or more of A, B, and C," "one or more of A, B, or C," "A, B and / or C," and "A, B, or C" refers to A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together.

[0020] As used herein, the terms "determine," "compute," and "calculate," and variations thereof, are used interchangeably and include any suitable type of methodology, process, operation, or technique.

[0021] Various aspects of the disclosure are described herein with reference to figures that may be schematic illustrations of idealized configurations.

[0022] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the present disclosure.

[0023] As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the terms "comprises", "includes", "comprising", "includes", "including", and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0024] When it is appropriate to refer to a general element or set of elements rather than a specific element, the description may refer to the element or set of elements by its root term. For example, when it is not necessary to mention a specific element X 1 , X 2 When describing, these elements may be collectively referred to as "X".

[0025] Data center interconnects are becoming increasingly high throughput, so the components that process data are becoming faster and more power-hungry. The interconnection between devices, modules, and systems is accomplished through SerDes IP, which is used to transmit and receive interconnect signals. To keep up with the pace of the market, people want to design faster and less power-hungry SerDes IP.

[0026] The concepts of the present invention relate to an architecture that can be used to design a data modulator for a low-power and high-speed SerDes transmitter. The architecture is faster and consumes less power than current transmitter topologies used in SerDes systems.

[0027] The related art design of SerDes IP transmitter has the data path speed or the clock path speed, or both, switched at the rate and speed of the output data. Therefore, when increasing the rate of the output data, the clock and / or data path rate also increases. This leads to very challenging designs that consume high power and may be limited in bandwidth. In high-speed transmitter designs, such as 212.5G SerDes, where the output pulse width is about 9.4ps, the related art topology may not be able to meet industry regulations.

[0028] Thus, the inventive concept relates to a SerDes transmitter (TX) using a K-input data modulator (KDM). In operation, data is generated in the digital domain and passed through a low-rate parallel bus to a parallel-to-serial block, which serializes the data to one-quarter rate (or other desired rate) of the final rate. In addition, the data is arranged in a specific manner suitable for the KDM DAC. The clock system is fed by the TX phase-locked loop and generates a high-rate clock (e.g., one-quarter rate) for the 2:1 multiplexer and the KDM driver. An additional low-rate block is used to generate a clock for the parallel-to-serial block.

[0029] In general, example embodiments utilize a specific data arrangement at the input of the KDM, data and clock multiplexing at the last stage (output of the DAC), which allows full rate signals to be generated on passive devices, and specific hardware that eliminates the need to obtain full rate signals through active devices. The KDM can be implemented in voltage mode or current mode. In order to generate the desired output signal without using a high-speed data path or clock chain, specific data and clock arrangements and hardware need to be used. It is worth noting that the required high-speed signal is generated at the output of the transmitter through a passive load, thereby reducing power consumption.

[0030] The transmitter according to the example implementation uses an ultra-high speed and low power data modulator that can be implemented in a SerDes system (example: 200G PAM4 / 6 / 8 or USR NRZ / PAM4). It is worth noting that there are no active devices in the transmitter that operate at full rate output data. Instead, there is a specific combination and timing of low rate data and clock multiplexing that generates a full rate data signal at the output of the KDM through passive devices.

[0031] Figure 1 An optical system 100 is shown according to at least one example embodiment. The optical system 100 includes a device 104, a communication network 108, and a device 112. In at least one example embodiment, the devices 104 and 112 correspond to one or more of a personal computer (PC), a laptop computer, a tablet computer, a smart phone, a server, a collection of servers, etc. In some embodiments, the devices 104 and 112 may correspond to any suitable type of device that communicates with other devices that are also connected to a common type of communication network 108. As another specific but non-limiting example, the devices 104 and 112 may correspond to servers that provide information resources, services, and / or applications to user devices, client devices, or other hosts in the system 100.

[0032] Examples of communication networks 108 that can be used to connect devices 104 and 112 include Internet Protocol (IP) networks, Ethernet, InfiniBand (IB) networks, Fibre Channel networks, the Internet, cellular communication networks, wireless communication networks, combinations thereof (e.g., Fibre Channel over Ethernet), variations thereof, etc. In a specific but non-limiting example, communication network 108 is a network capable of using optical signals to transmit data between devices 104 and 112. In this case, devices 104 and 112 and communication network 108 may include waveguides (e.g., optical fibers) that carry optical signals.

[0033] The device 104 includes a transceiver 116 for sending and receiving signals, such as data signals. The data signals may be optical signals modulated with data or other suitable signals for carrying data.

[0034] The transceiver 116 may include a digital data source 120, a transmitter 124, a receiver 128, and a processing circuit 132 that controls the transceiver 116. The digital data generator 120 may include suitable hardware and / or software for outputting data in a digital format (e.g., binary format). The digital data output by the digital data source 120 may be retrieved from a memory (not shown) or generated based on input (e.g., user input).

[0035] Transmitter 124 includes suitable software and / or hardware for receiving digital data from digital data source 120 and outputting a data signal based on the digital data for transmission to device 112 via communication network 108. Additional details of the structure of transmitter 124 are discussed in more detail below with reference to the accompanying drawings.

[0036] The receiver 128 may include suitable hardware and / or software for receiving signals, such as data signals, from the communication network 108. For example, the receiver 128 may include a photodetector for detecting light signals and / or a demodulator for demodulating received data signals to extract data for storage in a memory.

[0037] The processing circuit 132 may include software, hardware, or a combination thereof for controlling the transceiver 116. For example, the processing circuit 132 may include a memory containing executable instructions and a processor (e.g., a microprocessor) that executes the instructions on the memory. The memory may correspond to any suitable type of memory device or a collection of memory devices configured to store instructions. Non-limiting examples of suitable storage devices that can be used include flash memory, random access memory (RAM), read-only memory (ROM), their variants, their combinations, and the like. In some embodiments, the memory and the processor may be integrated into a common device (e.g., a microprocessor may include an integrated memory). Additionally or alternatively, the processing circuit 132 may include hardware, such as an application specific integrated circuit (ASIC). Other non-limiting examples of the processing circuit 132 include an integrated circuit (IC) chip, a central processing unit (CPU), a general processing unit (GPU), a microprocessor, a field programmable gate array (FPGA), a collection of logic gates or transistors, resistors, capacitors, inductors, diodes, and the like. Some or all of the processing circuits 132 may be provided on a printed circuit board (PCB) or a collection of PCBs. It should be appreciated that any suitable type of electrical component or collection of electrical components may be suitable for inclusion in processing circuitry 132. Processing circuitry 132 may send and / or receive signals to and / or from other elements of transceiver 116 to control the overall operation of transceiver 116.

[0038] The transceiver 116 or selected elements of the transceiver 116 may take the form of a pluggable card or controller for the device 104. For example, the transceiver 116 or selected elements of the transceiver 116 may be implemented on a network interface card (NIC).

[0039] Device 112 may include a transceiver 136 for transmitting and receiving signals, such as data signals, through communication network 108. The same or similar structure as transceiver 116 may be applied to transceiver 136, and thus, the structure of transceiver 136 is not described separately.

[0040] Although not explicitly shown, it is understood that devices 104 and 112 and transceivers 116 and 120 may include other processing devices, storage devices, and / or communication interfaces typically associated with computing tasks, such as sending and receiving data over wired and / or wireless connections.

[0041] Figure 2 According to at least one example embodiment, Figure 1 Additional details of transmitter 124 in FIG.

[0042] The transmitter 124 includes a parallel-input serial-output (PISO) device 200, a DAC 204, an electrostatic (ESD) device 208, and signal generators 212 and 216. The PISO device 200 includes suitable components (e.g., switches) for serializing parallel input data to output serialized data. That is, the PISO device 200 is configured to output digital serialized data based on digital parallel input data. The PISO device 200 can receive digital parallel input data from the digital data source 120 via a digital data bus 220.

[0043] The DAC 204 receives serialized digital data from the PISO device 200 via the DAC control bus 224. As shown, the serialized digital data sent via the DAC control bus 224 may include multiple data streams DS1 and DS2, where some bits of the data streams are binary encoded (i.e., streams are labeled bin0 to bin5) and some bits of the data streams are unary or thermometer encoded (i.e., streams are labeled thm0 to thm2). Figure 5 At least some of these streams are also shown. Figure 2 The symbols in indicate the position of the bit in the data block and whether it is a bit portion of the binary code of the data block or the thermometer code of the data block. For example, for a data block of the first data stream DS1 and a data block of the second data stream DS2, bin0 to bin5 indicate the first to fifth less significant bits of the data block, where bin0 is the least significant bit (LSB) of the data block and thm0 to thm2 are the more significant bits of the data block, where thm2 is the most significant bit (MSB) of the data block. The symbols <1:0> for each data path of bus 224 indicate that each arrow represents two data lines for carrying differential data, where each input bit is represented by a differential signal having a "positive" and a "negative" portion, where each portion is input to the input of DAC204. Although DAC204 is shown and described as including a differential input and a differential output, it should be understood that the input and output of DAC204 can be single-ended if desired.

[0044] although Figure 2 A data block is shown having a combination of binary coded bits (bin) and thermometer coded bits (thm), but it should be understood that the data block may include all binary coded bits, all thermometer coded bits, some or all bits encoded by another encoding process, or any combination thereof.

[0045] DAC 204 converts the serialized digital data into an analog signal corresponding to a data signal for transmission over communication network 108. To this end, DAC 204 may include a multiplexer (MUX) 228 for multiplexing the digital data stream from PISO device 200 such that the symbols in the stream are arranged in a particular order, which allows DAC 204 to up-convert (e.g., passively up-convert) the rate of data received from PISO device 200 to a final rate ready for transmission. To help achieve this result, DAC 204 includes a k-input data modulator (KDM) 232 that operates to increase the data rate as a result of the particular arrangement of the symbols output from MUX 228 and the manipulation of the timing for sampling the symbols using a clock signal (or clocks). Throughout this instant description, a symbol is a signal representing one or more bits of digital data, where the number of bits is represented in a single symbol according to a modulation scheme (e.g., PAM4, PAM6, PAM8, etc.). DAC 204 also includes a conversion circuit 236 that converts the modulated data signal from KDM 232 into an analog signal for output to ESD device 208. Figure 3A-Figure 5 Additional details of DAC 204 are discussed in greater detail.

[0046] The ESD device 208 is coupled to the output of the DAC 204 and a node (or nodes) that is configured to be connected to a load (e.g., a transmission line). For example, the ESD device is coupled between the output of the DAC 204 and the differential output nodes or pins TXP and TXN. The ESD device 208 may include suitable circuitry for reducing or eliminating electrostatic shocks at the differential output nodes or pins TXP and TXN of the transmitter 124. In at least one example embodiment, the ESD device 208 includes an inductor and at least one capacitor in a T-coil configuration.

[0047] Signal generator 212 includes suitable components for receiving control signal CON1 from processing circuit 132 and generating control signal CON2 and clock signal CLK1 for PISO device 200. Control signal CON2 and / or clock signal CLK1 may be generated by signal generator 212 based on control signal CON1. ​​Clock signal CLK1 may control the rate at which digital data input to PISO device 200 is serialized. Control signals CON1 and / or CON2 may include set / reset signals, enable / disable signals, frequency setting signals for setting the frequency of CLK1 (e.g., a programmable frequency divider that receives CLKI and / or CLKQ to generate CLK1), signals for adjusting the speed of data received via bus 224, and / or other adjustment signals (e.g., signals that adjust one or more clock signals).

[0048] The signal generator 216 includes a clock signal CLK for generating the KDM 232. I and the clock signal CLK of MUX228 Q In at least one example embodiment, the signal generator 216 includes a phase-locked loop (PLL) circuit that generates a clock signal CLK of a desired frequency. I and CLK Q KDM232 can use the clock signal CLK I To control the rate of digital-to-analog conversion, MUX228 uses the clock signal CLK Q The arrangement of symbols in the data stream is controlled via switching of MUX 228 .

[0049] Clock signal CLK l ,CLK I and CLK Q The frequency of the clock signal CLK is based on empirical evidence and / or a preferred set of design parameters. 1 ,CLK I and / or CLK Q The frequency of the first clock signal CLK may be set based on the speed at which digital data is received from the digital data source 120 and / or the speed at which data is desired to be transmitted from the transmitter 124. In at least one example embodiment, the first clock signal CLK 1 The frequency of the clock signal CLK is less than I and CLK Q The signal generator 212 can receive the clock signal CLK I and CLK Q And use the clock signal CLK I and CLK Q To adjust the clock signal CLK 1 frequency so that the PISO device 200 is properly synchronized with the DAC 204 and the MUX 228.

[0050] Figure 3A A general schematic diagram of a K input data modulator KDM300 implemented with voltage control (also referred to as KDM-V300) and a timing diagram 316 for controlling KDM-V300 are shown. KDM-V300 may correspond to KDM232 in DAC204 to modulate data from MUX228 as part of the digital-to-analog conversion process. Figure 3A In the example of , KDM-V300 is a dual input modulator that receives two data streams DS1 and DS2. KDM-V300 includes MUX304 and amplifier blocks 308 and 312 that receive data bits in data streams DS1 and DS2 from MUX228, respectively. Amplifier blocks 308 and 312 can receive digital bits DS2 of the corresponding data stream DS1 and output symbols based on the values ​​of the received digital bits. Figure 3A In the example of FIG. 1 , data streams DS1 and DS2 include symbols S1 to S16 output from MUX 304 as output data in a sequence from symbol S1 to symbol S16. As described in more detail below, the symbols of data streams DS1 and DS2 are specially ordered and sampled according to a special timing before being input to KDM-V 300 to achieve sequential ordering at a higher rate than the input symbols at the output.

[0051] As shown in the timing diagram 316, the principle of KDM-V300 is to use data switching and clock switching to generate output data (or output symbols), which means that the data streams DS1 and DS2 are switched at the clock CLK of MUX304. I The middle of the clock signal (i.e., the stable period of the clock signal) is output (switched), and the clock CLK I is switched in the middle of data streams S1 and S2. Therefore, each time the clock CLK I When different inputs of MUX 304 are switched and selected, two output symbols are generated. That is, in addition to Figure 3A CLK I The KDM-V300 enables the clock CLK to I Two symbols are output from MUX 304 on each falling edge and each rising edge of . As shown in timing diagram 216, the effect of this scheme is that the rate of each data stream DS1 and DS2 input to KDM-V 300 is doubled to achieve the final desired rate of transmission. Figure 3A In the example of FIG. 1 , the initial rate of each data stream DS1 and DS2 is 53.12 Gs / s, and the rate output by MUX 304 is 106.25 Gs / s. Here, the rate corresponds to the sampling rate, which is converted into the bit rate of data transmission after the symbol digital-to-analog conversion.

[0052] It will be appreciated that example embodiments employ a specific data arrangement of data streams DS1 and DS2 to ensure the correct order of output symbols. For example, data stream DS1 includes symbols S1, S2, S5, S6, S9, S10, S13, and S14, while data stream DS2 includes symbols S3, S4, S7, S8, S11, S12, and S15. The specific arrangement of symbols can be accomplished by controlling the PISO device 200 and / or the digital data source 120 so that upon entering MUX228, data stream DS1 includes the first two symbols S1 and S2 (and other symbols shown) in the output data, while the next data stream DS2 includes two symbols S3 and S4 (and other symbols shown) in the output data. The next symbol that appears after two consecutive symbols in each data stream depends on the number of data streams received by the KDM-V300. In at least one example embodiment, the next symbol that appears after two consecutive symbols in a data stream is equal to twice the number of data streams input to the modulator minus one. Therefore, in Figure 3A In the example, the number of data streams received by KDM-V300 is two, so the data stream DS1 is arranged so that symbol S5 appears after consecutive symbols S1 and S2 (i.e., (2 input streams x2 = 4–1 = symbol S5 as the next symbol appearing after S2 in DS1). The same data arrangement may apply to Figure 3A DS2 in , and may further be applicable to other numbers of data streams (e.g., see Figure 3B ).

[0053] like Figure 3A As shown, the MUX 304 is configured to receive a first data stream DS1 (having passed through the amplifier block 308) at a first rate including a plurality of first symbols S1, S2, S5, S6, S9, S10, S13 and S14. Figure 3A The first rate in corresponds to 53.125Gs / s. MUX304 is also configured to receive a second data stream DS2 (which has passed through amplifier block 312) including a plurality of second symbols S3, S4, S7, S8, S11, S12 and S15. MUX304 is configured to receive a second data stream DS2 (which has passed through amplifier block 312) based on a first clock signal CLK I The plurality of first symbols and the plurality of second symbols are selectively output to form a third data stream of output data DSO that achieves a second rate greater than a first rate at which the third data stream DSO is transmitted by the transmitter. Figure 3A The second rate in corresponds to 106.25Gs / s. Therefore, the second rate is at least twice the first rate. In this example, the clock signal CLK I The frequency of is 26.26 GHz (or one quarter of the rate of the third data stream DS0, or half of the rate of the first data stream DS1 and the second data stream DS2).

[0054] As shown in the timing diagram 316, each symbol in the plurality of first symbols and each symbol in the plurality of second symbols spans a first amount of time Tsymbol (18.8 ps in this example), while the first clock signal CLK I The period spans a second amount of time that is greater than the first time period. Figure 3A , the second time quantity corresponds to 37.6 ps. Therefore, the second time quantity is twice as long as the first time quantity.

[0055] Still referring to the timing diagram 316, MUX304 is configured to I During the first half cycle of the first clock signal CLK I During the second half cycle of the clock signal CLK I In the first (leftmost) cycle of , the first subset of the plurality of first symbols includes the first symbol S1 and the second symbol S2, and the second subset of the plurality of second symbols includes the third symbol S3 and the fourth symbol S4. As shown in the figure, in the third data stream DSO output from MUX304, the first symbol S1, the second symbol S2, the third symbol S3 and the fourth symbol S4 are arranged in sequence. Figure 3A (and Figure 3B ), the multiplexer 304 is implemented with voltage control. However, example embodiments are not limited thereto and the multiplexer 304 may be implemented with current control (see Fig. 6A and Figure 6B ). In this case, the same timing can be achieved for the current control implementation. Figure 3A In the example embodiment, it should be understood that the length of each symbol input to the KDM-V300 is reduced by half from 18.8ps to 9.4ps to achieve a higher rate of 106.25Gs / s. In at least one example embodiment, at least one of the first data stream and the second data stream is thermometer coded (see Figure 2 thm flow in).

[0056] Figure 3B A general schematic diagram of a K-input data modulator KDM300A implemented with voltage control (also referred to as KDM-V300A) is shown, along with a timing diagram 328 for controlling the KDM-V300A. Figure 3B Similar to Figure 3A , except that the KDM-V300A has four inputs to receive four data streams DS1 to DS4. The four data streams DS1 to DS4 are quarter rate streams received by the KDM-V300A at 26.56Gs / s, while the frequency of the clock signal CLKI is 13.28GHz, and the duty cycle of each stream is 25% to allow each stream to output the clock signal CLKI Two symbols per cycle of . Figure 3A Similarly, the symbols in the data streams DS1 to DS4 have a specific arrangement so that the clock signal CLK I During one of the four phases of , two consecutive symbols in each stream are output from MUX 304A (indicated by the thin bars under symbols S1 and S2, S3 and S4, S5 and S6, etc.). Figure 3B In the clock signal CLK I The period is 75.3ps, and the length of each input symbol is 37.65ps, which is shortened to 9.4ps in the output stream DSO, reaching a rate of 106.25Gs / s at the output of MUX304A. Figure 3A As shown, the clock signal CLK I It is half the rate of the input data streams DS1 to DS4 (13.28GHz vs. 26.56Gs / s).

[0057] Figure 4 In more detail, the Figure 3A The KDM-V300 is a two-bit series source terminated (SST) voltage mode DAC. The DAC that implements the KDM-V300 can be a single-ended output DAC or a differential output DAC (such as Figure 2 shown). Figure 4 The KDM-V example is shown for a single-ended output DAC. However, it should be understood that the KDM-V300 can be modified to process and output differential signals. In this case, the Figure 4 The components in the illustrated structure are modified to enable differential signals in the received data streams DS1 and DS2 and to output differential analog signals. Such modifications are within the capabilities of those of ordinary skill in the art.

[0058] like Figure 4 As shown, the KDM-V300 includes a first amplifier block 308, which is configured to receive the first bit and the second bit (LSB and MSB) of the two-bit data block of the first data stream DS1 at a first rate and output a first signal and a second signal based on the values ​​of the first bit and the second bit. The KDM-V300 also includes a second amplifier block 312, which is configured to receive the third bit and the fourth bit (LSB and MSB) of the two-bit data block of the second data stream DS2 at the first rate and output a third signal and a fourth signal based on the values ​​of the third bit and the fourth bit.

[0059] exist Figure 4In the example of , the first amplifier block 308 includes a first amplifier 308A configured to receive a first bit and output a first signal, and a second amplifier 308B configured to receive a second bit and output a second signal. In addition, the second amplifier block includes a third amplifier 312A configured to receive a third bit and output a third signal, and a fourth amplifier 312B configured to receive a fourth bit and output a fourth signal. Figure 4 In the first data stream DS1, the first bit (LSB) is a less significant bit than the second bit (MSB), and in the second data stream DS2, the third bit (LSB) is a less significant bit than the fourth bit (MSB). As shown by the 1x and 2x symbols, the gain of the second amplifier 308A and the fourth amplifier 312A is at least twice the gain of the first amplifier 308B and the third amplifier 312B to ensure appropriate signal strength for digital-to-analog conversion.

[0060] Figure 4 Also shown is a modulator 304 configured to receive the first signal, the second signal, the third signal, and the fourth signal, and selectively output symbols of the first signal, the second signal, the third signal, and the fourth signal based on the first clock signal to form a third data stream DSO having a second rate greater than the first rate (see timing diagram 316 in FIG. 3 ). The modulator 304 includes a first multiplexer block 304-1 configured to receive the first signal and the second signal and output symbols of the first signal, the second signal, the third signal, and the fourth signal based on the first clock signal CLK I The modulator 304 further includes a second multiplexer block 304-2, which is configured to receive the third signal and the fourth signal and output the symbols of the first signal and the second signal according to the first clock signal CLK I_n The reciprocal of outputs the signs of the third signal and the fourth signal.

[0061] As further shown, the first multiplexer block 304-1 includes a first output MSB1 configured to output a symbol of the first signal and a second output LSB1 configured to output a symbol of the second signal. The second multiplexer block 304-2 includes a first output MSB2 configured to output a symbol of the third signal and a second output LSB2 configured to output a symbol of the fourth signal. The first output MSB1 of the first multiplexer block 304-1 is connected to the first output MSB2 of the second multiplexer block 304-2, and the second output LSB1 of the first multiplexer block 304-1 is connected to the second output LSB2 of the second multiplexer block 304-2.

[0062] Figure 4Also shown is a conversion circuit 400 configured to receive symbols of a third data stream DSO and output analog signals representing the first data stream DS1 and the second data stream DS2. In this case, the third data stream DSO is formed by a combination of the outputs LSB1, MSB2, LSB2, and MSB2. The conversion circuit 400 includes a voltage divider circuit connected to the first output and the second output of both the first multiplexer block and the second multiplexer block. The voltage divider circuit is as shown in FIG. Figure 4 , with resistors RT1, RT2 and a load resistor RL. The values ​​of these resistors are design parameters that are set based on empirical evidence and / or preference, and may be weighted differently.

[0063] As mentioned above, Figure 4 In more detail, the Figure 3A However, the same details apply to Figure 3B The KDM-V300A in the example above only doubles the number of amplifier blocks and multiplexer blocks to handle the two additional data streams DS3 and DS4. The outputs of the two additional multiplexer blocks are connected to the same Figure 4 The outputs of multiplexer locks 304-1 and 304-2 are connected in the same manner as shown (ie, MSB1, MSB2 and outputs MSB3 and MSB4 not shown are connected together, and LSB1, LSB2 and outputs LSB3 and LSB4 not shown are connected together).

[0064] Figure 5 According to at least one example embodiment, the Figure 2 DAC204. However, Figure 5 The DAC 204 in the example is a 7-bit DAC and therefore does not include Figure 2 Receive input of data bin5<1:0>. DAC 204 is a 7-bit DAC, where bin0 to bin4 represent the first to fifth bits of the data block, thm0 represents the sixth bit of the data block twice higher than bit bin4, and the combination of thm1 and thm2 represents the seventh bit of the data block twice higher than bit thm0. In at least one example embodiment, the bits of thm1 and thm2 are processed together to form the seventh bit of the data block. Including thermometer coded bits thm0, thm1, and thm2 with binary coded bits bin0 to bin4 in the data block can help mitigate mismatches between DAC units because, for example, Figure 5 As shown, each DAC unit receiving a binary coded bit is scaled by double for each next most significant bit. Using thermometer coded bits as the most significant bits in a data block means that additional scaling can be avoided for DAC units receiving bits thm0, thm1, and thm2, thereby reducing component mismatches between DAC units (e.g., amplifier and / or resistor mismatches).

[0065] like Figure 5 As shown, DAC204 includes a plurality of KDM DAC units. As shown for the data stream at position bin3, each DAC unit may include a Figure 2 3. As further shown, the multiplexer 228 is a 2:1 multiplexer that outputs the bits of each stream DS1 and DS2 to the corresponding amplifier blocks 308 and 312. From there, the KDM-V 300 and the conversion circuit 236 (including two resistors RT) operate as described above to output analog signals at an increased speed compared to the data speed input to the DAC 204. Here, it should be understood that Figure 5 A simplified version of the KDM DAC unit receiving bit bin3 is shown. In practice and as described above with reference to Figure 4 As described above, each KDM DAC unit can be modified to process and output a differential signal or a single-ended signal according to the knowledge of a person of ordinary skill in the art.

[0066] Figure 5 Further shown are inverter blocks 500 and 504 to provide a corresponding clock signal CLK to one side of the corresponding MUX 228 and 304. Q and CLK I The inverted version of .

[0067] Figure 5Each KDM DAC unit in includes the names x0.25, x0.5, x1, x2, x4, and x8. These names indicate the gain values ​​of the amplifiers in the amplifier blocks in the KDM DAC units and the resistors in the conversion circuit 236 relative to the base value of the amplifier gain and the base value of the resistors. That is, each name indicates the weights applied to the amplifiers and resistors in a particular KDM DAC unit. Weights can be applied in an inverse manner to the gain values ​​of the amplifiers and the resistance values ​​of the resistors. For example, KDM DAC unit x1 means that the gain value of the amplifier in the corresponding KDM-V300 and the value of the resistor in the corresponding conversion circuit 236 are equal to a given basic gain and a given basic resistance value, while KDM DAC unit x2 means that the gain value is twice the basic gain value and the resistance value is halved compared to the basic resistance value. At the same time, KDM DAC x0.5 means that the gain value is half the basic gain and the resistance value is twice the basic resistance value, while KDM DAC x4 means that the gain value is four times the basic gain value and the resistance value is one quarter of the basic resistance value. Similar logic applies to the remaining KDM DAC units. Weighting can be accomplished by adjusting the gain and resistor values ​​within each KDM-V 300 and / or by placing one or more additional KDM-V 300 in parallel. These weights are used to ensure that each input bit has the appropriate effect on the final analog signal. As mentioned above, the scaling of the DAC cells receiving bits thm0, thm1, and thm2 remains at x8 (rather than x16 and x32) because these bits are thermometer coded rather than binary coded.

[0068] Given that Figures 1 to 5 , example embodiments provide a transmitter 124 including a PISO device 200 configured to receive parallel input data and output serialized data at a first rate. The transmitter 124 also includes a DAC 204. The DAC includes a first amplifier block 308 configured to receive a first bit and a second bit of a first data stream of serialized data at the first rate and output a first signal and a second signal based on values ​​(e.g., binary values) of the first bit and the second bit. The DAC includes a second amplifier block 312 configured to receive a third bit and a fourth bit of a second data stream of serialized data at the first rate and output a third signal and a fourth signal based on values ​​(e.g., binary values) of the third bit and the fourth bit. The first bit, the second bit, the third bit, and the fourth bit of the data may be input to the first amplifier block and the second amplifier block according to a predetermined arrangement (see Figure 3A and Figure 3B). The DAC includes a multiplexer 304 configured to receive the first signal, the second signal, the third signal, and the fourth signal, and selectively output symbols of the first signal, the second signal, the third signal, and the fourth signal based on the first clock signal to form a third data stream DSO having a second rate greater than the first rate. The DAC also includes a conversion circuit configured to receive symbols of the third data stream from the modulator and output an analog signal representing the third data stream. The second rate may be twice the first rate. The transmitter 124 may also include a first signal generator 216 configured to apply the first clock signal to the multiplexer and a second signal generator 212 configured to apply the second clock signal to the PISO device 200.

[0069] Example embodiments have been discussed with respect to KDM implemented with voltage control. However, example embodiments are not limited thereto, and KDM may be implemented with current control, as discussed in more detail below.

[0070] Fig. 6A A DAC 600 including a data modulator 604 implemented with current control is shown according to at least one example embodiment. The DAC 600 implemented with current control may replace the DAC implemented with voltage control described above.

[0071] like Fig. 6A As shown, the data modulator 604 can be implemented by a multiplexer, which includes a clock signal CLKn and CLKp (which can correspond to CLK in the description of the previous figure). I ) driven by a plurality of switches, wherein the clock signal CLKn is the inverse of the clock signal CLKp. DAC 600 also includes amplifier blocks 608 and 612 that receive data from the corresponding data streams DA1 and DS2. DAC 600 is a two-bit DAC, so each amplifier block 608 and 612 includes two current sources I LSB and 2I LSB , each current source is connected to two switches. Similar to the weighting of the KDM-V 300 amplifier discussed above, the current source 2I LSB A current source I connected to the switch receiving the MSB and output connected to the switch receiving the LSB LSB In the case where the input data is binary coded, the signal output from each amplifier block 608 and 612 may have a current of twice the current value 0I LSB ,I LSB , 2I LSB or 3I LSB Since DAC 600 is a two-bit DAC, each current value indicates four possible states of digital input data (e.g., 00=0I LSB 、01=I LSB、10=2I LSB 、11=3I LSB ).

[0072] The DAC 600 also includes a conversion circuit 616 that converts the signal output from the data modulator 604 into a differential voltage signal Voutp / Voutn as an analog signal output from the DAC 600 .

[0073] Here, it should be understood that the above-described DAC 600 using current control is a very high-speed design when the current source is operated continuously (i.e., turning the current source on and off slows down the operation). Since the modulator 604 multiplexes only one current source at a time to the output, the other current sources can be turned off. To overcome this problem, the DAC 600 includes a dummy load that sinks or sources current from the unused current sources. The dummy load in FIG6 is represented by resistor R2, which ensures that the current source remains active when not in use.

[0074] Figure 6B FIG. 6 shows an N-bit DAC 600A including a modulator 604A implemented with current control according to at least one example embodiment. The modulator 604A and the conversion circuit 616A are Fig. 6A The modulator 604 and conversion circuit 616 in FIG. 6 are substantially the same. However, amplifier blocks 608A and 612A are configured to process N bits of input data from data streams DS1 and DS2. Therefore, each amplifier block 608A and 612A includes N sets of switches connected to N current sources. To achieve the same weighting as above, 2I LSB Each additional current source beyond the current source outputs twice the current of the immediately preceding current source. For example, for a three-bit DAC, the third current source in each amplifier 608A and 612A has an output amplitude of I LSB or 4I LSB Four times the current.

[0075] In view of the foregoing, it should be understood that the present inventive concept is particularly directed to a transmitter using an ultra-high speed and low power data modulator that can be implemented in a SerDes system. Notably, there are no active devices in the transmitter that operate at full rate output data. Instead, there is a specific combination and timing of low rate data and clock multiplexing that generates a full rate data signal at the output of the KDM through passive devices, thereby reducing power consumption while still operating at high speed.

[0076] Specific details are given in the description to provide a thorough understanding of the embodiments. However, one of ordinary skill in the art will appreciate that the embodiments can be practiced without these specific details. In other cases, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail to avoid obscuring the embodiments.

[0077] While exemplary embodiments of the present disclosure have been described in detail herein, it should be understood that the inventive concepts may be otherwise variously embodied and employed, and that the appended claims are intended to be interpreted to include such variations unless limited by the prior art.

[0078] It should be understood that the inventive concept covers the combination of any one or more other embodiments, any one or more features disclosed herein, any one or more features substantially disclosed herein, any one or more features substantially disclosed herein with any one or more other features substantially disclosed herein, any one aspect / feature / embodiment in combination with any one or more other aspects / features / embodiments, and the use of any one or more embodiments or features disclosed herein. It should be understood that any feature described herein may be claimed in combination with any other feature described herein, regardless of whether these features are from the same described embodiment.

[0079] Example implementations may be configured as follows:

[0080] (1) A data modulator for a transmitter, the data modulator comprising:

[0081] Multiplexer, which is configured as:

[0082] receiving a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols at a first rate; and

[0083] Based on a first clock signal, the plurality of first symbols and the plurality of second symbols are selectively output to form a third data stream, the third data stream achieving a second rate greater than the first rate for transmission of the third data stream by the transmitter.

[0084] (2) A data modulator according to (1), wherein the second rate is at least twice the first rate.

[0085] (3) A data modulator according to one or more of (1) to (2), wherein each of the plurality of first symbols and each of the plurality of second symbols spans a first amount of time, and wherein a period of the first clock signal spans a second amount of time greater than the first amount of time.

[0086] (4) A data modulator according to one or more of (1) to (3), wherein the second amount of time is twice as long as the first amount of time.

[0087] (5) A data modulator according to one or more of (1) to (4), wherein the multiplexer is configured to output a first subset of the multiple first symbols during a first half cycle of the first clock signal, and to output a second subset of the multiple second symbols during a second half cycle of the first clock signal.

[0088] (6) A data modulator according to one or more of (1) to (5), wherein the first subset of the plurality of first symbols includes a first symbol and a second symbol, and wherein the second subset of the plurality of second symbols includes a third symbol and a fourth symbol.

[0089] (7) The data modulator according to one or more of (1) to (6), wherein a first symbol, a second symbol, a third symbol, and a fourth symbol are arranged in order in the third data stream output from the multiplexer.

[0090] (8) The data modulator according to one or more of (1) to (7), wherein the multiplexer is implemented by voltage control.

[0091] (9) The data modulator according to one or more of (1) to (8), wherein the multiplexer is implemented by current control.

[0092] (10) A data modulator according to one or more of (1) to (9), wherein at least one of the first data stream and the second data stream is thermometer coded.

[0093] (11) A digital-to-analog converter (DAC), comprising:

[0094] a first amplifier block configured to receive a first bit and a second bit of a first data stream at a first rate and output a first signal and a second signal based on values ​​of the first bit and the second bit;

[0095] a second amplifier block configured to receive third and fourth bits of the second data stream at the first rate and output third and fourth signals based on values ​​of the third and fourth bits;

[0096] a modulator configured to receive the first signal, the second signal, the third signal, and the fourth signal and selectively output symbols of the first signal, the second signal, the third signal, and the fourth signal based on a first clock signal to form a third data stream having a second rate greater than the first rate; and

[0097] A conversion circuit is configured to receive the symbols of the third data stream and output analog signals representing the first data stream and the second data stream.

[0098] (12) A DAC according to (11), wherein the first amplifier block includes a first amplifier configured to receive the first bit and output the first signal, and a second amplifier configured to receive the second bit and output the second signal, and wherein the second amplifier block includes a third amplifier configured to receive the third bit and output the third signal, and a fourth amplifier configured to receive the fourth bit and output the fourth signal.

[0099] (13) A DAC according to one or more of (11) to (12), wherein the first bit in the first data stream is a less significant bit than the second bit, wherein the third bit in the second data stream is a less significant bit than the fourth bit, and wherein the gains of the second amplifier and the fourth amplifier are at least twice the gains of the first amplifier and the third amplifier.

[0100] (14) A DAC according to one or more of (11) to (13), wherein the modulator includes a first multiplexer block configured to receive the first signal and the second signal and output the signs of the first signal and the second signal according to the first clock signal, and a second multiplexer block configured to receive the third signal and the fourth signal and output the signs of the third signal and the fourth signal according to the inverse of the first clock signal.

[0101] (15) A DAC according to one or more of (11) to (14), wherein the first multiplexer block includes a first output configured to output a symbol of the first signal and a second output configured to output a symbol of the second signal, and wherein the second multiplexer block includes a first output configured to output a symbol of the third signal and a second output configured to output a symbol of the fourth signal.

[0102] (16) A DAC according to one or more of (11) to (15), wherein the first output of the first multiplexer block is connected to the first output of the second multiplexer block, and wherein the second output of the first multiplexer block is connected to the second output of the second multiplexer block.

[0103] (17) A DAC according to one or more of (11) to (16), wherein the conversion circuit includes a voltage divider circuit connected to the first output and the second output of both the first multiplexer block and the second multiplexer block.

[0104] (18) A transmitter comprising:

[0105] a parallel-input serial-output (PISO) device configured to receive parallel input data and output serialized data at a first rate; and

[0106] Digital-to-analog (DAC) converters, including:

[0107] a first amplifier block configured to receive a first bit and a second bit of a first data stream of the serialized data at the first rate and output a first signal and a second signal based on values ​​of the first bit and the second bit;

[0108] a second amplifier block configured to receive a third bit and a fourth bit of a second data stream of the serialized data at the first rate and output a third signal and a fourth signal based on values ​​of the third bit and the fourth bit, wherein the first bit, the second bit, the third bit, and the fourth bit of data are received by the first amplifier block and the second amplifier block according to a predetermined arrangement;

[0109] a modulator configured to receive the first signal, the second signal, the third signal, and the fourth signal and selectively output symbols of the first signal, the second signal, the third signal, and the fourth signal based on a first clock signal to form a third data stream having a second rate greater than the first rate; and

[0110] A conversion circuit is configured to receive symbols of the third data stream from the modulator and output an analog signal representing the third data stream.

[0111] (19) The transmitter of claim 18, wherein the second rate is twice the first rate.

[0112] (20) The transmitter of claim 18, further comprising:

[0113] a first signal generator configured to apply the first clock signal to the modulator; and

[0114] A second signal generator is configured to apply a second clock signal to the PISO device.

Claims

1. A data modulator for a transmitter, the data modulator comprising: A multiplexer, the multiplexer being configured to: receiving a first data stream including a plurality of first symbols and a second data stream including a plurality of second symbols at a first rate; as well as Based on a first clock signal, the plurality of first symbols and the plurality of second symbols are selectively output to form a third data stream, the third data stream achieving a second rate greater than the first rate for transmission of the third data stream by the transmitter, wherein the multiplexer is configured to output a first subset of the plurality of first symbols during a first half cycle of the first clock signal, and to output a second subset of the plurality of second symbols during a second half cycle of the first clock signal, wherein the first subset of the plurality of first symbols includes a first symbol and a second symbol, wherein the second subset of the plurality of second symbols includes a third symbol and a fourth symbol, wherein the first symbol, the second symbol, the third symbol, and the fourth symbol are sequentially arranged in the third data stream output from the multiplexer.

2. The data modulator of claim 1, wherein the second rate is at least twice the first rate.

3. The data modulator of claim 1, wherein each symbol of the plurality of first symbols and each symbol of the plurality of second symbols spans a first amount of time, and wherein a period of the first clock signal spans a second amount of time greater than the first amount of time.

4. The data modulator of claim 3, wherein the second amount of time is twice as long as the first amount of time.

5. The data modulator of claim 1, wherein the multiplexer is implemented by voltage control.

6. The data modulator of claim 1, wherein the multiplexer is implemented by current control.

7. The data modulator of claim 1, wherein at least one of the first data stream and the second data stream is thermometer coded.

8. A digital-to-analog converter (DAC), comprising: a first amplifier block configured to receive a first bit and a second bit of a first data stream at a first rate and output a first signal and a second signal based on values ​​of the first bit and the second bit; a second amplifier block configured to receive third and fourth bits of the second data stream at the first rate and output third and fourth signals based on values ​​of the third and fourth bits; a modulator configured to receive the first signal, the second signal, the third signal, and the fourth signal and selectively output symbols of the first signal, the second signal, the third signal, and the fourth signal based on a first clock signal to form a third data stream having a second rate greater than the first rate, wherein the modulator is configured to output a first subset of a plurality of first symbols during a first half cycle of the first clock signal and to output a second subset of a plurality of second symbols during a second half cycle of the first clock signal, wherein the first subset of the plurality of first symbols includes a first symbol and a second symbol, wherein the second subset of the plurality of second symbols includes a third symbol and a fourth symbol, and wherein the first symbol, the second symbol, the third symbol, and the fourth symbol are sequentially arranged in the third data stream output from the modulator; and A conversion circuit is configured to receive the symbols of the third data stream and output analog signals representing the first data stream and the second data stream.

9. The DAC of claim 8 , wherein the first amplifier block includes a first amplifier configured to receive the first bit and output the first signal, and a second amplifier configured to receive the second bit and output the second signal, and wherein the second amplifier block includes a third amplifier configured to receive the third bit and output the third signal, and a fourth amplifier configured to receive the fourth bit and output the fourth signal.

10. The DAC of claim 9, wherein the first bit is a less significant bit than the second bit in the first data stream, wherein the third bit is a less significant bit than the fourth bit in the second data stream, and wherein the gains of the second and fourth amplifiers are at least twice the gains of the first and third amplifiers.

11. The DAC of claim 8, wherein the modulator comprises a first multiplexer block configured to receive the first and second signals and output signs of the first and second signals according to the first clock signal, and a second multiplexer block configured to receive the third and fourth signals and output signs of the third and fourth signals according to the inverse of the first clock signal.

12. The DAC of claim 11 , wherein the first multiplexer block comprises a first output configured to output a sign of the first signal and a second output configured to output a sign of the second signal, and wherein the second multiplexer block comprises a first output configured to output a sign of the third signal and a second output configured to output a sign of the fourth signal.

13. The DAC of claim 12, wherein the first output of the first multiplexer block is connected to the first output of the second multiplexer block, and wherein the second output of the first multiplexer block is connected to the second output of the second multiplexer block.

14. The DAC of claim 13, wherein the conversion circuit comprises a voltage divider circuit connected to the first and second outputs of both the first and second multiplexer blocks.

15. A transmitter comprising: a parallel-input serial-output (PISO) device configured to receive parallel input data and output serialized data at a first rate; and Digital-to-analog (DAC) converters, including: a first amplifier block configured to receive a first bit and a second bit of a first data stream of the serialized data at the first rate and output a first signal and a second signal based on values ​​of the first bit and the second bit; a second amplifier block configured to receive a third bit and a fourth bit of a second data stream of the serialized data at the first rate and to output a third signal and a fourth signal based on values ​​of the third bit and the fourth bit, wherein the first bit, the second bit, the third bit, and the fourth bit of data are received by the first amplifier block and the second amplifier block according to a predetermined arrangement; a modulator configured to receive the first signal, the second signal, the third signal, and the fourth signal, and selectively output symbols of the first signal, the second signal, the third signal, and the fourth signal based on a first clock signal to form a third data stream having a second rate greater than the first rate, wherein the modulator is configured to output a first subset of a plurality of first symbols during a first half cycle of the first clock signal, and to output a second subset of a plurality of second symbols during a second half cycle of the first clock signal, wherein the first subset of the plurality of first symbols includes a first symbol and a second symbol, wherein the second subset of the plurality of second symbols includes a third symbol and a fourth symbol, and wherein the first symbol, the second symbol, the third symbol, and the fourth symbol are arranged in sequence in the third data stream output from the modulator; and A conversion circuit is configured to receive symbols of the third data stream from the modulator and output an analog signal representing the third data stream.

16. The transmitter of claim 15, wherein the second rate is twice the first rate.

17. The transmitter of claim 15, further comprising: a first signal generator configured to apply the first clock signal to the modulator; and A second signal generator is configured to apply a second clock signal to the PISO device.

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