Implementation method and system of fence instruction in l2
By allocating fence requests to CWQ in the CPU system and returning to sync_done after the valid information becomes invalid, the performance degradation caused by fence instructions preventing instructions from entering L2 is solved, thus improving CPU performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG STARFIVE TECH LTD
- Filing Date
- 2022-06-14
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the fence instruction prevents new instructions from entering L2 when executed in the CPU system, resulting in a decrease in overall performance.
By assigning fence requests to CWQ for arbitration and sending sync_done back to lsu after the valid information becomes invalid, while also supporting snapshot functionality to allow new instructions to enter the pipeline, queue resources are released to receive more reload requests.
This allows for the release of queue resources without preventing new instructions from entering L2, enabling the system to receive more reload requests from the core and improving CPU performance.
Smart Images
Figure CN114996015B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of CPU technology, and specifically to a method and system for implementing the fence instruction in L2. Background Technology
[0002] In a CPU system, to ensure that the results of previous instructions are visible before a new instruction is executed, the fence instruction is often used. Simply put, the fence instruction ensures that the instructions following the fence instruction must wait until both the fence instruction and the instructions preceding the fence instruction have been executed in L2 before the subsequent instructions can continue to execute. Of course, a simple approach is to prevent new instructions from entering L2 after the fence instruction appears, which seriously affects the overall performance of the CPU.
[0003] Therefore, this paper provides a method and system for implementing fence instructions in L2, which not only does not prevent new instructions from entering L2, but also allows the corresponding reload instructions to be added to the pipeline, releasing the queue that receives requests from the core to receive more reload requests from the core. Summary of the Invention
[0004] To address the shortcomings of existing technologies, this invention discloses a method and system for implementing fence instructions in L2, which solves the aforementioned problems.
[0005] This invention is achieved through the following technical solution:
[0006] In a first aspect, the present invention provides a method for implementing the fence instruction in L2, comprising the following steps:
[0007] S1 initializes the fence request and assigns it to CWQ, thereby participating in and winning arbitration.
[0008] S2 uses allocate orq to capture the valid information of the current orq / wrq / cpq;
[0009] After S3 completes the process of invalidating the valid data in orq / wrq / ocsq snapshots, it sends sync_done back to lsu.
[0010] Furthermore, in the method described, L2 performs the following steps:
[0011] T1 receives requests from the core and external extends, and also receives requests from CRQ, CWQ, EPQ, ORQ, EFQ, and CPQ, and selects one of these requests to enter the pipeline.
[0012] T2 generates a relevant allocation scheme based on the request type and the TAG and MESI status information in the current L2.
[0013] T3 sends read or write requests to downstream memory via L2, and the downstream memory returns reload data to populate EFQ;
[0014] T4 uses the L2de pipeline on EFQ to write the reloaded data into L2$, and simultaneously returns the data to the requesting core.
[0015] Furthermore, in the method, L2 receives requests from the core and external extend, including receiving read requests from the core and placing them in the CRQ; receiving write requests from the core and placing them in the CWQ; and receiving probe requests from external sources and placing them in the EPQ.
[0016] Furthermore, in the method, within the pipeline, based on the request type and the current TAG and MESI status information in L2, it is determined whether: data can be directly written to L2; whether data can be directly returned to the requester; whether it is necessary to reload data or grant permissions to downstream memory; whether an evict needs to be generated; whether it is necessary to write data to downstream memory; and whether it is necessary to probe the core. If it is determined that data reload or permissions to downstream memory are needed, an ORQ is allocated; if it is determined that data write to downstream memory is needed, a WRQ is allocated; and if it is determined that a probe to the core is needed, a CPQ is allocated. L2 sends probe requests to the core, all of which are accomplished through CPQ.
[0017] Furthermore, in the method, when a read request is sent to the downstream memory via L2, it is sent via ORQ to read the data from the downstream memory and obtain the corresponding permissions; when a write request is sent to the downstream memory via L2, it is sent via WRQ to write the data from L2 to the next level memory.
[0018] Secondly, the present invention provides a system for implementing L2 fence instructions, the system being used to implement the L2 fence instruction implementation method described in the first aspect, including probe, eviction, TAG RAM, DATA RAM, CRQ, CWQ, EPQ, ORQ, WRQ, EFQ, and CPQ.
[0019] Furthermore, the probe is used for spying and listening, probing dirty data in the core or modifying the MESI status information in the core in order to obtain E privileges;
[0020] The eviction is used to keep the data stored in the cache relatively new, and is generated when data needs to be replaced out of the cache;
[0021] The TAG RAM is used to record the cacheline's addr and the cacheline's MESI status information in L2 and all L2 cores;
[0022] The DATA RAM is used to record cacheline data information;
[0023] The CRQ is a queue used to receive read requests from the core.
[0024] The CWQ is a queue used to receive write requests from the core;
[0025] The EPQ is a queue used to receive probe requests from external sources;
[0026] The ORQ is used when a request in L2, after being uploaded to the L2 pipeline, finds that the cacheline does not exist in the current cache or that the access permissions of the cacheline in the current cache are insufficient. In this case, an ORQ needs to be requested, and the data is reloaded to the next level of memory through the ORQ to obtain the corresponding permissions.
[0027] The WRQ is used when L2 needs to write a certain cacheline to the next level of memory. In this case, a request is made to provide a WRQ, and the data is written to the next level of memory through the WRQ.
[0028] The EFQ is used to first fill the data back into the EFQ when the L2 is filled by reload data, and then write the data to L2$ through the L2 pipeline on the EFQ while returning the data to the request module.
[0029] The CPQ is used to probe the corresponding core. The probe request is first stored in the CPQ, and then the probe request is sent to the corresponding core through the CPQ.
[0030] The beneficial effects of this invention are as follows:
[0031] This invention does not prematurely prevent the core from making requests to L2; it does not prematurely prevent new requests from being added to the pipeline; and by adding new instructions to the pipeline, it releases queue resources, allowing it to receive more reload requests from the core. It is highly practical. Attached Figure Description
[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0033] Figure 1 This is a basic block diagram of embodiment L2 of the present invention;
[0034] Figure 2 This is a flowchart illustrating how the fence function is implemented in an embodiment of the present invention, which does not support the snapshot function.
[0035] Figure 3 This is a flowchart illustrating how the snapshot function is supported and the fence function is implemented in an embodiment of the present invention. Detailed Implementation
[0036] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0037] Example 1
[0038] This embodiment provides a method for implementing the fence instruction in L2, including the following steps:
[0039] S1 initializes the fence request and assigns it to CWQ, thereby participating in and winning arbitration.
[0040] S2 uses allocate orq to capture the valid information of the current orq / wrq / cpq;
[0041] After S3 completes the process of invalidating the valid data in orq / wrq / ocsq snapshots, it sends sync_done back to lsu.
[0042] This embodiment supports the snapshot function. After the fence command enters the pipeline, it does not prevent new requests from CRQ / CWQ / EPQ from entering the pipeline. When new commands enter the pipeline, queue resources are released, allowing more reload requests from the core to be received.
[0043] This embodiment does not prematurely prevent new requests from being added to the pipeline. Adding new instructions to the pipeline releases queue resources, allowing more reload requests from the core to be received.
[0044] Example 2
[0045] At other levels, this embodiment provides an L2 operating mode, the block diagram of which is as follows: Figure 1 As shown, its basic functions are described below:
[0046] Receive requests from the core and external extends, including
[0047] Receive read requests from the core and place them in the CRQ (core read queue);
[0048] Receive write requests from the core and place them in the CWQ (core write queue);
[0049] Receive probe requests from external sources and place them in the EPQ (extend probe queue);
[0050] The arbitration module receives requests from CRQ, CWQ, EPQ, ORQ, EFQ, and CPQ, and selects one of these requests to enter the pipeline.
[0051] In the pipeline, the following is determined based on the request type, and the current L2 TAG and MESI status information:
[0052] Can data be written directly to L2? Can data be returned directly to the requester? Is it necessary to reload data or grant permissions to downstream memory? Is it necessary to generate an evict? Is it necessary to write data to downstream memory? Is it necessary to probe the core?
[0053] In this embodiment, if it is determined that data or permissions need to be reloaded to the downstream memory, an ORQ (outstanding request queue) is allocated.
[0054] In this embodiment, if it is determined that data needs to be written to the downstream memory, a WRQ (writerequet queue) is allocated.
[0055] In this embodiment, if it is determined that a probe core is needed, a CPQ (core probe queue) is allocated. L2 sends probe requests to the core, and all of these are done through the CPQ (core probe queue).
[0056] L2 sends a request to the downstream memory:
[0057] Read requests are sent through an ORQ (outstanding request queue) to read data from downstream memory and obtain the corresponding permissions.
[0058] For write requests, data is written from L2 to the next level of memory via WRQ (write request queue).
[0059] Downstream memory returns reloaded data to fill the EFQ (Extend fill queue).
[0060] Then, the data reloaded from the EFQ (Extend fill queue) pipeline is written into L2$, and the data is returned to the requested core.
[0061] Example 3
[0062] This embodiment provides a protocol for maintaining data consistency in a memory system, used to indicate the permissions granted to the current core of the cacheline, as follows:
[0063] M:modify indicates that the core has modified the cacheline. This cacheline only exists in this cache. If other caches need to access this cacheline, they need to use the probe function to obtain the latest dirty data and acquire the corresponding permissions.
[0064] E:Exclusive indicates that the cacheline exists only in this cache. If other caches need to access the cacheline, they need to obtain the corresponding data and permissions through probe.
[0065] S:Shared indicates that the cacheline exists not only in this cache but may also exist in other caches. If other caches need to access the cacheline and obtain E / M status, they need to obtain the corresponding data and permissions through probe.
[0066] I:Invalid indicates that the cacheline is not in this cache.
[0067] Example 4
[0068] At the implementation level, refer to Figure 2 As shown, this embodiment provides a process for implementing the fence function without supporting the snapshot function, as detailed below:
[0069] Fence requests are assigned to the CWQ (core write queue);
[0070] The core write queue will participate in the fence request and win arbitration, putting it on the pipeline while preventing CRQ / CWQ / EPQ requests from going on the pipeline again;
[0071] Once orq / wrq / cpq are all empty, return sync_done to lsu, and allow crq / cwq / esq requests to go back onto the pipeline.
[0072] Reference Figure 3 As shown, this embodiment also provides a process for supporting the snapshot function and implementing the fence function, as detailed below:
[0073] Fence requests are assigned to the core write queue;
[0074] The core write queue participates in the fence request and wins arbitration.
[0075] Allocate orq, and take a snapshot of the valid information of the current orq / wrq / cpq;
[0076] Until the valid value of the orq / wrq / ocsq snapshot has changed from valid to invalid, it is returned to sync_done to lsu.
[0077] In this embodiment, as can be seen from the above process, supporting the snapshot function and implementing the fence function has the following advantages: after the fence instruction enters the pipeline, it will not prevent new requests from CRQ / CWQ / EPQ from entering the pipeline. This can prevent new requests from entering the pipeline too early. When new instructions enter the pipeline, the queue resources are released and more reload requests from the core can be received.
[0078] Example 5
[0079] This embodiment provides a system for implementing the fence instruction in L2, specifically including:
[0080] probe: eavesdropping and monitoring. In a multi-core environment, in order to maintain data consistency, it is necessary to probe the dirty data in the core or modify the MESI status information in the core in order to obtain E privileges.
[0081] Eviction: Due to the limited capacity of the cache, in order to keep the data stored in the cache relatively new, eviction occurs when data needs to be replaced in the cache.
[0082] TAG RAM: Records the cacheline's address and the MESI status information of that cacheline in L2 and all L2 cores.
[0083] DATA RAM: Records cacheline data information.
[0084] CRQ (core read queue): A queue that receives and stores read requests from the core.
[0085] CWQ (core write queue): A queue that receives write requests from the core.
[0086] EPQ (extend probe queue): A queue that receives probe requests from external sources.
[0087] ORQ (Outstanding Request Queue): When a request in L2 reaches the L2 pipeline, and it is found that the cacheline does not exist in the current cache or the access permissions of the cacheline in the current cache are insufficient, an ORQ needs to be requested. The ORQ is used to reload data to the next level of memory and obtain the corresponding permissions.
[0088] WRQ (write request queue): When L2 needs to write a certain cacheline to the next level of memory, it requests a WRQ, and the data is written to the next level of memory through the WRQ.
[0089] EFQ (Extend fill queue): When reloaded data fills L2, the data is first filled into EFQ, and then written to L2$ through the L2 pipeline on EFQ, while returning the data to the request module.
[0090] CPQ (core probe queue): Since multiple cores are attached to an L2 module, the latest data needed by a module core may be in other cores, or a core may need to obtain E / M permissions. In this case, the corresponding core needs to be probed. The probe request is first stored in CPQ, and then a probe request is sent to the corresponding core through CPQ.
[0091] In summary, this invention does not prematurely prevent the core from sending requests to L2; it does not prematurely prevent new requests from being added to the pipeline; and by adding new instructions to the pipeline, it releases queue resources, allowing it to receive more reload requests from the core. It is highly practical.
[0092] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for implementing the fence instruction in L2, characterized in that, The method includes the following steps: S1 initialization assigns fence requests to CWQ, which then participate in and win arbitration; S2 uses allocate orq to capture the valid information of the current orq / wrq / cpq; After S3 returns sync_done to lsu after the valid value for orq / wrq / cpq snapshots has changed from valid to invalid, S3 returns sync_done to lsu. The method supports snapshot functionality. After the fence instruction enters the pipeline, it does not prevent new requests from orq / wrq / cpq from entering the pipeline. When new instructions enter the pipeline, queue resources are released, allowing more reload requests from the core to be received.
2. The method for implementing the fence instruction in L2 according to claim 1, characterized in that, In the method described, L2 operates by including the following steps: T1 receives requests from the core and external extend, as well as requests from CRQ, CWQ, EPQ, orq, EFQ, and cpq, and selects one of these requests to enter the pipeline. T2 generates a relevant allocation scheme based on the request type and the TAG and MESI status information in the current L2. T3 sends read or write requests to downstream memory via L2, and the downstream memory returns reload data to fill EFQ; T4 uses the L2de pipeline on EFQ to write the reloaded data into L2$, and simultaneously returns the data to the requesting core.
3. The method for implementing the fence instruction in L2 according to claim 2, characterized in that, In the method, L2 receives requests from the core and external extend, including receiving read requests from the core and placing them in the CRQ; receiving write requests from the core and placing them in the CWQ; and receiving probe requests from external sources and placing them in the EPQ.
4. The method for implementing the fence instruction in L2 according to claim 2, characterized in that, In the method, within the pipeline, it is determined whether direct writing to L2 is possible based on the request type and the current TAG and MESI status information in L2. Can data be directly returned to the requester? Is it necessary to reload data or grant permissions to downstream memory? Is it necessary to generate an evict? Is it necessary to write data to downstream memory? Whether to probe the core; if it is determined that data reload or permissions need to be sent to downstream memory, an ORQ is allocated; if it is determined that data write needs to be sent to downstream memory, a WRQ is allocated; if it is determined that to probe the core, a CPQ is allocated. L2 sends probe requests to the core through CPQ.
5. The method for implementing the fence instruction in L2 according to claim 2, characterized in that, In the method, when a read request is sent to the downstream memory via L2, it is sent via orq, and the data is read from the downstream memory and the corresponding permissions are obtained; when a write request is sent to the downstream memory via L2, it is sent via wrq, and the data is written from L2 to the next level memory.
6. A system for implementing a fence instruction in L2, the system being used to implement the method for implementing a fence instruction in L2 as described in any one of claims 1-5, characterized in that, Including probe, eviction, TAG RAM, DATA RAM, CRQ, CWQ, EPQ, orq, wrq, EFQ and cpq.
7. The system for implementing the fence instruction in L2 according to claim 6, characterized in that, The probe is used for spying and listening, probing dirty data in the core or modifying the MESI status information in the core in order to obtain E privileges; The eviction is used to keep the data stored in the cache relatively new, and is generated when data needs to be replaced out of the cache; The TAG RAM is used to record the cacheline's addr and the cacheline's MESI status information in L2 and all L2 cores; The DATA RAM is used to record cacheline data information; The CRQ is a queue used to receive read requests from the core. The CWQ is a queue used to receive write requests from the core; The EPQ is a queue used to receive probe requests from external sources; The orq is used when a request in L2, after being uploaded to the L2 pipeline, finds that the cacheline does not exist in the current cache or that the access permissions of the cacheline in the current cache are insufficient. In this case, an orq needs to be requested, and the data is reloaded to the next level of memory through the orq and the corresponding permissions are obtained. The wrq is used when L2 needs to write a certain cacheline to the next level of memory, and then requests a wrq to write the data to the next level of memory. The EFQ is used to first fill the data back into the EFQ when the L2 is filled by reload data, and then write the data to L2$ through the L2 pipeline on the EFQ while returning the data to the request module. The cpq is used to probe the corresponding core. The probe request is first stored in the cpq, and then the probe request is sent to the corresponding core through the cpq.