Analog-to-digital conversion circuit, chip, analog-to-digital conversion method and electronic device
By combining a fully parallel analog-to-digital converter module and an N-bit successive approximation analog-to-digital converter module in the Flash-SAR ADC, and by using a K-bit resistor string to reduce the number of capacitors, the problems of high circuit area and power consumption are solved, and more efficient analog-to-digital conversion is achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CHIPSEA TECH SHENZHEN CO LTD
- Filing Date
- 2022-06-29
- Publication Date
- 2026-06-12
Smart Images
Figure CN115021756B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of signal processing technology, and in particular to an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method, and an electronic device. Background Technology
[0002] An analog-to-digital converter that combines a fully parallel (Flash) analog-to-digital converter (ADC) with a successive approximation register (SAR) ADC is a hybrid analog-to-digital converter, also known as a Flash-SAR ADC.
[0003] The Flash-SAR ADC in related technologies suffers from technical problems such as large circuit area and high power consumption. Summary of the Invention
[0004] In view of this, embodiments of this application provide an analog-to-digital conversion circuit, a chip, an analog-to-digital conversion method, and an electronic device to reduce the circuit area of the analog-to-digital conversion circuit and reduce power consumption.
[0005] According to one aspect of this application, an analog-to-digital converter circuit is provided, comprising:
[0006] The fully parallel analog-to-digital converter module includes: a K-bit resistor string;
[0007] The N-bit successive approximation analog-to-digital converter module includes: an M-bit capacitor-based digital-to-analog converter array, used to perform N-bit analog-to-digital conversion on the analog input signal to obtain an N-bit digital signal. The N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal, where N = K + M, and K, M, and N are positive integers.
[0008] in:
[0009] The fully parallel analog-to-digital converter module is configured to sample and convert analog input signals to obtain high-K-bit digital signals;
[0010] The N-bit successive approximation analog-to-digital converter module is configured to obtain the low M-bit digital signal through a K-bit resistor string and an M-bit capacitor digital-to-analog converter array, and the low M-bit digital signal is obtained from the high K-bit digital signal in the N-bit analog-to-digital conversion.
[0011] According to another aspect of this application, an analog-to-digital conversion method is provided for an analog-to-digital conversion circuit. The analog-to-digital conversion circuit includes: a fully parallel analog-to-digital conversion module, including: a K-bit resistor string; and an N-bit successive approximation analog-to-digital conversion module, including: an M-bit capacitor digital-to-analog conversion array. The N-bit successive approximation analog-to-digital conversion module is used to perform N-bit analog-to-digital conversion on an analog input signal to obtain an N-bit digital signal, wherein the N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal; wherein N = K + M, and K, M, and N are positive integers.
[0012] Analog-to-digital conversion methods include:
[0013] The fully parallel analog-to-digital converter module samples and converts the analog input signal to obtain a high-K-bit digital signal;
[0014] The N-bit successive approximation analog-to-digital converter module obtains the low M-bit digital signal through a K-bit resistor string and an M-bit capacitor digital-to-analog converter array, and the low M-bit digital signal is obtained from the high K-bit digital signal in the N-bit analog-to-digital conversion.
[0015] According to another aspect of this application, a chip is provided, including the analog-to-digital conversion circuit of the embodiments of this application.
[0016] According to another aspect of this application, an electronic device is provided, including: an analog-to-digital conversion circuit according to embodiments of this application.
[0017] One or more technical solutions provided in the embodiments of this application reduce the number of capacitors in the capacitor digital-to-analog converter array in the successive approximation analog-to-digital converter module by reusing the K-bit resistor string in the fully parallel analog-to-digital converter module, thereby reducing circuit area and power consumption. Attached Figure Description
[0018] Further details, features, and advantages of this application are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:
[0019] Figure 1 A schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0020] Figure 2 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0021] Figure 3 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0022] Figure 4 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0023] Figure 5 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0024] Figure 6 Another schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0025] Figure 7 A schematic diagram of an example of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0026] Figure 8A schematic diagram of another example of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown;
[0027] Figure 9 A flowchart illustrating an exemplary embodiment of the analog-to-digital conversion method of this application is shown. Detailed Implementation
[0028] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.
[0029] It should be understood that the steps described in the method embodiments of this application may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this application is not limited in this respect.
[0030] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the following description. It should be noted that the concepts of "first", "second", etc., mentioned in this application are used only to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.
[0031] It should be noted that the terms "a" and "a plurality of" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".
[0032] This application provides an analog-to-digital converter circuit.
[0033] Figure 1 A schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown, such as... Figure 1As shown, the analog-to-digital converter circuit 100 includes a fully parallel analog-to-digital converter module 110 and an N-bit successive approximation analog-to-digital converter module 120. The fully parallel analog-to-digital converter module 110 includes a K-bit resistor string 111. The N-bit successive approximation analog-to-digital converter module 120 includes an M-bit capacitor digital-to-analog converter array 121. The N-bit successive approximation analog-to-digital converter module 120 is used to perform N-bit analog-to-digital conversion on the analog input signal to obtain an N-bit digital signal, wherein the N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal. N = K + M, and K, M, and N are positive integers.
[0034] The fully parallel analog-to-digital converter module 110 is configured to sample and convert the analog input signal to obtain the high K bits of the N-bit digital signal. The N-bit successive approximation analog-to-digital converter module 120 is configured to obtain the low M bits of the N-bit digital signal through the K-bit resistor string 111 and the M-bit capacitor digital-to-analog converter array 121, and the low M bits of the digital signal are obtained from the high K bits of the digital signal in the N-bit analog-to-digital conversion.
[0035] In this embodiment, the analog-to-digital converter circuit 100 uses a hybrid resistor-capacitor structure composed of a K-bit resistor string 111 from the fully parallel analog-to-digital converter module 110 and an M-bit capacitor digital-to-analog converter array 121 from the N-bit successive approximation analog-to-digital converter module 120 to achieve N-bit digital-to-analog conversion. By reusing the K-bit resistor string in the fully parallel analog-to-digital converter module, the number of capacitors in the capacitor digital-to-analog converter array in the successive approximation analog-to-digital converter module is reduced, thereby reducing circuit area and power consumption.
[0036] It should be understood that, despite Figure 1 The diagram shows the components and their positional relationships within the analog-to-digital converter circuit 100, but this embodiment does not limit this.
[0037] In this embodiment, the M-bit capacitor digital-to-analog converter array 121 can be a binary weighted capacitor array or a segmented capacitor array (also known as a bridging capacitor array), and this embodiment does not limit this. An example of a segmented capacitor array is to separate two independent binary weighted capacitor arrays by segmented capacitors (referred to as Cs) to at least reduce the overall capacitance value.
[0038] In this embodiment, the K-bit resistor string 111 can first be used by the fully parallel analog-to-digital converter 110 to generate the high K bits of the N-bit digital signal, and then used by the N-bit successive approximation analog-to-digital converter 120 to generate the low M bits of the N-bit digital signal. Possible implementations of the multiplexed K-bit resistor string 111 are described below.
[0039] Method 1
[0040] The N-bit successive approximation analog-to-digital converter module 120 is configured to: perform digital-to-analog conversion on the high K-bit digital signal through the K-bit resistor string 111, and obtain the low M-bit digital signal in the N-bit digital signal through the M-bit capacitor digital-to-analog converter array 121.
[0041] Figure 2 A schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown, such as... Figure 2 As shown, the analog-to-digital conversion circuit 100 further includes: a switching module 130, configured to input the temperature code (including 2 k bits) corresponding to the high K-bit digital signal. k -1 bit), controls the K-bit resistor series 111 to output a reference voltage signal (V). REF The reference signal terminals corresponding to each capacitor in the M-bit capacitor digital-to-analog converter array 121 are configured to receive the aforementioned reference voltage signal (V). REF ).
[0042] like Figure 2 As shown, the fully parallel analog-to-digital converter module 110 includes a comparison module 112 connected to a K-bit resistor string 111. The comparison module 112 is configured to generate a temperature code corresponding to the high-K-bit digital signal. Furthermore, the corresponding high-K-bit digital signal can be obtained based on this temperature code.
[0043] As an example, switch module 130 includes switches corresponding to the number of bits in the temperature code, with each bit in the temperature code controlling one switch. As an example, the K-bit resistor string 111 may include 2... K -1 equivalent resistor, comparator module 112 includes 2 K -1 comparator, each comparator receiving a segmented reference voltage corresponding to a resistor; correspondingly, the switching module 130 may include 2 K -1 switch, each switch corresponds to a segmented reference voltage corresponding to a resistor.
[0044] The following explanation uses a single sampling and conversion as an example. For instance, during sampling, the fully parallel analog-to-digital converter (ADC) 110 and the N-bit successive approximation ADC 120 simultaneously sample the analog input signal. During the conversion by the fully parallel ADC 110, the comparator 112 generates a temperature code for the high-K-bit digital signal corresponding to the analog input signal, and further encodes the temperature code to obtain the high-K-bit digital signal corresponding to the analog input signal. The comparator 112 feeds back the temperature code to the switch 130. The switch 130 controls the K-bit resistor string 111 according to the temperature code to output a reference voltage signal (V). REF The reference signal (V) is received at the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog converter array 121. REFAt this point, the K-bit resistor string 111 in the fully parallel analog-to-digital converter module is used as the high K-bit digital-to-digital converter module of the N-bit successive approximation analog-to-digital converter module 120, and the M-bit capacitor digital-to-digital converter array 121 is used as the low M-bit digital-to-digital converter module of the N-bit successive approximation analog-to-digital converter module 120. The N-bit successive approximation analog-to-digital converter module 120 directly compares from the (M-1)th bit through the M-bit capacitor digital-to-digital converter array, and only needs to compare M times until the low M-bit digital signal corresponding to the analog input signal is generated.
[0045] Figure 3 A schematic block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown, such as... Figure 3 As shown, the analog-to-digital converter circuit 100 further includes a switching module 130 configured to control the K-bit resistor string 111 according to the high K-bit digital signal to output a reference voltage signal (V). REF The reference signal terminals corresponding to each capacitor in the M-bit capacitor digital-to-analog converter array 121 are configured to receive the aforementioned reference voltage signal (V). REF ).
[0046] like Figure 3 As shown, the fully parallel analog-to-digital converter module 110 includes: a comparison module 112 connected to a K-bit resistor string 111, the comparison module 112 being configured to generate a temperature code for a high-K-bit digital signal corresponding to an analog input signal; and an encoding module 113 connected to the comparison module 112, configured to generate a high-K-bit digital signal corresponding to the analog input signal using the temperature code.
[0047] As an example, the switch module 130 may include K control signal terminals, each corresponding to one bit of a high-K-bit digital signal. As another example, the switch module 130 may be a switch tree with K control signal terminals.
[0048] The following explanation uses a single sampling and conversion as an example. For instance, during sampling, the fully parallel analog-to-digital converter (ADC) module 110 and the N-bit successive approximation ADC module 120 simultaneously sample the analog input signal. During the conversion by the fully parallel ADC module 110, the comparison module 112 generates a temperature code for the high-K-bit digital signal corresponding to the analog input signal. The encoding module 113 further encodes the temperature code to obtain the high-K-bit digital signal corresponding to the analog input signal. The encoding module 113 feeds back the high-K-bit digital signal to the switching module 130. The switching module 130 controls the K-bit resistor string 111 according to the high-K-bit digital signal to output a reference voltage signal (V). REF The reference signal (V) is received at the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog converter array 121. REFAt this point, the K-bit resistor string 111 in the fully parallel analog-to-digital converter module is used as the high K-bit digital-to-digital converter module of the N-bit successive approximation analog-to-digital converter module 120, and the M-bit capacitor digital-to-digital converter array 121 is used as the low M-bit digital-to-digital converter module of the N-bit successive approximation analog-to-digital converter module 120. The N-bit successive approximation analog-to-digital converter module 120 directly compares from the (M-1)th bit through the M-bit capacitor digital-to-digital converter array, and only needs to compare M times until the low M-bit digital signal corresponding to the analog input signal is generated.
[0049] Figure 4 A schematic block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown, such as... Figure 4 As shown, the analog-to-digital converter circuit 100 also includes a switching module 130.
[0050] like Figure 4 As shown, the fully parallel analog-to-digital converter module 110 includes: a comparison module 112 connected to a K-bit resistor string 111, the comparison module 112 being configured to generate a temperature code for a high-K-bit digital signal corresponding to an analog input signal; and an encoding module 113 connected to the comparison module 112, configured to generate a high-K-bit digital signal corresponding to the analog input signal using the temperature code.
[0051] like Figure 4 As shown, the N-bit successive approximation analog-to-digital converter module 120 further includes an M-bit successive comparison logic 122 and a comparison unit 124. The M-bit successive comparison logic 122 is configured to control the M-bit capacitor analog-to-digital converter array 121 to perform the low M-bit analog-to-digital conversion in the N-bit analog-to-digital conversion, thereby obtaining the low M-bit digital signal corresponding to the analog input signal.
[0052] like Figure 4 As shown, the analog-to-digital converter circuit 100 further includes a comparison unit 124. One input terminal of the comparison unit 124 is connected to the analog voltage output terminal of the M-bit capacitor analog-to-digital converter array 121. The M-bit successive comparison logic 122 listens to the comparison output of the comparison unit 124.
[0053] It should be noted that, in Figure 4 In the diagram, a dashed line is used to connect the encoding circuit 113 and the switch module 130, and another dashed line is used to connect the comparison module 112 and the switch module 130. The purpose of this is to illustrate that the signal of either the encoding circuit 113 or the comparison module 112 is used to control the switch module 130, and it is not a limitation on the connection relationship.
[0054] Method 2
[0055] The N-bit successive approximation analog-to-digital converter module 120 is configured to: control the M-bit capacitor analog-to-digital converter array to perform digital-to-analog conversion based on the high K-bit digital signal or the temperature code corresponding to the high K-bit digital signal, and obtain the low M-bit digital signal in the N-bit digital signal through the M-bit capacitor analog-to-digital converter array and the K-bit resistor string.
[0056] Figure 5 A schematic block diagram of an analog-to-digital conversion circuit according to an exemplary embodiment of this application is shown, such as... Figure 5 As shown, it also includes a switch module 130.
[0057] like Figure 5 As shown, the N-bit successive approximation analog-to-digital converter module 120 also includes an M-bit successive approximation logic 122, configured to output an M-bit control signal. The M-bit capacitor analog-to-digital converter array 121 includes a high-K-bit capacitor analog-to-digital converter array, a low-MK-bit capacitor analog-to-digital converter array, and compensation capacitors.
[0058] The M-bit control signal is used to control the low MK-bit capacitor digital-to-analog converter array and the K-bit resistor string to obtain a low M-bit digital signal. Specifically, the M-bit control signal includes a first control signal and a second control signal.
[0059] Switching module 130, connected to M-bit successive approximation logic 122, is configured to control a K-bit resistor series to output a reference voltage signal (V) according to a first control signal. REF A compensation capacitor is configured to receive the reference voltage signal (V). REF A low-MK-bit capacitor digital-to-analog converter array is configured to receive a second control signal for performing digital-to-analog conversion.
[0060] like Figure 5 As shown, the fully parallel analog-to-digital converter module 110 includes: a comparison module 112 connected to a K-bit resistor string 111, configured to generate a temperature code for a high-K-bit digital signal corresponding to the analog input signal; and an encoding module 113 connected to the comparison module 112, configured to generate a high-K-bit digital signal corresponding to the analog input signal using this temperature code. The high-K-bit capacitor-based analog-to-digital converter array is configured to receive the temperature code corresponding to the analog input signal.
[0061] As an example, the switch module 130 includes K control signal terminals, each corresponding to a single switch control signal in the first control signal. As another example, the switch module 130 may be a switch tree with K control signals.
[0062] The following explanation uses a single sampling and conversion as an example. For instance, during sampling, the fully parallel analog-to-digital converter (ADC) module 110 and the N-bit successive approximation ADC module 120 simultaneously sample the analog input signal. During the conversion by the fully parallel ADC module 110, the comparison module 112 generates a bit temperature code for the high-K digital signal corresponding to the analog input signal. The encoding module 113 further encodes the temperature code to obtain the high-K bit digital signal corresponding to the analog input signal. The encoding module 113 feeds back the high-K bit digital signal to the high-K bit capacitor ADC array 121 of the M-bit capacitor ADC array, causing the high-K bit capacitor ADC array to flip according to the high-K bit digital signal. The N-bit successive approximation ADC module 120 only needs to start the conversion from the remaining low-MK bit capacitor ADC array in the M-bit capacitor ADC array until the low-M bit digital signal corresponding to the analog input signal is generated.
[0063] Specifically, during the conversion to obtain the low M-bit digital signal, the second control signal in the M-bit control signal output by the M-bit successive approximation logic 122 controls the low MK-bit capacitor digital-to-analog converter array to perform the conversion, and the first control signal in the M-bit control signal controls the switching module 130, causing the switching module 130 to control the K-bit resistor string 111 to output a reference voltage signal (V). REF The reference signal terminal of the compensation capacitor in the M-bit capacitor-to-analog converter array 121 receives the reference voltage signal (V). REF In other words, in this process, the conversion of the low M-bit digital signal is jointly completed by the low MK-bit capacitor digital-to-analog converter array in the M-bit capacitor digital-to-analog converter array and the K-bit resistor string 111 in the fully parallel analog-to-digital converter array.
[0064] Figure 6 A schematic block diagram of another analog-to-digital converter circuit according to an exemplary embodiment of this application is shown, such as... Figure 6 As shown, it also includes a switch module 130.
[0065] like Figure 6 As shown, the N-bit successive approximation analog-to-digital converter module 120 also includes an M-bit successive approximation logic 122, configured to output an M-bit control signal. The M-bit capacitor analog-to-digital converter array 121 includes a high-K-bit capacitor analog-to-digital converter array, a low-MK-bit capacitor analog-to-digital converter array, and compensation capacitors.
[0066] The M-bit control signal is used to control the low MK-bit capacitor digital-to-analog converter array and the K-bit resistor string to obtain a low M-bit digital signal. Specifically, the M-bit control signal includes a first control signal and a second control signal.
[0067] The N-bit successive approximation analog-to-digital converter module 120 further includes an encoding module 123, configured to generate a temperature code corresponding to the first control signal.
[0068] Switch module 130, connected to encoding module 123, is configured to control a K-bit resistor string according to the temperature code corresponding to the first control signal to output a reference voltage signal (V). REF A compensation capacitor is configured to receive the reference voltage signal (V). REF A low-MK-bit capacitor digital-to-analog converter array is configured to receive a second control signal for performing digital-to-analog conversion.
[0069] As an example, the switch module 130 includes a number of switches corresponding to the number of bits of the temperature encoding, each switch corresponding to a segmented reference voltage corresponding to the resistance of the K-bit resistor string 111.
[0070] like Figure 6 As shown, the fully parallel analog-to-digital converter module 110 includes: a comparison module 112 connected to a K-bit resistor string 111, configured to generate a temperature code for a high-K-bit digital signal corresponding to the analog input signal; and an encoding module 113 connected to the comparison module 112, configured to generate a high-K-bit digital signal corresponding to the analog input signal using this temperature code. The high-K-bit capacitor-based analog-to-digital converter array is configured to receive the high-K-bit digital signal corresponding to the analog input signal.
[0071] The following explanation uses a single sampling and conversion as an example. For instance, during sampling, the fully parallel analog-to-digital converter (ADC) module 110 and the N-bit successive approximation ADC module 120 simultaneously sample the analog input signal. During the conversion by the fully parallel ADC module 110, the comparison module 112 generates a temperature code for the high-K bit digital signal corresponding to the analog input signal. The encoding module 113 further encodes the temperature code to obtain the high-K bit digital signal corresponding to the analog input signal. The encoding module 113 feeds back the high-K bit digital signal to the high-K bit capacitor ADC array 121 of the M-bit capacitor ADC array, causing the high-K bit capacitor ADC array to flip according to the high-K bit digital signal. The N-bit successive approximation ADC module 120 only needs to start the conversion from the remaining low-MK bit capacitor ADC array in the M-bit capacitor ADC array until the low-M bit digital signal corresponding to the analog input signal is generated.
[0072] Specifically, during the conversion to obtain the low M-bit digital signal, the second control signal in the M-bit control signal output by the M-bit successive approximation logic 122 controls the low MK-bit capacitor digital-to-analog converter array to perform the conversion. The first control signal in the M-bit control signal controls the switching module 130, causing the switching module 130 to control the K-bit resistor string 111 to output a reference voltage signal (VREF). The reference signal terminal of the compensation capacitor in the M-bit capacitor digital-to-analog converter array 121 receives the reference voltage signal (VREF). That is, in this process, the conversion of the low M-bit digital signal is jointly completed by the low MK-bit capacitor digital-to-analog converter array in the M-bit capacitor digital-to-analog converter array and the K-bit resistor string 111 in the fully parallel analog-to-digital converter array.
[0073] like Figure 5 and 6 As shown, the analog-to-digital converter circuit 100 further includes a comparison unit 124. One input terminal of the comparison unit 124 is connected to the analog voltage output terminal of the M-bit capacitor analog-to-digital converter array 121. The M-bit successive comparison logic 122 listens to the comparison output of the comparison unit 124.
[0074] Some examples of this embodiment are described below.
[0075] Figure 7 This illustration shows a schematic diagram of an example analog-to-digital conversion circuit according to an exemplary embodiment of this application. The analog-to-digital conversion circuit is an N-bit Flash SAR hybrid ADC, such as... Figure 7 As shown, it includes a K-bit Flash ADC, an M-bit DAC differential capacitor array, a comparator COMP, an M-bit SAR logic, an encoding circuit 1, and an encoding circuit 2.
[0076] This K-bit Flash ADC includes sampling capacitors CS1 and CS2, a K-bit resistor string, and 2*(2 K -1) comparators. During the ADC sampling phase, the Flash ADC and SAR ADC sample simultaneously. After sampling is completed, the temperature code result TP corresponding to the differential signal can be obtained in one clock cycle [2]. K -1:0] and TP[2 K The K-bit binary code result T[K-1:0] is obtained through encoding circuit 1. The comparison result of the K-bit Flash ADC is then fed back to the K-bit resistor string (as the high K-bit resistor array in the SAR ADC) through encoding circuit 1.
[0077] This N-bit SAR ADC includes a K-bit resistor string, an M-bit DAC differential capacitor array, a comparator COMP, and M-bit SAR logic. The M-bit DAC differential capacitor array includes an M-bit capacitor array, which may include, but is not limited to, a binary weighted DAC differential capacitor array and a bridged DAC differential capacitor array. After the encoding circuit 1 feeds back the comparison result of the K-bit Flash ADC to the high K bits of the SAR ADC, the SAR ADC begins the comparison of the (M-1)th bit, with the remaining comparisons performed M times. The high K bits of the SAR ADC directly reuse the K-bit resistor string from the Flash ADC, controlled by two sets of switches SW1 and SW2. The DAC differential capacitor array includes an M-bit capacitor array, controlled by M-bit SAR logic. The SAR ADC can reuse resistor strings with fewer than or equal to K bits, and the DAC array includes an M-bit capacitor array, for a total of 2*2 capacitors. M Compared to the traditional method, it reduces 2*(2 N -2 M ) capacitors. For example, for a SAR ADC with N=12, K=4, and M=8, the number of capacitors that can be saved is 2*(2 12 -2 8 =7680, the saved capacitor portion accounts for about 94% of the traditional structure capacitor.
[0078] The encoding circuit 2 accumulates the K-bit binary code result T[K-1:0] of the Flash ADC and the M-bit binary result D[M-1:0] of the SAR ADC to obtain the N-bit binary code result D[N-1:0].
[0079] Figure 8 The diagram shows another example of the analog-to-digital conversion circuit of an exemplary embodiment of this application. The analog-to-digital conversion circuit is an N-bit Flash SAR hybrid structure ADC. The circuit includes a K-bit Flash ADC, an M-bit DAC differential capacitor array, a comparator COMP, M-bit SAR logic, encoding circuit 1, and encoding circuit 2.
[0080] This K-bit Flash ADC includes sampling capacitors CS1 and CS2, a K-bit resistor string, and 2*(2 K -1) comparators. During the ADC sampling phase, the Flash ADC and SAR ADC sample simultaneously. After sampling is completed, the temperature code result TP corresponding to the differential signal can be obtained in one clock cycle [2]. K -1:0] and TP[2 K -1:0], and then through encoding circuit 1, the K-bit binary code result T[K-1:0] can be obtained. And through encoding circuit 1, the comparison result of the K-bit Flash ADC is fed back to the high K-bit capacitor array in the SAR ADC.
[0081] This N-bit SAR ADC includes a K-bit resistor string, an M-bit DAC differential capacitor array, a comparator COMP, and M-bit SAR logic. The M-bit DAC differential capacitor array includes a high K-bit capacitor array and a low MK-bit capacitor array. The DAC differential capacitor array is not limited to binary weighted DAC differential capacitor arrays or bridged DAC differential capacitor arrays. After the encoding circuit 1 feeds back the comparison result of the K-bit Flash ADC to the high K-bit capacitor array in the SAR ADC, the SAR ADC begins the comparison of the (M-1)th bit, with the remaining comparisons performed M times. The lowest bit capacitor CPT(0) in the high K bits of the DAC differential capacitor array is twice the highest bit capacitor CP(MK-1) in the low MK bits. The low M bits of the SAR ADC include an MK-bit capacitor array and a K-bit resistor string. The K-bit resistor string multiplexes the resistor string in the Flash ADC and is controlled by two sets of switches SW1 and SW2. The MK-bit capacitor array and the K-bit resistor string are controlled by M-bit SAR logic. SARADCs can reuse resistors with a number of bits less than or equal to K bits, and the DAC array only requires an M-bit capacitor array, resulting in a total of 2*2 capacitors. M Compared to the traditional method, it reduces 2*(2 N -2 M ) capacitors. For example, for a SAR ADC with N=12, K=4, and M=8, the number of capacitors that can be saved is 2*(21) 2 -2 8 =7680, the saved capacitor portion accounts for about 94% of the traditional structure capacitor.
[0082] The encoding circuit 2 accumulates the K-bit binary code result T[K-1:0] of the Flash ADC and the M-bit binary result D[M-1:0] of the SAR ADC to obtain the N-bit binary code result D[N-1:0].
[0083] This embodiment also provides an analog-to-digital conversion method for an analog-to-digital conversion circuit, which is applied to the analog-to-digital conversion circuit of this application embodiment.
[0084] Figure 9 A flowchart of an analog-to-digital conversion method according to an exemplary embodiment of this application is shown, such as... Figure 9 As shown, the method includes steps S901 to S902.
[0085] In step S901, the fully parallel analog-to-digital converter module samples and converts the analog input signal to obtain the high K-bit digital signal corresponding to the analog input signal.
[0086] The fully parallel analog-to-digital converter module includes a K-bit resistor string; the N-bit successive approximation analog-to-digital converter module includes an M-bit capacitor digital-to-analog converter array, where N = K + M, and K, M, and N are positive integers.
[0087] In step S902, the N-bit successive approximation analog-to-digital converter module obtains the low M-bit digital signal through a K-bit resistor string and an M-bit capacitor digital-to-analog converter array, and the low M-bit digital signal is obtained from the high K-bit digital signal in the N-bit analog-to-digital conversion.
[0088] The analog-to-digital conversion method in this embodiment uses a hybrid resistor-capacitor structure, consisting of a K-bit resistor string from a fully parallel analog-to-digital conversion module and an M-bit capacitor array from an N-bit successive approximation analog-to-digital conversion module, to achieve N-bit analog-to-digital conversion. By reusing the K-bit resistor string in the fully parallel analog-to-digital conversion module, the number of capacitors in the capacitor array of the successive approximation analog-to-digital conversion module is reduced, thereby reducing circuit area and power consumption.
[0089] As one implementation method, step S902 above includes:
[0090] The high K-bit digital signal is converted from digital to analog by a K-bit resistor string, and the low M-bit digital signal is obtained by an M-bit capacitor digital-to-analog converter array.
[0091] As an example, a high-K-bit digital signal is converted from digital to analog using a K-bit resistor string, and a low-M-bit digital signal is obtained using an M-bit capacitor-based digital-to-analog converter array, including:
[0092] Based on the high K-bit digital signal or the temperature code corresponding to the high K-bit digital signal, the K-bit resistor string is controlled to output the first reference voltage signal, wherein the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog converter array receives the first reference voltage signal.
[0093] As another implementation, the N-bit successive approximation analog-to-digital converter module obtains the low M-bit digital signal through a K-bit resistor string and an M-bit capacitor digital-to-analog converter array, including:
[0094] Based on the high K-bit digital signal or the temperature code corresponding to the high K-bit digital signal, the M-bit capacitor digital-to-analog converter array is controlled to perform digital-to-analog conversion, and the low M-bit digital signal is obtained through the M-bit capacitor digital-to-analog converter array and the K-bit resistor string.
[0095] As an example, an M-bit capacitor digital-to-analog converter array includes: a high K-bit capacitor digital-to-analog converter array, a low MK-bit capacitor digital-to-analog converter array, and a compensation capacitor;
[0096] The process of obtaining the low M-bit digital signal through an M-bit capacitor-to-analog converter array and a K-bit resistor string includes:
[0097] The output is an M-bit control signal, which is used to control the low MK-bit capacitor digital-to-analog converter array and the K-bit resistor string to obtain a low M-bit digital signal; and the M-bit control signal includes a first control signal and a second control signal.
[0098] The first control signal controls the K-position resistor string to output the second reference voltage signal, wherein the reference signal terminal corresponding to the compensation capacitor is configured to receive the second reference voltage signal.
[0099] The second control signal controls the low MK-bit capacitor digital-to-analog converter array to perform digital-to-analog conversion.
[0100] This application also provides a chip including the aforementioned analog-to-digital converter (ADC) circuit. The chip (Integrated Circuit, IC) can be, but is not limited to, a System-on-Chip (SoC) chip or a System-in-Package (SIP) chip. This chip achieves N-bit analog-to-digital conversion by using a hybrid resistor-capacitor structure formed by combining a K-bit resistor string from a fully parallel ADC module and an M-bit capacitor array from an N-bit successive approximation ADC module. By reusing the K-bit resistor string in the fully parallel ADC module, the number of capacitors in the capacitor array of the successive approximation ADC module is reduced, thereby reducing circuit area and power consumption.
[0101] This application also provides an electronic device, which includes a device body and a chip as described above disposed within the device body. The electronic device may be, but is not limited to, a weight scale, body fat scale, nutrition scale, infrared electronic thermometer, pulse oximeter, body composition analyzer, power bank, wireless charger, fast charger, car charger, adapter, display, USB (Universal Serial Bus) docking station, stylus, true wireless earphones, car center console screen, automobile, smart wearable device, mobile terminal, and smart home device. Smart wearable devices include, but are not limited to, smartwatches, smart bracelets, and neck massagers. Mobile terminals include, but are not limited to, smartphones, laptops, tablets, and POS (point of sales terminal) machines. Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart robot vacuums, and smart lights. This electronic device achieves N-bit digital-to-analog conversion by using a K-bit resistor string of a fully parallel analog-to-digital converter module and an M-bit capacitor array of an N-bit successive approximation analog-to-digital converter module to form a resistor-capacitor hybrid structure. By reusing the K-bit resistor string in the fully parallel analog-to-digital converter module, the number of capacitors in the capacitor digital-to-analog converter array in the successive approximation analog-to-digital converter module is reduced, which can reduce circuit area and power consumption.
[0102] The above are merely preferred embodiments of this application and are not intended to limit this application in any way. Although this application has disclosed preferred embodiments as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of this application without departing from the scope of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. An analog-to-digital converter circuit, characterized in that, include: The fully parallel analog-to-digital converter module includes: a K-bit resistor string; The N-bit successive approximation analog-to-digital converter module includes: an M-bit capacitor-based digital-to-analog converter array, used to perform N-bit analog-to-digital conversion on the analog input signal to obtain an N-bit digital signal, wherein the N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal, where N = K + M, and K, M and N are positive integers; A switching module is used to control the K-position resistor string to output a reference voltage signal; in: The fully parallel analog-to-digital converter module is configured to sample and convert the analog input signal to obtain the high K-bit digital signal; The N-bit successive approximation analog-to-digital converter module is configured to obtain the low M-bit digital signal based on the reference voltage signal through the K-bit resistor string and the M-bit capacitor digital-to-analog converter array, and the low M-bit digital signal is obtained from the high K-bit digital signal in the N-bit analog-to-digital conversion.
2. The analog-to-digital converter circuit according to claim 1, characterized in that, The N-bit successive approximation analog-to-digital converter module is configured to: perform digital-to-analog conversion on the high K-bit digital signal through the K-bit resistor string, and obtain the low M-bit digital signal through the M-bit capacitor digital-to-analog converter array.
3. The analog-to-digital converter circuit according to claim 2, characterized in that, The switching module is further configured to control the K-bit resistor string to output a first reference voltage signal based on the high K-bit digital signal or the temperature code corresponding to the high K-bit digital signal. The reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog converter array is configured to receive the first reference voltage signal.
4. The analog-to-digital converter circuit according to claim 1, characterized in that, The N-bit successive approximation analog-to-digital converter module is configured to: control the M-bit capacitor analog-to-digital converter array to perform digital-to-analog conversion based on the high K-bit digital signal or the temperature code corresponding to the high K-bit digital signal, and obtain the low M-bit digital signal through the M-bit capacitor analog-to-digital converter array and the K-bit resistor string.
5. The analog-to-digital converter circuit according to claim 4, characterized in that, The M-bit capacitor digital-to-analog converter array includes: a high K-bit capacitor digital-to-analog converter array, a low MK-bit capacitor digital-to-analog converter array, and a compensation capacitor; The fully parallel analog-to-digital converter module is configured to control the high-K-bit capacitor digital-to-analog converter array according to the high-K-bit digital signal or the temperature code corresponding to the high-K-bit digital signal; The N-bit successive approximation analog-to-digital converter module includes an M-bit successive approximation logic unit, which is configured to output an M-bit control signal. The M-bit control signal is used to control the low MK-bit capacitor digital-to-analog converter array and the K-bit resistor string to obtain the low M-bit digital signal.
6. The analog-to-digital converter circuit according to claim 5, characterized in that, The M-bit control signal includes a first control signal and a second control signal; the switching module is further configured to control the K-bit resistor string according to the first control signal to output a second reference voltage signal, wherein the reference signal terminal corresponding to the compensation capacitor is configured to receive the second reference voltage signal; The low-MK-bit capacitor digital-to-analog converter array is configured to receive the second control signal to perform digital-to-analog conversion.
7. An analog-to-digital conversion method for an analog-to-digital conversion circuit, characterized in that, The analog-to-digital conversion circuit includes: The fully parallel analog-to-digital converter module includes: a K-bit resistor string; and a switching module for controlling the K-bit resistor string to output a reference voltage signal. The N-bit successive approximation analog-to-digital converter module includes: an M-bit capacitor-based digital-to-analog converter array. The N-bit successive approximation analog-to-digital converter module is used to perform N-bit analog-to-digital conversion on the analog input signal based on the reference voltage signal to obtain an N-bit digital signal. The N-bit digital signal includes a high K-bit digital signal and a low M-bit digital signal; where N = K + M, and K, M, and N are positive integers. The analog-to-digital conversion method includes: The fully parallel analog-to-digital converter module samples and converts the analog input signal to obtain the high K-bit digital signal; The N-bit successive approximation analog-to-digital converter module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor digital-to-analog converter array, and the low M-bit digital signal is obtained from the high K-bit digital signal in the N-bit analog-to-digital conversion.
8. The analog-to-digital conversion method according to claim 7, characterized in that, The N-bit successive approximation analog-to-digital converter module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor analog-to-digital converter array, including: The high K-bit digital signal is converted from digital to analog by the K-bit resistor string, and the low M-bit digital signal is obtained by the M-bit capacitor digital-to-analog converter array.
9. The analog-to-digital conversion method according to claim 8, characterized in that, The step of performing digital-to-analog conversion on the high K-bit digital signal through the K-bit resistor string and obtaining the low M-bit digital signal through the M-bit capacitor digital-to-analog converter array includes: Based on the high K-bit digital signal or the temperature code corresponding to the high K-bit digital signal, the K-bit resistor string is controlled to output a first reference voltage signal, wherein the reference signal terminal corresponding to each capacitor in the M-bit capacitor digital-to-analog converter array receives the first reference voltage signal.
10. The analog-to-digital conversion method according to claim 7, characterized in that, The N-bit successive approximation analog-to-digital converter module obtains the low M-bit digital signal through the K-bit resistor string and the M-bit capacitor analog-to-digital converter array, including: Based on the high K-bit digital signal or the temperature code corresponding to the high K-bit digital signal, the M-bit capacitor digital-to-analog converter array is controlled to perform digital-to-analog conversion, and the low M-bit digital signal is obtained through the M-bit capacitor digital-to-analog converter array and the K-bit resistor string.
11. The analog-to-digital conversion method according to claim 10, characterized in that, The M-bit capacitor digital-to-analog converter array includes: a high K-bit capacitor digital-to-analog converter array, a low MK-bit capacitor digital-to-analog converter array, and a compensation capacitor; The step of obtaining the low M-bit digital signal through the M-bit capacitor-to-analog converter array and the K-bit resistor string includes: Output an M-bit control signal, wherein the M-bit control signal is used to control the low MK-bit capacitor digital-to-analog converter array and the K-bit resistor string to obtain the low M-bit digital signal; and the M-bit control signal includes a first control signal and a second control signal; The first control signal controls the K-position resistor string to output a second reference voltage signal, wherein the reference signal terminal corresponding to the compensation capacitor is configured to receive the second reference voltage signal; The second control signal controls the low MK-bit capacitor digital-to-analog converter array to perform digital-to-analog conversion.
12. A chip, characterized in that, Includes the analog-to-digital conversion circuit according to any one of claims 1 to 6.
13. An electronic device, characterized in that, include: The analog-to-digital converter circuit according to any one of claims 1 to 6.