TD converter and PLL circuit

Abstract

To provide a time to digital (TD) converter having low switching noise generated from an electric power source during a gating action so as to achieve excellent noise characteristics, and provide a phase locked loop (PLL) having the TD converter.SOLUTION: A TD converter 10 comprises a plurality of oscillators 400 comprising at least a first oscillator 400A and a second oscillator 400B which operate in different operation modes having different oscillatory frequencies depending on a control signal representing a time difference between a reference clock and an object clock; and an operation circuit 500 that calculates a digital output value depending on the time difference for each of the plurality of oscillators using one of a plurality of pieces of phase information held therein according to the reference clock. The first oscillator and the second oscillator are each operative in two operation modes, a high-speed operation mode and a low-speed operation mode having the oscillatory frequency lower than that of the high-speed operation mode.SELECTED DRAWING: Figure 18

Description

【Technical Field】 【0001】 The present invention relates to a TD converter and a PLL circuit. 【Background Art】 【0002】 Patent Document 1 describes "an apparatus for measuring the duration of the level of an electrical signal". Patent Document 2 describes "a TD (Time to Digital) converter using operations in the time domain". [Prior Art Documents] [Patent Documents] [Patent Document 1] U.S. Patent Application Publication No. 2014 / 0218009 [Patent Document 2] Japanese Patent Application Laid-Open No. 2014-003580 【Summary of the Invention】 【0003】 In a first aspect of the present invention, a TD converter is provided. The TD converter includes at least a plurality of oscillators including a first oscillator and a second oscillator that operate in operation modes with different oscillation frequencies according to an input signal indicating a time difference between a reference clock and a target clock, and an arithmetic circuit that calculates a digital output value corresponding to the time difference using a plurality of phase information respectively held according to the reference clock in the plurality of oscillators. 【0004】 In the TD converter, each of the first oscillator and the second oscillator may be configured to be operable in at least two operation modes: a high-speed operation mode and a low-speed operation mode in which the oscillation frequency is lower than that in the high-speed operation mode. 【0005】 In any of the TD converters, when the first oscillator operates in the high-speed operation mode, the second oscillator may operate in the low-speed operation mode, and when the first oscillator operates in the low-speed operation mode, the second oscillator may operate in the high-speed operation mode. 【0006】 In any of the above TD converters, each of the plurality of oscillators may include a ring oscillator in which delay elements are connected in a ring shape in cascaded order. 【0007】 In either of the TD converters, the first oscillator and the second oscillator may be configured to switch the operating mode by switching the delay time in the delay element according to the input signal. 【0008】 In any of the TD converters, each of the plurality of phase information may include rotation information indicating the number of rotations of the ring oscillator, and position information indicating the position of the delay element where the logic level of the input and the logic level of the output are equal. 【0009】 In any of the TD converters, the arithmetic circuit may include: a plurality of decoders that each calculate virtual phase information representing virtual phase information using the frequency information and position information for the plurality of phase information; a plurality of difference detectors that each input the plurality of virtual phase information calculated by the plurality of decoders and each detect a TDC value representing the difference between the input virtual phase information and the virtual phase information at a point in time when the reference clock was one clock cycle earlier; and an arithmetic processing unit that calculates the digital output value based on the plurality of TDC values ​​detected by the plurality of difference detectors. 【0010】 In any of the TD converters, the arithmetic processing unit may include a dependency value extraction unit that extracts a dependency value from each of the plurality of TDC values ​​that indicates a value that changes depending on the time difference. 【0011】 In any of the TD converters, the dependency value extraction unit may consist of a subtractor that calculates the difference between a first TDC value and a second TDC value among the plurality of TDC values. 【0012】 In any of the TD converters, the dependency value extraction unit may output the dependency value as the digital output value. 【0013】 In any of the TD converters, the calculation processing unit may further include: an independent value extraction unit that extracts an independent value from each of the plurality of TDC values ​​that is independent of the time difference; and a difference output unit that calculates the difference between the dependent value and the independent value and outputs the difference as the digital output value. 【0014】 In any of the above TD converters, the independent value extraction unit may consist of an adder that calculates the sum of a first TDC value and a second TDC value among the plurality of TDC values. 【0015】 In any of the TD converters, the arithmetic processing unit may further include a multiplier that multiplies the dependent value or the independent value by a predetermined coefficient. 【0016】 In any of the TD converters, the input signal may be a pulse signal having a pulse width corresponding to the time difference between the reference clock and the target clock. 【0017】 A second embodiment of the present invention provides a PLL circuit, which comprises any of the TD converters. 【0018】 It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing] 【0019】 [Figure 1] An example of a conventional PLL circuit configuration is shown. [Figure 2] An example of an ADPLL circuit configuration is shown. [Figure 3] An example of a conventional TDC configuration is shown. [Figure 4] The diagram shows a conventional TDC conversion. [Figure 5] This shows an example of the oscillator configuration used in conventional TDC. [Figure 6]Shows a diagram representing TDC conversion in the prior art [Figure 7] Shows a configuration example of a TDC in the prior art. [Figure 8] Shows a configuration example of a TDC in Patent Document 1. [Figure 9] Shows a configuration example of an oscillator used in the TDC in Patent Document 1. [Figure 10] Shows a configuration example of a differential detector that may be used in the TDC in Patent Document 1. [Figure 11] Shows another configuration example of a differential detector that may be used in the TDC in Patent Document 1. [Figure 12] Shows a diagram representing TDC conversion in Patent Document 1. [Figure 13] Shows a diagram representing the quantization noise transfer model of TDC conversion in Patent Document 1. [Figure 14] Shows a diagram representing the power supply dependency of TDC conversion in Patent Document 1. [Figure 15] Shows another configuration example of a TDC in Patent Document 1. [Figure 16] Shows a diagram representing TDC conversion in another configuration example of Patent Document 1. [Figure 17] Shows a diagram representing power supply voltage fluctuations in another configuration example of Patent Document 1. [Figure 18] Shows a configuration example of the TD converter 10 according to the first embodiment. [Figure 19] Shows a configuration example of a ring oscillator that may be included in the oscillator 400. [Figure 20] Shows a first configuration example of the arithmetic processing unit 530. [Figure 21] Shows the operation state of the arithmetic processing unit 530 according to the first configuration example. [Figure 22] Shows a second configuration example of the arithmetic processing unit 530. [Figure 23] Shows the operation state of the arithmetic processing unit 530 according to the second configuration example. [Figure 24] Shows a third configuration example of the arithmetic processing unit 5)0. [Figure 25]This shows the calculation performed by the arithmetic processing unit 530 in the third configuration example. [Figure 26] An example of a timing chart for the TD converter 10 according to the first embodiment is shown. [Figure 27] The diagram shows the power supply voltage fluctuation in the TD converter 10 according to the first embodiment. [Figure 28] An example configuration of the TD converter 10 according to the second embodiment is shown. [Figure 29] An example of a timing chart for the TD converter 10 according to the second embodiment is shown. [Figure 30] An example configuration of the TD converter 10 according to the third embodiment is shown. [Figure 31] A fourth configuration example of the arithmetic processing unit 530 is shown. [Figure 32] This shows the calculation performed by the arithmetic processing unit 530 in the fourth configuration example. [Figure 33] An example configuration of the TD converter 10 according to the fourth embodiment is shown. [Figure 34] A fifth configuration example of the arithmetic processing unit 530 is shown. [Figure 35] This shows the calculation performed by the arithmetic processing unit 530 in the fifth configuration example. [Figure 36] An example configuration of the TD converter 10 according to the fifth embodiment is shown. [Figure 37] A sixth configuration example of the arithmetic processing unit 530 is shown. [Modes for carrying out the invention] 【0020】 The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention. 【0021】 As CMOS LSI manufacturing processes become more miniaturized and power supply voltages decrease accordingly, digital circuits have seen significant improvements in area reduction, power consumption, and speed. On the other hand, analog circuits have not benefited as much from miniaturization due to increased characteristic variations and leakage current, resulting in limited improvements in area reduction, power consumption, and speed. Therefore, with process miniaturization, it has become common practice to replace some or all of the circuits previously implemented with analog circuits with digital circuits. 【0022】 A Phase Locked Loop (PLL) circuit is one example. A PLL circuit is a circuit that outputs a signal with the same frequency and synchronized phase as an input reference clock from another oscillator circuit using feedback control. PLL circuits are used in a wide range of applications, such as clock generators that generate high-frequency clocks with high precision, and frequency synthesizers in communication ICs. 【0023】 Figure 1 shows an example of a conventional PLL circuit configuration. In conventional PLL circuits, analog circuits such as charge pumps and loop filters occupy the majority of the area, hindering chip size reduction. Furthermore, variations in the characteristics of these analog circuits due to manufacturing variations and leakage currents also hinder the development of faster, higher-performance, and more robust PLL circuits. 【0024】 On the other hand, all-digital PLL (ADPLL) circuits, which replace analog circuits within a PLL circuit with digital circuits, benefit from process miniaturization. As miniaturization and voltage reduction progress, improvements in area reduction, power consumption reduction, and speed increase can be expected. 【0025】 Figure 2 shows an example of an ADPLL circuit configuration. In an ADPLL circuit, each block is composed of a digital circuit, so the same methods as for other digital circuits can be used for the design, verification, and testing of each circuit, making it easy to modify the circuit in response to process changes. Furthermore, by replacing the charge pump and loop filter with digital circuits, the invariance of characteristics due to manufacturing process, power supply voltage, and temperature fluctuations in these blocks is ensured, greatly improving the robustness of the entire PLL. In addition, the modulation noise component generated in a Fractional-N PLL can be largely eliminated because the amount of noise can be predicted with great accuracy due to the digital circuit of the charge pump. 【0026】 Therefore, ADPLL circuits are an extremely important technology for achieving area savings and increased robustness in PLL circuits. 【0027】 In an ADPLL circuit, the block that previously consisted of a PFD (Phase Frequency Detector) circuit and a charge pump circuit in a conventional PLL circuit is replaced with a TD converter (Time to Digital Converter: TDC) and a digital charge pump circuit, as shown in Figure 2. In such an ADPLL circuit, the time resolution of the TDC is the resolution of the time difference comparison between the reference clock and the divided feedback clock, and is one of the main causes of phase noise in a PLL circuit. In other words, a high time resolution of the TDC is necessary to realize a PLL circuit with good noise performance. 【0028】 Figure 3 shows an example of a conventional TDC configuration. A conventional TDC consists of cascaded delay elements and a latch circuit that holds (latches) the output value of each delay element. The latch circuit receives a reference clock immediately after the input (rising edge or falling edge input) of the target clock (for example, the "divided clock" in Figure 2) and holds the output value of each delay element. In such a TDC, by observing how many of the cascaded delay elements the change point of the target clock has propagated to, the time difference between the target clock and the reference clock can be quantized by the delay time of the delay elements and converted into a digital value. 【0029】 Figure 4 shows a diagram representing a conventional TDC conversion. In this figure, the vertical axis represents the TDC output code, and the horizontal axis represents time. Also, in this figure, the dotted line represents the ideal TDC output, and the solid line represents the actual TDC output. In TDC conversion, while the ideal TDC output is linear, in reality a stepped digital value is obtained, which becomes a quantization error and affects the noise performance of the PLL. The time resolution of such a TDC depends on the delay time of each delay element. Therefore, in order to make the time resolution finer, that is, to reduce the quantization error, the delay time of the delay elements needs to be shortened. On the other hand, when constructing a PLL circuit, not only the time resolution but also the conversion range in which correct TD conversion is performed is important. In the example configuration in Figure 3, for example, if N delay elements with delay τ are connected in cascaded order, the time difference in which correct TD conversion can be performed is between 0 and N × τ. For the PLL to perform frequency pull-in at high speed, it must have a sufficiently wide TD conversion range. In a typical PLL, it is desirable to have a range equivalent to one period of the reference clock, and the number of delay element stages N is set accordingly. Therefore, increasing the time resolution requires increasing the number of delay element stages N, which increases the circuit size. An example of a circuit that solves this problem is shown in the following figure. 【0030】 Figure 5 shows an example of the configuration of an oscillator used in conventional TDC. In this example, a ring oscillator is formed by looping cascaded delay elements. In this configuration, inverters with opposite polarity inputs and outputs are generally used as delay elements, and the number of delay element stages N is odd. Such an oscillator is equipped with two latch circuits at the output of each delay element forming the ring oscillator, which hold the output value at the timing of the target clock and the reference clock. In addition, such an oscillator is equipped with a loop counter that counts up or down the number of loops each time the change point of the delay element in the ring oscillator completes one loop, and further, it is equipped with two latch circuits that each hold the count of the loop counter at the timing of the target clock and the reference clock. In such a configuration, for example, if the loop counter value held at the timing of the target clock is M, and the change point of the delay element is at the Kth stage, and then the loop counter value held at the timing of the reference clock is M+m, and the change point of the delay element is at the K+k stage, then if the delay time per stage of the delay element is τ, then the time difference Δt between the reference clock and the target clock is Δt = τ × [{N × (M + mM)} + (K + kK)] = τ × (Nm + k). This is shown in the following figure. 【0031】 Figure 6 shows a diagram representing TDC conversion in the conventional technology. In this figure, the vertical axis represents the TDC output code, and the horizontal axis represents time. The TDC output increases stepwise with time, and returns to 0 (resets) when it reaches the maximum value that the loop counter can count. In such TDC conversion, the TDC output code is held at the timing of the reference clock and the timing of the target clock, and the difference between these TDC output codes becomes the TDC value. An example of a TDC configuration that realizes such calculation is shown in the following figure. 【0032】 Figure 7 shows an example of a TDC configuration in the prior art. In the prior art TDC, a reference clock and a target clock are input to an oscillator, and the oscillator outputs loop information, which is the value of the loop counter, and position information, which is the position of the change point of the delay element, as phase information, at the timing of the reference clock and the timing of the target clock, respectively. Next, the decoder calculates virtual phase information, which is the TDC output code, by performing the calculation loop information × number of stages N + position information. Then, after taking the difference between each of the virtual phase pieces in the subtractor, the TDC value is obtained by performing overflow processing. Note that in such overflow processing, for example, if the latch timing in the reference clock and the latch timing in the target clock are separated before and after the reset operation due to the loop counter overflow, the result of taking the difference may be negative or an excessively large value, so in that case, the value of counter maximum value × number of stages N is added or subtracted to make it an appropriate value. 【0033】 This circuit allows for a wide TD conversion range without increasing the number of delay element stages, even when the delay time of the delay element is short. However, a disadvantage is that quantization is performed using both the reference clock and the target clock, and the difference between the results is taken. As a result, quantization is performed twice in a single measurement, increasing the quantization noise power by √2 times. Further reduction of quantization noise is possible by arranging multiple circuits with the same configuration and averaging their respective TDC values, but this increases the circuit size and power consumption. Shortening the delay time of the delay element is the most effective solution, but generally, the delay time is limited by the performance of the transistors and the performance of the manufacturing process, such as the capacitance component, making reduction difficult. 【0034】 Therefore, a prior art technique implemented to reduce quantization noise is TDC, as shown in the following figure in Patent Document 1. 【0035】 Figure 8 shows an example of the TDC configuration in Patent Document 1. The TDC in Patent Document 1 consists of a PFD circuit that generates a PFD pulse signal with a width corresponding to the time difference between a reference clock and a target clock, an oscillator, a decoder, and a difference detector. The oscillator receives the PFD pulse signal generated by the PFD circuit and the reference clock (in this example, a signal with the polarity of the reference clock reversed). The oscillator then outputs rotation information and position information held at the timing of the reference clock, and virtual phase information is calculated by the decoder. Subsequently, the TDC value is obtained by detecting the difference with the difference detector. 【0036】 Figure 9 shows an example of the oscillator configuration used in TDC in Patent Document 1. Such an oscillator includes an N-stage ring oscillator using inverters as delay elements, and a latch circuit that holds the output value is connected to the output of each delay element. The oscillator also includes a loop counter that counts the number of loops of the ring oscillator. Each delay element, which is composed of inverters, is input with a PFD pulse as a control signal to control the operating mode. The delay elements are circuits in which the delay time is switched according to this control signal. For example, the delay elements can switch the delay time so that the delay time is short when the control signal is high and long when the control signal is low. 【0037】 Figure 10 shows an example of the configuration of a difference detector that may be used for TDC in Patent Document 1. The difference detector consists of a first D flip-flop (DFF) that holds virtual phase information at a point in time one clock cycle prior to the reference clock, a subtractor that calculates the difference between the input virtual phase information and the output of the first DFF, and an overflow processing unit, which outputs the value obtained by overflow processing the above difference as the TDC value. The overflow processing is as described above, so its explanation is omitted here. 【0038】 Figure 11 shows another configuration example of a difference detector that may be used for TDC in Patent Document 1. Depending on the circuit configuration of the latch built into the oscillator, data retention may be released midway depending on the state of the reference clock. For this reason, the difference detector may consist of a first DFF that takes virtual position information and holds virtual phase information at a point in time when the reference clock is one clock cycle prior, a second DFF that takes the output of the first DFF and holds virtual phase information at a point in time when the reference clock is two clock cycles prior, a subtractor that calculates the difference between the output of the first DFF and the output of the second DFF, and an overflow processing unit, and the value obtained by overflow processing the above difference may be output as the TDC value. 【0039】 The TDC operation in the configuration described in Figures 8 to 11 will be explained using diagrams. 【0040】 Figure 12 shows a diagram representing the TDC conversion described in Patent Document 1. In this figure, the vertical axis represents virtual phase information, and the horizontal axis represents time. In reality, the virtual phase information (i.e., the TDC output code, which is the result of decoding the oscillator output) takes quantum values, so the graph becomes a very fine step waveform, but in this figure, it is drawn as a straight line for simplification. As shown in this figure, the TDC output increases over time, with its slope changing in two ways. During the period when the PFD pulse is High, the delay time of the delay element is shortened, causing the oscillator to operate in a high-speed mode with a high oscillation frequency. As a result, during the period when the PFD pulse is High, the slope of the change in the TDC output becomes larger. On the other hand, during the period when the PFD pulse is Low, the delay time of the delay element is lengthened, causing the oscillator to operate in a low-speed mode with a low oscillation frequency. As a result, during the period when the PFD pulse is Low, the slope of the change in the TDC output becomes smaller. In this diagram, the duration for which the PFD pulse is High coincides with the time from the rising edge of the target clock to the falling edge of the reference clock. However, this is determined by the configuration of the PFD circuit and is not necessarily required. The virtual phase information is held at the timing of the rising edge of the reference clock, and as shown in the diagram, the difference between the value at the held timing and the value at the timing immediately preceding it becomes the TDC value. 【0041】 The behavior of quantization noise in this configuration is explained below. The nth TDC value D[n] is expressed as D[n]=Dr[n]-Dr[n-1] using the TDC output code Dr[n]. The TDC output code Dr[n] is expressed as Dr[n]=Dt[n]+Er[n] using the true value Dt[n] in an ideal TDC and the quantization error Er[n] generated by quantization. That is, the nth TDC value D[n] is D[n]=Dt[n]-Dt[n-1]+Er[n]-Er[n-1]. In other words, the quantization error Eq[n] contained in the nth TDC value D[n] is Eq[n]=Er[n]-Er[n-1]. When this is depicted in a signal processing model, it looks like the following figure Z -1 This means that the delayed value will be subtracted. 【0042】 Figure 13 shows a diagram representing the transfer model of quantization noise in TDC conversion as described in Patent Document 1. The transfer function H(Z) of this signal processing model is H(Z) = 1 - Z -1 It is expressed as follows, and its absolute value |H(Z)| is expressed by the following equation. Thus, it can be seen that the noise shaping effect of the first derivative can be obtained by the TDC transformation in Patent Document 1. 【number】 【0043】 Here, fs is the frequency of the reference clock, and f is the frequency component of the noise. Generally, quantization noise is white noise that is uniformly distributed across frequency components, but in this case, the noise shaping effect suppresses the noise more as the frequency component decreases. For example, if the frequency of the reference clock is 80 MHz, the 1 MHz component of the quantization noise will be suppressed by approximately 21 dB, which will greatly contribute to reducing the phase noise of the PLL. Next, we will explain the effect of suppressing the influence of changes in power supply voltage on phase noise in this configuration. The response to changes in power supply voltage when using the TDC shown in Figures 8 to 11 is shown in the following figure. 【0044】 Figure 14 shows a diagram illustrating the power supply dependence of TDC conversion in Patent Document 1. The delay element shown in Figure 9 is typically a simple inverter composed of CMOS transistors, and generally, the delay time decreases as the power supply voltage increases and increases as the power supply voltage decreases. Therefore, even if the width of the PFD pulse is the same, the obtained TDC value will change significantly depending on the power supply voltage. This means that if a PLL is configured and feedback is applied so that the output value of the TDC is constant, the width of the PFD pulse when the PLL is locked will change depending on the power supply voltage. In other words, fluctuations in the power supply voltage will cause fluctuations in the phase of the divided clock, meaning that fluctuations in the power supply voltage will appear as phase noise in the PLL. Therefore, Patent Document 1 uses the configuration shown in the following figure as a countermeasure against this. 【0045】 Figure 15 shows another configuration example of the TDC in Patent Document 1. In the TDC shown in this figure, in addition to the TDC shown in Figure 8, a second oscillator that always operates at a constant speed, a second decoder, and a second difference detector are further included. The TDC value is obtained by subtracting from the output of the first difference detector the output of the second difference detector multiplied by a certain coefficient. 【0046】 The TDC conversion in this configuration and its effect on changes in power supply voltage will be explained using the following diagram. 【0047】 Figure 16 shows a diagram illustrating TDC conversion in another configuration example of Patent Document 1. In this figure, the vertical axis represents virtual phase information, and the horizontal axis represents time. In this figure, the solid line represents the virtual phase information from the first oscillator, and the dashed line represents the virtual phase information from the second oscillator multiplied by a certain coefficient. The left side of the figure shows the case when the power supply voltage is low, and the right side shows the case when the power supply voltage is high. As already mentioned, the response of the first oscillator changes rapidly in the high-speed operation section corresponding to the section where the PFD pulse is high, and changes slowly otherwise. On the other hand, the value of the second oscillator changes at a constant speed. The difference between the virtual phase information of the first oscillator acquired by the reference clock and the value obtained by multiplying the virtual phase information of the second oscillator by a certain coefficient is the TDC value. Here, by applying PLL feedback so that this TDC value becomes 0, the PFD pulse width is appropriately adjusted and the PLL locks. In this case, for example, if the power supply voltage increases, the delay time of the delay element of the first oscillator decreases, so the virtual phase information that changes in one period also increases. Similarly, the delay time of the delay element of the second oscillator also decreases, so the virtual phase information that changes in one period also increases in conjunction, and as a result, the output TDC value does not change when the PLL is locked. In other words, even if the power supply voltage changes, the PFD pulse width when the PLL is locked does not change, and the change in power supply voltage is not converted into phase noise. Therefore, the impact on phase noise can be suppressed for slow changes in power supply voltage. However, performance deteriorates for rapid changes in power supply voltage. The simulation results of power supply voltage fluctuations in this configuration are shown in the following figure. 【0048】 Figure 17 shows a diagram illustrating power supply voltage fluctuations in another configuration example of Patent Document 1. In this figure, the vertical axis from top to bottom represents the reference clock, PFD pulse, power supply voltage, and current consumption, while the horizontal axis represents time. To obtain the simulation results shown in this figure, the ring oscillator is operated while rapidly switching the inverter delay time. Generally, the current consumption of a ring oscillator is proportional to the product of the delay time and the capacitive component of each inverter input, and the shorter the delay time, i.e., the faster the operation, the greater the current consumption. Therefore, when the operation of the ring oscillator is switched between high-speed and low-speed operation modes by the PFD pulse, the current consumed by the ring oscillator changes significantly. The bottom graph in this figure shows the current consumption of the ring oscillator, and it can be seen that the current consumption increases significantly while the PFD pulse is high, i.e., during the high-speed operation section, and is very low in other sections. In actual circuits, the power supply differs from an ideal power supply and has finite impedances such as parasitic resistance and inductance components. Therefore, when the current consumption changes rapidly, the power supply voltage fluctuates rapidly. In this case, if the width of the PFD pulse is short, the change in power supply voltage will not converge and the system will transition to the next operating mode. While the power supply voltage is changing, the delay time of the delay element will naturally change moment by moment in accordance with that power supply voltage, and will not be a constant delay time. Therefore, in cases where the system transitions to the next operating mode without the change in power supply voltage converging, the effect of the delay time change on the power supply voltage fluctuation will vary depending on the width of the PFD pulse, causing errors in the TDC value. This error will result in phase noise, hindering the reduction of noise in the PLL. In other words, the configuration described in Patent Document 1 lacks resistance to high-speed power supply voltage changes caused by its own current changes, and has the problem of degrading noise performance due to errors caused by power supply voltage changes. 【0049】 Similar problems can be seen in Patent Document 2. In Patent Document 2, switching noise is reduced by reducing the amount of current that changes during the gating operation of the oscillator (corresponding to the period when the PFD pulse is High in the above explanation), but fundamentally it is the same as Patent Document 1 in that it is affected by switching noise. 【0050】 Therefore, in light of these circumstances, the objective of each embodiment described below is to provide a TDC with good noise performance by suppressing the switching noise of the power supply that occurs during gating operation. 【0051】 Figure 18 shows an example configuration of the TD converter 10 according to the first embodiment. The TD converter 10 uses multiple phase information held in each of the multiple oscillators to convert the time difference between a reference clock and a target clock into a digital output value. In this case, the TD converter 10 operates at least two of the multiple oscillators in operating modes in which the oscillation frequencies differ from each other, according to the input signal indicating the time difference. Here, such an input signal may be a pulse signal having a pulse width corresponding to the time difference between the reference clock and the target clock. 【0052】 The TD converter 10 includes a PFD circuit 100, a first negation circuit 200, a second negation circuit 300, a plurality of oscillators 400, and an arithmetic circuit 500. 【0053】 The PFD circuit 100 receives a reference clock and a target clock whose time difference from the reference clock should be detected as input. Note that if the TD converter 10 is used in a PLL circuit, the divided clock, which is the feedback clock, may be used as the "target clock". The PFD circuit 100 generates and outputs a PFD pulse, which is a pulse signal with a pulse width corresponding to the time difference between the reference clock and the target clock. 【0054】 The first negation circuit 200 receives a reference clock signal. The first negation circuit 200 performs a negation operation and outputs a signal with the polarity of the reference clock reversed. 【0055】 The second negation circuit 300 receives the PFD pulse as input. The second negation circuit 300 performs a negation operation and outputs a signal with the polarity of the PFD pulse reversed. 【0056】 The plurality of oscillators 400 have at least a first oscillator 400A and a second oscillator 400B. In this embodiment, the case in which the plurality of oscillators 400 have only two oscillators, the first oscillator 400A and the second oscillator 400B, is shown as an example. However, the plurality of oscillators 400 may have one or more other oscillators in addition to the first oscillator 400A and the second oscillator 400B. Here, unless there is a particular need to distinguish them, the first oscillator 400A, the second oscillator 400B, and the other oscillators will be collectively referred to as oscillator 400. It is desirable that all oscillators 400 have the same circuit configuration and the same circuit arrangement, etc., so that their electrical characteristics are as similar as possible. 【0057】 Each of the first oscillator 400A and the second oscillator 400B may be configured to operate in at least two operating modes: a high-speed operating mode and a low-speed operating mode in which the oscillation frequency is lower than that of the high-speed operating mode, and the two operating modes may be switchable by a control signal. In this case, the first oscillator 400A may use a PFD pulse as a control signal to switch the operating mode, while the second oscillator 400B may use a signal obtained by inverting the polarity of the PFD pulse as a control signal to switch the operating mode. 【0058】 More specifically, the first oscillator 400A may receive input from the output of the PFD circuit 100 (i.e., the PFD pulse) and the output of the first negation circuit 200 (i.e., a signal with the polarity of the reference clock reversed). The first oscillator 400A may switch between a high-speed operation mode and a low-speed operation mode depending on the value of the PFD pulse. On the other hand, the second oscillator 400B may receive input from the output of the second negation circuit 300 (i.e., a signal with the polarity of the PFD pulse reversed) and the output of the first negation circuit 200. The second oscillator 400B may switch between a high-speed operation mode and a low-speed operation mode depending on the value of the signal with the polarity of the PFD pulse reversed. As a result, when the first oscillator 400A operates in high-speed mode, the second oscillator 400B may operate in low-speed mode, and when the first oscillator 400A operates in low-speed mode, the second oscillator 400B may operate in high-speed mode. The first oscillator 400A and the second oscillator 400B can operate in operating modes in which their oscillation frequencies differ from each other, for example, in this way, depending on an input signal (PFD pulse) indicating the time difference between a reference clock and a target clock. 【0059】 The oscillator 400 maintains phase information according to a reference clock (in this figure, a signal obtained by inverting the polarity of the reference clock). If the oscillator 400 includes a ring oscillator in which delay elements are connected in a ring shape, such phase information may include rotation information indicating the number of rotations of the ring oscillator, and position information indicating the position of the delay element where the logic level of the input and the logic level of the output are equal. 【0060】 The arithmetic circuit 500 uses multiple phase information held in each of the multiple oscillators 400 according to the reference clock to calculate a digital output value corresponding to the time difference between the reference clock and the target clock. Here, each of the multiple phase information may include, as described above, loop information indicating the number of times the ring oscillator has looped, and position information indicating the position of the delay element where the logic level of the input and the logic level of the output are equal. 【0061】 The arithmetic circuit 500 may include a plurality of decoders 510, a plurality of difference detectors 520, and an arithmetic processing unit 530. 【0062】 Multiple decoders 510 may each calculate virtual phase information representing virtual phase information using rotation information and position information for multiple phase information. In this embodiment, one example is shown where the multiple decoders 510 include only the first decoder 510A and the second decoder 510B. However, the multiple decoders 510 may have one or more other decoders in place of, or in addition to, the first decoder 510A and the second decoder 510B. Here, unless otherwise necessary, the first decoder 510A, the second decoder 510B, and the other decoders will be collectively referred to as decoder 510. 【0063】 Decoder 510 may calculate virtual phase information, which is the TDC output code, by calculating the number of stages of delay elements constituting the ring oscillator included in the corresponding oscillator 400, where N is the number of stages of delay elements, and then calculating the number of stages of delay elements × N + phase information. The first decoder 510A may calculate the first virtual phase information using the number of stages of delay information and position information included in the phase information held by the first oscillator 400A. Similarly, the second decoder 510B may calculate the second virtual phase information using the number of stages of delay information and position information included in the phase information held by the second oscillator 400B. 【0064】 Multiple difference detectors 520 may each receive multiple virtual phase information calculated by multiple decoders 510 and detect a TDC value that represents the difference between the input virtual phase information and the virtual phase information at a point in time one clock cycle prior to the reference clock. In this embodiment, one example is shown in which the multiple difference detectors 520 include only the first difference detector 520A and the second difference detector 520B. However, the multiple difference detectors 520 may have one or more other difference detectors in place of, or in addition to, the first difference detector 520A and the second difference detector 520B. Here, unless otherwise necessary, the first difference detector 520A, the second difference detector 520B, and the other difference detectors will be collectively referred to as difference detectors 520. 【0065】 The difference detector 520 may consist of a first DFF that holds virtual phase information at a point in time one clock cycle prior to the reference clock, a subtractor that calculates the difference between the input virtual phase information and the output of the first DFF, and an overflow processing unit, as shown in Figure 10. Alternatively, the difference detector 520 may consist of a first DFF that takes in virtual position information and holds virtual phase information at a point in time one clock cycle prior to the reference clock, a second DFF that takes in the output of the first DFF and holds virtual phase information at a point in time two clock cycles prior to the reference clock, a subtractor that calculates the difference between the output of the first DFF and the output of the second DFF, and an overflow processing unit, as shown in Figure 11. The first difference detector 520A may receive the first virtual phase information calculated by the first decoder 510A and the reference clock as input. The first difference detector 520A may detect a first TDC value that represents the difference between the input first virtual phase information and the first virtual phase information at a point in time when the reference clock was one clock cycle earlier. Similarly, the second difference detector 520B may be input with the second virtual phase information calculated by the second decoder 510B and the reference clock. The second difference detector 520B may then detect a second TDC value that represents the difference between the input second virtual phase information and the second virtual phase information at a point in time when the reference clock was one clock cycle earlier. 【0066】 The arithmetic processing unit 530 may calculate a digital output value corresponding to the time difference between the reference clock and the target clock based on multiple TDC values ​​detected by multiple difference detectors 520. In this embodiment, the arithmetic processing unit 530 may calculate a digital output value corresponding to the time difference between the reference clock and the target clock based on a first TDC value detected by the first difference detector 520A and a second TDC value detected by the second difference detector 520B. Details of the arithmetic processing unit 530 will be described later. 【0067】 Figure 19 shows an example configuration of a ring oscillator that may be included in the oscillator 400. In the ring oscillator, an inverter may be used as the delay element 410. Such delay elements 410 may be connected in cascaded order in a ring shape. Each delay element 410 may be input to a control signal that controls the operating mode. The delay elements 410 may be configured such that the delay time is switched according to this control signal. For example, the delay element 410 may be able to switch the delay time such that the delay time is short when the control signal is high and long when the control signal is low. 【0068】 Each of the multiple oscillators 400 may include a ring oscillator in which delay elements 410 are connected in a ring shape. Here, as described above, the first oscillator 400A may use the PFD pulse as a control signal. Therefore, the first oscillator 400A may operate in high-speed mode by switching so that the delay time of the delay element 410 is shortened when the PFD pulse is High. Also, the first oscillator 400A may operate in low-speed mode by switching so that the delay time of the delay element 410 is lengthened when the PFD pulse is Low. On the other hand, the second oscillator 400B may use a signal with the polarity of the PFD pulse reversed as a control signal. Therefore, the second oscillator 400B may operate in low-speed mode by switching so that the delay time of the delay element 410 is lengthened when the PFD pulse is High. Furthermore, the second oscillator 400B may operate in high-speed mode by switching to a shorter delay time in the delay element 410 when the PFD pulse is low. Each of the first oscillator 400A and the second oscillator 400B may be configured to switch operating modes by switching the delay time in the delay element 410 in response to the input signal (PFD pulse), for example in this manner. 【0069】 Although not shown in the diagram here, each of the multiple oscillators 400 may include a latch circuit that holds the output value of each delay element 410 at the timing of a reference clock (in this embodiment, a signal with the polarity of the reference clock reversed) and a loop counter that counts the number of times the ring oscillator has cycled, as shown in Figure 9. 【0070】 Figure 20 shows a first configuration example of the arithmetic processing unit 530. The arithmetic processing unit 530 in the first configuration example may include a dependency value extraction unit 532. The dependency value extraction unit 532 may extract a dependency value from each of a plurality of TDC values ​​that indicates a value that changes depending on the time difference between the reference clock and the target clock. More specifically, the dependency value extraction unit 532 may be composed of a first subtractor 533. The first subtractor 533 may calculate the difference between a first TDC value and a second TDC value among the plurality of TDC values. The dependency value extraction unit 532 may extract the difference between the first TDC value and the second TDC value calculated by the first subtractor 533 as a dependency value. In the first configuration example, the dependency value extraction unit 532 may output the dependency value extracted in this way as a digital output value. This will be explained in detail using a graph. 【0071】 Figure 21 shows the calculation performed by the arithmetic processing unit 530 according to the first configuration example. In this figure, the vertical axis represents the TDC value, and the horizontal axis represents the time difference between the reference clock and the target clock, i.e., the pulse width of the PFD pulse. In this figure, the dashed line represents the first TDC value, the dashed line represents the second TDC value, and the solid line represents the output value of the first subtractor 533. 【0072】 The first TDC value increases as the pulse width of the PFD pulse increases, because the proportion of time that the first oscillator 400A operates in high-speed mode during one cycle increases. Therefore, the first TDC value has a positive slope. On the other hand, the second TDC value decreases as the pulse width of the PFD pulse increases, because the proportion of time that the second oscillator 400B operates in low-speed mode during one cycle increases. Therefore, the second TDC value has a negative slope. 【0073】 Therefore, the output value of the first subtractor 533, which calculates the difference between the first TDC value and the second TDC value, shows a response that changes more significantly depending on the pulse width of the PFD pulse. In this example, since the second TDC value is subtracted from the first TDC value, it shows a response with a positive slope. In this way, the first subtractor 533 provides a dependency value extraction unit 532, that is, a time difference information extraction unit, which extracts a dependency value from each TDC value that shows a value that changes depending on the pulse width of the PFD pulse. In the first configuration example, the dependency value extraction unit 532 may output the dependency value showing the time difference information extracted in this way as a digital output value. 【0074】 Figure 22 shows a second configuration example of the arithmetic processing unit 530. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 20, and explanations are omitted below except for differences. The arithmetic processing unit 530 according to the second configuration example may further include an independent value extraction unit 534, a multiplier 537, and a difference output unit 538, in addition to the functional units included in the arithmetic processing unit 530 according to the first configuration example. 【0075】 The independence value extraction unit 534 may extract an independence value from each of the multiple TDC values ​​that represents a value independent of the time difference between the reference clock and the target clock. More specifically, the independence value extraction unit 534 may consist of an adder 535. The adder 535 may calculate the sum of a first TDC value and a second TDC value among the multiple TDC values. The independence value extraction unit 534 may extract the sum of the first TDC value and the second TDC value calculated by the adder 535 as the independence value. 【0076】 The multiplier 537 may multiply the independent value extracted by the independent value extraction unit 534 by a predetermined coefficient. 【0077】 The difference output unit 538 may calculate the difference between the dependent value extracted by the dependent value extraction unit 532 and the independent value extracted by the independent value extraction unit 534, and output the difference as a digital output value. More specifically, the difference output unit 538 may consist of a second subtractor 539. The second subtractor 539 may calculate the difference between the dependent value extracted by the dependent value extraction unit 532 and the independent value extracted by the independent value extraction unit 534 and multiplied by a coefficient by the multiplier 537. The difference output unit 538 may output the difference calculated by the second subtractor 539 as a digital value. This will be explained in detail using a graph. 【0078】 Figure 23 shows the calculation performed by the arithmetic processing unit 530 according to the second configuration example. In this figure, the vertical axis represents the TDC value, and the horizontal axis represents the time difference between the reference clock and the target clock, i.e., the pulse width of the PFD pulse. In this figure, the dashed line represents the output value of the first subtractor 533, the dashed line represents the output value of the adder 535, the dotted line represents the output value of the multiplier 537, and the solid line represents the output value of the second subtractor 539. 【0079】 The first oscillator 400A and the second oscillator 400B have nearly identical electrical characteristics by using the same circuit configuration and circuit arrangement. Therefore, the absolute value of the slope of the first TDC value and the absolute value of the slope of the second TDC value are nearly equal. Thus, the output of the adder 535, which calculates the sum of the first TDC value and the second TDC value, functions as an independent value extraction unit 534 that extracts an independent value that is independent of the pulse width of the PFD pulse. The multiplier 537 may multiply the output of the adder 535, which thus takes a value that is approximately constant with respect to the pulse width, by a predetermined appropriate coefficient. The second subtractor 539 may obtain the final digital output value by calculating the difference between the output of the first subtractor 533 and the output of the multiplier 537. 【0080】 In the arithmetic processing unit 530 according to the second configuration example, the zero-crossing point of the TDC output can be controlled by the coefficient in the multiplier 537, for example, as shown above. Therefore, in a PLL circuit using such a TD converter 10, it is possible to control which phase state the PLL is locked in. Furthermore, if the power supply voltage increases or decreases at a sufficiently slow rate compared to the period of the reference clock, the operating speed of the first oscillator 400A and the second oscillator 400B increases or decreases at the same rate, so the output value of the first subtractor 533 and the output value of the adder 535 also increase or decrease at the same rate. As a result, the zero-crossing point of the final obtained digital output value does not change, and the phase difference at which the PLL circuit is locked does not change due to the power supply. 【0081】 Generally, in a type of PLL circuit called a Fractional-N PLL, the frequency division ratio in the frequency divider shown in Figure 2 is dynamically changed to achieve an average fractional frequency division ratio. Therefore, the difference between the phase of the reference clock and the phase of the divided clock increases and decreases over time, but on average it operates to maintain a constant phase difference. In other words, the pulse width of the PFD pulse will have a certain degree of variation. PFD circuits generally have a defined phase difference range in which they operate stably, and they exhibit discontinuous responses when the pulse width of the PFD pulse is zero or at its maximum width. Therefore, in order to achieve stable PLL operation, it is necessary to avoid these regions. 【0082】 Since the phase difference at which the digital output value crosses zero is the phase difference that corresponds to the average pulse width of the PFD pulse, the coefficient given to the multiplier 537 must be determined to ensure stable operation of the PFD circuit, taking into account the range of variation in the PFD pulse that can occur when operating as a Fractional-N PLL. The coefficient given to the multiplier 537 may be a predetermined design value for stable operation of the PLL circuit, and within the range in which the PLL circuit operates stably, the choice of this coefficient does not directly affect the effectiveness of the TD converter 10. 【0083】 Figure 24 shows a third configuration example of the arithmetic processing unit 530. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 22, and explanations are omitted below except for differences. In the arithmetic processing unit 530 according to the second configuration example, the output of the adder 535 is input to the multiplier 537, and the difference between the output of the multiplier 537 and the output of the first subtractor 533 is taken by the second subtractor 539 to obtain a digital output value. In the arithmetic processing unit 530 according to the third configuration example, the output of the first subtractor 533 is input to the multiplier 537, and the difference between the output of the multiplier 537 and the output of the adder 535 is taken by the second subtractor 539 to obtain a digital output value. 【0084】 Figure 25 shows the calculation performed by the arithmetic processing unit 530 according to the third configuration example. In this figure, the vertical axis represents the TDC value, and the horizontal axis represents the time difference between the reference clock and the target clock, i.e., the pulse width of the PFD pulse. In this figure, the dashed line represents the output value of the first subtractor 533, the dashed line represents the output value of the adder 535, the dotted line represents the output value of the multiplier 537, and the solid line represents the output value of the second subtractor 539. 【0085】 In the arithmetic processing unit 530 according to the third configuration example, the multiplier 537 may multiply the output of the first subtractor 533, which shows a response with a positive slope with respect to the pulse width of the PFD pulse, by a predetermined appropriate coefficient. The second subtractor 539 may then obtain the final digital output value by calculating the difference between the output of the multiplier 537 and the output of the adder 535. That is, instead of multiplying the independent value extracted by the independent value extraction unit 534 by a predetermined coefficient, the multiplier 537 may multiply the dependent value extracted by the dependent value extraction unit 532 by a predetermined coefficient. Therefore, the arithmetic processing unit 530 may further include a multiplier 537 that multiplies a dependent value or an independent value by a predetermined coefficient, as in the second or third configuration example. 【0086】 Similar to the second configuration example, the arithmetic processing unit 530 in the third configuration example can also control the zero-crossing point of the TDC output by the coefficient in the multiplier 537. Therefore, in a PLL circuit using such a TD converter 10, it is possible to control which phase state the PLL is locked in. Furthermore, if the power supply voltage increases or decreases at a sufficiently slow rate compared to the period of the reference clock, the operating speed of the first oscillator 400A and the second oscillator 400B increases or decreases at the same rate, so the output value of the first subtractor 533 and the output value of the adder 535 also increase or decrease at the same rate. As a result, the zero-crossing point of the final obtained digital output value does not change, and the phase difference at which the PLL circuit is locked does not change due to the power supply. Thus, the TD converter 10 can obtain the same effect as when using the arithmetic processing unit 530 in the second configuration example, even when using the arithmetic processing unit 530 in the third configuration example. 【0087】 Figure 26 shows an example of a timing chart for the TD converter 10 according to the first embodiment. In this figure, the vertical axis, from top to bottom, represents the target clock, reference clock, PFD pulse, operating mode of the first oscillator 400A, operating mode of the second oscillator 400B, first virtual phase information, second virtual phase information, first TDC value, second TDC value, and digital output value, while the horizontal axis represents time. 【0088】 As shown in this figure, PFD pulses are generated at the rising edge of the target clock and the rising edge of the reference clock. During the period when these PFD pulses are High, the first oscillator 400A operates in high-speed mode and the second oscillator 400B operates in low-speed mode. Conversely, during the period when the PFD pulses are Low, the first oscillator 400A operates in low-speed mode and the second oscillator 400B operates in high-speed mode. 【0089】 Then, at the falling edge of the reference clock, the first virtual phase information (i.e., the output of the first decoder 510A) and the second virtual phase information (i.e., the output of the second decoder 510B) are updated. Also, at the rising edge of the reference clock, the first TDC value (i.e., the output of the first difference detector 520A) and the second TDC value (i.e., the output of the second difference detector 520B) are updated, and the digital output value is updated accordingly. 【0090】 Figure 27 shows a diagram illustrating the power supply voltage fluctuation in the TD converter 10 according to the first embodiment. In this figure, the vertical axis from top to bottom represents the reference clock, PFD pulse, power supply voltage, and current consumption, while the horizontal axis represents time. In obtaining the simulation results shown in this figure, the ring oscillator was operated while rapidly switching the inverter delay time, similar to how the simulation results shown in Figure 17 were obtained. 【0091】 In Figure 17, the power supply voltage changed due to a change in current consumption in response to the change in the PFD pulse. However, in this figure, there is almost no change in the power supply voltage in response to the change in the PFD pulse. This is because, in the TD converter 10 according to the first embodiment, the two oscillators 400, the first oscillator 400A and the second oscillator 400B, operate complementaryly in different operating modes, and as shown in this figure, the combined current consumption of the two oscillators 400 remains constant. Thus, in the TD converter 10 according to the first embodiment, there is no change in the power supply voltage in response to the PFD pulse, and the oscillators 400 always operate at an ideal power supply voltage. As a result, errors in the digital output value due to changes in the power supply voltage are eliminated, and more accurate TD conversion can be achieved. 【0092】 Figure 28 shows an example configuration of the TD converter 10 according to the second embodiment. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 18, and explanations are omitted below except for differences. In the first embodiment, one example was shown in which the first oscillator 400A and the second oscillator 400B hold phase information according to a clock signal of the same polarity (a signal with the polarity of the reference clock reversed). However, in the second embodiment, the first oscillator 400A and the second oscillator 400B may hold phase information according to clock signals with different polarities. 【0093】 In the first embodiment, the output of the second negative circuit 300 and the output of the first negative circuit 200 were input to the second oscillator 400B. However, in the second embodiment, the output of the second negative circuit 300 and a reference clock may be input to the second oscillator 400B. Therefore, in the second embodiment, the first oscillator 400A may hold phase information according to a signal with the polarity of the reference clock inverted, while the second oscillator 400B may hold phase information according to the reference clock. In the second embodiment, the first oscillator 400A and the second oscillator 400B may, for example, hold phase information according to clock signals with different polarities in this manner. 【0094】 Furthermore, the TD converter 10 according to the second embodiment may further include a DFF 600. The DFF 600 may receive the second virtual phase information calculated by the second decoder 510B and the output of the first negation circuit 200 as inputs. The DFF 600 may then take the output of the second decoder 510B as a clock signal with the same polarity as the first oscillator 400A (a signal with the polarity of the reference clock reversed) and output it to the second difference detector 520B. 【0095】 As an alternative configuration, a reference clock may be input to the DFF600, and the output of the first negation circuit 200 may be input to the second difference detector 520B. That is, the clock used for the DFF600 may have the same polarity as the clock used for the second oscillator 400B, and the clock used for the second difference detector 520B may have the opposite polarity to the clock used for the first difference detector 520A. 【0096】 Figure 29 shows an example of a timing chart for the TD converter 10 according to the second embodiment. In this figure, the vertical axis, from top to bottom, represents the target clock, reference clock, PFD pulse, operating mode of the first oscillator 400A, operating mode of the second oscillator 400B, first virtual phase information, second virtual phase information, output of the DFF 600, first TDC value, second TDC value, and digital output value, while the horizontal axis represents time. 【0097】 In the first embodiment, the second virtual phase information was updated at the falling edge of the reference clock, just like the first virtual phase information, whereas in the second embodiment, the second virtual phase information is updated at the rising edge of the reference clock. The output of the DFF600 is then updated at the falling edge of the reference clock. 【0098】 In the first embodiment, the acquisition of the second virtual phase information was performed while the second oscillator 400B was operating in high-speed mode. However, in the second embodiment, the acquisition of the second virtual phase information can be performed just before the second oscillator 400B terminates its low-speed mode, thereby easing the required operating speed of the latch circuit and loop counter included in the second oscillator 400B. 【0099】 Figure 30 shows an example configuration of the TD converter 10 according to the third embodiment. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 18, and descriptions are omitted below except for differences. In the third embodiment, the plurality of oscillators 400 may further include a third oscillator 400C. Furthermore, in the third embodiment, only the output of the second negative circuit 300 is input to the second oscillator 400B, and the output of the first negative circuit 200 is not input. That is, the second oscillator 400B only needs to operate in a different operating mode from the first oscillator 400A, and does not need to retain phase information. Therefore, in the third embodiment, the plurality of decoders 510 do not need to include a second decoder 510B. Also, the plurality of difference detectors 520 do not need to include a second difference detector 520B. On the other hand, the plurality of decoders 510 may include a third decoder 510C. Furthermore, the multiple difference detectors 520 may include a third difference detector 520C. 【0100】 It is desirable that the third oscillator 400C, like the first oscillator 400A and the second oscillator 400B, have the same circuit configuration and circuit layout so that their electrical characteristics are as similar as possible. 【0101】 The output of the first negation circuit 200 (i.e., a signal with the polarity of the reference clock reversed) may be input to the third oscillator 400C. On the other hand, neither signal is required to be input to the third oscillator 400C as a control signal to control the operating mode. In other words, the third oscillator 400C may always operate at a constant oscillation frequency regardless of the pulse width of the PFD pulse. That is, in the third embodiment, the first oscillator 400A switches the operating mode using the PFD pulse as a control signal, and the second oscillator 400B switches the operating mode using a signal with the polarity of the PFD pulse reversed as a control signal, while the third oscillator 400C may continue to operate in a fixed operating mode with a constant oscillation frequency. In this figure, an example is shown in which only one set of oscillators 400 (the first oscillator 400A and the second oscillator 400B) are operated complementaryly in high-speed and low-speed modes, and only one oscillator 400 (the third oscillator 400C) is operated in fixed mode. However, the diagram is not limited to this. Multiple sets of oscillators 400 may be operated complementaryly in high-speed and low-speed modes, multiple oscillators 400 may be operated in fixed mode, or multiple sets of oscillators 400 may be operated complementaryly in high-speed and low-speed modes, and multiple oscillators 400 may be operated in fixed mode. 【0102】 The third oscillator 400C, like the first oscillator 400A, holds phase information according to a reference clock (in this figure, a signal with the polarity of the reference clock reversed). Such phase information may include orbital information and positional information. 【0103】 The third decoder 510C, like the first decoder 510A, may calculate a third virtual phase information using the rotation information and position information contained in the phase information held by the third oscillator 400C. 【0104】 The third difference detector 520C, like the first difference detector 520A, may detect a third TDC value that indicates the difference between the input third virtual phase information and the third virtual phase information at a point in time when the reference clock was one clock cycle earlier. 【0105】 The arithmetic processing unit 530 may calculate a digital output value corresponding to the time difference between the reference clock and the target clock based on the first TDC value detected by the first difference detector 520A and the third TDC value detected by the third difference detector 520C. Details of the arithmetic processing unit 530 according to the third embodiment are shown in the following figure. 【0106】 Figure 31 shows a fourth configuration example of the arithmetic processing unit 530. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 22, and explanations are omitted below except for differences. The arithmetic processing unit 530 in the fourth configuration example does not need to include the dependency value extraction unit 532 and the independent value extraction unit 534. The multiplier 537 may multiply the third TDC value by a predetermined coefficient. The second subtractor 539 may calculate the difference between the first TDC value and the output of the multiplier 537 and output the difference as a digital output value. 【0107】 Figure 32 shows the calculation performed by the arithmetic processing unit 530 according to the fourth configuration example. In this figure, the vertical axis represents the TDC value, and the horizontal axis represents the time difference between the reference clock and the target clock, i.e., the pulse width of the PFD pulse. In this figure, the dashed line represents the first TDC value, the dashed line represents the third TDC value, the dotted line represents the output value of the multiplier 537, and the solid line represents the output value of the second subtractor 539. 【0108】 The first TDC value increases as the pulse width of the PFD pulse lengthens, because the proportion of time that the first oscillator 400A operates in high-speed mode during one cycle increases. Therefore, the first TDC value has a positive slope. On the other hand, the third TDC value is a constant output that does not depend on the pulse width of the PFD pulse because the third oscillator 400C is always operating at a constant oscillation frequency. The multiplier 537 may multiply the third TDC value, which thus takes a value that is approximately constant with respect to the pulse width, by a predetermined appropriate coefficient. The second subtractor 539 may then obtain the final digital output value by calculating the difference between the first TDC value and the output of the multiplier 537. 【0109】 In the TD converter 10 according to the third embodiment, the zero-crossing point of the TDC output can also be controlled by the coefficient in the multiplier 537. Therefore, even in a PLL circuit using such a TD converter 10, it is possible to control which phase state the PLL is locked in. Furthermore, if the power supply voltage increases or decreases at a sufficiently slow rate compared to the period of the reference clock, the operating speed of the first oscillator 400A and the third oscillator 400C will increase or decrease at the same rate, and therefore the first TDC value and the third TDC value will also increase or decrease at the same rate. As a result, the zero-crossing point of the final obtained digital output value does not change, and the phase difference at which the PLL circuit is locked does not change due to the power supply. 【0110】 Furthermore, in the TD converter 10 according to the third embodiment, the two oscillators 400, the first oscillator 400A and the second oscillator 400B, operate complementaryly in different operating modes, so the combined current consumption of the two oscillators 400 remains constant. As a result, there is no change in the power supply voltage in response to the PFD pulse, and the oscillators 400 always operate at an ideal power supply voltage. This eliminates errors in the digital output value due to changes in the power supply voltage, enabling more accurate TD conversion. 【0111】 Figure 33 shows an example configuration of the TD converter 10 according to the fourth embodiment. In this figure, the same reference numerals are used for components having the same function and configuration as in Figures 18 and 30, and explanations are omitted below except for differences. The TD converter 10 according to the fourth embodiment is the TD converter 10 according to the first embodiment with the addition of a third oscillator 400C, a third decoder 510C, and a third difference detector 520C from the TD converter 10 according to the third embodiment. In this figure, one example is shown in which only one set of oscillators 400 (the first oscillator 400A and the second oscillator 400B) are operated complementaryly in high-speed and low-speed operation modes, and only one oscillator 400 (the third oscillator 400C) is operated in fixed operation mode, but it is not limited to this. Multiple sets of oscillators 400 may be operated complementaryly in high-speed and low-speed operation modes, multiple oscillators 400 may be operated in fixed operation mode, or multiple sets of oscillators 400 may be operated complementaryly in high-speed and low-speed operation modes, and multiple oscillators 400 may be operated in fixed operation mode. Details of the arithmetic processing unit 530 according to the fourth embodiment are shown in the following figure. 【0112】 Figure 34 shows a fifth configuration example of the arithmetic processing unit 530. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 31, and explanations are omitted below except for differences. In the arithmetic processing unit 530 according to the fourth configuration example, the second subtractor 539 may calculate the difference between the first TDC value and the output of the second TDC value and the multiplier 537, and output the difference as a digital output value. 【0113】 Figure 35 shows the calculation performed by the arithmetic processing unit 530 according to the fifth configuration example. In this figure, the vertical axis represents the TDC value, and the horizontal axis represents the time difference between the reference clock and the target clock, i.e., the pulse width of the PFD pulse. In this figure, the dashed line represents the first TDC value, the dashed line represents the second TDC value, the dotted line represents the third TDC value, the dashed line represents the difference between the first TDC value and the second TDC value, the long dashed line represents the output value of the multiplier 537, and the solid line represents the output value of the second subtractor 539. 【0114】 The first TDC value increases as the pulse width of the PFD pulse increases, because the proportion of time that the first oscillator 400A operates in high-speed mode during one cycle increases. Therefore, the first TDC value has a positive slope. On the other hand, the second TDC value decreases as the pulse width of the PFD pulse increases, because the proportion of time that the second oscillator 400B operates in low-speed mode during one cycle increases. Therefore, the second TDC value has a negative slope. Consequently, the difference between the first and second TDC values ​​shows a response that changes more significantly depending on the pulse width of the PFD pulse. In this example, since the second TDC value is subtracted from the first TDC value, it shows a response with a positive slope. 【0115】 Furthermore, the third TDC value is a constant output that does not depend on the pulse width of the PFD pulse because the third oscillator 400C is always operating at a constant oscillation frequency. The multiplier 537 may multiply the third TDC value, which thus takes a value that is approximately constant with respect to the pulse width, by a predetermined appropriate coefficient. The second subtractor 539 may then obtain the final digital output value by subtracting the output value of the multiplier 537 from the difference between the first TDC value and the second TDC value. 【0116】 In the TD converter 10 according to the fourth embodiment, the zero-crossing point of the TDC output can also be controlled by the coefficient in the multiplier 537. Therefore, even in a PLL circuit using such a TD converter 10, it is possible to control which phase state the PLL is locked in. Furthermore, if the power supply voltage increases or decreases at a sufficiently slow rate compared to the period of the reference clock, the operating speed of the first oscillator 400A, the second oscillator 400B, and the third oscillator 400C will increase or decrease at the same rate, and the first TDC value, the second TDC value, and the third TDC value will also increase or decrease at the same rate. As a result, the zero-crossing point of the final obtained digital output value does not change, and the phase difference at which the PLL circuit is locked does not change due to the power supply. 【0117】 Furthermore, in the TD converter 10 according to the fourth embodiment, the two oscillators 400, the first oscillator 400A and the second oscillator 400B, operate complementaryly in different operating modes, so the combined current consumption of the two oscillators 400 remains constant. Therefore, there is no change in the power supply voltage in response to the PFD pulse, and the oscillators 400 always operate at an ideal power supply voltage. As a result, errors in the digital output value due to changes in the power supply voltage are eliminated, enabling more accurate TD conversion. 【0118】 Figure 36 shows an example of the configuration of the TD converter 10 according to the fifth embodiment. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 18, and explanations are omitted below except for differences. In the TD converter 10 according to the first embodiment, one example was shown in which one set of oscillators 400 (first oscillator 400A and second oscillator 400B) are operated complementaryly in different operating modes, but in the TD converter 10 according to the fifth embodiment, two sets of oscillators 400 may be operated complementaryly in different operating modes. 【0119】 In the TD converter 10 according to the fifth embodiment, the plurality of oscillators 400 may further include a fourth oscillator 400A' and a fifth oscillator 400B'. The fourth oscillator 400A' may be the same as the first oscillator 400A, and the fifth oscillator 400B' may be the same as the second oscillator 400B, so their explanation is omitted here. 【0120】 Furthermore, the decoder 510 may further include a fourth decoder 510A' and a fifth decoder 510B'. The fourth decoder 510A' may be the same as the first decoder 510A, and the fifth decoder 510B' may be the same as the second decoder 510B, so their explanation is omitted here. 【0121】 Furthermore, the multiple difference detectors 520 may further include a fourth difference detector 520A' and a fifth difference detector 520B'. The fourth difference detector 520A' may be the same as the first difference detector 520A, and the fifth difference detector 520B' may be the same as the second difference detector 520B, so their explanation is omitted here. The fourth difference detector 520A' detects the fourth TDC value, and the fifth difference detector 520B' detects the fifth TDC value. Details of the arithmetic processing unit 530 according to the fifth embodiment are shown in the following figure. 【0122】 Figure 37 shows a sixth configuration example of the arithmetic processing unit 530. In this figure, the same reference numerals are used for components having the same function and configuration as in Figure 22, and explanations are omitted below except for differences. In the arithmetic processing unit 530 according to the sixth configuration example, the first subtractor 533 may subtract the second TDC value and the fifth TDC value from the sum of the first TDC value and the fourth TDC value. The adder 535 may sum all of the first TDC value, the second TDC value, the fourth TDC value, and the fifth TDC value. 【0123】 In the TD converter 10 according to the sixth embodiment, the influence of quantization noise generated at each point and other noise generated during the operation of the oscillator 400 can be reduced to 1 / √2 compared to the first embodiment. In the above description, the case in which two sets of oscillators 400 are operated complementaryly in different operating modes was shown as an example, but the number of sets of oscillators 400 that operate complementaryly is not limited to two sets, but can be extended to N sets. In this case, the influence of noise becomes 1 / √N, so a further noise reduction effect can be expected. However, since the current consumption must always be constant, the number of oscillators 400 operating at high speed and the number of oscillators 400 operating at low speed must be the same. 【0124】 As described using various embodiments, a TD converter 10 is provided that can minimize the change in current consumption during gating operation, thereby suppressing the occurrence of power supply voltage switching and reducing switching noise during TD conversion. A PLL circuit equipped with such a TD converter 10 is also provided. Although each embodiment has been described separately in the above description, these embodiments may be combined with other embodiments as appropriate, as long as there is no particular contradiction. 【0125】 Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention. 【0126】 It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols] 【0127】 10 TD converter 100 PFD circuit 200 First Negation Circuit 300 Second Negation Circuit 400 Oscillators 410 Delay element 500 arithmetic circuit 510 Decoder 520 Differential Detectors 530 Arithmetic Processing Unit 532 Dependency Value Extraction Unit 533 First Subtractor 534 Independent Value Extraction Unit 535 Adder 537 Multiplier 538 Difference Output Section 539 Second Subtractor 600 DFF

Claims

[Claim 1] A plurality of oscillators having at least a first oscillator and a second oscillator that operate in operating modes with different oscillation frequencies in response to a control signal indicating the time difference between a reference clock and a target clock, A calculation circuit that uses a plurality of phase information held in each of the plurality of oscillators according to the reference clock to calculate a digital output value corresponding to the time difference, Equipped with, Each of the first oscillator and the second oscillator is configured to operate in at least two operating modes: a high-speed operating mode and a low-speed operating mode in which the oscillation frequency is lower than that of the high-speed operating mode. When the first oscillator operates in the high-speed operation mode, the second oscillator operates in the low-speed operation mode, and when the first oscillator operates in the low-speed operation mode, the second oscillator operates in the high-speed operation mode. TD converter. [Claim 2] A plurality of oscillators having at least a first oscillator and a second oscillator that operate in operating modes with different oscillation frequencies in response to a control signal indicating the time difference between a reference clock and a target clock, A calculation circuit that uses a plurality of phase information held in each of the plurality of oscillators according to the reference clock to calculate a digital output value corresponding to the time difference, Equipped with, Each of the aforementioned plurality of oscillators includes a ring oscillator in which delay elements are connected in a ring shape in series, Each of the aforementioned plurality of phase information includes rotation information indicating the number of rotations of the ring oscillator, and position information indicating the position of the delay element where the logic level of the input and the logic level of the output are equal. The aforementioned arithmetic circuit is A plurality of decoders that calculate virtual phase information representing virtual phase information using the rotation information and position information for the plurality of phase information, Multiple difference detectors each input multiple virtual phase information calculated by the multiple decoders, and each detector detects a TDC value that represents the difference between the input virtual phase information and the virtual phase information at a point in time when the reference clock was one clock cycle prior. A calculation processing unit that calculates the digital output value based on a plurality of TDC values ​​detected by the plurality of difference detectors, It has, The aforementioned arithmetic processing unit is A dependency value extraction unit extracts a dependency value from each of the plurality of TDC values ​​that indicates a value that changes depending on the time difference, An independent value extraction unit that extracts an independent value from each of the plurality of TDC values ​​that represents a value independent of the time difference, A difference output unit calculates the difference between the dependent value and the independent value and outputs the difference as the digital output value, including TD converter. [Claim 3] The TD converter according to claim 2, wherein each of the first oscillator and the second oscillator is configured to operate in at least two operating modes: a high-speed operating mode and a low-speed operating mode in which the oscillation frequency is lower than that of the high-speed operating mode. [Claim 4] The TD converter according to claim 3, wherein the second oscillator operates in the low-speed operation mode when the first oscillator operates in the high-speed operation mode, and the second oscillator operates in the high-speed operation mode when the first oscillator operates in the low-speed operation mode. [Claim 5] The TD converter according to claim 1, wherein each of the plurality of oscillators includes a ring oscillator in which delay elements are connected in a ring shape. [Claim 6] The TD converter according to claim 2 or 5, wherein each of the first oscillator and the second oscillator is configured to switch the operating mode by switching the delay time in the delay element according to the control signal. [Claim 7] The TD converter according to claim 5, wherein each of the plurality of phase information includes rotation information indicating the number of rotations of the ring oscillator, and position information indicating the position of the delay element where the logic level of the input and the logic level of the output are equal. [Claim 8] The aforementioned arithmetic circuit is A plurality of decoders that calculate virtual phase information representing virtual phase information using the rotation information and position information for the plurality of phase information, Multiple difference detectors each input multiple virtual phase information calculated by the multiple decoders, and each detector detects a TDC value that represents the difference between the input virtual phase information and the virtual phase information at a point in time when the reference clock was one clock cycle prior. A calculation processing unit that calculates the digital output value based on a plurality of TDC values ​​detected by the plurality of difference detectors, The TD converter according to claim 7, having the following features. [Claim 9] The TD converter according to claim 8, wherein the calculation processing unit includes a dependency value extraction unit that extracts a dependency value from each of the plurality of TDC values ​​that indicates a value that changes depending on the time difference. [Claim 10] The TD converter according to claim 2 or 9, wherein the dependency value extraction unit is comprised of a subtractor that calculates the difference between a first TDC value and a second TDC value among the plurality of TDC values. [Claim 11] The TD converter according to claim 9, wherein the dependency value extraction unit outputs the dependency value as the digital output value. [Claim 12] The TD converter according to claim 2, wherein the independent value extraction unit is comprised of an adder that calculates the sum of a first TDC value and a second TDC value among the plurality of TDC values. [Claim 13] The TD converter according to claim 2, wherein the calculation processing unit further includes a multiplier that multiplies the dependent value or the independent value by a predetermined coefficient. [Claim 14] The TD converter according to any one of claims 1 to 5, wherein the control signal is a pulse signal having a pulse width corresponding to the time difference between the reference clock and the target clock. [Claim 15] A PLL circuit comprising a TD converter according to any one of claims 1 to 5.

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