Display panel and display device

Abstract

The embodiment of the present invention discloses a display panel and a display device. The display panel includes: a plurality of scan lines, a plurality of rows of pixel circuits and at least one scan circuit; the scan circuit group includes at least one first scan circuit and a plurality of second scan circuits, at least one first scan circuit and a plurality of second scan circuits are cascaded in sequence, the second scan circuit is used to provide a scan signal to the corresponding pixel circuit through the scan line, the first scan circuit is used to provide a scan signal to the pixel circuit through the scan line before the second scan circuit generates a scan signal, and at least one first scan circuit and a plurality of second scan circuits generate scan signals with a sequentially shifted timing step by step; wherein, the first level signal input terminals of two adjacent scan circuits are connected to different conduction level signal lines. The technical solution of the embodiment of the present invention helps to reduce the influence of signal coupling in the scan circuit on the scan signal, thereby improving the display effect.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the continuous development of display technology, people have higher and higher requirements for the performance of display panels. The display panel includes a scanning circuit and a pixel circuit. The scanning circuit is used to provide a scanning signal to the corresponding at least one row of pixel circuits, so that each row of pixel circuits drives the light-emitting device to emit light under the control of the scanning signal, so that the display panel displays. At present, there is a problem of signal coupling between the signal lines connected to the scanning circuit, which makes the scanning signal output by the scanning circuit easily affected by the signal coupling, resulting in a poor display effect. Summary of the invention

[0003] Embodiments of the present invention provide a display panel and a display device to reduce the influence of signal coupling in a scanning circuit on a scanning signal, thereby improving the display effect.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising: a plurality of scan lines, a plurality of rows of pixel circuits, and at least one scan circuit group, wherein a first level signal input terminal of a scan circuit in the scan circuit group is connected to a level signal line, and is used to output a signal on the level signal line in response to a clock signal to generate a scan signal;

[0005] The scanning circuit group includes at least one first scanning circuit and a plurality of second scanning circuits, the at least one first scanning circuit and the plurality of second scanning circuits are cascaded in sequence, the second scanning circuit is used to provide the scanning signal to the corresponding pixel circuit through the scanning line, the first scanning circuit is used to provide the scanning signal to the pixel circuit through the scanning line before the second scanning circuit generates the scanning signal, and the at least one first scanning circuit and the plurality of second scanning circuits generate the scanning signal with the timing sequentially shifted backward step by step;

[0006] Among the at least one first scanning circuit and the plurality of second scanning circuits, the first level signal input terminals of two adjacent scanning circuits are respectively connected to different level signal lines.

[0007] Optionally, the level signal line includes a first level signal line and a second level signal line;

[0008] In the at least one first scanning circuit and the plurality of second scanning circuits, the first level signal input terminals of the odd-numbered scanning circuits are connected to the first level signal line, and the first level signal input terminals of the even-numbered scanning circuits are connected to the second level signal line;

[0009] Preferably, the first level signal line and the second level signal line are separately provided.

[0010] Optionally, voltage values ​​of signals transmitted by the first level signal line and the second level signal line are the same or different;

[0011] Optionally, the voltage values ​​of the signals transmitted by the first level signal line and the second level signal line are related to the coupling degree of the clock signal to the signals transmitted by the first level signal line and the second level signal line;

[0012] Preferably, in the case where the level signal line is used to transmit a first level signal, among the signals transmitted by the first level signal line and the second level signal line, the one with which the clock signal has a greater coupling degree has a greater voltage value corresponding to it, and the one with which the clock signal has a smaller coupling degree has a smaller voltage value corresponding to it;

[0013] In the case where the level signal line is used to transmit the second level signal, among the signals transmitted by the first level signal line and the second level signal line, the one to which the clock signal has a greater coupling degree has a smaller voltage value corresponding to it, and the one to which the clock signal has a smaller coupling degree has a larger voltage value corresponding to it;

[0014] The voltage of the first level signal is greater than the voltage of the second level signal.

[0015] Optionally, the first scanning circuit and the second scanning circuit both include an output module, the level signal input end of the output module is the first level signal input end, and the output module is used to respond to the signal of its own control end to output the signal on the level signal line to generate the scanning signal.

[0016] Optionally, the second level signal input terminals of the first scanning circuit and the second scanning circuit are both connected to a third level signal line, and the first level signal input terminal and the second level signal input terminal are both used to transmit a first level signal or a second level signal;

[0017] Preferably, the first scanning circuit and the second scanning circuit further include an output control module, the level signal input terminal of the output control module is the second level signal input terminal, and the output control module is used to control the output module through the signal on the third level signal line;

[0018] Preferably, the level signal line and the third level signal line connected to the first level signal input terminal are arranged separately from each other.

[0019] Optionally, the display panel further includes a first clock signal line and a second clock signal line, wherein the first clock signal line and the second clock signal line are used to provide clock signals to the plurality of scanning circuits;

[0020] The first clock signal line, the second clock signal line, the first level signal line and the second level signal line are sequentially arranged on one side of the scanning circuit, and the distance between the first clock signal line and the first level signal line is equal to the distance between the second clock signal line and the second level signal line;

[0021] Preferably, the second level signal input terminals of the first scanning circuit and the second scanning circuit are both connected to a third level signal line, and the first level signal input terminal and the second level signal input terminal are both used to transmit a first level signal or a second level signal;

[0022] The third level signal line is located between the second clock signal line and the first level signal line;

[0023] Preferably, the distance between two adjacent signal lines among the first clock signal line, the second clock signal line, the third level signal line, the first level signal line and the second level signal line is equal.

[0024] Optionally, the display panel includes a display area and a frame area surrounding the display area, and the plurality of level signal lines are located in the frame area and extend from the second scanning circuit of the last stage in the scanning circuit group to the first scanning circuit of the first stage;

[0025] Wherein, in the region between the first-stage second scanning circuit and the last-stage first scanning circuit in the frame region, a plurality of the level signal lines are separately arranged;

[0026] Preferably, the frame area includes a first frame area extending along a first direction and a second frame area extending along a second direction, the first scanning circuit is located in the first frame area, the second scanning circuit is located in the second frame area, and the plurality of level signal lines in the area between the last level of the first scanning circuit in the first frame area and the first level of the second scanning circuit in the second frame area are separately arranged;

[0027] Preferably, the area between the last level of the first scanning circuit in the first border area and the first level of the second scanning circuit in the second border area is an arc angle area;

[0028] Preferably, the first border area includes a first sub-border area and a second sub-border area, the second border area includes a third sub-border area and a fourth sub-border area, the first sub-border area is adjacent to the third sub-border area, and the second sub-border area is adjacent to the fourth sub-border area; the at least one scanning circuit group includes a first scanning circuit group and a second scanning circuit group, the first scanning circuit in the first scanning circuit group is located in the first sub-border area, the second scanning circuit in the first scanning circuit group is located in the third sub-border area, the first scanning circuit in the second scanning circuit group is located in the second sub-border area, and the second scanning circuit in the second scanning circuit group is located in the fourth sub-frame area; a plurality of the level signal lines extend from the last level second scanning circuit in the first scanning circuit group to the first level first scanning circuit in the first scanning circuit group, and extend to the last level second scanning circuit in the second scanning circuit group via the first level first scanning circuit in the second scanning circuit group, and a plurality of the level signal lines in the area between the first level first scanning circuit in the first scanning circuit group and the first level first scanning circuit in the second scanning circuit group are separately arranged.

[0029] Optionally, the display panel includes a frame area, and a bonding connection portion is provided in the frame area;

[0030] Wherein, at least two of the level signal lines are connected to the same bonding connection part, and one bonding connection part is used to transmit signals to at least two of the level signal lines;

[0031] Alternatively, a plurality of the level signal lines are connected to a plurality of the bonding connection parts in a one-to-one correspondence, and one of the bonding connection parts is used to transmit a signal to a corresponding one of the level signal lines.

[0032] Optionally, the number of the first scanning circuits in the scanning circuit group is m, the number of rows of the pixel circuits and the number of the second scanning circuits in the scanning circuit group are both n; wherein m is a positive integer greater than or equal to 1, and n is a positive integer greater than m;

[0033] The pixel circuit comprises a first scanning signal input terminal and a second scanning signal input terminal, and the scanning signal output terminal of the first scanning circuit of the i-th level is connected to the first scanning signal input terminal of the pixel circuit of the i-th row through the scanning line; wherein 1≤i≤m;

[0034] The scanning signal output end of the second scanning circuit of the jth level is connected to the second scanning signal input end of the pixel circuit of the jth row through the scanning line, and the scanning signal output end of the second scanning circuit of the kth level is also connected to the first scanning signal input end of the pixel circuit of the k+mth row through the scanning line; wherein, 1≤j≤n, 1≤k≤nm.

[0035] In a second aspect, an embodiment of the present invention provides a display device, comprising the display panel described in the first aspect.

[0036] The display panel and display device provided by the embodiments of the present invention, by setting the first level signal input terminals of two adjacent scanning circuits to be connected to different level signal lines, help to reduce the capacitive load on each level signal line, so as to weaken the signal coupling effect of the clock signal on the level signal line, thereby weakening the influence of the signal coupling effect on the conduction level signal in the scanning signal output by the scanning circuit, so as to reduce the influence of the scanning signal on the conduction state of the transistor in the pixel circuit, thereby reducing the brightness difference of the light-emitting devices driven by the pixel circuits in each row, and alleviating display abnormality problems such as horizontal fine stripes. In addition, since the scanning signals with sequentially shifted timing are generated step by step from the first-stage first scanning circuit to the last-stage second scanning circuit, the first-level signal input terminals of two adjacent first scanning circuits are connected to different level signal lines, the first-level signal input terminals of adjacent first scanning circuits and second scanning circuits are connected to different level signal lines, and the first-level signal input terminals of two adjacent second scanning circuits are connected to different level signal lines. This allows the present solution to reduce the influence of signal coupling on the scanning signal output by each stage of the scanning circuit while helping to avoid the influence of signal coupling on the scanning signal from being transmitted to the scanning circuit of the subsequent stage, thereby affecting the overall display effect of the display panel. Therefore, the technical solution of the embodiment of the present invention also helps to improve the overall display effect of the display panel.

[0037] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0039] Figure 1 is a structural schematic diagram of a display panel provided by an embodiment of the present invention;

[0040] Figure 2 It is a structural schematic diagram of a pixel circuit used in a display panel;

[0041] Figure 3 It is a schematic diagram of the module structure of a scanning circuit used in a display panel;

[0042] Figure 4 It is a structural schematic diagram of a scanning circuit used in a display panel;

[0043] Figure 5 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0044] Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0045] Figure 7 It is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0047] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0048] As described in the background art, there is a problem of signal coupling between the signal lines connected to the scanning circuit, which makes the scanning signal output by the scanning circuit easily affected by the signal coupling, resulting in poor display effect. The inventors have found that the reasons for the above problem are as follows:

[0049] The existing display panel generally includes a plurality of cascaded scanning circuits, and the scanning circuit is usually connected to a first clock signal line, a second clock signal line, a high-level signal line and a low-level signal line. The first clock signal line is used to transmit a first clock signal, the second clock signal line is used to transmit a second clock signal, the high-level signal line is used to transmit a high-level signal, and the low-level signal line is used to transmit a low-level signal. The scanning circuit can alternately output a high-level signal and a low-level signal under the control of an input start signal, a first clock signal, a second clock signal, a high-level signal and a low-level signal, so as to shift the timing of the pulse signal in the start signal and then output it, thereby obtaining a scanning signal. There is a parasitic capacitance between the signal lines connected to the scanning circuit, so that the signal jump on one signal line will couple the signals on other signal lines, thereby changing the signals on other signal lines, and finally affecting the scanning signal output by the scanning circuit.

[0050] The following uses the example that a signal jump will couple the signal on the high-level signal line and change the signal on the high-level signal line. There are parasitic capacitances between the first clock signal line and the high-level signal line, and between the second clock signal line and the high-level signal line. When the first clock signal on the first clock signal line or the second clock signal on the second clock signal line jumps, the high-level signal on the high-level signal line will be coupled, for example, the potential of the high-level signal will be pulled down, so that the potential of the high-level signal in the scanning signal is lower, thereby affecting the conduction degree of the transistors in the corresponding at least one row of pixel circuits, and then affecting the brightness of the light-emitting devices driven by the corresponding at least one row of pixel circuits, so that the brightness of the light-emitting devices driven by the pixel circuits in these rows is different from the brightness of the light-emitting devices driven by the pixel circuits in other rows, resulting in display abnormalities such as fine horizontal stripes along the horizontal direction. Moreover, the high-level signal input ends of the scanning circuits at each level in the existing display panel are usually connected to the same high-level signal line, so that the capacitive load on the high-level signal line is relatively large. This will cause a stronger coupling effect between the first clock signal and the second clock signal on the high-level signal line, thereby aggravating the display abnormalities such as the above-mentioned fine horizontal lines, resulting in a deterioration in the display effect.

[0051] In view of the above problems, an embodiment of the present invention provides a display panel. Figure 1 is a schematic diagram of the structure of a display panel provided by an embodiment of the present invention. Figure 1 The display panel provided by the embodiment of the present invention comprises: a plurality of scanning lines 10, a plurality of rows of pixel circuits 20 and at least one scanning circuit group. Each scanning circuit group comprises a plurality of scanning circuits 30, and a first level signal input terminal of the scanning circuit 30 is connected to a level signal line 40, and is used to output a signal on the level signal line 40 in response to a clock signal to generate a scanning signal.

[0052] The multiple scanning circuits 30 in the scanning circuit group include at least one first scanning circuit 31 and multiple second scanning circuits 32. The at least one first scanning circuit 31 and the multiple second scanning circuits 32 are cascaded in sequence. The multiple second scanning circuits 32 can be set in a one-to-one correspondence with multiple rows of pixel circuits 20. The second scanning circuit 32 is used to provide a scanning signal to the corresponding pixel circuit 20 through the scanning line 10. The first scanning circuit 31 is used to provide a scanning signal to the pixel circuit 20 through the scanning line 10 before the second scanning circuit 32 generates a scanning signal, and the at least one first scanning circuit 31 and the multiple second scanning circuits 32 generate scanning signals with the timing shifted backward step by step.

[0053] Among them, in at least one first scanning circuit 31 and multiple second scanning circuits 32, the first level signal input terminals of two adjacent scanning circuits 30 are connected to different level signal lines 40. Specifically, the multiple level signal lines 40 connected to the first level signal input terminals of two adjacent scanning circuits 30 can be separately set.

[0054] Specifically, the display panel in the embodiment of the present invention can be an organic light-emitting diode (OLED) display panel, an active matrix organic light-emitting diode (AMOLED) display panel, or a micron-sized light-emitting diode (Micro-OLED or Mini-OLED) display panel, etc.

[0055] The display panel includes a display area AA and a non-display area surrounding the display area AA, and the non-display area includes a frame area of ​​the display panel. Multiple rows of pixel circuits 20 are arranged in the display area AA, and the scan line 10 extends along the row direction of the pixel circuit 20. The scan circuit 30 is located in the frame area of ​​the display panel. The pixel circuit 20 includes a switching transistor, a driving transistor and a storage capacitor, and each scan line 10 is connected to the gate of the switching transistor in a row of pixel circuits 20. The scan circuit 30 is connected to the start signal and the clock signal, and the level signal line 40 is connected to the fixed level signal. For example, the level signal line 40 is connected to a high level signal, or the level signal line 40 is connected to a low level signal. The scan circuit 30 can output the level signal on the level signal line 40 under the control of the clock signal to shift the timing of the conduction level signal in the start signal, thereby obtaining a scan signal. The scan signal output end of the scan circuit 30 is connected to the corresponding scan line 10 to transmit the scan signal to the gate of the switch transistor in the pixel circuit 20 through the scan line 10, and the conduction state of the switch transistor in the pixel circuit 20 is controlled by the scan signal.

[0056] The scanning circuit 30 includes a first scanning circuit 31 and a second scanning circuit 32. The number of the second scanning circuits 32 can be equal to the number of rows of the pixel circuits 20. The first-stage second scanning circuits 32 to the last-stage second scanning circuits 32 can be arranged in one-to-one correspondence with the first-row pixel circuits 20 to the last-row pixel circuits 20. Each second scanning circuit 32 is connected to at least one scanning line 10 to provide a scanning signal to a row of pixel circuits 20 connected thereto through the scanning line 10. Due to the working timing requirements of the pixel circuit, the timing of the scanning signal connected to some pixel circuits needs to be earlier than the timing of the scanning signal output by the first-stage second scanning circuit 32. Therefore, the first scanning circuit 31 can be arranged before the second scanning circuit 32. The first scanning circuit 31 can be a pre-scanning circuit. Each first scanning circuit 31 is connected to the corresponding scanning line 10 to provide a scanning signal to a row of pixel circuits 20 connected thereto through the scanning line 10, and the timing of the scanning signal generated by each first scanning circuit 31 is located before the timing of the scanning signal generated by the second scanning circuit 32.

[0057] The cascade connection between the scanning circuits 30 may mean that the scanning signal output terminal of the previous scanning circuit 30 is connected to the start signal input terminal of the next scanning circuit 30. When the number of the first scanning circuit 31 is one, the first scanning circuit 31 is cascaded with the first second scanning circuit 32, and the first second scanning circuit 32 to the last second scanning circuit 32 are cascaded in sequence. When the number of the first scanning circuits 31 is two or more, the first first scanning circuit 31 to the last first scanning circuit 31 are cascaded in sequence, the first second scanning circuit 32 to the last second scanning circuit 32 are cascaded in sequence, and the last first scanning circuit 31 is cascaded with the first second scanning circuit 32. Exemplarily, at least one first scanning circuit 31 and a plurality of second scanning circuits 32 in the scanning circuit group are arranged in sequence, and the start signal input terminal of the first-level first scanning circuit 31 is connected to the start signal, and from the first-level first scanning circuit 31 to the last-level second scanning circuit 32, the scanning signal output terminal of the previous-level scanning circuit 30 is connected to the start signal input terminal of the next-level scanning circuit 30, so that the scanning signal output by the previous-level scanning circuit 30 is used as the start signal of the next-level scanning circuit 30, so that the first-level first scanning circuit 31 to the last-level second scanning circuit 32 generate scanning signals with sequentially shifted timing step by step, and provide the scanning signals to the corresponding pixel circuits 20 through the scanning lines 10, thereby realizing the operation of driving the pixel circuits 20 row by row.

[0058] The number of level signal lines 40 in the display panel can be at least two. From the first-stage first scanning circuit 31 to the last-stage second scanning circuit 32, the level signal lines 40 connected to the first level signal input terminals of any two adjacent scanning circuits 30 are different. For example, the level signal lines 40 connected to the first level signal input terminals of two adjacent first scanning circuits 31 are different, the level signal lines 40 connected to the first level signal input terminals of the adjacent first scanning circuits 31 and the second scanning circuits 32 are different, and the level signal lines 40 connected to the first level signal input terminals of the adjacent second scanning circuits 32 are also different. In this way, it is not necessary to connect the first level signal input terminals of all scanning circuits 30 to the same level signal line 40. Since the scanning circuit 30 needs to be connected to the clock signal line to access the clock signal, and there is a parasitic capacitance between the clock signal line and the level signal line 40, the high and low level jumps of the clock signal will couple the conduction level signal on the level signal line 40, thereby affecting the scanning signal output by the scanning circuit 30. If the first level signal input terminals of all scanning circuits 30 are connected to the same level signal line 40 , the capacitive load on the level signal line 40 will be larger, thereby aggravating the coupling effect of the clock signal on the conduction level signal on the level signal line 40 .

[0059] The technical solution of this embodiment helps to reduce the capacitive load on each level signal line 40 by setting the first level signal input terminals of two adjacent scanning circuits 30 to be connected to different level signal lines 40, so as to weaken the signal coupling effect of the clock signal on the level signal line 40, thereby weakening the influence of the signal coupling effect on the conduction level signal in the scanning signal output by the scanning circuit 30, so as to reduce the influence of the scanning signal on the conduction state of the transistor in the pixel circuit 20, thereby reducing the brightness difference of the light-emitting devices driven by the pixel circuits 20 in each row, and alleviating display abnormalities such as fine horizontal stripes. In addition, since the scanning signals with sequentially shifted timing are generated step by step from the first-stage first scanning circuit 31 to the last-stage second scanning circuit 32, the first-level signal input terminals of two adjacent first scanning circuits 31 are connected to different level signal lines 40, the first-level signal input terminals of adjacent first scanning circuits 31 and second scanning circuits 32 are connected to different level signal lines 40, and the first-level signal input terminals of two adjacent second scanning circuits 32 are connected to different level signal lines 40. This allows the present scheme to reduce the influence of the signal coupling effect on the scanning signal output by each stage of the scanning circuit 30 while helping to avoid the influence of the signal coupling effect on the scanning signal from being transmitted to the scanning circuit 30 of the subsequent stage, thereby affecting the overall display effect of the display panel. Therefore, the present scheme also helps to improve the overall display effect of the display panel.

[0060] Continue to see Figure 1, based on the above embodiment, optionally, the number of the first scanning circuits 31 is m, the number of the second scanning circuits 32 and the number of rows of the pixel circuits 20 are both n; wherein m is a positive integer greater than or equal to 1, and n is a positive integer greater than m. The pixel circuit 20 includes a first scanning signal input terminal and a second scanning signal input terminal, and the scanning signal output terminal of the i-th level first scanning circuit 31 is connected to the first scanning signal input terminal of the i-th row pixel circuit 20 through the scanning line 10; wherein 1≤i≤m. The scanning signal output terminal of the j-th level second scanning circuit 32 is connected to the second scanning signal input terminal of the j-th row pixel circuit 20 through the scanning line 10, and the scanning signal output terminal of the k-th level second scanning circuit 32 is also connected to the first scanning signal input terminal of the k+m-th row pixel circuit 20 through the scanning line 10; wherein 1≤j≤n, 1≤k≤nm.

[0061] Exemplarily, the scan line 10 includes a first scan line 11 and a second scan line 12. The scan signal output terminal of the i-th level first scan circuit 31 is connected to the first scan signal input terminal of the i-th row of pixel circuits 20 through the second scan line 12, so as to provide scan signals to the first scan signal input terminals of the first m rows of pixel circuits 20 through the m first scan circuits 31. Figure 1 The case where m=5 is schematically shown in FIG. 1 . In other embodiments, the specific value of m can also be set according to the working timing requirements of the pixel circuit 20. The scanning signal output terminal of the second scanning circuit 32 of the jth level is connected to the second scanning signal input terminal of the pixel circuit 20 of the jth row through the first scanning line 11, so as to provide the scanning signal to the second scanning signal input terminal of each row of pixel circuits 20 through the second scanning circuit 32, and the scanning signal output terminal of the second scanning circuit 32 of the kth level is also connected to the first scanning signal input terminal of the pixel circuit 20 of the k+mth row through the second scanning line 12, so as to provide the scanning signal to the first scanning signal input terminal of the pixel circuits 20 of the m+1th to nth rows through the second scanning circuit 32.

[0062] The embodiment of the present invention is further described below in conjunction with a specific pixel circuit structure. Figure 2 It is a schematic diagram of the structure of a pixel circuit used in a display panel. Figure 1 and Figure 2, exemplarily, the pixel circuit 20 may include a driving transistor DT, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a storage capacitor Cst and a light-emitting device D0. The working phases of the pixel circuit 20 include an initialization phase, a data writing phase and a light-emitting phase. The first transistor T1 and the third transistor T3 are turned on in the initialization phase in response to the scanning signal S1, so that the initialization signal Vref can be written into the gate of the driving transistor DT through the first transistor T1, the gate voltage of the driving transistor DT is initialized, and the driving transistor DT is controlled to be turned on. The initialization signal Vref can also be written into the first electrode of the light-emitting device D0 through the third transistor T3 to initialize the voltage of the first electrode of the light-emitting device D0. The second transistor T2 is turned on in response to the scan signal S2, and the fourth transistor T4 is turned on in the data writing stage in response to the scan signal S3, so that when the second transistor T2 and the fourth transistor T4 are both turned on, the data voltage Data is sequentially written into the gate of the driving transistor DT through the fourth transistor T4, the driving transistor DT and the second transistor T2, and the gate voltage of the driving transistor DT is stored through the storage capacitor Cst, and the threshold voltage of the driving transistor DT is compensated through the second transistor T2. The fifth transistor T5 and the sixth transistor T6 are turned on in the light emitting stage in response to the light emitting control signal EM. In the light emitting stage, the first power supply voltage VDD is written into the first electrode of the driving transistor DT through the fifth transistor T5, and the second power supply voltage VSS is written into the second electrode of the light emitting device D0. The driving transistor DT generates a driving current according to its own gate voltage, and drives the light emitting device D0 to emit light with a corresponding brightness, so that the display panel can display.

[0063] The first transistor T1 to the sixth transistor T6 in the pixel circuit 20 are switch transistors, and the scan signal output by the scan circuit 30 is used to control at least some of the transistors in the first transistor T1 to the sixth transistor T6 to work. The first scan signal input terminal and the second scan signal input terminal in the pixel circuit 20 can be the gate of any transistor in the first transistor T1 to the sixth transistor T6. For example, the first scan signal input terminal in the pixel circuit 20 is the gate of the first transistor T1, and the second scan signal input terminal is the gate of the second transistor T2. Since the working timing of the first transistor T1 is relatively early, the scan signal S1 can be provided to the first transistor T1 in the first m rows of pixel circuits 20 through the first scan circuit 31, and the scan signal S1 can be provided to the first transistor T1 in the pixel circuits 20 in the m+1 to n rows through the second scan circuit 32, and the scan signal S2 can be provided to the second transistor T2 in each row of pixel circuits 20 through the second scan circuit 32. The specific value of m can be set according to the timing difference between the scan signal S1 and the scan signal S2.

[0064] See also Figure 1 Optionally, the level signal line 40 includes a first level signal line 41 and a second level signal line 42. In the at least one first scanning circuit 31 and the plurality of second scanning circuits 32, from the first-stage first scanning circuit 31 to the last-stage second scanning circuit 32, the first level signal input terminal of the scanning circuit 30 of the odd-numbered stages is connected to the first level signal line 41, and the first level signal input terminal of the scanning circuit 30 of the even-numbered stages is connected to the second level signal line 42.

[0065] Specifically, the first level signal line 41 and the second level signal line 42 are both used to transmit a first level signal or a second level signal. The voltage of the first level signal is greater than the voltage of the second level signal, for example, the first level signal is a preset high level signal, and the second level signal is a preset low level signal. Exemplarily, when the transistor controlled by the scan signal is an N-type transistor, the first level signal line 41 and the second level signal line 42 are both used to transmit a preset high level signal, and the preset high level signal can be a high level signal for controlling the conduction of the N-type transistor; when the transistor controlled by the scan signal is a P-type transistor, the first level signal line 41 and the second level signal line 42 are both used to transmit a preset low level signal, and the preset low level signal can be a low level signal for controlling the conduction of the P-type transistor. Optionally, the first level signal line 41 and the second level signal line 42 are separately arranged, that is, the first level signal line 41 and the second level signal line 42 are two independent signal lines.

[0066] Compared with the solution in which the first level signal input terminals of all scanning circuits 30 are connected to the same level signal line 40, the technical solution of this embodiment, by setting the first level signal input terminals of the odd-numbered scanning circuits 30 to be connected to the first level signal line 41, and the first level signal input terminals of the even-numbered scanning circuits 30 to be connected to the second level signal line 42, helps to reduce the capacitive load on the first level signal line 41 and the second level signal line 42, so as to respectively weaken the signal coupling effect of the clock signal on the first level signal line 41 and the second level signal line 42, and the first level signal line 41 and the second level signal line 42 are separately set, which also helps to weaken the signal coupling effect between the two, and further weaken the influence of the above-mentioned signal coupling effect on the conduction level signal in the scanning signal output by the scanning circuit 30, so as to reduce the influence of the scanning signal on the conduction state of the transistor in the pixel circuit 20, thereby reducing the brightness difference of the light-emitting devices driven by the pixel circuits 20 in each row, so as to alleviate the display abnormality problems such as horizontal fine stripes.

[0067] Figure 3 This is a schematic diagram of the module structure of a scanning circuit used in a display panel. Figure 1 and Figure 3Further, the first scanning circuit 31 and the second scanning circuit 32 each include an output module 370, and the level signal input terminal I1 of the output module 370 can be used as the first level signal input terminal, for example, a certain level signal input terminal I1 of the output module 370 is used as the first level signal input terminal. The output module 370 is used to respond to the signal of its own control terminal to output the signal on the level signal line 40() to generate a scanning signal, and the level signal line 40 can specifically be a first level signal line 41 or a second level signal line 42. In at least one first scanning circuit 31 and multiple second scanning circuits 32, the level signal input terminal I1 of the output module 370 in the scanning circuit 30 of odd levels is connected to the first level signal line 41, and the level signal input terminal I1 of the output module 370 in the scanning circuit 30 of even levels is connected to the second level signal line 42.

[0068] Exemplarily, the first scanning circuit 31 and the second scanning circuit 32 may further include a first input module 310, a second input module 320, a node control module 330, a first output control module 340, a second output control module 350, and a third output module 360. The clock signal controlling the operation of the scanning circuit 30 includes a first clock signal SCK1 and a second clock signal SCK2. The conduction level signal connected to the level signal line 40 may be a first level signal VGH or a second level signal VGL. The first level signal VGH may be a high level signal, and the second level signal VGL may be a low level signal. The following description is made by taking the example that the level signal connected to the level signal line 40 is the first level signal VGH, and the first level signal VGH is a high level signal.

[0069] The first input module 310 is used to write the second level signal VGL to the first node N1 in response to the first clock signal SCK1, and the second input module 320 is used to write the start signal SIN to the second node N2, the third node N3, the fourth node N4 and the second control terminal G2 of the output module 370 in response to the first clock signal SCK1. The conduction level signal in the start signal SIN is the first level signal VGH. The node control module 330 is used to write the first clock signal SCK1 to the first node N1 in response to the signal of the second node N2 to control the signal of the first node N1. The first output control module 340 is used to control the signals of the third node N3, the fourth node N4 and the second control terminal G2 of the output module 370 through the first level signal VGH or the second clock signal SCK2 in response to the signals of the first node N1 and the third node N3. The second output control module 350 is used to control the signal of the first control terminal G1 of the output module 370 in response to the signal of the first node N1 and the second clock signal SCK2. The third output control module 360 ​​is used to respond to the signal of the fourth node N4 and write the first level signal VGH to the first control terminal G1 of the output module 370 to control the signal of the first control terminal G1 of the output module 370. By controlling the signals of the first control terminal G1 and the second control terminal G2 of the output module 370, the output module 370 can respond to the signals of the first control terminal G1 and the second control terminal G2 of the output module 370, and output the first level signal VGH and the second level signal VGL alternately to the scan signal output terminal O, thereby shifting the timing of the first level signal VGH in the start signal SIN and outputting it to obtain a scan signal.

[0070] Since there is a parasitic capacitance between the signal line of the first clock signal SCK1 and the level signal line 40, and there is a parasitic capacitance between the signal line of the second clock signal SCK2 and the level signal line 40, the high-low level jump of the first clock signal SCK1 and the second clock signal SCK2 will couple the first level signal VGH on the level signal line 40, thereby affecting the scanning signal output by the scanning circuit 30. Compared with the solution that the level signal input terminal I1 of the output module 370 in all scanning circuits 30 is connected to the same level signal line 40, the technical solution of this embodiment is to set the level signal input terminal I1 of the output module 370 in the odd-level scanning circuit 30 from the first-level first scanning circuit 31 to the last-level second scanning circuit 32 to be connected to the first level signal line 41 to access the first level signal VGH, and the level signal input terminal I1 of the output module 370 in the even-level scanning circuit 30 is connected to the second level signal line 42 to access the first level signal VGH. It helps to reduce the capacitive load on the first level signal line 41 and the second level signal line 42, so as to weaken the signal coupling effect of the first clock signal SCK1 and the second clock signal SCK2 on the first level signal line 41 and the second level signal line 42 respectively, thereby weakening the influence of the above-mentioned signal coupling effect on the conduction level signal in the scanning signal output by the scanning circuit 30, so as to reduce the influence of the scanning signal on the conduction state of the transistor in the pixel circuit 20, thereby reducing the brightness difference of the light-emitting devices driven by the pixel circuits 20 in each row, so as to alleviate display abnormalities such as horizontal fine stripes.

[0071] Combination Figure 1 and Figure 3 , further, the second level signal input terminals of the first scanning circuit 31 and the second scanning circuit 32 are both connected to the third level signal line 43, and the first level signal input terminals and the second level signal input terminals of the first scanning circuit 31 and the second scanning circuit 32 are both high level signal input terminals or low level signal input terminals. Optionally, the first scanning circuit 31 and the second scanning circuit 32 further include an output control module, and the level signal input terminal I2 of the output control module in the first scanning circuit 31 and the second scanning circuit 32 is used as the second level signal input terminal, and the output control module is used to control the output module 370 through the signal on the third level signal line 43.

[0072] Exemplarily, the third level signal line 43 is also used to transmit a level signal, and the level signal may be a first level signal VGH or a second level signal VGL. The following is still described by taking the level signal transmitted by the third level signal line 43 as the first level signal VGH, and the first level signal VGH is a high level signal as an example. The output control modules in the first scanning circuit 31 and the second scanning circuit 32 may include Figure 3The first level signal VGH is connected to each module except the output module 370, such as the first output control module 340 and the third output control module 360. The level signal input terminal I2 of the first output control module 340 and the third output control module 360 ​​in each of the first scanning circuit 31 and the second scanning circuit 32 can be connected to the third level signal line 43 to access the first level signal VGH through the third level signal line 43. Optionally, the level signal line 40 connected to the first level signal input terminal and the level signal line 40 connected to the second level signal input terminal are arranged separately from each other, for example, the first level signal line 41, the second level signal line 42 and the third level signal line 43 are arranged separately from each other.

[0073] The technical solution of this embodiment is to set the level signal input terminal I1 of the output module 370 in the odd-numbered scanning circuit 30 to be connected to the first level signal line 41, and the level signal input terminal I1 of the output module 370 in the even-numbered scanning circuit 30 is connected to the second level signal line 42, and the level signal input terminal I2 of the output control module in each scanning circuit 30 is connected to the third level signal line 43, so that the output control module in each scanning circuit 30 does not need to be connected to the first level signal line 41 and the second level signal line 42 to access the first level signal VGH, which helps to further reduce the first level signal line 41 and the second level signal line 42. 42, and the first level signal line 41, the second level signal line 42 and the third level signal line 43 can be set separately from each other. Compared with the solution in which the output modules 370 and the output control modules in all the scanning circuits 30 are connected to the same level signal line, the present solution can make the capacitive loads on the first level signal line 41, the second level signal line 42 and the third level signal line 43 smaller, which helps to weaken the signal coupling effect of the first clock signal SCK1 and the second clock signal SCK2 on the first level signal line 41, the second level signal line 42 and the third level signal line 43, thereby weakening the influence of the above-mentioned signal coupling effect on the conduction level signal in the scanning signal output by the scanning circuit 30.

[0074] There may be multiple types of scanning circuits applicable to the display panel provided in the embodiment of the present invention. The following takes the specific structure of one scanning circuit as an example to further illustrate the embodiment of the present invention. Figure 4 FIG. 1 is a schematic diagram of a scanning circuit used in a display panel. Figure 4Optionally, the first input module 310 includes a seventh transistor T7, the second input module 320 includes an eighth transistor T8, the node control module 330 includes a ninth transistor T9, the first output control module 340 includes a tenth transistor T10, an eleventh transistor T11 and a first capacitor C1, the second output control module 350 includes a twelfth transistor T12, a thirteenth transistor T13 and a second capacitor C2, the third output module 360 ​​includes a fourteenth transistor T14, and the output module 370 includes a fifteenth transistor T15, a sixteenth transistor T16 and a third capacitor C3. The scanning circuit may further include a seventeenth transistor T17, an eighteenth transistor T18 and a nineteenth transistor T19.

[0075] Among them, the gate of the seventh transistor T7 is connected to the first clock signal SCK1, and the first electrode of the seventh transistor T7 is connected to the second level signal VGL. The gate of the eighth transistor T8 is connected to the first clock signal SCK1, and the first electrode of the eighth transistor T8 is connected to the start signal SIN. The first electrode of the ninth transistor T9 is connected to the first clock signal SCK1, and the ninth transistor T9 can be a double-gate transistor. For example, the ninth transistor T9 is a double-gate transistor composed of a first double-gate transistor T9a and a second double-gate transistor T9b, and the first electrode of the second double-gate transistor T9b is connected to the first clock signal SCK1. The first electrode of the tenth transistor T10 is connected to the first level signal VGH, and the first electrode of the eleventh transistor T11 is connected to the second clock signal SCK2. The first electrode of the twelfth transistor T12 and the gate of the thirteenth transistor T13 are connected to the second clock signal SCK2. The first electrode of the fourteenth transistor T14 is connected to the first level signal VGH. The first electrode of the fifteenth transistor T15 is connected to the first level signal VGH, and the first electrode of the sixteenth transistor T16 is connected to the second level signal VGL. The seventeenth transistor T17 is connected between the first node N1 and the gate of the twelfth transistor T12, and the gate of the seventeenth transistor T17 is connected to the second level signal VGL. The eighteenth transistor T18 is connected between the third node N3 and the fourth node N4, and the gate of the eighteenth transistor T18 is connected to the second level signal VGL. The gate of the nineteenth transistor T19 is connected to the reset signal RST, the first electrode of the nineteenth transistor T19 is connected to the first level signal VGH, and the second electrode of the nineteenth transistor T19 is connected between the second node N2 and the fourth node N4.

[0076] Combination Figure 1 and Figure 4, the first electrode of the fifteenth transistor T15 in the scanning circuit 30 can be used as the level signal input terminal I1 of the output module 370, the first output control module 340, the third output control module 360 ​​and the nineteenth transistor T19 can all be used as output control modules in the scanning circuit 30, and the first electrode of the tenth transistor T10, the first electrode of the fourteenth transistor T14 and the first electrode of the nineteenth transistor T19 can all be used as the level signal input terminal I2 of the corresponding output control module. That is to say, when the first level signal line 41, the second level signal line 42 and the third level signal line 43 are all used to transmit the conduction level signal, the conduction level signal is the first level signal VGH, and the first level signal VGH is a high level signal, it can be set that in the first-level first scanning circuit 31 to the last-level second scanning circuit 32, the first electrode of the fifteenth transistor T15 in each odd-level scanning circuit 30 is connected to the first level signal line 41, the first electrode of the fifteenth transistor T15 in each even-level scanning circuit 30 is connected to the second level signal line 42, and the first electrode of the tenth transistor T10, the first electrode of the fourteenth transistor T14 and the first electrode of the nineteenth transistor T19 in each scanning circuit 30 are connected to the third level signal line 43.

[0077] It should be noted that the above embodiment is described only by taking the case where the conduction level signal transmitted by the first level signal line 41, the second level signal line 42 and the third level signal line 43 is the first level signal VGH, and the first level signal VGH is a high level signal. In other embodiments, the conduction level signal transmitted by the first level signal line 41, the second level signal line 42 and the third level signal line 43 can also be the second level signal VGL, and the second level signal VGL is a low level signal. In this case, the level signal input terminal I3 of the output module 370 (for example, the first pole of the sixteenth transistor T16) can be used as the first level signal input terminal, and the level signal input terminal I4 of the output control module (for example, the first pole of the seventh transistor T7, the gate of the seventeenth transistor T17 and the gate of the eighteenth transistor T18) can be used as the second level signal input terminal. In this way, in the first-level first scanning circuit 31 to the last-level second scanning circuit 32, the first electrode of the sixteenth transistor T16 in each odd-level scanning circuit 30 is connected to the first-level signal line 41, the first electrode of the sixteenth transistor T16 in each even-level scanning circuit 30 is connected to the second-level signal line 42, and the first electrode of the seventh transistor T7, the gate of the seventeenth transistor T17 and the gate of the eighteenth transistor T18 in each scanning circuit 30 are connected to the third-level signal line 43.

[0078] Figure 5 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 3 and Figure 5 On the basis of the above embodiments, the display panel further includes a first clock signal line 51 and a second clock signal line 52, and the first clock signal line 51 and the second clock signal line 52 are used to provide clock signals to multiple scanning circuits 30, for example, the first clock signal line 51 and the second clock signal line 52 are used to transmit clock signals that are inverted from each other. The scanning circuit 30 includes a first clock signal terminal M1 and a second clock signal terminal M2, and the scanning circuit 30 is used to respond to the signals of the first clock signal terminal M1 and the second clock signal terminal M2, and output the signal on the level signal line 40 to generate a scanning signal. In at least one first scanning circuit 31 and multiple second scanning circuits 32, the first clock signal terminal M1 of the scanning circuit 30 of the odd-numbered stage is connected to the first clock signal line 51, and the second clock signal terminal M2 is connected to the second clock signal line 52, and the first clock signal terminal M1 of the scanning circuit 30 of the even-numbered stage is connected to the second clock signal line 52, and the second clock signal terminal M2 is connected to the first clock signal line 51.

[0079] Among them, the first clock signal line 51, the second clock signal line 52, the first level signal line 41 and the second level signal line 42 are arranged in sequence on one side of each scanning circuit 30, and the distance between the first clock signal line 51 and the first level signal line 41 is equal to the distance between the second clock signal line 52 and the second level signal line 42.

[0080] Optionally, the first clock signal line 51, the second clock signal line 52, the first level signal line 41 and the second level signal line 42 are all located in the border area, and in the direction from the display area to the border area, the first clock signal line 51, the second clock signal line 52, the first level signal line 41 and the second level signal line 42 are arranged in sequence.

[0081] Exemplarily, the first clock signal line 51 is used to transmit the first clock signal SCK1, and the second clock signal line 52 is used to transmit the second clock signal SCK2. The first clock signal SCK1 and the second clock signal SCK2 both include clock signals composed of multiple pulse signals, and the phases of the first clock signal SCK1 and the second clock signal SCK2 are opposite. The scanning circuit 30 can output a scanning signal under the control of the first clock signal SCK1 and the second clock signal SCK2. The first clock signal terminal M1 in the scanning circuit 30 can be a control terminal of the first input module 310, the second input module 320 and the node control module 330, and the second clock signal terminal M2 can be a control terminal of the first output control module 340 and the second output control module 350. From the first-stage first scanning circuit 31 to the last-stage second scanning circuit 32, the first clock signal terminal M1 of the odd-numbered scanning circuit 30 is connected to the first clock signal line 51 to access the first clock signal SCK1, and the second clock signal terminal M2 is connected to the second clock signal line 52 to access the second clock signal SCK2 ( Figure 3 The scanning circuit shown may be an odd-numbered scanning circuit 30), wherein the first clock signal terminal M1 of the even-numbered scanning circuit 30 is connected to the second clock signal line 52 to access the second clock signal SCK2, and the second clock signal terminal M2 is connected to the first clock signal line 51 to access the first clock signal SCK1.

[0082] The inventor has found that, for odd-numbered scanning circuits 30, the jump of the first clock signal SCK1 on the first clock signal line 51 has a greater impact on the display effect caused by the coupling effect of the on-level signal on the level signal line 40, and for even-numbered scanning circuits 30, the jump of the second clock signal SCK2 on the second clock signal line 52 has a greater impact on the display effect caused by the coupling effect of the on-level signal on the level signal line 40. Figures 2 to 5 , taking the example that the first scan line 11 is connected to the gate of the first transistor T1 in the pixel circuit 20, the second scan line 12 is connected to the gate of the second transistor T2 in the pixel circuit 20, and the first transistor T1 and the second transistor T2 in the pixel circuit 20 are oxide transistors, that is, N-type transistors, and the remaining transistors are P-type transistors, then the first scan circuit 31 and the second scan circuit 32 provide the pixel circuit 20 with a scan signal S1 and a scan signal S2, the conduction level signal on the level signal line 40 is a first level signal VGH, and the first level signal VGH is a high level signal.

[0083] In the data writing stage of the pixel circuit 20, the second transistor T2 is turned on in response to the scanning signal S2, and the fourth transistor T4 is turned on in response to the scanning signal S3, so that the data voltage Data is sequentially written into the gate of the driving transistor DT through the fourth transistor T4, the driving transistor DT and the second transistor T2, so that the driving transistor DT generates a driving current according to the data voltage Data to drive the light-emitting device D0 to emit light. For the odd-numbered scanning circuits 30 from the first-stage first scanning circuit 31 to the last-stage second scanning circuit 32, in the process of the scanning circuit 30 outputting the first level signal VGH in the scanning signal S2, the first clock signal SCK1 on the first clock signal line 51 jumps from a high level signal to a low level signal, and the signal jump occurs during the conduction period of the fourth transistor T4 in the data writing stage. Due to the parasitic capacitance between the first clock signal line 51 and the level signal line 40, the jump of the first clock signal SCK1 will couple the first level signal VGH on the level signal line 40, and pull down the potential of the first level signal VGH, thereby reducing the potential of the first level signal VGH in the scanning signal S2, which will affect the conduction state of the second transistor T2, making it difficult for the data voltage Data to be fully written into the gate of the driving transistor DT, so that the brightness of the light-emitting device D0 driven by at least one row of pixel circuits 20 connected to the scanning circuit 30 will be affected, resulting in display abnormalities such as horizontal fine stripes. However, the jump of the second clock signal SCK2 on the second clock signal line 52 does not occur during the conduction period of the fourth transistor T4 in the data writing stage. Therefore, for the odd-level scanning circuit 30, the main reason for display abnormalities such as horizontal fine stripes lies in the coupling effect of the jump of the first clock signal SCK1 on the first clock signal line 51 on the conduction level signal on the level signal line 40.

[0084] Similarly, for the even-numbered scanning circuit 30, in the process of the scanning circuit 30 outputting the first level signal VGH in the scanning signal S2, since the jump of the second clock signal SCK2 on the second clock signal line 52 occurs during the conduction period of the fourth transistor T4 in the data writing stage, and the jump of the first clock signal SCK1 on the first clock signal line 51 does not occur during this period, therefore, for the even-numbered scanning circuit 30, the main reason for causing display abnormalities such as horizontal fine stripes is the coupling effect of the jump of the second clock signal SCK2 on the second clock signal line 52 on the conduction level signal on the level signal line 40.

[0085] In view of this, if the odd-numbered scanning circuits 30 and the even-numbered scanning circuits 30 are both connected to the same level signal line 40, not only will the capacitive load on the level signal line 40 be larger, thereby exacerbating the coupling effect of the first clock signal SCK1 and the second clock signal SCK2 on the on-level signal on the level signal line 40, but also the on-level signal connected to the odd-numbered scanning circuits 30 is mainly affected by the coupling effect of the first clock signal SCK1 on the first clock signal line 51, and the on-level signal connected to the even-numbered scanning circuits 30 is mainly affected by the coupling effect of the second clock signal SCK2 on the second clock signal line 52. However, the distance between the first clock signal line 51 and the level signal line 40 is different from the distance between the second clock signal line 52 and the level signal line 40. Therefore, for the odd-numbered and even-numbered scanning circuits 30, the degree of coupling of the clock signal to the on-level signal is different, which will also have different degrees of influence on the scanning signals output by the odd-numbered and even-numbered scanning circuits 30, thereby causing display differences.

[0086] The technical solution of this embodiment is that, by setting the first scanning circuit 31 of the first stage to the second scanning circuit 32 of the last stage, the first level signal input terminal of the scanning circuit 30 of the odd-numbered stage is connected to the first level signal line 41, and the first level signal input terminal of the scanning circuit 30 of the even-numbered stage is connected to the second level signal line 42, the first clock signal line 51, the second clock signal line 52, the first level signal line 41 and the second level signal line 42 are sequentially arranged on one side of each scanning circuit 30, and the distance between the first clock signal line 51 and the first level signal line 41 is equal to the distance between the second clock signal line 52 and the second level signal line 42, which not only helps to reduce the distance between the first level signal line 41 and the second level signal line 42. 2, thereby weakening the coupling effect of the first clock signal SCK1 and the second clock signal SCK2 on the signals on the first level signal line 41 and the second level signal line 42, and can also make the coupling degree of the first clock signal SCK1 on the first clock signal line 51 to the signal on the first level signal line 41 similar to the coupling degree of the second clock signal SCK2 on the second clock signal line 52 to the signal on the second level signal line 42, so that the above-mentioned coupling effect has similar effects on the scanning signals output by the scanning circuit 30 of the odd-numbered and even-numbered poles, which helps to weaken the display differences between pixels in different rows, thereby alleviating display anomalies such as horizontal fine stripes and improving the overall display effect.

[0087] See also Figure 5Optionally, the third level signal line 43 is located between the second clock signal line 52 and the first level signal line 41. In this way, the first clock signal line 51 and the second clock signal line 52 can be located on one side of the third level signal line 43, and the first level signal line 41 and the second level signal line 42 can be located on the other side of the third level signal line 43, so that the first clock signal line 51 and the second clock signal line 52 are separated from the first level signal line 41 and the second level signal line 42 by the third level signal line 43, thereby weakening the coupling effect of the first clock signal SCK1 and the second clock signal SCK2 on the signals on the first level signal line 41 and the second level signal line 42.

[0088] Furthermore, the distances between two adjacent signal lines among the first clock signal line 51, the second clock signal line 52, the third level signal line 43, the first level signal line 41 and the second level signal line 42 can be set equal. The advantage of such a setting is that not only can the first clock signal line 51 and the second clock signal line 52 be separated from the first level signal line 41 and the second level signal line 42 by the third level signal line 43, thereby weakening the coupling effect of the first clock signal SCK1 and the second clock signal SCK2 on the signals on the first level signal line 41 and the second level signal line 42, but also the coupling degree of the first clock signal SCK1 on the first clock signal line 51 to the signals on the first level signal line 41 can be similar to the coupling degree of the second clock signal SCK2 on the second clock signal line 52 to the signals on the second level signal line 42, so that the above coupling effect has similar effects on the scanning signals output by the scanning circuit 30 of the odd-numbered and even-numbered poles, which helps to weaken the display differences between pixels in different rows, thereby alleviating display abnormalities such as fine horizontal stripes, and improving the overall display effect.

[0089] See also Figure 5 In one embodiment, the voltage values ​​of the signals transmitted by the first level signal line 41 and the second level signal line 42 may be set to be the same. The first level signal line 41 and the second level signal line 42 are both used to transmit a preset high level signal, or are both used to transmit a preset low level signal, and the voltage values ​​of the signals transmitted by the first level signal line 41 and the second level signal line 42 are the same, so that the same voltage signal can be transmitted to the first level signal line 41 and the second level signal line 42, and there is no need to set different voltage signal generating circuits in the driver chip of the display device to transmit different voltage signals to the two, which helps to save the volume of the driver chip and reduce the power consumption of the display device.

[0090] See also Figure 5In another embodiment, the voltage values ​​of the signals transmitted by the first level signal line 41 and the second level signal line 42 may be set to be different. Specifically, the voltage values ​​of the signals transmitted by the first level signal line 41 and the second level signal line 42 may be set to be related to the coupling degree of the clock signal to the signals transmitted by the first level signal line 41 and the second level signal line 42. Wherein, in the case where the level signal line 40 is used to transmit the first level signal (such as a preset high level signal), among the signals transmitted by the first level signal line 41 and the second level signal line 42, the one with a greater coupling degree of the clock signal, the greater the voltage value of the corresponding signal, and the one with a smaller coupling degree of the clock signal, the smaller the voltage value of the corresponding signal. Wherein, in the case where the level signal line 40 is used to transmit the second level signal (such as a preset low level signal), among the signals transmitted by the first level signal line 41 and the second level signal line 42, the one with a greater coupling degree of the clock signal, the smaller the voltage value of the corresponding signal, and the one with a smaller coupling degree of the clock signal, the greater the voltage value of the corresponding signal.

[0091] Exemplarily, in the test phase, each row of pixel circuits 20 can be driven by each level of scanning circuits 30 to scan row by row, so as to determine the coupling degree of the clock signal to the signal transmitted by the first level signal line 41 and the second level signal line 42 according to the difference between the brightness of the light-emitting device driven by each row of pixel circuits 20 and the target brightness. The stronger the coupling degree of the clock signal to the signal transmitted by the first level signal line 41 and the second level signal line 42, the greater the impact on the scanning signal output by the scanning circuit 30, the less sufficient the data voltage written by the pixel circuit 20, and the greater the difference between the brightness of the light-emitting device and the target brightness. Similarly, the weaker the coupling degree of the clock signal to the signal transmitted by the first level signal line 41 and the second level signal line 42, the less the impact on the scanning signal output by the scanning circuit 30, the more sufficient the data voltage written by the pixel circuit 20, and the smaller the difference between the brightness of the light-emitting device and the target brightness.

[0092] In the case where the signals transmitted by the first level signal line 41 and the second level signal line 42 are both high level signals, the jump of the clock signal from high level to low level will pull down the potential of the high level signal transmitted by the first level signal line 41 and the second level signal line 42, thereby reducing the voltage value of the high level signal output by the scanning circuit 30. Therefore, the coupling degree of the clock signal to the first level signal line 41 and the coupling degree of the clock signal to the second level signal line 42 can be compared. For the signals transmitted by the first level signal line 41 and the second level signal line 42, the greater the coupling degree of the clock signal, the greater the voltage value of the corresponding signal is set, and the smaller the coupling degree of the clock signal, the smaller the voltage value of the corresponding signal is set, so as to compensate for the difference in scanning signals output by the odd-numbered scanning circuit and the even-numbered scanning circuit caused by the above coupling effect, thereby improving the display effect.

[0093] In the case where the signals transmitted by the first level signal line 41 and the second level signal line 42 are both low level signals, the jump of the clock signal from the low level to the high level will pull up the potential of the low level signal transmitted by the first level signal line 41 and the second level signal line 42, thereby increasing the voltage value of the high level signal output by the scanning circuit 30. Therefore, the coupling degree of the clock signal to the first level signal line 41 and the coupling degree of the clock signal to the second level signal line 42 can be compared. For the signals transmitted by the first level signal line 41 and the second level signal line 42, the greater the coupling degree of the clock signal to the one with which the voltage value of the corresponding signal is set to be smaller, and the smaller the coupling degree of the clock signal to the one with which the voltage value of the corresponding signal is set to be larger, so as to compensate for the difference in scanning signals output by the odd-numbered scanning circuit and the even-numbered scanning circuit caused by the above coupling effect, thereby improving the display effect.

[0094] Figure 6 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 6 The display panel includes a display area AA and a frame area NAA surrounding the display area AA.

[0095] A plurality of level signal lines are located in the frame area NAA and extend from the last second scanning circuit 32 in the scanning circuit group to the first first scanning circuit 31. In the region between the first second scanning circuit 32 and the last first scanning circuit 31 in the frame area, a plurality of level signal lines 40 are separately arranged. Exemplarily, in the border area NAA, the multiple level signal lines 40 in the area between the first-level second scanning circuit 32 and the last-level first scanning circuit 31 may include a first level signal line 41 and a second level signal line 42, or include a first level signal line 41, a second level signal line 42 and a third level signal line 43. If the multiple level signal lines 40 in the area between the first-level second scanning circuit 32 and the last-level first scanning circuit 31 are not separately arranged, for example, the first level signal line 41 and the second level signal line 42 in the area are combined into one, or the first level signal line 41, the second level signal line 42 and the third level signal line 43 in the area are merged into one level signal line, there will be signal coupling between the level signal lines 40 connected to the first scanning circuits 31 at each level, thereby causing abnormalities in the scanning signals output by the first scanning circuits 31 at each level, and the abnormal scanning signals will be transmitted step by step to the scanning signals output by the subsequent second scanning circuits 32 at each level, thereby affecting the overall display effect of the display panel. The technical solution of this embodiment, by separating and setting multiple level signal lines 40 in the area between the first-level second scanning circuit 32 and the last-level first scanning circuit 31, helps to weaken the influence of the coupling between the signal lines on the scanning signal, thereby improving the display effect.

[0096] Continue to see Figure 6 Optionally, the border area NAA includes a first border area NAA10 extending along the first direction X and a second border area NAA20 extending along the second direction Y, the first scanning circuit 31 is located in the first border area NAA10, the second scanning circuit 32 is located in the second border area NAA20, and the multiple level signal lines 40 in the area between the last-level first scanning circuit 31 of the first border area NAA10 and the first-level second scanning circuit 32 of the second border area NAA20 are separately arranged.

[0097] Specifically, the first direction X and the second direction Y may intersect, and the first border area NAA10 and the second border area NAA20 may be border areas located on different sides of the display area AA. For example, the first border area NAA10 may be a border area NAA located above the display area AA (hereinafter referred to as the upper border area), and the second border area NAA20 may be a border area NAA located on the left side of the midpoint perpendicular line L of the display panel (hereinafter referred to as the left border area), and / or a border area NAA located on the right side of the midpoint perpendicular line L of the display panel (hereinafter referred to as the right border area). In the case where a scanning circuit group includes m-level first scanning circuits 31 and n-level second scanning circuits 32, the m-level first scanning circuits 31 can be arranged to be cascaded in sequence in the first border area NAA10, and the n-level second scanning circuits 32 can be arranged to be cascaded in sequence in the second border area NAA20, the last-level first scanning circuit 31 is located on the side of the first border area NAA10 close to the second border area NAA20, the first-level second scanning circuit 32 is located on the side of the second border area NAA20 close to the first border area NAA10, and the last-level first scanning circuit 31 is cascaded with the first-level second scanning circuit 32. By separating and arranging the multiple level signal lines 40 in the area between the last-level first scanning circuit 31 in the first border area NAA10 and the first-level second scanning circuit 32 in the second border area NAA20, it is helpful to reduce the influence of the coupling between the signal lines on the scanning signal, thereby improving the display effect.

[0098] Further, when the n-level second scanning circuit 32 in a scanning circuit group is set in the left frame area, the area between the last-level first scanning circuit 31 in the first frame area NAA10 and the first-level second scanning circuit 32 in the second frame area NAA20 can be the third frame area NAA1, and when the n-level second scanning circuit 32 in a scanning circuit group is set in the right frame area, the area between the last-level first scanning circuit 31 in the first frame area NAA10 and the first-level second scanning circuit 32 in the second frame area NAA20 can be the fourth frame area NAA2, and both the third frame area NAA1 and the fourth frame area NAA2 can be arc angle areas. By separating and setting the multiple level signal lines 40 in the arc angle area, it helps to reduce the influence of the coupling between the signal lines on the scanning signal, thereby improving the display effect.

[0099] Continue to see Figure 6Optionally, the first border area NAA10 includes a first sub-border area NAA11 and a second sub-border area NAA12, the second border area NAA20 includes a third sub-border area NAA21 and a fourth sub-border area NAA22, the first sub-border area NAA11 is adjacent to the third sub-border area NAA21, and the second sub-border area NAA12 is adjacent to the fourth sub-border area NAA22. At least one scanning circuit group includes a first scanning circuit group and a second scanning circuit group, and the first scanning circuit group and the second scanning circuit group are respectively located on the left and right sides of the midpoint perpendicular line L of the display panel. Specifically, the first scanning circuit 31 in the first scanning circuit group is located in the first sub-border area NAA11, the second scanning circuit 32 in the first scanning circuit group is located in the third sub-border area NAA21, the first scanning circuit 31 in the second scanning circuit group is located in the second sub-border area NAA12, and the second scanning circuit 32 in the second scanning circuit group is located in the fourth sub-border area NAA22. A plurality of level signal lines 40 extend from the last-level second scanning circuit 32 in the first scanning circuit group to the first-level first scanning circuit 31 in the first scanning circuit group, and extend to the last-level second scanning circuit 32 in the second scanning circuit group via the first-level first scanning circuit 31 in the second scanning circuit group, and the plurality of level signal lines 40 in the area between the first-level first scanning circuit 32 in the first scanning circuit group and the first-level first scanning circuit 31 in the second scanning circuit group are separately arranged.

[0100] Exemplarily, the first sub-frame area NAA11 may be at least a portion of the first frame area NAA10 located to the left of the midpoint perpendicular line L of the display panel, the second sub-frame area NAA12 may be at least a portion of the first frame area NAA10 located to the right of the midpoint perpendicular line L of the display panel, the third sub-frame area NAA21 may be located in the left frame area, and the fourth sub-frame area NAA22 may be located in the right frame area. The first scanning circuit group and the second scanning circuit group may each include an m-level first scanning circuit 31 and an n-level second scanning circuit 32. In the first scanning circuit group, the m-level first scanning circuits 31 are cascaded in sequence in the first sub-border area NAA11, and the first-level first scanning circuit 31 to the last-level first scanning circuit 31 are arranged in sequence from the side close to the perpendicular midline L to the side away from the perpendicular midline L in the first direction X, and the n-level second scanning circuits 32 are cascaded in sequence in the third sub-border area NAA21, and the first-level second scanning circuits 32 to the last-level second scanning circuits 32 are arranged in sequence from the side close to the first border area NAA10 to the side away from the first border area NAA10 in the second direction Y, and the last-level first scanning circuit 31 is cascaded with the first-level second scanning circuit 32. In the second scanning circuit group, the m-level first scanning circuits 31 are cascaded in sequence in the second sub-border area NAA12, and the first-level first scanning circuit 31 to the last-level first scanning circuit 31 are arranged in sequence from the side close to the perpendicular midline L to the side away from the perpendicular midline L in the first direction X, and the n-level second scanning circuits 32 are cascaded in sequence in the fourth sub-border area NAA22, and the first-level second scanning circuits 32 to the last-level second scanning circuits 32 are arranged in sequence from the side close to the first border area NAA10 to the side away from the first border area NAA10 in the second direction Y, and the last-level first scanning circuit 31 is cascaded with the first-level second scanning circuit 32.

[0101] The first border area NAA10 may also include an area between the first sub-border area NAA11 and the second sub-border area NAA12. For example, if the area is the fifth border area NAA3, the area between the first-level first scanning circuit 32 in the first scanning circuit group and the first-level first scanning circuit 31 in the second scanning circuit group may include the fifth border area NAA3. A plurality of level signal lines 40 may extend from the area where the last-level second scanning circuit 32 of the first scanning circuit group in the third sub-border area NAA21 is located, through the third border area NAA1, the first sub-border area NAA11, the fifth border area NAA3, the second sub-border area NAA12 and the fourth border area NAA2 in sequence, to the last-level second scanning circuit 32 of the second scanning circuit group in the fourth sub-border area NAA22.

[0102] The multiple level signal lines 40 in the fifth border area NAA3 can be separately arranged, for example, the first level signal line 41 and the second level signal line 42 in the fifth border area NAA3 can be separately arranged. If the first level signal line 41 and the second level signal line 42 in the fifth border area NAA3 are combined into one, there will be signal coupling between the level signal lines connected to the first scanning circuits 31 at each level in the first scanning circuit group and the second scanning circuit group, which will also cause abnormalities in the scanning signals output by the first scanning circuits 31 at each level in the first scanning circuit group and the second scanning circuit group, and the abnormal scanning signals will be transmitted step by step to the scanning signals output by the subsequent second scanning circuits 32 at each level, thereby affecting the overall display effect of the display panel. The technical solution of this embodiment, by separating the first level signal line 41 and the second level signal line 42 in the fifth border area NAA3, helps to reduce the influence of the coupling between the signal lines on the scanning signal, thereby improving the display effect. Furthermore, the first level signal line 41, the second level signal line 42 and the third level signal line 43 in the fifth border area NAA3 may be separately arranged, so as to further reduce the influence of the coupling between the signal lines on the scanning signal, so as to improve the display effect.

[0103] Continue to see Figure 6In one embodiment, a bonding connection portion 60 is provided in the frame area NAA, at least two level signal lines 40 are connected to the same bonding connection portion 60, and one bonding connection portion 60 is used to transmit signals to at least two level signal lines 40. For example, each conduction level signal line 40 is connected to the same bonding connection portion 60, and the bonding connection portion 60 is used to transmit signals to each conduction level signal line 40. Specifically, the bonding connection portion 60 is used to receive a conduction level signal, and the driving chip in the display device can be provided on a flexible printed circuit (Flexible Printed Circuit, FPC), and the flexible printed circuit board can be connected to the bonding connection portion 60, so that the driving chip provides a conduction level signal to the bonding connection portion 60 through the FPC. In the case where the level signal line 40 includes the first level signal line 41 and the second level signal line 42, the first level signal line 41 and the second level signal line 42 can be connected to the same bonding connection part 60 to transmit the same signal to the first level signal line 41 and the second level signal line 42 through the bonding connection part 60. In the case where the level signal line 40 also includes the third level signal line 43, the first level signal line 41, the second level signal line 42 and the third level signal line 43 can be connected to the same bonding connection part 60 to transmit the same signal to the first level signal line 41, the second level signal line 42 and the third level signal line 43 through the bonding connection part 60. In this way, there is no need to set different voltage signal generating circuits in the driving chip to transmit different voltage signals to each level signal line 40, which helps to save the volume of the driving chip and reduce the power consumption of the display device. The number of bonding connection parts 60 can be one, so as to provide signals to one side of each level signal line 40 through the bonding connection part 60, or the number of bonding connection parts 60 can be two, so as to simultaneously transmit signals to both sides of each level signal line 40 through the bonding connection part 60, thereby reducing the voltage drop on each level signal line 40.

[0104] Figure 7 is a schematic diagram of the structure of another display panel provided by an embodiment of the present invention. Figure 7 In another embodiment, a plurality of bonding connections are provided in the border area NAA, and a plurality of level signal lines 40 can be connected to the plurality of bonding connections in a one-to-one correspondence, and a bonding connection can be used to transmit a signal to a corresponding level signal line 40 .

[0105] Exemplarily, in the case where the level signal line 40 includes a first level signal line 41, a second level signal line 42, and a third level signal line 43, a first bonding connection portion 61, a second bonding connection portion 62, and a third bonding connection portion 63 may be provided in the border area NAA. The first level signal line 41 is connected to the first bonding connection portion 61, and the first bonding connection portion 61 is used to transmit a first conduction level signal to the first level signal line 41. The second level signal line 42 is connected to the second bonding connection portion 62, and the second bonding connection portion 62 is used to transmit a second conduction level signal to the second level signal line 42. The third level signal line 43 is connected to the third bonding connection portion 63, and the third bonding connection portion 63 is used to transmit a third conduction level signal to the third level signal line 43.

[0106] The advantage of such a configuration is that different signals can be transmitted to the first level signal line 41, the second level signal line 42 and the third level signal line 43 respectively through the first bonding connection part 61, the second bonding connection part 62 and the third bonding connection part 63. For example, a normal level signal for controlling the conduction of the transistor in the pixel circuit can be transmitted to the third level signal line 43 through the third bonding connection part 63, and according to the degree of coupling of the clock signal to the signal transmitted by the first level signal line 41 and the second level signal line 42, conduction level signals with different voltage values ​​are transmitted to the first level signal line 41 and the second level signal line 42 through the first bonding connection part 61 and the second bonding connection part 62 to compensate for the difference in scanning signals output by the odd-level scanning circuit and the even-level scanning circuit caused by the coupling effect of the clock signal on the signals on the first level signal line 41 and the second level signal line 42, thereby improving the display effect.

[0107] The embodiment of the present invention further provides a display device, which may be a mobile phone, a computer or a tablet computer, etc. The display device provided by the embodiment of the present invention includes the display panel in any of the above embodiments, and thus has the corresponding structure and beneficial effects of the display panel, which will not be described in detail here.

[0108] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A plurality of scanning lines, a plurality of rows of pixel circuits and at least one scanning circuit group, wherein a first level signal input terminal of a scanning circuit in the scanning circuit group is connected to a level signal line and is used to output a signal on the level signal line in response to a clock signal to generate a scanning signal; The scanning circuit group includes at least one first scanning circuit and a plurality of second scanning circuits, the at least one first scanning circuit and the plurality of second scanning circuits are cascaded in sequence, the second scanning circuit is used to provide the scanning signal to the corresponding pixel circuit through the scanning line, the first scanning circuit is used to provide the scanning signal to the pixel circuit through the scanning line before the second scanning circuit generates the scanning signal, and the at least one first scanning circuit and the plurality of second scanning circuits generate the scanning signal with the timing sequentially shifted backward step by step; Among the at least one first scanning circuit and the plurality of second scanning circuits, the first level signal input terminals of two adjacent scanning circuits are respectively connected to different level signal lines; The level signal line includes a first level signal line and a second level signal line; Voltage values ​​of the signals transmitted by the first level signal line and the second level signal line are the same or different; The voltage values ​​of the signals transmitted by the first level signal line and the second level signal line are related to the coupling degree of the clock signal to the signals transmitted by the first level signal line and the second level signal line; In the case where the level signal line is used to transmit a first level signal, among the signals transmitted by the first level signal line and the second level signal line, the one with a greater coupling degree of the clock signal has a greater voltage value corresponding to it, and the one with a smaller coupling degree of the clock signal has a smaller voltage value corresponding to it; In the case where the level signal line is used to transmit the second level signal, among the signals transmitted by the first level signal line and the second level signal line, the one to which the clock signal has a greater coupling degree has a smaller voltage value corresponding to it, and the one to which the clock signal has a smaller coupling degree has a larger voltage value corresponding to it; The voltage of the first level signal is greater than the voltage of the second level signal.

2. The display panel according to claim 1, characterized in that: In the at least one first scanning circuit and the multiple second scanning circuits, the first level signal input terminals of the odd-numbered scanning circuits are connected to the first level signal lines, and the first level signal input terminals of the even-numbered scanning circuits are connected to the second level signal lines.

3. The display panel according to claim 2, characterized in that: The first level signal line and the second level signal line are provided separately.

4. The display panel according to claim 1, characterized in that: The first scanning circuit and the second scanning circuit both include an output module, the level signal input end of the output module is the first level signal input end, and the output module is used to respond to the signal of its own control end to output the signal on the level signal line to generate the scanning signal.

5. The display panel according to claim 1, characterized in that: The second level signal input terminals of the first scanning circuit and the second scanning circuit are both connected to the third level signal line, and the first level signal input terminal and the second level signal input terminal are both used to transmit the first level signal or the second level signal.

6. The display panel according to claim 5, characterized in that: The first scanning circuit and the second scanning circuit further include an output control module, the level signal input end of the output control module is the second level signal input end, and the output control module is used to control the output module through the signal on the third level signal line.

7. The display panel according to claim 6, characterized in that: The level signal line and the third level signal line connected to the first level signal input terminal are arranged separately from each other.

8. The display panel according to any one of claims 1 to 2, characterized in that: The display panel further comprises a first clock signal line and a second clock signal line, wherein the first clock signal line and the second clock signal line are used to provide clock signals to the plurality of scanning circuits; Among them, the first clock signal line, the second clock signal line, the first level signal line and the second level signal line are arranged in sequence on one side of the scanning circuit, and the distance between the first clock signal line and the first level signal line is equal to the distance between the second clock signal line and the second level signal line.

9. The display panel according to claim 8, characterized in that: The second level signal input terminals of the first scanning circuit and the second scanning circuit are both connected to the third level signal line, and the first level signal input terminal and the second level signal input terminal are both used to transmit the first level signal or the second level signal; The third level signal line is located between the second clock signal line and the first level signal line.

10. The display panel according to claim 9, characterized in that: Among the first clock signal line, the second clock signal line, the third level signal line, the first level signal line and the second level signal line, distances between two adjacent signal lines are equal.

11. The display panel according to any one of claims 1 to 10, characterized in that: The display panel comprises a display area and a frame area surrounding the display area, and the plurality of level signal lines are located in the frame area and extend from the second scanning circuit of the last stage in the scanning circuit group to the first scanning circuit of the first stage; In which, in the area between the first-level second scanning circuit and the last-level first scanning circuit in the border area, the plurality of level signal lines are separately arranged.

12. The display panel according to claim 11, characterized in that: The border area includes a first border area extending along a first direction and a second border area extending along a second direction, the first scanning circuit is located in the first border area, the second scanning circuit is located in the second border area, and the plurality of level signal lines in the area between the last level of the first scanning circuit in the first border area and the first level of the second scanning circuit in the second border area are separately arranged.

13. The display panel according to claim 12, characterized in that: The area between the last level of the first scanning circuit in the first border area and the first level of the second scanning circuit in the second border area is an arc angle area.

14. The display panel according to claim 13, characterized in that: The first frame area includes a first sub-frame area and a second sub-frame area, the second frame area includes a third sub-frame area and a fourth sub-frame area, the first sub-frame area is adjacent to the third sub-frame area, and the second sub-frame area is adjacent to the fourth sub-frame area; the at least one scanning circuit group includes a first scanning circuit group and a second scanning circuit group, the first scanning circuit in the first scanning circuit group is located in the first sub-frame area, the second scanning circuit in the first scanning circuit group is located in the third sub-frame area, the first scanning circuit in the second scanning circuit group is located in the second sub-frame area, and the second scanning circuit in the second scanning circuit group is located in the fourth sub-frame area; The plurality of level signal lines extend from the last-level second scanning circuit in the first scanning circuit group to the first-level first scanning circuit in the first scanning circuit group, and extend to the last-level second scanning circuit in the second scanning circuit group via the first-level first scanning circuit in the second scanning circuit group, and the plurality of level signal lines are separately arranged in the area between the first-level first scanning circuit in the first scanning circuit group and the first-level first scanning circuit in the second scanning circuit group.

15. The display panel according to any one of claims 1 to 10, characterized in that: The display panel includes a frame area, and a bonding connection portion is provided in the frame area; Wherein, at least two of the level signal lines are connected to the same bonding connection part, and one bonding connection part is used to transmit signals to at least two of the level signal lines; Alternatively, a plurality of the level signal lines are connected to a plurality of the bonding connection parts in a one-to-one correspondence, and one of the bonding connection parts is used to transmit a signal to a corresponding one of the level signal lines.

16. The display panel according to any one of claims 1 to 10, characterized in that: The number of the first scanning circuits in the scanning circuit group is m, and the number of rows of the pixel circuits and the number of the second scanning circuits in the scanning circuit group are both n; wherein m is a positive integer greater than or equal to 1, and n is a positive integer greater than m; The pixel circuit comprises a first scanning signal input terminal and a second scanning signal input terminal, and the scanning signal output terminal of the first scanning circuit of the i-th level is connected to the first scanning signal input terminal of the pixel circuit of the i-th row through the scanning line; wherein 1≤i≤m; The scanning signal output end of the second scanning circuit of the jth level is connected to the second scanning signal input end of the pixel circuit of the jth row through the scanning line, and the scanning signal output end of the second scanning circuit of the kth level is also connected to the first scanning signal input end of the pixel circuit of the k+mth row through the scanning line; wherein, 1≤j≤n, 1≤k≤nm.

17. A display device, characterized in that: The invention comprises the display panel described in any one of claims 1 to 16.

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