Integrator and Delta-Sigma Modulator Based on Full Dynamic Amplifier

By using a full dynamic amplifier in DSM and using common mode voltage as the bias voltage, the problems of high power consumption and complexity of existing DSM are solved, and the effect of no static power consumption and flexible adjustment of power consumption and bandwidth is achieved.

CN115051713BActive Publication Date: 2025-03-28HANGZHOU VANGO TECH
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Patent Information

Application Number
CN202210768700.X
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2022-06-30
Publication Date
2025-03-28
Estimated Expiration
2042-06-30

AI Technical Summary

Technical Problem

Existing DSMs have high power consumption and complexity, and bias circuits are needed to ensure the static working point of the OTA, and static parameters need to be adjusted manually when adjusting bandwidth and power consumption.

Method used

A fully dynamic amplifier is adopted to form a fully dynamic amplifier through a charge and discharge circuit and an inverter-type common source common gate structure signal amplifier circuit, using the common mode voltage as the bias voltage at the signal output terminal to eliminate static power consumption, and adjust the power consumption and bandwidth by changing the sampling frequency.

Benefits of technology

A fully dynamic amplifier without static power consumption is realized, simplifying the bandwidth and power consumption adjustment process, reducing system complexity, and improving gain.

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Abstract

The present invention relates to an integrator and a Delta‑Sigma modulator based on a full-dynamic amplifier, including a full-dynamic amplifier, which includes a charge-discharge circuit and a signal amplification circuit with a common source and common gate structure. When the clock signal connected to the integrator is a first level signal, the power supply voltage supplies power to the charge-discharge circuit, and the signal amplification circuit connects to the common mode voltage signal and outputs it; when the clock signal is a second level signal, the charge-discharge circuit discharges and provides a working voltage to the signal amplification circuit, and the signal amplification circuit amplifies and outputs the differential input signal. The present invention connects the signal output end of the signal amplification circuit to the common mode voltage V cm As the bias voltage, there is no need for a bias circuit, that is, there is no static power consumption, thus achieving the purpose of saving static power consumption. And there is no need to manually adjust the bias current, and the bandwidth and power consumption can be changed by only changing the sampling frequency, thereby reducing the complexity of the system in application.
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