A zero-crossing detection dynamic delay compensation circuit

Abstract

The application discloses a zero-crossing detection dynamic delay compensation circuit, which is characterized in that a zero-crossing detection circuit is arranged, and a turn-off delay compensation signal is outputted when the source-drain current of a rectifier tube of an active rectifier circuit appears zero-crossing, so that a turn-off delay compensation enabling signal corresponding to the turn-off delay compensation signal is generated by a turn-off delay compensation circuit to perform turn-off delay compensation on the active rectifier circuit, thereby realizing negative feedback control of the active rectifier circuit, improving the delay compensation effect of the active rectifier circuit and making the delay compensation effect controllable; the opening delay of the active rectifier circuit is compensated by arranging an opening delay compensation circuit, and dynamic delay compensation is formed in combination with the turn-off delay compensation circuit, thereby realizing high response speed of the opening delay compensation and the turn-off delay compensation of the active rectifier circuit. The application can be widely applied in the field of electronic technology.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to a zero-crossing detection dynamic delay compensation circuit. Background Technology

[0002] Compared to wired power transfer, wireless power transfer systems achieve contactless power transmission, offering flexibility, convenience, and one-to-many power supply capabilities. They are widely used in consumer electronics, biomedicine, and the Internet of Things (IoT). In recent years, thanks to improvements in the power supply distance and power of resonant wireless power transfer systems, as well as the implementation of one-to-many power supply technology, resonant wireless power transfer systems offer greater flexibility and practicality compared to traditional inductive wireless power transfer systems. The resonant circuits of wireless power transfer systems commonly employ two topologies: series-parallel (serial-parallel type) and series-series (serial-serial type), with the series-serial type offering superior stability.

[0003] In string resonant wireless power transfer systems, integrated active rectifier bridge structures are widely used due to their significantly improved rectification efficiency compared to passive rectifier bridge structures. However, circuit delay is a major factor limiting their output power. Based on this, adaptive delay compensation circuits and dynamic delay compensation circuits have been proposed. Adaptive delay compensation circuits, benefiting from their negative feedback control loop, can achieve good delay compensation, but their settling time is typically long. Dynamic delay compensation circuits, benefiting from their timely response speed, can achieve rapid delay compensation, but their delay compensation effect becomes uncontrollable due to the lack of negative feedback control, requiring manual external adjustment. Summary of the Invention

[0004] To address the aforementioned technical problems, embodiments of the present invention provide a zero-crossing detection dynamic delay compensation circuit.

[0005] The technical solution adopted in the embodiments of the present invention is as follows:

[0006] A zero-crossing detection dynamic delay compensation circuit, comprising:

[0007] Active rectifier circuit;

[0008] The zero-crossing detection circuit is used to output a turn-off delay compensation signal when the source-drain current of the rectifier tube in the active rectifier circuit crosses zero.

[0009] The dynamic delay compensation circuit includes an on-delay compensation circuit and an off-delay compensation circuit. The on-delay compensation circuit generates a corresponding on-delay compensation enable signal when the rectifier diode of the active rectifier circuit is turned on. The on-delay compensation enable signal is used to compensate for the on-delay of the active rectifier circuit. The off-delay compensation circuit generates a corresponding off-delay compensation enable signal based on the off-delay compensation signal. The off-delay compensation enable signal is used to compensate for the off-delay of the active rectifier circuit.

[0010] As an optional implementation, the zero-crossing detection dynamic delay compensation circuit further includes an active rectification startup circuit, an active rectification control circuit, and a voltage divider circuit. The active rectification startup circuit is used to start the active rectification circuit normally. The active rectification control circuit is used to switch the active rectification circuit between full-bridge rectification mode and non-rectification mode. The voltage divider circuit is used to divide the voltage and provide it to the active rectification startup circuit and the active rectification control circuit as the input voltage.

[0011] As an optional implementation, the active rectification control circuit includes a first comparator, a second comparator, a third comparator, a fourth comparator, a first selector, a second selector, a third selector, and a fourth selector;

[0012] The active rectifier circuit includes a first AC signal input port, a second AC signal input port, a first output port, a second output port, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit.

[0013] The source of the first PMOS transistor is connected to the non-inverting input of the first comparator. The output of the first comparator is connected to the input of the first selector. The output of the first selector is connected to the input of the first driving circuit. The output of the first driving circuit is connected to the gate of the first PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain of the first NMOS transistor is connected to the first AC signal input port. The first AC signal input port is connected to the inverting input of the first comparator. The inverting input of the first comparator is connected to the inverting input of the third comparator. The output of the third comparator is connected to the input of the third selector. The output of the third selector is connected to the input of the third driving circuit. The output of the third driving circuit is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is connected to the non-inverting input of the third comparator. The non-inverting input of the third comparator is connected to the source of the second NMOS transistor. The source of the second NMOS transistor is connected to the second output. The system is as follows: the second output port is connected to the non-inverting input of the fourth comparator; the output of the fourth comparator is connected to the input of the fourth selector; the output of the fourth selector is connected to the input of the fourth driving circuit; the output of the fourth driving circuit is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor; the drain of the second PMOS transistor is connected to the second AC signal input port; the second AC signal input port is connected to the inverting input of the fourth comparator; the inverting input of the fourth comparator is connected to the inverting input of the second comparator; the output of the second comparator is connected to the input of the second selector; the output of the second selector is connected to the input of the second driving circuit; the output of the second driving circuit is connected to the gate of the second PMOS transistor; the source of the second PMOS transistor is connected to the non-inverting input of the second comparator; the non-inverting input of the second comparator is connected to the first output port; and the first output port is connected to the source of the first PMOS transistor.

[0014] As an optional implementation, the first input terminal of the zero-crossing detection circuit is connected to the first AC signal input port, the second input terminal of the zero-crossing detection circuit is connected to the second AC signal input port, the third input terminal of the zero-crossing detection circuit is connected to the output terminal of the first driving circuit, and the fourth input terminal of the zero-crossing detection circuit is connected to the output terminal of the second driving circuit.

[0015] The zero-crossing detection circuit outputs a turn-off delay compensation signal when the source-drain current of the rectifier diode in the active rectifier circuit crosses zero, including at least one of the following:

[0016] The zero-crossing detection circuit determines whether the source-drain current of the first PMOS transistor has reached zero based on the signal at the first AC signal input port and the signal at the output of the first driving circuit. If so, it outputs the turn-off delay compensation signal.

[0017] The zero-crossing detection circuit determines whether the source-drain current of the second PMOS transistor has reached a zero-crossing point based on the signal at the second AC signal input port and the signal at the output port of the second driving circuit. If so, it outputs the turn-off delay compensation signal.

[0018] As an optional implementation, the first input terminal of the shutdown delay compensation circuit is connected to the output terminal of the third driving circuit, the second input terminal of the shutdown delay compensation circuit is connected to the output terminal of the fourth driving circuit, and the third input terminal of the shutdown delay compensation circuit is connected to the output terminal of the zero-crossing detection circuit.

[0019] As an optional implementation, the shutdown delay compensation enable signal includes a first enable signal and a second enable signal. The first enable signal is used to compensate for the shutdown delay of the output signal of the first driving circuit and the output signal of the third driving circuit, and the second enable signal is used to compensate for the shutdown delay of the output signal of the second driving circuit and the output signal of the fourth driving circuit.

[0020] The shutdown delay compensation circuit outputs a first enable signal and a second enable signal according to the shutdown delay compensation signal. The first enable signal is output to the first comparator and the third comparator, and the second enable signal is output to the second comparator and the fourth comparator.

[0021] As an optional implementation, the power-on delay compensation circuit includes a first power-on delay compensation module, a second power-on delay compensation module, a third power-on delay compensation module, and a fourth power-on delay compensation module.

[0022] The first input terminal of the first turn-on delay compensation module is connected to the first AC signal input port, the second input terminal of the first turn-on delay compensation module is connected to the output terminal of the first driving circuit, and the output terminal of the first turn-on delay compensation module is connected to the first comparator; the first input terminal of the second turn-on delay compensation module is connected to the second AC signal input port, the second input terminal of the second turn-on delay compensation module is connected to the output terminal of the second driving circuit, and the output terminal of the second turn-on delay compensation module is connected to the second comparator; the first input terminal of the third turn-on delay compensation module is connected to the first AC signal input port, the second input terminal of the third turn-on delay compensation module is connected to the output terminal of the third driving circuit, and the output terminal of the third turn-on delay compensation module is connected to the third comparator; the first input terminal of the fourth turn-on delay compensation module is connected to the second AC signal input port, the second input terminal of the fourth turn-on delay compensation module is connected to the output terminal of the fourth driving circuit, and the output terminal of the second turn-on delay compensation module is connected to the fourth comparator.

[0023] As an optional implementation, the enable signal for turn-on delay compensation includes a third enable signal, a fourth enable signal, a fifth enable signal, and a sixth enable signal. The third enable signal is used to compensate for the turn-on delay of the output signal of the first driving circuit, the fourth enable signal is used to compensate for the turn-on delay of the output signal of the second driving circuit, the fifth enable signal is used to compensate for the turn-on delay of the output signal of the third driving circuit, and the sixth enable signal is used to compensate for the turn-on delay of the output signal of the fourth driving circuit.

[0024] When the first enable delay compensation module receives the signal from the output terminal of the first drive circuit and the signal from the first AC signal input port, it outputs the third enable signal. When the second enable delay compensation module receives the signal from the output terminal of the second drive circuit and the signal from the second AC signal input port, it outputs the fourth enable signal. When the third enable delay compensation module receives the signal from the output terminal of the third drive circuit and the signal from the first AC signal input port, it outputs the fifth enable signal. When the fourth enable delay compensation module receives the signal from the output terminal of the fourth drive circuit and the signal from the second AC signal input port, it outputs the sixth enable signal.

[0025] As an optional implementation, the voltage divider circuit includes an analog power input port, an analog ground output port, a first resistor, a second resistor, a third resistor, and a fourth resistor. The analog power input port is connected to the first output port through an inductor, and the analog ground output port is grounded through an inductor.

[0026] The analog power input port is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the analog ground output port, the analog ground output port is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first reference voltage signal.

[0027] The signal at the analog power input port is divided by the first resistor and the second resistor, and a feedback voltage signal is output at the second end of the first resistor.

[0028] The first reference voltage signal is divided by the third resistor and the fourth resistor, and a second reference voltage signal is output at the first terminal of the third resistor;

[0029] The first reference voltage signal and the feedback voltage signal are the input voltages of the active rectifier control circuit, and the second reference voltage signal and the feedback voltage signal are the input voltages of the active rectifier start-up circuit.

[0030] As an optional implementation, the active rectification control circuit further includes a fifth comparator and an output voltage regulator circuit, and the active rectification startup circuit includes a sixth comparator and a startup logic circuit.

[0031] The non-inverting input of the fifth comparator is connected to the second terminal of the third resistor, the inverting input of the fifth comparator is connected to the second terminal of the first resistor, the output of the fifth comparator is connected to the input of the output voltage regulator circuit, and the output of the output voltage regulator circuit is connected to the first comparator, the second comparator, the third comparator, the fourth comparator, the first selector, the second selector, the third selector, and the fourth selector, respectively.

[0032] The non-inverting input of the sixth comparator is connected to the first terminal of the third resistor, the inverting input of the sixth comparator is connected to the second terminal of the first resistor, the output of the sixth comparator is connected to the input of the startup logic circuit, and the output of the startup logic resistor is connected to the first comparator, the second comparator, the third comparator, the fourth comparator, the first selector, the second selector, the third selector, and the fourth selector, respectively.

[0033] The zero-crossing detection dynamic delay compensation circuit of this invention, by setting a zero-crossing detection circuit, outputs a turn-off delay compensation signal when the source-leakage current of the rectifier tube in the active rectifier circuit crosses zero. This enables the turn-off delay compensation circuit to generate a corresponding turn-off delay compensation enable signal to perform turn-off delay compensation on the active rectifier circuit, thereby realizing negative feedback control of the active rectifier circuit, improving the delay compensation effect of the active rectifier circuit, and making the delay compensation effect controllable. By setting an on-time delay compensation circuit to compensate for the on-time delay of the active rectifier circuit, and combining it with the turn-off delay compensation circuit to form dynamic delay compensation, a high response speed for both on-time and turn-off delay compensation of the active rectifier circuit is achieved. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the circuit connection of the zero-crossing detection dynamic delay compensation circuit according to an embodiment of the present invention;

[0035] Figure 2 This is a waveform diagram illustrating the working principle of the zero-crossing detection dynamic delay compensation circuit in an embodiment of the present invention.

[0036] Figure 3 The waveform diagram shows a performance comparison between the zero-crossing detection dynamic delay compensation circuit of this invention and the traditional dynamic compensation circuit.

[0037] Figure 4 This is a simulation diagram comparing the performance of the zero-crossing detection dynamic delay compensation circuit with and without dynamic delay compensation enabled, according to an embodiment of the present invention.

[0038] Figure 5 The regulated output V0 of the zero-crossing detection dynamic delay compensation circuit and the output signal V of the output voltage regulator circuit in this embodiment of the invention are... CTRL Simulation diagram;

[0039] Figure 6 This is a schematic diagram illustrating the effect of the zero-crossing detection dynamic delay compensation circuit of the present invention on improving the output power and output efficiency of the wireless power receiving system.

[0040] Reference numerals: CMP1, first comparator; CMP2, second comparator; CMP3, third comparator; CMP4, fourth comparator; Mux1, first selector; Mux2, second selector; Mux3, third selector; Mux4, fourth selector; V IN1 First AC signal input port; V IN2 Second AC signal input port; PV DD First output port; PV SS Second output port; M P1 First PMOS transistor; M P2 Second PMOS transistor; MN1 , First NMOS transistor; M N2 1. Second NMOS transistor; Buff1, First drive circuit; Buff2, Second drive circuit; Buff3, Third drive circuit; Buff4, Fourth drive circuit; AV DD Analog power input port; AV SS 1. Analog ground output port; R1, first resistor; R2, second resistor; R3, third resistor; R4, fourth resistor; CMP5, fifth comparator; CMP6, sixth comparator. Detailed Implementation

[0041] To enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present application, and not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort should fall within the scope of protection of the present application.

[0042] The terms "first," "second," "third," and "fourth," etc., used in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0043] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0044] In string resonant wireless power transfer systems, integrated active rectifier bridge structures are widely used due to their significantly improved rectification efficiency compared to passive rectifier bridge structures. However, circuit delay is a major factor limiting their output power. Based on this, adaptive delay compensation circuits and dynamic delay compensation circuits have been proposed. Adaptive delay compensation circuits, benefiting from their negative feedback control loop, can achieve good delay compensation, but their settling time is typically long. Dynamic delay compensation circuits, benefiting from their timely response speed, can achieve rapid delay compensation, but their delay compensation effect becomes uncontrollable due to the lack of negative feedback control, requiring manual external adjustment. To address this, this invention proposes a zero-crossing detection dynamic delay compensation circuit. By setting a zero-crossing detection circuit, a turn-off delay compensation signal is output when the source-leakage current of the rectifier diode in the active rectifier circuit crosses zero. This enables the turn-off delay compensation circuit to generate a corresponding turn-off delay compensation enable signal to compensate for the turn-off delay of the active rectifier circuit, thereby achieving negative feedback control of the active rectifier circuit, improving the delay compensation effect, and making the delay compensation effect controllable. By setting an on-time delay compensation circuit to compensate for the on-time delay of the active rectifier circuit, combined with the turn-off delay compensation circuit to form dynamic delay compensation, a high response speed for both on-time and turn-off delay compensation of the active rectifier circuit is achieved.

[0045] like Figure 1 As shown, this embodiment of the invention proposes a zero-crossing detection dynamic delay compensation circuit, comprising:

[0046] Active rectifier circuit;

[0047] The zero-crossing detection circuit is used to output a turn-off delay compensation signal when the source-drain current of the rectifier tube in the active rectifier circuit crosses zero.

[0048] The dynamic delay compensation circuit includes an on-delay compensation circuit and an off-delay compensation circuit. The on-delay compensation circuit generates a corresponding on-delay compensation enable signal when the rectifier diode of the active rectifier circuit is turned on. The on-delay compensation enable signal is used to compensate for the on-delay of the active rectifier circuit. The off-delay compensation circuit generates a corresponding off-delay compensation enable signal based on the off-delay compensation signal. The off-delay compensation enable signal is used to compensate for the off-delay of the active rectifier circuit.

[0049] In one embodiment of the present invention, an active rectifier circuit is applied to the wireless power receiving circuit to rectify the output of the wireless power receiving circuit.

[0050] Specifically, when the input current (the source-drain current of the rectifier diode in the active rectifier circuit) crosses zero, the zero-crossing detection circuit causes the turn-off delay compensation circuit to output a turn-off delay compensation signal with a pulse width of a few microseconds, thereby compensating for the turn-off delay of the active rectifier circuit; the turn-on delay compensation circuit generates a turn-on delay compensation signal with a pulse width of a segment when the rectifier diode in the active rectifier circuit turns on, compensating for the turn-on delay of the active rectifier circuit, thereby improving the maximum output power of the system.

[0051] This invention discloses a zero-crossing detection dynamic delay compensation circuit. By setting a zero-crossing detection circuit, a turn-off delay compensation signal is output when the source-leakage current of the rectifier diode in the active rectifier circuit crosses zero. This causes the turn-off delay compensation circuit to generate a corresponding turn-off delay compensation enable signal to perform turn-off delay compensation on the active rectifier circuit, thereby achieving negative feedback control of the active rectifier circuit, improving the delay compensation effect and making the delay compensation effect controllable. By setting an on-time delay compensation circuit to compensate for the on-time delay of the active rectifier circuit, and combining it with the turn-off delay compensation circuit to form dynamic delay compensation, a high response speed for both on-time and turn-off delay compensation of the active rectifier circuit is achieved.

[0052] As an optional implementation, the active rectification control circuit includes a first comparator CMP1, a second comparator CMP2, a third comparator CMP3, a fourth comparator CMP4, a first selector Mux1, a second selector Mux2, a third selector Mux3, and a fourth selector Mux4.

[0053] The active rectifier circuit includes a first AC signal input port V. IN1 Second AC signal input port V IN2 First output port PV DD Second output port PV SS The first PMOS transistor M P1 The second PMOS transistor M P2 The first NMOS transistor M N1 The second NMOS transistor M N2 The first driving circuit Buff1, the second driving circuit Buff2, the third driving circuit Buff3, and the fourth driving circuit Buff4;

[0054] The first PMOS transistor M P1 The source of the transistor is connected to the non-inverting input of the first comparator CMP1. The output of the first comparator CMP1 is connected to the input of the first selector Mux1. The output of the first selector Mux1 is connected to the input of the first drive circuit Buff1. The output of the first drive circuit Buff1 is connected to the first PMOS transistor M. P1The gate connection of the first PMOS transistor M P1 The drain of the first NMOS transistor M N1 The drain connection of the first NMOS transistor M N1 The drain of the first AC signal input port V IN1 Connection, the first AC signal input port V IN1 The inverting input of the first comparator CMP1 is connected to the inverting input of the third comparator CMP3. The output of the third comparator CMP3 is connected to the input of the third selector Mux3. The output of the third selector Mux3 is connected to the input of the third drive circuit Buff3. The output of the third drive circuit Buff3 is connected to the first NMOS transistor M. N1 The gate connection of the first NMOS transistor is such that the source M is connected to the gate of the first NMOS transistor. N1 The non-inverting input of the third comparator CMP3 is connected to the non-inverting input of the second NMOS transistor M. N2 The source connection of the second NMOS transistor M N2 The source and the second output port PV SS Connection, second output port PV SS The output of the fourth comparator CMP4 is connected to the input of the fourth selector Mux4, the output of the fourth selector Mux4 is connected to the input of the fourth driver circuit Buff4, and the output of the fourth driver circuit Buff4 is connected to the second NMOS transistor M. N2 The gate connection of the second NMOS transistor M N2 The drain of the second PMOS transistor M P2 The drain connection of the second PMOS transistor M P2 The drain of the second AC signal input port V IN2 Connect, the second AC signal input port V IN2 The inverting input of the fourth comparator CMP4 is connected to the inverting input of the second comparator CMP2. The output of the second comparator CMP2 is connected to the input of the second selector Mux2. The output of the second selector Mux2 is connected to the input of the second drive circuit Buff2. The output of the second drive circuit Buff2 is connected to the second PMOS transistor M. P2 The gate connection of the second PMOS transistor M P2The source of is connected to the non-inverting input of the second comparator CMP2, and the non-inverting input of the second comparator CMP2 is connected to the first output port PV. DD Connection, first output port PV DD With the first PMOS transistor M P1 The source connection.

[0055] Among them, the first AC signal input port V IN1 Second AC signal input port V IN2 A receiving resonant circuit connected to the wireless power receiving circuit. (Refer to...) Figure 1 The receiving resonant circuit of the wireless power receiving circuit consists of a resonant inductor L. RX and resonant capacitor C RX Series connection; first output port PV DD The second output port PV is connected to the regulated output V0 via the parasitic inductor L1. SS It is grounded via parasitic inductance L3.

[0056] As an optional implementation, the first input terminal of the zero-crossing detection circuit is connected to the first AC signal input port V. IN1 The connection is made between the second input terminal of the zero-crossing detection circuit and the second AC signal input port V. IN2 The connection is made between the third input terminal of the zero-crossing detection circuit and the output terminal (output signal V) of the first driving circuit. GP1 The zero-crossing detection circuit is connected to the output terminal (output signal V) of the second driving circuit Buff2. GP2 )connect;

[0057] In embodiments of the present invention, the zero-crossing detection circuit outputs a turn-off delay compensation signal when the source-drain current of the rectifier diode in the active rectifier circuit crosses zero, including at least one of the following:

[0058] The zero-crossing detection circuit is based on the first AC signal input port V IN1 The signal and the signal V at the output terminal of the first driving circuit Buff1 GP1 Determine the first PMOS transistor M P1 If the source and drain currents cross zero, then output the turn-off delay compensation signal.

[0059] The zero-crossing detection circuit is based on the second AC signal input port V IN2 The signal and the output signal V of the second driving circuit Buff2 GP2 Determine the second PMOS transistor M P2 If the source and drain currents cross zero, then output the shutdown delay compensation signal.

[0060] As an optional implementation, the first input terminal of the turn-off delay compensation circuit is connected to the output terminal (output signal V) of the third driving circuit Buff3. GN1 The second input terminal of the shutdown delay compensation circuit is connected to the output terminal (output signal V) of the fourth drive circuit Buff4. GN2 The third input terminal of the shutdown delay compensation circuit is connected to the output terminal (output signal V) of the zero-crossing detection circuit. ZCS )connect.

[0061] As an optional implementation, the shutdown delay compensation enable signal includes a first enable signal V. OFF_EN1 Second enable signal V OFF_EN2 The first enable signal V OFF_EN1 Used to compensate for the output signal V of the first driving circuit Buff1 GP1 and the output signal V of the third driving circuit Buff3 GN1 The shutdown delay, the second enable signal V OFF_EN2 Used to compensate for the output signal V of the second drive circuit Buff2 GP2 and the output signal V of the fourth driving circuit Buff4 GN2 Shutdown delay;

[0062] The shutdown delay compensation circuit outputs the first enable signal V according to the shutdown delay compensation signal. OFF_EN1 and the second enable signal V OFF_EN2 The first enable signal V OFF_EN1 The output is sent to the first comparator CMP1 and the third comparator CMP3, and the second enable signal V OFF_EN2 The output is sent to the second comparator CMP2 and the fourth comparator CMP4.

[0063] As an optional implementation, the power-on delay compensation circuit includes a first power-on delay compensation module, a second power-on delay compensation module, a third power-on delay compensation module, and a fourth power-on delay compensation module.

[0064] The first input terminal of the first start-up delay compensation module is connected to the first AC signal input port V IN1 The first activation delay compensation module's second input terminal is connected to the output terminal of the first drive circuit Buff1, and the first activation delay compensation module's output terminal is connected to the first comparator CMP1; the second activation delay compensation module's first input terminal is connected to the second AC signal input port V. IN2The second input terminal of the second enable delay compensation module is connected to the output terminal of the second drive circuit Buff2, and the output terminal of the second enable delay compensation module is connected to the second comparator CMP2; the first input terminal of the third enable delay compensation module is connected to the first AC signal input port V. IN1 The second input terminal of the third enable delay compensation module is connected to the output terminal of the third drive circuit Buff3, and the output terminal of the third enable delay compensation module is connected to the third comparator CMP3; the first input terminal of the fourth enable delay compensation module is connected to the second AC signal input port V. IN2 The second input terminal of the fourth enable delay compensation module is connected to the output terminal Buff4 of the fourth drive circuit, and the output terminal of the second enable delay compensation module is connected to the fourth comparator CMP4.

[0065] As an optional implementation, the enable signal for the delay compensation includes a third enable signal, a fourth enable signal, a fifth enable signal, and a sixth enable signal. The third enable signal is used to compensate for the output signal V of the first drive circuit Buff1. GP1 The fourth enable signal is used to compensate for the turn-on delay of the second drive circuit Buff2's output signal V. GP2 The fifth enable signal is used to compensate for the turn-on delay of the third drive circuit Buff3's output signal V. GN1 The sixth enable signal is used to compensate for the turn-on delay of the fourth drive circuit Buff4's output signal V. GN2 Opening delay;

[0066] The first start-up delay compensation module receives signal V from the output terminal of the first drive circuit Buff1. GP1 and the first AC signal input port V IN1 When the signal is received, the third enable signal is output, and the second enable delay compensation module receives the signal V from the output terminal of the second drive circuit Buff2. GP2 and the second AC signal input port V IN2 When the signal is received, the fourth enable signal is output, and the third enable delay compensation module receives the signal V from the output terminal of the third drive circuit Buff3. GN1 and the first AC signal input port V IN1 When the signal is received, the fifth enable signal is output, and the fourth enable delay compensation module receives the signal V from the output terminal of the fourth drive circuit Buff4. GN2 and the second AC signal input port V IN2 When the signal is received, the sixth enable signal is output.

[0067] As an optional implementation, the voltage divider circuit includes an analog power input port AV. DD Analog ground output port AV SS The first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4, and the analog power input port AV DD Through the inductor and the first output port PV DD Connection, the analog ground output port AV SS Grounded via inductance;

[0068] The analog power input port AV DD The first terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to the analog ground output port AV. SS Connection, the analog ground output port AV SS The first terminal of the fourth resistor R4 is connected to the first terminal of the third resistor R3, and the second terminal of the third resistor R3 is connected to the first reference voltage signal V. REF1 ;

[0069] The analog power input port AV DD The signal is divided by the first resistor R1 and the second resistor R2, and a feedback voltage signal V is output at the second terminal of the first resistor R1. FB ;

[0070] The first reference voltage signal V REF1 Through the voltage division of the third resistor R3 and the fourth resistor R4, a second reference voltage signal V is output at the first terminal of the third resistor R3. REF2 ;

[0071] In an embodiment of the present invention, the first reference voltage signal V REF1 and the feedback voltage signal V FB The input voltage of the active rectifier control circuit is the second reference voltage signal V. REF2 and the feedback voltage signal V FB The input voltage of the active rectifier startup circuit is denoted as .

[0072] As an optional implementation, the active rectification control circuit further includes a fifth comparator CMP5 and an output voltage regulator circuit, and the active rectification startup circuit includes a sixth comparator CMP6 and a startup logic circuit.

[0073] The non-inverting input of the fifth comparator CMP5 is connected to the second terminal of the third resistor R3, the inverting input of the fifth comparator CMP5 is connected to the second terminal of the first resistor R1, the output of the fifth comparator CMP5 is connected to the input of the output voltage regulator circuit, and the output of the output voltage regulator circuit (output signal V) CTRL These components are respectively connected to the first comparator CMP1, the second comparator CMP2, the third comparator CMP3, the fourth comparator CMP4, the first selector Mux1, the second selector Mux2, the third selector Mux3, and the fourth selector Mux4;

[0074] The non-inverting input of the sixth comparator CMP6 is connected to the first terminal of the third resistor R3, and the inverting input of the sixth comparator CMP6 is connected to the second terminal of the first resistor R1. The output of the sixth comparator CMP6 (output signal V) STUP It is connected to the first comparator CMP1, the second comparator CMP2, the third comparator CMP3, the fourth comparator CMP4, the first selector Mux1, the second selector Mux2, the third selector Mux3, and the fourth selector Mux4.

[0075] Figure 2 This is a waveform diagram illustrating the working principle of the zero-crossing detection dynamic delay compensation circuit in an embodiment of the present invention. The first PMOS transistor M... P1 Taking delay compensation as an example, observe Figure 2 It can be seen that, without enabling the dynamic delay compensation of this embodiment of the invention, the delay of the active rectifier circuit itself will cause the output signal V of the first drive circuit Buff1 to be affected. GP1 The inability to turn on and off in a timely manner leads to the first PMOS transistor M... P1 Source-drain circuit I P Reverse current occurs, thereby reducing the system's load-carrying capacity. In this embodiment of the invention, the first PMOS transistor M... P1 When powered on, the first power-on delay compensation module generates a corresponding power-on delay compensation signal V. ON_ENP1 (Third enable signal) An offset voltage is added to the first comparator CMP1 to reduce the output signal V of the first drive circuit Buff1. GP1 Turn-on delay; in the source-drain circuit I of the first PMOS transistor P A corresponding turn-off delay compensation signal (first enable signal V) is generated before / when the zero point is crossed. OFF_EN1 To reduce the output signal V of the first drive circuit Buff1. GP1 The shutdown delay.

[0076] Figure 3This is a waveform comparison of the performance of the zero-crossing detection dynamic delay compensation circuit in this embodiment of the invention and a traditional dynamic compensation circuit. The first PMOS transistor M... P1 Taking delay compensation as an example, according to Figure 3 It can be seen that, due to the inability of traditional dynamic compensation circuits to obtain the first PMOS transistor M... P1 Source-drain current I P At the zero-crossing point, the turn-off delay compensation signal of the traditional dynamic compensation circuit is the output signal V of the first drive circuit Buff1. GP1 This occurs when the signal changes from high to low, and the delay compensation circuit needs to be kept normally open to ensure its proper functioning. If the offset voltage applied to the first comparator CMP1 is too large, the output signal V of the first drive circuit Buff1 will be affected. GP1 At I P A flip-over occurs before the zero-crossing point, leading to control logic disorder. The zero-crossing detection dynamic delay compensation circuit of this embodiment obtains the first PMOS transistor M by setting a zero-crossing detection circuit. P1 Source-drain current I P At the zero-crossing moment, the output signal V of the first drive circuit Buff1 is realized. GP1 The precise turn-off delay compensation improves the reliability and robustness of the active rectifier circuit.

[0077] Figure 4 This is a simulation diagram comparing the performance of the zero-crossing detection dynamic delay compensation circuit with and without dynamic delay compensation enabled, according to an embodiment of the present invention. The first PMOS transistor M... P1 Taking delay compensation as an example, according to Figure 4 It can be seen that, in this embodiment of the invention, the zero-crossing detection dynamic delay compensation circuit outputs the signal V of the first driving circuit Buff1 when dynamic delay compensation is enabled. GP1 The turn-on and turn-off delays have been improved, with the turn-off delay improvement being more significant. Precise zero-crossing turn-off has been achieved without overcompensation, and the overall circuit does not generate any unnecessary digital switching noise.

[0078] Figure 5 The regulated output V0 of the zero-crossing detection dynamic delay compensation circuit and the output signal V of the output voltage regulator circuit in this embodiment of the invention are... CTRL The simulation diagram. Based on... Figure 5 It can be seen that the output signal V through the output voltage regulator circuit CTRL The normal switching of the circuit enables a regulated 5V output V0 and allows the circuit to start up automatically (V0 starts from 0 in the simulation).

[0079] Figure 6 This is a schematic diagram illustrating the improvement effect of the zero-crossing detection dynamic delay compensation circuit of this invention on the output power and output efficiency of a wireless power receiving system. According to... Figure 6It can be seen that when the dynamic delay compensation of this embodiment of the invention is activated, the wireless power receiving system achieves an output power of 1000mW, which is eight times the output power when the dynamic delay compensation is not enabled, and the output efficiency is increased by 38.4% at 125mW.

[0080] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A zero-crossing detection dynamic delay compensation circuit, characterized in that, include: Active rectifier circuit; The zero-crossing detection circuit is used to output a turn-off delay compensation signal when the source-drain current of the rectifier tube in the active rectifier circuit crosses zero. A dynamic delay compensation circuit includes an on-delay compensation circuit and an off-delay compensation circuit. The on-delay compensation circuit generates a corresponding on-delay compensation enable signal when the rectifier diode of the active rectifier circuit is turned on. The on-delay compensation enable signal is used to compensate for the on-delay of the active rectifier circuit. The off-delay compensation circuit generates a corresponding off-delay compensation enable signal based on the off-delay compensation signal. The off-delay compensation enable signal is used to compensate for the off-delay of the active rectifier circuit. The zero-crossing detection dynamic delay compensation circuit further includes an active rectification control circuit, which is used to switch the active rectification circuit between full-bridge rectification mode and non-rectification mode. The active rectification control circuit includes a first comparator, a second comparator, a third comparator, a fourth comparator, a first selector, a second selector, a third selector, and a fourth selector. The active rectifier circuit includes a first AC signal input port, a second AC signal input port, a first output port, a second output port, a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, a first driving circuit, a second driving circuit, a third driving circuit, and a fourth driving circuit. The source of the first PMOS transistor is connected to the non-inverting input of the first comparator. The output of the first comparator is connected to the input of the first selector. The output of the first selector is connected to the input of the first driving circuit. The output of the first driving circuit is connected to the gate of the first PMOS transistor. The drain of the first PMOS transistor is connected to the drain of the first NMOS transistor. The drain of the first NMOS transistor is connected to the first AC signal input port. The first AC signal input port is connected to the inverting input of the first comparator. The inverting input of the first comparator is connected to the inverting input of the third comparator. The output of the third comparator is connected to the input of the third selector. The output of the third selector is connected to the input of the third driving circuit. The output of the third driving circuit is connected to the gate of the first NMOS transistor. The source of the first NMOS transistor is connected to the non-inverting input of the third comparator. The non-inverting input of the third comparator is connected to the source of the second NMOS transistor. The source of the second NMOS transistor is connected to the second output. The system is as follows: the second output port is connected to the non-inverting input of the fourth comparator; the output of the fourth comparator is connected to the input of the fourth selector; the output of the fourth selector is connected to the input of the fourth driving circuit; the output of the fourth driving circuit is connected to the gate of the second NMOS transistor; the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor; the drain of the second PMOS transistor is connected to the second AC signal input port; the second AC signal input port is connected to the inverting input of the fourth comparator; the inverting input of the fourth comparator is connected to the inverting input of the second comparator; the output of the second comparator is connected to the input of the second selector; the output of the second selector is connected to the input of the second driving circuit; the output of the second driving circuit is connected to the gate of the second PMOS transistor; the source of the second PMOS transistor is connected to the non-inverting input of the second comparator; the non-inverting input of the second comparator is connected to the first output port; and the first output port is connected to the source of the first PMOS transistor.

2. The zero-crossing detection dynamic delay compensation circuit according to claim 1, characterized in that, It also includes an active rectifier startup circuit and a voltage divider circuit. The active rectifier startup circuit is used to start the active rectifier circuit normally, and the voltage divider circuit is used to divide the voltage and provide it as the input voltage to the active rectifier startup circuit and the active rectifier control circuit.

3. The zero-crossing detection dynamic delay compensation circuit according to claim 1, characterized in that, The first input terminal of the zero-crossing detection circuit is connected to the first AC signal input port, the second input terminal of the zero-crossing detection circuit is connected to the second AC signal input port, the third input terminal of the zero-crossing detection circuit is connected to the output terminal of the first driving circuit, and the fourth input terminal of the zero-crossing detection circuit is connected to the output terminal of the second driving circuit. The zero-crossing detection circuit outputs a turn-off delay compensation signal when the source-drain current of the rectifier diode in the active rectifier circuit crosses zero, including at least one of the following: The zero-crossing detection circuit determines whether the source-drain current of the first PMOS transistor has reached zero based on the signal at the first AC signal input port and the signal at the output of the first driving circuit. If so, it outputs the turn-off delay compensation signal. The zero-crossing detection circuit determines whether the source-drain current of the second PMOS transistor has reached a zero-crossing point based on the signal at the second AC signal input port and the signal at the output port of the second driving circuit. If so, it outputs the turn-off delay compensation signal.

4. The zero-crossing detection dynamic delay compensation circuit according to claim 3, characterized in that, The first input terminal of the shutdown delay compensation circuit is connected to the output terminal of the third driving circuit, the second input terminal of the shutdown delay compensation circuit is connected to the output terminal of the fourth driving circuit, and the third input terminal of the shutdown delay compensation circuit is connected to the output terminal of the zero-crossing detection circuit.

5. The zero-crossing detection dynamic delay compensation circuit according to claim 4, characterized in that, The shutdown delay compensation enable signal includes a first enable signal and a second enable signal. The first enable signal is used to compensate for the shutdown delay of the output signal of the first drive circuit and the output signal of the third drive circuit. The second enable signal is used to compensate for the shutdown delay of the output signal of the second drive circuit and the output signal of the fourth drive circuit. The shutdown delay compensation circuit outputs a first enable signal and a second enable signal according to the shutdown delay compensation signal. The first enable signal is output to the first comparator and the third comparator, and the second enable signal is output to the second comparator and the fourth comparator.

6. The zero-crossing detection dynamic delay compensation circuit according to claim 1, characterized in that, The power-on delay compensation circuit includes a first power-on delay compensation module, a second power-on delay compensation module, a third power-on delay compensation module, and a fourth power-on delay compensation module. The first input terminal of the first turn-on delay compensation module is connected to the first AC signal input port, the second input terminal of the first turn-on delay compensation module is connected to the output terminal of the first driving circuit, and the output terminal of the first turn-on delay compensation module is connected to the first comparator; the first input terminal of the second turn-on delay compensation module is connected to the second AC signal input port, the second input terminal of the second turn-on delay compensation module is connected to the output terminal of the second driving circuit, and the output terminal of the second turn-on delay compensation module is connected to the second comparator; the first input terminal of the third turn-on delay compensation module is connected to the first AC signal input port, the second input terminal of the third turn-on delay compensation module is connected to the output terminal of the third driving circuit, and the output terminal of the third turn-on delay compensation module is connected to the third comparator; the first input terminal of the fourth turn-on delay compensation module is connected to the second AC signal input port, the second input terminal of the fourth turn-on delay compensation module is connected to the output terminal of the fourth driving circuit, and the output terminal of the second turn-on delay compensation module is connected to the fourth comparator.

7. The zero-crossing detection dynamic delay compensation circuit according to claim 6, characterized in that, The enable signal for turn-on delay compensation includes a third enable signal, a fourth enable signal, a fifth enable signal, and a sixth enable signal. The third enable signal is used to compensate for the turn-on delay of the output signal of the first driving circuit, the fourth enable signal is used to compensate for the turn-on delay of the output signal of the second driving circuit, the fifth enable signal is used to compensate for the turn-on delay of the output signal of the third driving circuit, and the sixth enable signal is used to compensate for the turn-on delay of the output signal of the fourth driving circuit. When the first enable delay compensation module receives the signal from the output terminal of the first drive circuit and the signal from the first AC signal input port, it outputs the third enable signal. When the second enable delay compensation module receives the signal from the output terminal of the second drive circuit and the signal from the second AC signal input port, it outputs the fourth enable signal. When the third enable delay compensation module receives the signal from the output terminal of the third drive circuit and the signal from the first AC signal input port, it outputs the fifth enable signal. When the fourth enable delay compensation module receives the signal from the output terminal of the fourth drive circuit and the signal from the second AC signal input port, it outputs the sixth enable signal.

8. The zero-crossing detection dynamic delay compensation circuit according to claim 2, characterized in that, The voltage divider circuit includes an analog power input port, an analog ground output port, a first resistor, a second resistor, a third resistor, and a fourth resistor. The analog power input port is connected to the first output port through an inductor, and the analog ground output port is grounded through an inductor. The analog power input port is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the analog ground output port, the analog ground output port is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the first end of the third resistor, and the second end of the third resistor is connected to the first reference voltage signal. The signal at the analog power input port is divided by the first resistor and the second resistor, and a feedback voltage signal is output at the second end of the first resistor. The first reference voltage signal is divided by the third resistor and the fourth resistor, and a second reference voltage signal is output at the first terminal of the third resistor; The first reference voltage signal and the feedback voltage signal are the input voltages of the active rectifier control circuit, and the second reference voltage signal and the feedback voltage signal are the input voltages of the active rectifier start-up circuit.

9. A zero-crossing detection dynamic delay compensation circuit according to claim 8, characterized in that, The active rectification control circuit also includes a fifth comparator and an output voltage regulator circuit, and the active rectification startup circuit includes a sixth comparator and a startup logic circuit. The non-inverting input of the fifth comparator is connected to the second terminal of the third resistor, the inverting input of the fifth comparator is connected to the second terminal of the first resistor, the output of the fifth comparator is connected to the input of the output voltage regulator circuit, and the output of the output voltage regulator circuit is connected to the first comparator, the second comparator, the third comparator, the fourth comparator, the first selector, the second selector, the third selector, and the fourth selector, respectively. The non-inverting input of the sixth comparator is connected to the first terminal of the third resistor, the inverting input of the sixth comparator is connected to the second terminal of the first resistor, the output of the sixth comparator is connected to the input of the startup logic circuit, and the output of the startup logic circuit is connected to the first comparator, the second comparator, the third comparator, the fourth comparator, the first selector, the second selector, the third selector, and the fourth selector, respectively.

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