Semiconductor device, programming method, memory, memory system, and electronic apparatus

Abstract

The application discloses a semiconductor device, a programming method, a memory, a memory system and an electronic device. The semiconductor device comprises a bit line unit, a word line unit, a bit line driving unit and a word line driving unit; the bit line unit is used for dividing the word line unit into a first word line unit and a second word line unit; the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit; the word line driving unit is used for providing a driving voltage for programming to the word line unit; and the bit line driving unit is used for applying a first bias voltage to the bit line unit dividing the first word line unit in a charging stage of programming and applying a second bias voltage to the bit line unit dividing the second word line unit in a discharging stage of programming.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor device, programming method, memory, memory system and electronic device. Background Technology

[0002] In existing 3D memory, word lines are driven from one end to the other, with signals transmitted from one end to the other. However, in 3D memory where word lines are also distributed in three dimensions, the length of the access path through each word line varies, resulting in signal loading delay. To address this delay, the word line driving unit of the 3D memory is typically placed in the middle of the storage area to reduce the difference in access path lengths between word lines.

[0003] However, as the number of stacked layers in 3D memory increases, the difference in the length of the access path through each word line also increases, resulting in the continued problem of signal loading delay. Summary of the Invention

[0004] This application aims to provide a semiconductor device, a programming method, a memory, a memory system, and an electronic device.

[0005] The technical solution of this application is implemented as follows:

[0006] A first aspect of this application provides a semiconductor device, the semiconductor device comprising:

[0007] Bit line unit, word line unit, bit line driver unit, and word line driver unit; among which...

[0008] The bit line unit is used to divide the word line unit into a first word line unit and a second word line unit; the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit;

[0009] The word line driving unit is used to provide a driving voltage for programming to the word line unit;

[0010] The bit line driving unit is configured to apply a first bias voltage to the bit line unit that divides the first word line unit during the charging phase of programming, and to apply a second bias voltage to the bit line unit that divides the second word line unit during the discharging phase of programming.

[0011] Optionally, the bit line unit is further configured to divide the first word line unit into a first word line subunit and a second word line subunit; the distance between the second word line subunit and the word line driving unit is greater than the distance between the first word line subunit and the word line driving unit.

[0012] Optionally, the bit line unit is further configured to divide the second word line unit into a third word line subunit and a fourth word line subunit; the distance between the fourth word line subunit and the word line driving unit is greater than the distance between the third word line subunit and the word line driving unit.

[0013] Optionally, the distance between the third word line subunit and the word line driving unit is greater than the distance between the first word line subunit and the word line driving unit, and less than the distance between the second word line subunit and the word line driving unit.

[0014] Optionally, the resistances of the first word line subunit, the second word line subunit, the third word line subunit, and the fourth word line subunit are equal.

[0015] Optionally, the bit line driving unit is specifically configured to apply a first bias voltage to the bit line unit that divides the first word line subunit, the second word line subunit, and the third word line subunit during the programming charging phase, and to apply a second bias voltage to the bit line unit that divides the fourth word line subunit, the third word line subunit, and the second word line subunit during the programming discharging phase.

[0016] Optionally, the word line unit includes multiple word line unit groups, each word line unit group includes multiple layers of word lines, and the difference in resistance between any two layers of word lines in each word line unit group does not exceed a preset threshold.

[0017] Optionally, the bit line unit is used to divide each word line unit group into a first word line group and a second word line group;

[0018] The first character line group in the plurality of character line unit groups constitutes the first character line unit, and the second character line group in the plurality of character line unit groups constitutes the second character line unit.

[0019] Optionally, the magnitude of the first bias voltage is positively correlated with the difference between the distances from the second word line unit and the first word line unit to the word line driving unit.

[0020] Optionally, the magnitude of the second bias voltage is positively correlated with the difference between the distances from the second word line unit and the first word line unit to the word line driving unit.

[0021] Optionally, the word line driving unit includes multiple word line driving subunits, each word line driving subunit corresponding to a layer of word lines, for providing a driving voltage for programming to the corresponding word line.

[0022] Optionally, it also includes: multiple metal bridges; each metal bridge corresponds to a word line.

[0023] Optionally, each of the word line driving units is electrically connected to the second word line unit via a corresponding metal bridge.

[0024] A second aspect of this application provides a programming method, including:

[0025] A driving voltage for programming is provided to the word line unit through a word line driving unit; wherein, the word line unit includes a first word line unit and a second word line unit, the first word line unit and the second word line unit are divided by a bit line unit, and the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit;

[0026] During the programming charging phase, a first bias voltage is applied to the bit line unit that divides the first word line unit via the bit line driving unit;

[0027] During the programming discharge phase, a second bias voltage is applied to the bit line unit that divides the second word line unit via the bit line driving unit.

[0028] Optionally, the first character line unit includes a first character line subunit and a second character line subunit; the distance between the second character line subunit and the character line driving unit is greater than the distance between the first character line subunit and the character line driving unit.

[0029] Optionally, the second character line unit includes a third character line subunit and a fourth character line subunit; the distance between the fourth character line subunit and the character line driving unit is greater than the distance between the third character line subunit and the character line driving unit.

[0030] Optionally, the distance between the third word line subunit and the word line driving unit is greater than the distance between the first word line subunit and the word line driving unit, and less than the distance between the second word line subunit and the word line driving unit.

[0031] Optionally, during the programming charging phase, applying a first bias voltage to the bit line unit that divides the first word line unit via the bit line driving unit includes:

[0032] During the charging phase of programming, a first bias voltage is applied to the bit line unit that divides the first word line subunit, the second word line subunit, and the third word line subunit through the bit line driving unit.

[0033] Optionally, during the programming discharge phase, applying a second bias voltage to the bit line unit that divides the second word line unit via the bit line driving unit includes:

[0034] During the programming discharge phase, a second bias voltage is applied to the bit line unit that divides the fourth word line subunit, the third word line subunit, and the second word line subunit through the bit line driving unit.

[0035] Optionally, the word line driving unit includes multiple word line driving sub-units, each word line driving sub-unit corresponding to a layer of word lines; the step of providing a driving voltage for programming to the word line unit through the word line driving unit includes:

[0036] Based on multiple word line driver subunits, driving voltages for programming are provided to the word lines of different layers.

[0037] A third aspect of this application provides a memory including a storage unit and a semiconductor device as described in the first aspect, wherein the semiconductor device is configured to control the storage unit to perform data storage based on commands, addresses, or control signals received from an external source.

[0038] A fourth aspect of this application provides a memory system including a controller and the memory described in the third aspect; the controller is coupled to the memory and is used to control the memory to store data.

[0039] A fifth aspect of this application provides an electronic device including the memory described in the third aspect.

[0040] Optionally, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

[0041] This application discloses a semiconductor device, a programming method, a memory, a memory system, and an electronic device. The semiconductor device includes: a bit line unit, a word line unit, a bit line driving unit, and a word line driving unit; wherein, the bit line unit is used to divide the word line unit into a first word line unit and a second word line unit; the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit; the word line driving unit is used to provide a driving voltage for programming to the word line unit; the bit line driving unit is used to apply a first bias voltage to the bit line unit dividing the first word line unit during the charging phase of programming, and to apply a second bias voltage to the bit line unit dividing the second word line unit during the discharging phase of programming. The semiconductor device and programming method provided in this application, by setting a bit line driving unit, applies a first bias voltage to the bit line units that divide the near-end word line sub-units (first word line units) during the charging phase, and applies a second bias voltage to the bit line units that divide the far-end word line sub-units (second word line units) during the discharging phase. This delays the time for the near-end word line sub-units to reach the operating voltage during the charging phase and shortens the discharge time of the far-end word line sub-units during the discharging phase, thereby reducing the programming time difference between the near-end and far-end word line sub-units. This minimizes the degradation in programming performance caused by the programming time deviation between word lines during memory operations, and improves the programming performance of the programming device. Attached Figure Description

[0042] Figure 1 A schematic diagram of the timing voltages of conventional word lines and bit lines provided for embodiments of this application;

[0043] Figure 2A This is a cross-sectional structural diagram of a semiconductor device provided in an embodiment of this application;

[0044] Figure 2B This is a top view of a semiconductor device provided in an embodiment of this application;

[0045] Figure 3 A schematic diagram of the timing voltages of word lines and bit lines of a semiconductor device provided in an embodiment of this application;

[0046] Figure 4 A flowchart illustrating a programming method provided in an embodiment of this application;

[0047] Figure 5A A schematic diagram of the structure of a memory system provided in this application embodiment. Figure 1 ;

[0048] Figure 5B This is a schematic diagram of the structure of a memory system provided in an embodiment of this application. Detailed Implementation

[0049] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0050] Furthermore, the accompanying drawings are merely illustrative of this application and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted. Some block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0051] The flowchart shown in the attached diagram is merely an illustrative example and does not necessarily include all steps. For example, some steps may be broken down, while others may be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0052] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0053] For 3D NAND memory devices, word line drivers are typically located in the middle of the memory area. Due to the different access paths between memory cells and word line drivers, signal loading delays occur. Specifically, the farther a memory cell is from the word line driver, the longer the access path between it and the word line driver. As a result, during programming, the word line signals of distant memory cells have loading delays compared to those of nearby memory cells, making it difficult to maintain consistency in the programming process and programming time for memory cells at different locations.

[0054] For example, please refer to Figure 1 , Figure 1The provided diagram illustrates the timing voltages of traditional word lines and bit lines. The horizontal axis represents time, and the vertical axis represents voltage. `WLn_near` represents word lines closer to the word line driver unit, `WLn_Far` represents word lines farther from the word line driver unit, `BL for inhibit` represents inhibited bit lines, `BL for 3BL` represents unselected bit lines, and `BL for PGM` represents selected bit lines. Because `WLn_near` is closer to the word line driver unit and has lower word line resistance, it reaches the operating voltage faster during the programming charging phase compared to `WLn_Far`. Conversely, `WLn_Far`, being farther from the word line driver unit and having higher word line resistance, requires more time to reach the operating voltage during the programming charging phase compared to `WLn_near`. Figure 1 As shown, the charging time difference between WLn_Far and WLn_near is Δt0.

[0055] Based on this, this application proposes a semiconductor device. Please refer to... Figure 2A and Figure 2B , Figure 2A This is a cross-sectional view of a semiconductor device provided in an embodiment of this application. Figure 2B This is a top view schematic diagram of a semiconductor device provided in an embodiment of this application. The semiconductor device includes:

[0056] Bit line unit 210, word line unit 220, bit line driver unit 250, and word line driver unit 230; wherein...

[0057] Bit line unit 210 is used to divide word line unit 220 into first word line unit 221 and second word line unit 222; the distance between second word line unit 222 and word line driving unit 230 is greater than the distance between first word line unit 221 and word line driving unit 230;

[0058] Word line driver unit 230 is used to provide a driving voltage for programming to word line unit 220;

[0059] Bit line driving unit 250 is used to apply a first bias voltage to the bit line unit that divides the first word line unit 221 during the charging phase of programming, and to apply a second bias voltage to the bit line unit that divides the second word line unit 222 during the discharging phase of programming.

[0060] In this embodiment, the resistance on the word lines is uniformly distributed, meaning the resistance value of the word line is proportional to its length. The word line driving unit 230 is located between the first word line unit 221 and the second word line unit 222, and is closer to the first word line unit 221. A metal bridge 240 is provided between the word line driving unit 230 and the second word line unit 222, and the word line driving unit 230 is electrically connected to the second word line unit 222 through the metal bridge 240. Here, the resistance value of the metal bridge 240 is less than the resistance values ​​of the first word line unit 221 and the second word line unit 222.

[0061] In one example, word line driver unit 230 includes multiple word line driver subunits, each corresponding to a layer of word lines, for providing a driving voltage for programming to the corresponding word lines.

[0062] In this embodiment, the word line unit 220 includes multiple word lines, and the word line driving unit 230 is a collection of multiple word line driving sub-units. The number of word line driving sub-units is equal to the number of word line layers, that is, the word line driving sub-units correspond one-to-one with the word lines. Thus, through multiple word line driving sub-units, independent driving of each layer of word lines is realized.

[0063] It should be noted that in this embodiment, since the resistance of the connecting wires between the various structures is very small compared to the resistance of the word line unit 220 and the metal bridge 240, the length of the connecting wires is not limited. The distance in this application refers to the transmission path of the electrical signal. Here, one connection endpoint is the word line driver unit 230, and the other connection endpoint is the word line unit 220. The greater the distance between the two connection endpoints, the longer the transmission path of the electrical signal between them, and also the greater the path resistance between them.

[0064] In this embodiment, the first word line unit 221 is directly connected to the word line driving unit 230 via a connecting wire, while the second word line unit 222 is connected to the word line driving unit 230 via a connecting wire and a metal bridge 240. The transmission path of the electrical signal between the second word line unit 222 and the word line driving unit 230 is longer, that is, the distance between the second word line unit 222 and the word line driving unit 230 is greater than the distance between the first word line unit 221 and the word line driving unit 230.

[0065] This embodiment reduces the programming time gap between near-end word line subunits and far-end word line subunits by setting a bit line driving unit to apply a first bias voltage to the bit line unit corresponding to the first word line unit during the charging phase and a second bias voltage to the bit line unit corresponding to the second word line unit during the discharging phase.

[0066] In one embodiment, the bit line unit 210 is further configured to divide the first word line unit 221 into a first word line subunit 2211 and a second word line subunit 2212; the distance between the second word line subunit 2212 and the word line driving unit 230 is greater than the distance between the first word line subunit 2211 and the word line driving unit 230.

[0067] The first word line unit 221 and the second word line unit 222 are located on both sides of the word line driving unit 230, and the first word line sub-unit 2211 is the word line unit on the first word line unit 221 that is closer to the word line driving unit 230. Here, the length of the first word line sub-unit 2211 and the length of the second word line sub-unit 2212 are equal, so the resistance R1 of the first word line sub-unit 2211 is equal to the resistance R2 of the second word line sub-unit 2212. However, the path resistance R2' between the second word line sub-unit 2212 and the word line driving unit 230 is different from the path resistance R1' between the first word line sub-unit 2211 and the word line driving unit 230. Since the path from the second word line subunit 2212 to the word line driver unit 230 is longer than the path from the first word line subunit 2211 to the word line driver unit 230, and the path from the second word line subunit 2212 to the word line driver unit 230 includes the path from the first word line subunit 2211 to the word line driver unit 230, the path resistance R2' between the second word line subunit 2212 and the word line driver unit 230 is equal to the resistance R2 of the second word line subunit 2212 plus the resistance R1 of the first word line subunit 2211.

[0068] For example, assuming the resistance R1 corresponding to the first word line subunit 2211 is 15KΩ and the resistance R2 corresponding to the second word line subunit 2212 is 15KΩ, ignoring the resistance of the wires between the word line driving unit 230 and the first word line subunit 2211 and the second word line subunit 2212, then the path resistance R1' between the first word line subunit 2211 and the word line driving unit 230 is 15KΩ, and the path resistance R2' between the second word line subunit 2212 and the word line driving unit 230 is 30KΩ.

[0069] It should be noted that, in this embodiment, the word line sub-units included in the first word line unit are not limited to the first word line sub-unit and the second word line sub-unit, and can also be multiple word line sub-units. The principle is similar to that described above, and will not be repeated here.

[0070] In one embodiment, the bit line unit 210 is further configured to divide the second word line unit 222 into a third word line subunit 2221 and a fourth word line subunit 2222; the distance between the fourth word line subunit 2222 and the word line driving unit 230 is greater than the distance between the third word line subunit 2221 and the word line driving unit 230.

[0071] The third word line subunit 2221 is a word line unit on the second word line unit 222 that is closer to the word line driver unit 230. Here, the length of the third word line subunit 2221 is equal to the length of the fourth word line subunit 2222, so the resistance R3 of the third word line subunit 2221 is equal to the resistance R4 of the fourth word line subunit 2222. However, the path resistance R4' between the fourth word line subunit 2222 and the word line driver unit 230 is different from the path resistance R3' between the third word line subunit 2221 and the word line driver unit 230. Since the path from the fourth word line subunit 2222 to the word line driver unit 230 is longer than the path from the third word line subunit 2221 to the word line driver unit 230, and the path from the fourth word line subunit 2222 to the word line driver unit 230 includes the path from the third word line subunit 2221 to the word line driver unit 230, the path resistance R4' between the fourth word line subunit 2222 and the word line driver unit 230 is equal to the resistance R4 of the fourth word line subunit 2222 plus the resistance R3 of the third word line subunit 2221 plus the resistance R5 of the metal bridge 240; and the path resistance R3' between the third word line subunit 2221 and the word line driver unit 230 is equal to the resistance R3 of the third word line subunit 2221 plus the resistance R5 of the metal bridge 240.

[0072] For example, assuming the resistor R3 corresponding to the third word line subunit 2221 is 15KΩ, the resistor R4 corresponding to the fourth word line subunit 2222 is 15KΩ, the resistor R5 of the metal bridge 240 is 10KΩ, and ignoring the resistance of the wires between the word line driving unit 230 and the third word line subunit 2221 and the fourth word line subunit 2222, then the path resistance R3' between the third word line subunit 2221 and the word line driving unit 230 is 25KΩ, and the path resistance R4' between the fourth word line subunit 2222 and the word line driving unit 230 is 40KΩ.

[0073] It should be noted that, in this embodiment, the word line sub-units included in the second word line unit may not be limited to the third and fourth word line sub-units, and may also include multiple word line sub-units. The principle is similar to that described above, and will not be elaborated on in detail.

[0074] In one embodiment, the distance between the third word line subunit 2221 and the word line driving unit 230 is greater than the distance between the first word line subunit 2211 and the word line driving unit 230, and less than the distance between the second word line subunit 2212 and the word line driving unit 230.

[0075] Please refer to Figure 2. Since the word line driving unit 230 is closer to the first word line unit 221, the path resistances between each word line subunit and the word line driving unit 230, from smallest to largest, are: the path resistance R1' corresponding to the first word line subunit 2211, the path resistance R3' corresponding to the third word line subunit 2221, the path resistance R2' corresponding to the second word line subunit 2212, and the path resistance R4' corresponding to the fourth word line subunit 2222.

[0076] In this embodiment, since the storage stack structure is a stepped structure, the lengths of the metal bridges 240 between word lines of different layers are different, and thus the resistance values ​​of the metal bridges 240 between word lines of different layers vary, ranging from 1KΩ to 10KΩ. Due to the presence of the metal bridges 240, the path resistance between each word line subunit and the word line driving unit 230 still satisfies the following order from smallest to largest: path resistance R1' corresponding to the first word line subunit 2211, path resistance R3' corresponding to the third word line subunit 2221, path resistance R2' corresponding to the second word line subunit 2212, and path resistance R4' corresponding to the fourth word line subunit 2222.

[0077] In one example, there are multiple metal bridges, each corresponding to a word line layer. Each word line driver subunit is electrically connected to a second word line unit via its corresponding metal bridge. Through multiple word line driver subunits and multiple metal bridges, independent driving of each word line layer is achieved. Here, the metal bridges can be multiple metal wires with different resistances, such as tungsten wires.

[0078] In one embodiment, the resistors R1 of the first word line subunit 2211, R2 of the second word line subunit 2212, R3 of the third word line subunit 2221, and R4 of the fourth word line subunit 2222 are equal. It should be noted that since the lengths of the first word line subunit 2211, the second word line subunit 2212, the third word line subunit 2221, and the fourth word line subunit 2222 are equal, R1, R2, R3, and R4 are also equal. If the lengths of these three subunits are not equal, then R1, R2, R3, and R4 will also be unequal.

[0079] Here, the first word line subunit, the second word line subunit, the third word line subunit, and the fourth word line subunit are all word line subunits of the same specification, that is, the word line unit is controlled in four equal parts. The only difference is that the distance (path) between each word line subunit and the word line driving unit is different, which makes the path resistance between each word line subunit and the word line driving unit different.

[0080] It should be noted that, depending on the actual programming performance requirements, word line units can also be divided into eight, sixteen, or thirty-two equal parts for control. Here, the specific number of word line sub-units is not limited.

[0081] In one embodiment, the bit line driving unit is specifically configured to apply a first bias voltage V to the bit line unit that divides the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221 during the programming charging phase. int During the programming discharge phase, a second bias voltage V is applied to the bit line unit that divides the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212. end Here, the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221 are near-end word line subunits that are closer to the word line driving unit; the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212 are far-end word line subunits that are farther from the word line driving unit, and the first bias voltage V int Second bias voltage V end The values ​​can be equal or unequal, and there is no restriction on this. It should be noted that in this embodiment, the bit line driving unit may also include multiple bit line driving sub-units, each of which is used to apply a bias voltage to different bit lines during the programming process.

[0082] As described in the above embodiments, the distance difference between each word line subunit and the word line driving unit results in the minimum path resistance between the first word line subunit and the word line driving unit, and the maximum path resistance between the fourth word line subunit and the word line driving unit. Therefore, when the operating voltage is applied simultaneously, the fourth word line subunit is the last to reach the operating voltage. In this embodiment, by applying a first bias voltage to the bit line unit corresponding to the first word line unit during the charging phase and applying a second bias voltage to the bit line unit corresponding to the second word line unit during the discharging phase, the programming time difference between the near-end word line subunit and the far-end word line subunit is reduced. This minimizes the degradation of programming performance caused by the programming time deviation between word lines during the storage operation, thereby improving the programming performance of the programming device.

[0083] Please see Figure 3 , Figure 3A schematic diagram of the timing voltages of the word lines and bit lines of a semiconductor device provided in an embodiment of this application. Among them, the curves from top to bottom correspond to the first word line unit 2211, the third word line unit 2221, the second word line unit 2212, the fourth word line unit 2222, BL for inhibit (suppress bit line), BL for 3BL(2222) (selected bit line unit corresponding to the fourth word line subunit 2222), BL for PGM(2222) (unselected bit line unit corresponding to the fourth word line subunit 2222), BL for 3BL(2212) (bit line unit corresponding to the second word line subunit 2212), BL for PGM(2212) (unselected bit line unit corresponding to the second word line subunit 2212), BL for 3BL(2221) (selected bit line unit corresponding to the third word line subunit 2221), BL for PGM(2221) (unselected bit line unit corresponding to the third word line subunit 2221), BL for 3BL(2211) (selected bit line unit corresponding to the first word line unit 2211), BL for... PGM(2211) is the unselected positioning line unit corresponding to the first character line unit 2211.

[0084] During the programming charging phase, a first bias voltage V is applied to the bit line units that divide the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221, based on the bit line driving unit. int An unselected voltage (e.g., Vdd) is applied to the bit line cells that are not used to divide the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221. Here, the first bias voltage Vdd is... int This maintains the voltages of the first word line unit 2211, the third word line unit 2221, and the second word line unit 2212 at an intermediate voltage state, increasing the charging time to delay the time it takes for each word line sub-unit to reach its operating voltage. This ensures that the programming time of the first word line unit 2211, the third word line unit 2221, and the second word line unit 2212 is nearly synchronized with the programming time of the fourth word line unit 2222. First bias voltage V int It is greater than the initial voltage of each word line sub-unit, but lower than the programmed operating voltage. For example... Figure 3 As shown, the intermediate voltage state maintenance times of the first word line unit 2211, the third word line unit 2221, and the second word line unit 2212 are Δt1, Δt2, and Δt3, respectively, and satisfy Δt1 < Δt2 < Δt3.

[0085] It should be noted that during the programming and charging phase, the bit line units that divide the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221 can be called selected bit lines, and the bit line units not used to divide the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221 can be called unselected bit lines. Selected bit lines are typically applied with a selected voltage (e.g., Vss), and unselected bit lines are typically applied with an unselected voltage (e.g., Vdd). In this embodiment, a first bias voltage V is applied to the bit line units that divide the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221. int This delays the time it takes for the first word line subunit 2211, the second word line subunit 2212, and the third word line subunit 2221 to reach the operating voltage, thereby reducing the effective programming time gap between the first word line subunit 2211, the second word line subunit 2212, the third word line subunit 2221, and the fourth word line subunit 2222.

[0086] During the programming discharge phase, based on the bit line driving unit, a second bias voltage Vend is applied to the bit line units that divide the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212. An unselected voltage (e.g., Vdd) is applied to the bit line units not used to divide the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212. Here, the second bias voltage Vend shortens the discharge time of the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212, thereby ensuring that the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212 can complete discharge almost simultaneously with the first word line unit 2211. Figure 3 As shown, the intermediate voltage state maintenance times of the fourth word line subunit 2222, the second word line subunit 2212 and the third word line subunit 2221 are Δt4, Δt5 and Δt6 respectively, and satisfy Δt4<Δt5<Δt6.

[0087] It should be noted that during the programming discharge stage, the bit line units that divide the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212 can be called selected positioning lines, and the bit line units not used to divide the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212 can be called unselected positioning lines. Selected positioning lines are typically applied with a selected voltage (e.g., Vss), and unselected positioning lines are typically applied with an unselected voltage (e.g., Vdd). In this embodiment, a first bias voltage V is applied to the bit line units that divide the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212. intThis shortens the discharge time of the fourth word line subunit 2222, the third word line subunit 2221, and the second word line subunit 2212, thereby reducing the effective programming time gap between the fourth word line subunit 2222, the third word line subunit 2221, the second word line subunit 2212, and the first word line subunit 2211.

[0088] This application embodiment sets up a bit line driving unit to apply a first bias voltage to the bit line unit that divides the near-end word line sub-unit during the charging phase and a second bias voltage to the bit line unit that divides the far-end word line sub-unit during the discharging phase. This delays the time for the near-end word line sub-unit to reach the operating voltage during the charging phase and shortens the discharge time of the far-end word line sub-unit during the discharging phase, thereby reducing the programming time difference between the near-end word line sub-unit and the far-end word line sub-unit.

[0089] In one embodiment, a word line unit includes multiple word line unit groups, each word line unit group comprising multiple layers of word lines, wherein the resistance difference between any two layers of word lines in each word line unit group does not exceed a preset threshold. It should be noted that the word line units are divided based on the preset threshold, grouping word lines whose resistance differences meet the preset threshold into a single group, and dividing them into different word line unit groups from top to bottom. The number of word line unit groups depends on the preset threshold and the number of word line layers.

[0090] Please refer to Figure 2 again. The word lines of different layers have different lengths, which results in different resistance values ​​for the word lines of different layers. From top to bottom, the resistance value of the word lines gradually increases. Therefore, word lines whose resistance value difference meets the preset threshold are grouped together, such as WLx and Wly in Figure 2. This makes the resistance value difference of the word lines in the same group smaller. Then, in the subsequent programming process, the word line unit group is controlled on a group basis, thereby further reducing the programming time difference between the word line sub-units within the word line unit group.

[0091] Here, word line subunits are divided along the extension direction of word lines, and word line unit groups are divided along the extension direction of bit lines. Thus, this embodiment of the application achieves the division of word line units in both vertical and horizontal dimensions, thereby greatly reducing the programming time difference between each word line subunit.

[0092] In one embodiment, the bit line unit is used to divide each word line unit group into a first word line group and a second word line group; the first word line group in the plurality of word line unit groups constitutes a first word line unit, and the second word line group in the plurality of word line unit groups constitutes a second word line unit.

[0093] Bit line units are horizontal divisions of word line units. This horizontal division allows for control of word line subunits in both vertical and horizontal dimensions, reducing resistance differences between the two dimensions. This significantly minimizes the programming time gap between word line subunits.

[0094] In one embodiment, the first bias voltage is positively correlated with the difference between the distance of the second word line unit and the distance of the first word line unit to the word line driving unit.

[0095] Understandably, the greater the difference in distance between the second word line unit and the first word line unit to the word line driver unit, the greater the difference in their charging time during the programming charging phase. Therefore, a first bias voltage is used to reduce the charging time difference between the second word line unit and the first word line unit.

[0096] In one embodiment, the second bias voltage is positively correlated with the difference between the distances of the second word line unit and the first word line unit to the word line driving unit.

[0097] Similarly, the greater the difference in distance between the second word line unit and the first word line unit to the word line drive unit, the greater the difference in their discharge time during the programming discharge phase. Therefore, a second bias voltage is used to reduce the discharge time difference between the second word line unit and the first word line unit.

[0098] This application also provides a programming method. Please refer to the embodiments therein. Figure 4 , Figure 4 This is a flowchart illustrating a programming method provided in an embodiment of this application. The programming method includes:

[0099] S401, a driving voltage for programming is provided to the word line unit through the word line driving unit; wherein, the word line unit includes a first word line unit and a second word line unit, the first word line unit and the second word line unit are divided by a bit line unit, and the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit;

[0100] S402, during the programming charging phase, a first bias voltage is applied to the bit line unit that divides the first word line unit through the bit line driving unit;

[0101] S403, during the programming discharge phase, applies a second bias voltage to the bit line unit that divides the second word line unit through the bit line driving unit.

[0102] In this embodiment, the programming process, driving voltage, and bias voltage can be controlled by a controller within the semiconductor device. Because the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit, the path resistance between the second word line sub-unit and the word line driving unit is greater than the path resistance between the first word line sub-unit and the word line driving unit. Therefore, during the programming charging phase, the first word line unit reaches the operating voltage faster, and during the programming discharging phase, the first word line completes discharging faster. Thus, by setting the bit line driving unit, a first bias voltage is applied to the first word line unit during the programming charging phase, thereby suppressing the voltage rise near the first word line unit and extending the charging time. During the programming discharging phase, a second bias voltage is applied to the second word line unit, shortening the discharging time. This reduces the programming time difference between word lines at different locations, solves the problem of signal loading delay for long-distance word lines, minimizes the programming performance degradation caused by programming time deviations between word lines during memory operations, and improves the programming performance of the programming device.

[0103] In one embodiment, the first word line unit includes a first word line subunit and a second word line subunit; the distance between the second word line subunit and the word line driving unit is greater than the distance between the first word line subunit and the word line driving unit.

[0104] The first word line unit and the second word line unit are located on opposite sides of the word line driving unit, and the first word line sub-unit is the word line unit closer to the word line driving unit on the first word line unit. Here, the length of the first word line unit and the length of the second word line sub-unit are equal, so the resistance of the first word line sub-unit is equal to the resistance of the second word line sub-unit. However, the path resistance between the second word line sub-unit and the word line driving unit is different from the path resistance between the first word line sub-unit and the word line driving unit. Specific examples are as described in the above method embodiments, and will not be repeated here.

[0105] In one embodiment, the second word line unit includes a third word line subunit and a fourth word line subunit; the distance between the fourth word line subunit and the word line driving unit is greater than the distance between the third word line subunit and the word line driving unit.

[0106] The third word line sub-unit is a word line unit on the first word line unit that is closer to the word line driver unit. Here, the length of the third word line sub-unit is equal to the length of the fourth word line sub-unit, and therefore the resistance of the third word line sub-unit is equal to the resistance of the fourth word line sub-unit. However, the path resistance between the fourth word line sub-unit and the word line driver unit is different from the path resistance between the third word line sub-unit and the word line driver unit. Specific examples are as described in the above method embodiments, and will not be repeated here.

[0107] In one embodiment, the distance between the third word line subunit and the word line driving unit is greater than the distance between the first word line subunit and the word line driving unit, but less than the distance between the second word line subunit and the word line driving unit.

[0108] For example, the path resistance between each word line subunit and the word line driving unit, from smallest to largest, is the path resistance corresponding to the first word line subunit, the path resistance corresponding to the third word line subunit, the path resistance corresponding to the second word line subunit, and the path resistance corresponding to the fourth word line subunit.

[0109] In one embodiment, during the programming charging phase, a first bias voltage is applied to the bit line unit that divides the first word line subunit, the second word line subunit, and the third word line subunit via the bit line driving unit. Here, the first word line subunit, the second word line subunit, and the third word line subunit are near-end word line subunits that are closer to the word line driving unit.

[0110] For example, during the programming charging phase, a first bias voltage is applied to the bitline units that divide the first, second, and third word line subunits, based on the bitline driving unit. Here, the first bias voltage maintains the voltages of the first, third, and second word line units at an intermediate voltage state, increasing the charging time to delay the time it takes for each word line subunit to reach its operating voltage. This makes the programming time of the first, third, and second word line units nearly synchronized with the programming time of the fourth word line unit. The first bias voltage is greater than the initial voltage of each word line subunit but lower than the programming operating voltage.

[0111] In one embodiment, during the programming discharge phase, a second bias voltage is applied to the bit line unit that divides the fourth word line subunit, the third word line subunit, and the second word line subunit via the bit line driving unit. Here, the fourth word line subunit, the third word line subunit, and the second word line subunit are far-end word line subunits located far from the word line driving unit.

[0112] During the programming discharge phase, based on the bit line driving unit, a second bias voltage is applied to the bit line unit that divides the fourth word line subunit, the third word line subunit, and the second word line subunit. Here, the second bias voltage shortens the discharge time of the fourth word line subunit, the third word line subunit, and the second word line subunit, so that they can be discharged simultaneously with the first word line unit, thereby reducing the effective programming time difference between the fourth word line subunit, the third word line subunit, the second word line unit, and the first word line subunit.

[0113] This application embodiment sets up a bit line driving unit to apply a first bias voltage to the bit line unit that divides the near-end word line sub-unit during the charging phase and a second bias voltage to the bit line unit that divides the far-end word line sub-unit during the discharging phase. This delays the time for the near-end word line sub-unit to reach the operating voltage during the charging phase and shortens the discharge time of the far-end word line sub-unit during the discharging phase, thereby reducing the programming time difference between the near-end and far-end word line sub-units.

[0114] In one embodiment, the word line driving unit includes multiple word line driving sub-units, each word line driving sub-unit corresponding to a layer of word lines; providing a driving voltage for programming to the word line units through the word line driving units includes:

[0115] Based on multiple word line driver subunits, driving voltages for programming are provided to word lines of different layers.

[0116] Here, a word line driver unit is a collection of multiple word line driver subunits. The number of word line driver subunits is equal to the number of word line layers, meaning there is a one-to-one correspondence between word line driver subunits and word lines. It should be noted that in this embodiment, a bit line driver unit may also include multiple bit line driver subunits, each used to apply a bias voltage to different bit lines during programming.

[0117] This application also provides a memory, including a storage unit and the aforementioned semiconductor device. The semiconductor device is configured to control the storage unit to store data based on commands, addresses, or control signals received from an external source. Specific examples are as described in the semiconductor device examples above, and will not be repeated here.

[0118] This application also provides a memory system, including a controller and the memory described above; the controller is coupled to the memory and is used to control the memory to store data.

[0119] In one example, such as Figure 5A As shown, the memory system 500 may include only one memory 501 and a corresponding memory controller 502.

[0120] In another example, such as Figure 5B As shown, the memory system 500 may include multiple memories 501 and a corresponding memory controller 502.

[0121] Of course, in other examples, the memory system may also include multiple memories and corresponding multiple memory controllers, which will not be enumerated.

[0122] In some implementations, the memory system may be implemented as a Universal Flash Storage (UFS) device, a multimedia card in the form of a solid-state drive (SSD), MMC, eMMC, RS-MMC, and micro MMC, a secure digital card in the form of an SD, mini SD, and micro SD, a PCMCIA card type storage device, a foreign component interconnect (PCI) type storage device, a high-speed PCI (PCI-E) type storage device, a compact flash (CF) card, a smart media card, or a memory stick, etc.

[0123] This application also provides an electronic device including the memory described above.

[0124] In one embodiment, the electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, and power bank.

[0125] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0126] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0127] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0128] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of modules is only a logical functional division, and in actual implementation, there may be other division methods, such as: multiple modules or components can be combined, or integrated into another system, or some features can be ignored or not executed. In addition, the coupling, direct coupling, or communication connection between the various components shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or modules can be electrical, mechanical, or other forms.

[0129] The modules described above as separate components may or may not be physically separate. The components shown as modules may or may not be physical units, that is, they may be located in one place or distributed across multiple network modules. Some or all of the modules may be selected to achieve the purpose of this embodiment according to actual needs.

[0130] In addition, each functional module in the various embodiments of this application can be integrated into one processing module, or each module can be a separate module, or two or more modules can be integrated into one module; the integrated module can be implemented in hardware or in the form of hardware plus software functional modules.

[0131] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: Bit line unit, word line unit, bit line driver unit, and word line driver unit; among which... The bit line unit divides the word line unit into a first word line unit and a second word line unit along the extension direction of the word line; the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit; The word line driving unit is used to provide a driving voltage for programming to the word line unit; The bit line driving unit is configured to apply a first bias voltage to the bit line unit that divides the first word line unit during the programming charging phase, so as to delay the time required for the first word line unit to reach the operating voltage during the programming charging phase; and to apply a second bias voltage to the bit line unit that divides the second word line unit during the programming discharging phase, so as to shorten the discharging time of the second word line unit during the programming discharging phase.

2. The semiconductor device according to claim 1, characterized in that, The bit line unit further divides the first word line unit into a first word line sub-unit and a second word line sub-unit along the extension direction of the word line; the distance between the second word line sub-unit and the word line driving unit is greater than the distance between the first word line sub-unit and the word line driving unit.

3. The semiconductor device according to claim 2, characterized in that, The bit line unit further divides the second word line unit into a third word line subunit and a fourth word line subunit along the extension direction of the word line; the distance between the fourth word line subunit and the word line driving unit is greater than the distance between the third word line subunit and the word line driving unit.

4. The semiconductor device according to claim 3, characterized in that, The distance between the third character line subunit and the character line driving unit is greater than the distance between the first character line subunit and the character line driving unit, but less than the distance between the second character line subunit and the character line driving unit.

5. The semiconductor device according to claim 3, characterized in that, The resistances of the first word line subunit, the second word line subunit, the third word line subunit, and the fourth word line subunit are equal.

6. The semiconductor device according to claim 3, characterized in that, The bit line driving unit is specifically configured to apply the first bias voltage to the bit line unit that divides the first word line subunit, the second word line subunit, and the third word line subunit during the programming charging phase, and to apply the second bias voltage to the bit line unit that divides the fourth word line subunit, the third word line subunit, and the second word line subunit during the programming discharging phase.

7. The semiconductor device according to claim 1, characterized in that, The word line unit includes multiple word line unit groups, and each word line unit group includes multiple layers of word lines. The difference in resistance between any two layers of word lines in each word line unit group does not exceed a preset threshold.

8. The semiconductor device according to claim 7, characterized in that, The bit line unit divides each word line unit group into a first word line group and a second word line group along the extension direction of the word line; The first character line group in the plurality of character line unit groups constitutes the first character line unit, and the second character line group in the plurality of character line unit groups constitutes the second character line unit.

9. The semiconductor device according to claim 1, characterized in that, The magnitude of the first bias voltage is positively correlated with the difference between the distances from the second word line unit and the first word line unit to the word line driving unit.

10. The semiconductor device according to claim 1, characterized in that, The magnitude of the second bias voltage is positively correlated with the difference between the distances from the second word line unit and the first word line unit to the word line driving unit.

11. The semiconductor device according to claim 1, characterized in that, The word line driving unit includes multiple word line driving subunits, each word line driving subunit corresponding to a layer of word lines, and is used to provide a driving voltage for programming to the corresponding word lines.

12. The semiconductor device according to claim 11, characterized in that, Also includes: Multiple metal bridges; each metal bridge corresponds to a layer of word lines.

13. The semiconductor device according to claim 12, characterized in that, Each of the word line driver subunits is electrically connected to the second word line unit via a corresponding metal bridge.

14. A programming method, characterized in that, include: A driving voltage for programming is provided to the word line unit through the word line driving unit; wherein, the word line unit includes a first word line unit and a second word line unit, the first word line unit and the second word line unit are divided along the extension direction of the word line by a bit line unit, and the distance between the second word line unit and the word line driving unit is greater than the distance between the first word line unit and the word line driving unit; During the charging phase of programming, a first bias voltage is applied to the bit line unit that divides the first word line unit through the bit line driving unit to delay the time required for the first word line unit to reach the operating voltage. During the programming discharge phase, a second bias voltage is applied to the bit line unit that divides the second word line unit through the bit line driving unit to shorten the discharge time of the second word line unit.

15. The programming method according to claim 14, characterized in that, The first word line unit includes a first word line sub-unit and a second word line sub-unit, which are divided along the extension direction of the word line by the bit line unit; the distance between the second word line sub-unit and the word line driving unit is greater than the distance between the first word line sub-unit and the word line driving unit.

16. The programming method according to claim 15, characterized in that, The second word line unit includes a third word line sub-unit and a fourth word line sub-unit, which are divided along the extension direction of the word line by the bit line unit; the distance between the fourth word line sub-unit and the word line driving unit is greater than the distance between the third word line sub-unit and the word line driving unit.

17. The programming method according to claim 16, characterized in that, The distance between the third character line subunit and the character line driving unit is greater than the distance between the first character line subunit and the character line driving unit, and less than the distance between the second character line subunit and the character line driving unit.

18. The programming method according to claim 17, characterized in that, During the programming charging phase, applying a first bias voltage to the bit line unit that divides the first word line unit via the bit line driving unit includes: During the programming charging phase, the first bias voltage is applied to the bit line unit that divides the first word line subunit, the second word line subunit, and the third word line subunit through the bit line driving unit.

19. The programming method according to claim 18, characterized in that, During the programming discharge phase, applying a second bias voltage to the bit line unit that divides the second word line unit via the bit line driving unit includes: During the programming discharge phase, the second bias voltage is applied to the bit line unit that divides the fourth word line subunit, the third word line subunit, and the second word line subunit through the bit line driving unit.

20. The programming method according to claim 14, characterized in that, The word line driving unit includes multiple word line driving subunits, and each word line driving subunit corresponds to a layer of word lines; The provision of a driving voltage for programming to the word line unit via the word line driving unit includes: Based on multiple word line driver subunits, driving voltages for programming are provided to the word lines of different layers.

21. A memory, characterized in that, The device includes a storage unit and a semiconductor device according to any one of claims 1-13, wherein the semiconductor device is configured to control the storage unit to perform data storage based on commands, addresses, or control signals received from an external source.

22. A memory system, characterized in that, It includes a controller and the memory of claim 21; the controller is coupled to the memory and is used to control the memory to store data.

23. An electronic device, characterized in that, Includes the memory as described in claim 21.

24. The electronic device according to claim 23, characterized in that, The electronic device includes at least one of the following: mobile phone, desktop computer, tablet computer, laptop computer, server, vehicle-mounted equipment, wearable device, and power bank.

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