Nonvolatile semiconductor memory device

Abstract

An embodiment of the present invention provides a non-volatile semiconductor memory device for suppressing malfunctions of memory strings during programming operations. The non-volatile semiconductor memory device of one embodiment includes: a first bit line disposed in a second direction intersecting a first direction and extending along the second direction; a second bit line disposed on the opposite side of the first bit line in the first direction and extending along the second direction; a first source line disposed in a third direction intersecting the first and second directions and extending along the third direction; a second source line disposed on the opposite side of the first source line in the first direction; a first semiconductor layer and a second semiconductor layer extending along the first direction; a first memory string disposed on a first side of the first semiconductor layer; a second memory string disposed on a second side opposite to the first side of the first semiconductor layer; a third memory string disposed on a first side of the second semiconductor layer and facing the first memory string; and a fourth memory string disposed on a second side opposite to the first side of the second semiconductor layer.

Description

[0001] Related applications

[0002] This application claims priority to Japanese Patent Application No. 2021-49290 (filed on March 23, 2021). This application incorporates the entire contents of that basic application by reference. Technical Field

[0003] One embodiment of this disclosure relates to a non-volatile semiconductor memory device. Background Technology

[0004] As a non-volatile semiconductor memory device, NAND (Not AND) type flash memory is known. Summary of the Invention

[0005] One embodiment of the present invention provides a non-volatile semiconductor memory device that suppresses malfunctions of the memory string during programming operations.

[0006] One embodiment of a non-volatile semiconductor memory device includes: a first bit line extending along a second direction intersecting a first direction; a second bit line disposed parallel to the first bit line on the opposite side of the first bit line in the first direction and extending along the second direction; a first source line disposed in a third direction intersecting the first and second directions and extending along the third direction; a second source line disposed parallel to the first source line on the opposite side of the first source line in the first direction and extending along the third direction; and a first semiconductor layer extending along the first... A first semiconductor layer extends in the first direction; a second semiconductor layer is disposed parallel to the first semiconductor layer in the second direction and extends along the first direction; a first memory string is disposed on the first side of the first semiconductor layer and includes a first selection transistor connected to the first bit line, a second selection transistor connected to the first source line, and a plurality of first memory cell transistors connected between the first selection transistor and the second selection transistor; a second memory string is disposed on the second side opposite to the first semiconductor layer and the first side of the first semiconductor layer, and includes... The first memory string includes a third selection transistor connected to the first bit line, a fourth selection transistor connected to the first source line, and a plurality of second memory cell transistors connected between the third and fourth selection transistors; a third memory string, disposed on the first side of the second semiconductor layer and facing the first memory string, includes a fifth selection transistor connected to the second bit line, a sixth selection transistor connected to the second source line, and a plurality of third memory cell transistors connected between the fifth and sixth selection transistors; the fourth... A memory string is disposed on the second side of the second semiconductor layer opposite to the first side, and includes a seventh select transistor connected to the second bit line, an eighth select transistor connected to the second source line, and a plurality of fourth memory cell transistors connected between the seventh select transistor and the eighth select transistor; a first select gate line electrically connected to the gate electrode of the first select transistor and the gate electrode of the sixth select transistor; and a second select gate line electrically connected to the gate electrode of the second select transistor and the gate electrode of the fifth select transistor. Attached Figure Description

[0007] Figure 1 This is a block diagram illustrating the configuration of a memory system including a non-volatile semiconductor memory device according to one embodiment.

[0008] Figure 2 This is a circuit diagram illustrating the circuit configuration of a memory cell array included in a non-volatile semiconductor memory device according to one embodiment.

[0009] Figure 3This is a diagram illustrating the configuration of a memory cell array in a non-volatile semiconductor memory device according to one embodiment.

[0010] Figure 4 This is a planar layout of the select gate line, bit line, source line, select transistor, and memory cell transistor of a non-volatile semiconductor memory device according to one embodiment.

[0011] Figure 5 This is a planar layout of the select gate line, bit line, source line, select transistor, and memory cell transistor of a non-volatile semiconductor memory device according to one embodiment.

[0012] Figure 6 yes Figure 4 The cross-sectional view of the non-volatile semiconductor memory device shown is a section cut off along line A1-A2.

[0013] Figure 7 It means Figure 4 The diagram shows the configuration of the gate line, bit line, and source line of a non-volatile semiconductor memory device.

[0014] Figure 8 This is a timing diagram illustrating the write operation in a semiconductor memory device according to one embodiment.

[0015] Figure 9 This is a circuit diagram illustrating an example of the circuit configuration of a sense amplifier assembly included in a non-volatile semiconductor memory device according to one embodiment.

[0016] Figure 10 This is a threshold distribution diagram illustrating an example of the threshold distribution of a memory cell transistor in one embodiment.

[0017] Figure 11 This diagram illustrates the operation of a sense amplifier module included in a non-volatile semiconductor memory device according to one embodiment.

[0018] Figure 12 This diagram illustrates the operation of a sense amplifier module included in a non-volatile semiconductor memory device according to one embodiment.

[0019] Figure 13 This diagram illustrates the operation of a sense amplifier module included in a non-volatile semiconductor memory device according to one embodiment.

[0020] Figure 14 This is a diagram illustrating an example of the verification operation of a non-volatile semiconductor memory device according to one embodiment.

[0021] Figure 15 This is a diagram illustrating an example of the programming operation of a non-volatile semiconductor memory device according to one embodiment.

[0022] Figure 16 This is a diagram illustrating an example of the programming operation of a non-volatile semiconductor memory device according to one embodiment. Detailed Implementation

[0023] Hereinafter, embodiments will be described with reference to the accompanying drawings. Furthermore, in the following description, constituent elements having the same or similar functions and configurations will be marked with common reference symbols. When multiple constituent elements having common reference symbols are distinguished, a suffix (e.g., uppercase or lowercase letters) will be added to the common reference symbol for differentiation.

[0024] In the following description, one embodiment of the non-volatile semiconductor memory device is, for example, a three-dimensional NAND flash memory. More specifically, it is a three-dimensional NAND flash memory in which the memory string and bit lines extend in the horizontal direction and the source lines extend in the vertical direction.

[0025] <First Embodiment>

[0026] <1. Example of composition>

[0027] <1-1. The Structure of a Memory System>

[0028] Figure 1 This is a block diagram illustrating an example of the configuration of a memory system 3 including a non-volatile semiconductor memory device 1 according to one embodiment. The configuration of the memory system 3 including the non-volatile semiconductor memory device 1 according to one embodiment is not limited to... Figure 1 The structure shown.

[0029] like Figure 1 As shown, the memory system 3 includes a non-volatile semiconductor memory device 1 and an external controller 2. The memory system 3 may be, for example, a memory card such as an SSD (solid-state drive) or an SDTM (Secure Digital Touch Memory) card. The memory system 3 may also include a host device (not shown). The external controller 2 controls the write, read, and erase operations of the non-volatile semiconductor memory device 1.

[0030] <1-2. Structure of Non-Volatile Semiconductor Memory Devices>

[0031] like Figure 1As shown, the non-volatile semiconductor memory device 1 includes an input / output circuit 10, a logic control circuit 11, a status register 12, an address register 13, an instruction register 14, a sequencer 15, a ready / busy circuit 16, a voltage generation circuit 17, a memory cell array 18, a row decoder 19, a sense amplifier module 20, a data register 21, and a column decoder 22.

[0032] Input / output circuit 10 controls the input (receive) and output (send) of signal DQ to external controller 2. Signal DQ includes, for example, data DAT, address ADD, and instruction CMD. More specifically, input / output circuit 10 sends the data DAT received from external controller 2 to data register 21, the address ADD received from external controller 2 to address register 13, and the instruction CMD received from external controller 2 to instruction register 14. Additionally, input / output circuit 10 sends status information STS received from status register 12, data DAT received from data register 21, and address ADD received from address register 13 to external controller 2.

[0033] The logic control circuit 11 receives various control signals from the external controller 2. The logic control circuit 11 controls the input / output circuit 10 and the sequencer 15 according to the received control signals.

[0034] Status register 12 temporarily stores status information STS for write, read and erase actions, and notifies external controller 2 whether each action has been completed normally.

[0035] Address register 13 temporarily stores the received address ADD. Address register 13 transmits the row address RADD to row decoder 19 and the column address CADD to column decoder 22.

[0036] The instruction register 14 temporarily stores the received instruction CMD and transmits it to the sequencer 15.

[0037] The sequencer 15 controls the overall operation of the non-volatile semiconductor memory device 1. More specifically, the sequencer 15 performs write operations, read operations, and erase operations based on received instructions (CMDs), such as the control status register 12, the ready / busy circuit 16, the voltage generation circuit 17, the row decoder 19, the sense amplifier module 20, the data register 21, and the column decoder 22. In one embodiment, the sequencer 15 is sometimes referred to as a "controller".

[0038] The ready / busy circuit 16 sends the ready / busy signal RBn to the external controller 2 according to the operating status of the sequencer 15.

[0039] The voltage generation circuit 17 generates the voltages required for write, read, and erase operations under the control of the sequencer 15, and supplies the generated voltages to components such as the memory cell array 18, the line decoder 19, and the sense amplifier module 20. The line decoder 19 and the sense amplifier module 20 apply the voltages supplied by the voltage generation circuit 17 to the memory cell transistors within the memory cell array 18.

[0040] The memory cell array 18 includes multiple blocks BLK (BLK0 to BLK3, ...) containing multiple non-volatile memory cell transistors (hereinafter also referred to as "memory cells") corresponding to rows and columns. Each block BLK contains multiple string components SU (SU0, SU1, SU2, ...). Here, the number of blocks BLK in the memory cell array 18 and the number of string components SU in each block BLK are arbitrary. Details about the memory cell array 18 will be described below.

[0041] The row decoder 19 decodes the row address RADD. Based on the decoding result, the row decoder 19 applies the required voltage to the memory cell array 18.

[0042] During a read operation, the sensing amplifier module 20 senses the data (threshold voltage) read from the memory cell array 18 and sends the sensed data to the data register 21. Conversely, during a write operation, the sensing amplifier module 20 sends the written data to the memory cell array 18.

[0043] Data register 21 has multiple latch circuits. The latch circuits temporarily store data being written or read.

[0044] The column decoder 22 decodes the column address CADD during write, read, and erase operations, and selects the latch circuit in the data register 21 based on the decoding result.

[0045] <2. Composition of Memory Cell Array>

[0046] Figure 2 This is a circuit diagram representing an example of a memory cell array 18. Figure 3 This is a diagram illustrating an example of the configuration of the memory cell array 18. Figure 2 and Figure 3 The configuration of the memory cell array 18 shown is an example, and the configuration of the memory cell array 18 in one embodiment is not limited to this. Figure 2 and Figure 3 The structure shown is sometimes omitted. Figure 1 Description of identical or similar structures.

[0047] As described above, the storage cell array 18 ( Figure 1 ) contains multiple blocks BLK ( Figure 1Each BLK block contains multiple string components SU ( Figure 1 Each string component SU comprises multiple memory strings MSI or multiple memory strings MSO arranged along the Z direction. In other words, each string component SU in this embodiment is defined along the Z direction. The memory strings MSI and MSO corresponding to a certain position in the Z direction constitute a memory group MG (memory string pair).

[0048] like Figure 2 As shown, a memory bank MG comprises two memory strings MSI and MSO. The two memory strings MSI and MSO each have select transistors ST1, ST2, MT0-MT3, ST3, and ST4 connected in series. The memory strings MSI and MSO are positioned opposite each other. Here, the select transistors ST1, ST2, MT0-MT3, ST3, and ST4 in the memory string MSI can also be positioned opposite each other in the X direction (first direction) from their corresponding positions in the memory string MSO. Figure 4 The selection transistors ST1, ST2, MT0-MT3, ST3, and ST4 in the memory string MSI are offset from those in the memory string MSO. This configuration is called a misaligned configuration.

[0049] In one embodiment of the non-volatile semiconductor memory device 1, two selection transistors (selection transistor ST1 and selection transistor ST2) are provided on the bit line BL side. Additionally, two selection transistors (selection transistor ST3 and selection transistor ST4) are provided on the source line CELSRC side. The configuration of the selection transistors in this embodiment of the non-volatile semiconductor memory device 1 is not limited to... Figure 2 and Figure 3 The configuration is shown. For example, the selection transistor disposed on the bit line BL side can be selection transistor ST1 or selection transistor ST2, and the selection transistor disposed on the source line CELSRC side can be selection transistor ST3 or selection transistor ST4. In a non-volatile semiconductor memory device 1 according to one embodiment, the area of ​​the memory cell array 18 can be reduced by reducing the number of selection transistors.

[0050] In the memory cell array 18 of a non-volatile semiconductor memory device 1 according to one embodiment, such as Figure 2 As shown, two memory strings, MSI and MSO, within the same memory bank MG are connected to the same bit line BL and the same source line CELSRC. Bit line BL is along the Y direction (the second direction, Figure 3 (Extends). In one embodiment, the X direction (first direction) intersects the Y direction (second direction), and the Z direction (third direction) intersects both the X and Y directions.

[0051] Furthermore, the even-numbered bit line BL (even) and the odd-numbered bit line BL (odd) are set opposite each other. For example, the even-numbered bit line BL (even) and the odd-numbered bit line BL (odd) are set in the X direction (first direction, Figure 3 They are opposite each other (facing each other).

[0052] like Figure 2 As shown, similarly to bit line BL, the source line CELSRC connected to the even-numbered bit line BL (even) via MG and the source line CELSRC connected to the odd-numbered bit line BL (odd) via MG are configured to be opposite each other (facing each other). For example, the source line CELSRC corresponding to the even-numbered bit line BL (even) and the source line CELSRC corresponding to the odd-numbered bit line BL (odd) are configured to be in the X direction (first direction, Figure 3 They are opposite each other (facing each other).

[0053] In addition, the source line CELSRC corresponding to the even bit line BL(even) is set on the odd bit line BL(odd) side in the X direction, and the source line CELSRC corresponding to the odd bit line BL(odd) is set on the even bit line BL(even) side in the X direction.

[0054] In one embodiment of the non-volatile semiconductor memory device 1, the memory group MG electrically connected to the even-numbered bit lines BL (even) is called memory group MGe, and the memory group MG electrically connected to the odd-numbered bit lines BL (odd) is called memory group MGo. Furthermore, the memory strings MS contained in memory group MGe are called memory strings MSIe and MSOe, and the memory strings MS contained in memory group MGo are called memory strings MSIo and MSOo.

[0055] Memory group MGe and memory group MGo are configured adjacent to each other. Furthermore, memory group MGe and memory group MGo are configured, for example, in the Y direction (second direction). Figure 3The even-numbered bit line BL(even) and the odd-numbered bit line BL(odd) are roughly symmetrical or symmetrical. Here, as described above, the even-numbered bit line BL(even) and the odd-numbered bit line BL(odd) are arranged opposite each other in the X direction. The source line CELSRC corresponding to the even-numbered bit line BL(even) is arranged on the side of the odd-numbered bit line BL(odd) in the X direction, and the source line CELSRC corresponding to the odd-numbered bit line BL(even) is arranged on the side of the even-numbered bit line BL(even) in the X direction. In addition, in memory group MGe, memory group MGo adjacent to the left of memory group MGe, and memory group MGo adjacent to the right of memory group MGe, the memory string MSI belonging to memory group MGe and memory group MGo adjacent to the left of memory group MGe belong to the same string component SU, and the memory string MSO belonging to memory group MGe and memory group MGo adjacent to the right of memory group MGe belong to the same string component SU. For example, the memory string MSIe belonging to memory group MGe and the memory string MSIo belonging to memory group MGo which is adjacent to memory group MGe on the left constitute one string component SU, and the memory string MSOo belonging to memory group MGo which is adjacent to memory group MGe on the right constitutes another string component SU with the memory string MSOe belonging to memory group MGe.

[0056] As a result, the transistors sequentially connected from the even-numbered bit line BL (even) to the source line CELSCR in memory bank MGe are symmetrical to the transistors sequentially connected from the source line CELSCR to the odd-numbered bit line BL (odd) in memory bank MGo. That is, the select transistors ST1, ST2, MT0-MT3, ST3, and ST4 in the memory string MSIe within memory bank MGe are symmetrical to the select transistors ST4, ST3, MT3-MT0, ST2, and ST1 in the memory string MSIo within memory bank MGo. Furthermore, the select transistors ST1, ST2, MT0-MT3, ST3, and ST4 in the memory string MSOe within memory bank MGe are symmetrical to the select transistors ST4, ST3, MT3-MT0, ST2, and ST1 in the memory string MSOo within memory bank MGo.

[0057] In one embodiment of the non-volatile semiconductor memory device 1, memory groups MGe and MGo are alternately and repeatedly configured.

[0058] Regarding a non-volatile semiconductor memory device 1 according to one embodiment, an example comprising two memory groups, MGe and MGo, will be described primarily. Memory group MGe is sometimes referred to as the "first semiconductor layer," the memory string MSIe disposed in memory group MGe is sometimes referred to as the "first memory string," the memory cell transistors MT0 to MT3 contained in the first memory string are sometimes referred to as "first memory cell transistors," and the side where the first memory string is disposed is sometimes referred to as the "first side." Memory string MSOe disposed in memory group MGe is sometimes referred to as the "second memory string," the memory cell transistors MT0 to MT3 contained in the second memory string are sometimes referred to as "second memory cell transistors," and the side where the second memory string is disposed is sometimes referred to as the "second side." Similar to memory group MGe, memory group MG0 is sometimes referred to as the "second semiconductor layer," memory string MSIo disposed in memory group MG0 is sometimes referred to as the "third memory string," memory cell transistors MT0 to MT3 contained in the third memory string are sometimes referred to as the "third memory cell transistors," and the side where the third memory string is disposed is sometimes referred to as the "first side." Similarly, memory string MSOo disposed in memory group MG0 is sometimes referred to as the "fourth memory string," memory cell transistors MT0 to MT3 contained in the fourth memory string are sometimes referred to as the "fourth memory cell transistors," and the side where the fourth memory string is disposed is sometimes referred to as the "second side." Furthermore, the second side is the opposite side of the first side relative to memory group MG.

[0059] The selection transistors ST1 and ST2 of the memory string MSIe in memory group MGe and the selection transistors ST3 and ST4 of the memory string MSIo in memory group MGo are connected to the common selection gate line SG4. The selection transistors ST3 and ST4 of the memory string MSIe in memory group MGe and the selection transistors ST1 and ST2 of the memory string MSIo in memory group MGo are connected to the common selection gate line SG5. The selection transistors ST4 and ST3 of the memory string MSOo in memory group MGo are connected to the selection gate line SG6. The selection transistors ST1 and ST2 of the memory string MSOo in memory group MGo are connected to the selection gate line SG7. The selection transistors ST1 and ST2 of the memory string MSOe in memory group MGe are connected to the selection gate line SG2. The selection transistors ST4 and ST3 of the memory string MSOe in memory group MGe are connected to the selection gate line SG3.

[0060] Each select gate line SG is electrically connected to a select gate decoder (SGDEC). Although not illustrated, the select gate decoder receives signals from, for example, the sequencer 15 or the voltage generation circuit 17 and is supplied with voltage. The select gate decoder uses the received signals and the supplied voltage to transmit signals to the select gate lines SG. Figure 2 As shown, for example, select gate decoder 190A is electrically connected to select gate line SG0 and sends a signal to select gate line SG0. Similarly, select gate decoders 190B, 190C, 190D, 190E, 190F, 190G, 190H, 190I, and 190J are electrically connected to select gate lines SG1, SG3, SG2, SG4, SG5, SG6, SG7, SG8, ​​and SG9, respectively, and send signals to each signal line.

[0061] The memory cell transistor MT0 of the memory string MSIe in memory group MGe and the memory cell transistor MT3 of the memory string MSIo in memory group MGo are connected to the common word line WLIo3e0. The memory cell transistor MT1 of the memory string MSIe in memory group MGe and the memory cell transistor MT2 of the memory string MSIo in memory group MGo are connected to the common word line WLIo2e1. The memory cell transistor MT2 of the memory string MSIe in memory group MGe and the memory cell transistor MT1 of the memory string MSIo in memory group MGo are connected to the common word line WLIo1e2. The memory cell transistor MT3 of the memory string MSIe in memory group MGe and the memory cell transistor MT0 of the memory string MSIo in memory group MGo are connected to the common word line WLIo0e3.

[0062] The memory cell transistor MT0 of memory string MSOe in memory group MGe and the memory cell transistor MT3 of memory string MSOo in memory group MGo are connected to the common word line WLOo3e0. The memory cell transistor MT1 of memory string MSOe in memory group MGe and the memory cell transistor MT2 of memory string MSOo in memory group MGo are connected to the common word line WLOo2e1. The memory cell transistor MT2 of memory string MSOe in memory group MGe and the memory cell transistor MT1 of memory string MSOo in memory group MGo are connected to the common word line WLOo1e2. The memory cell transistor MT3 of memory string MSOe in memory group MGe and the memory cell transistor MT0 of memory string MSOo in memory group MGo are connected to the common word line WLOo0e3.

[0063] The common word lines WLIo0e3, WLIo1e2, WLIo2e1, and WLIo3e0 connected to the memory cell transistors MT0-MT3 (first memory cell transistors) in the memory string MSIe (first memory string) of memory group MGe and the memory cell transistors MT0-MT3 (third memory cell transistors) in the memory string MSIo (third memory string) of memory group MGo are sometimes referred to as "first word lines (first WL)". The word lines WLOo0e3, WLOo1e2, WLOo2e1, and WLOo3e0 connected to the memory cell transistors MT0-MT3 (second memory cell transistors) in the memory string MSOe (second memory string) of memory group MGe and the memory cell transistors MT0-MT3 (fourth memory cell transistors) in the memory string MSOo (fourth memory string) of memory group MGo are sometimes referred to as "second word lines (second WL)".

[0064] As described above, the storage cell array 18 ( Figure 1 ) contains multiple blocks BLK ( Figure 1 Each BLK block contains multiple string components SU ( Figure 1 ).exist Figure 3 The image shows the semiconductor layer ( Figure 4 , Figure 5 For each memory group MG corresponding to a semiconductor layer 31 (memory group MG), the semiconductor layer is stacked along the Z direction to form memory strings MSI and MSO connected to each bit line BL (BL0, BL1, ..., BL2n, BL2n+1). Hereinafter, the configuration of the memory strings MSI and MSO corresponding to any semiconductor layer 31 (memory group MG) will be mainly described. Furthermore, in one embodiment, the "semiconductor layer" is sometimes referred to as a "channel layer".

[0065] like Figure 3 As shown, the memory cell array 18 includes multiple memory groups MG. More specifically, the semiconductor layers 31 stacked along the Z direction (memory strings MSI and memory strings MSO) are respectively contained within multiple memory groups MG separated in the Y direction. As described above, using... Figure 2 As explained, each memory group MG contains two memory strings MSI and MSO. Hereinafter, without specifying the memory strings MSI and MSO, the memory string will be referred to as memory string MS.

[0066] Memory string MSIe, for example, includes two select transistors ST1Ie and ST2Ie disposed on the select gate line SG side, four memory cell transistors MT3Ie to MT0Ie, and two select transistors ST3Ie and ST4Ie disposed on the source line CELSRC side. Memory string MSOe, for example, includes two select transistors ST1Oe and ST2Oe disposed on the select gate line SG side, four memory cell transistors MT0Oe to MT3Oe, and two select transistors ST3Oe and ST4Oe disposed on the source line CELSRC side. Memory string MSIo, for example, includes two select transistors ST1Io and ST2Io disposed on the select gate line SG side, four memory cell transistors MT3Io to MT0Io, and two select transistors ST3Io and ST4Io disposed on the source line CELSRC side. The memory string MSOo includes, for example, two select transistors ST1Oo and ST2Oo disposed on the select gate line SG side, four memory cell transistors MT0Oo to MT3Oo, and two select transistors ST3Oo and ST4Oo disposed on the source line CELSRC side. Hereinafter, without limiting the memory cell transistors MT3Ie to MT0Ie, MT0Oe to MT3Oe, MT3Io to MT0Io, and MT0Oo to MT3Oo, they will be referred to as memory cell transistors MT.

[0067] The memory cell transistor MT has a control gate and a charge storage layer, which non-volatilely stores data (threshold voltage). Furthermore, the memory cell transistor MT can be a MONOS (metal-oxide-nitride-oxide-silicon) type with an insulating layer for the charge storage layer, or an FG (floating gate) type with a conductive layer for the charge storage layer. In one embodiment shown below, the FG type will be described as an example. Additionally, the number of memory cell transistors MT included in each memory string MS can be, for example, 8, 16, 32, 48, 64, 96, or 128, and the number is not limited.

[0068] The current paths of the select transistors ST1Ie, ST2Ie, MT0Ie~MT3Ie, ST3Ie, and ST4Ie in the memory string MSIe are connected in series. The current paths of the select transistors ST1Oe, ST2Oe, MT0Oe~MT3Oe, ST3Oe, and ST4Oe in the memory string MSOe are also connected in series.

[0069] The current paths of the selection transistors ST1Io, ST2Io, MT0Io~MT3Io, ST3Io, and ST4Io in the memory string MSIo are connected in series. The current paths of the selection transistors ST1Oo, ST2Oo, MT0Oo~MT3Oo, ST3Oo, and ST4Oo in the memory string MSIoo are also connected in series.

[0070] The gates of the memory cell transistors MT of multiple memory groups MG arranged along the Z direction are connected via word line pillars WLP (word line contact plugs, conductive layer 33). Figure 4 , Figure 5 They are all connected to a single word line WL. More specifically, for example, the gates (gate electrodes) of multiple memory cell transistors MT0Io and MT3Ie of multiple memory groups MG arranged along the Z direction are all connected to word line WLIo0e3. Similarly, the gates (gate electrodes) of the multiple memory cell transistors MT1Io and MT2Ie of the multiple memory groups MG arranged along the Z direction are commonly connected to word line WLIo1e2; the gates (gate electrodes) of the multiple memory cell transistors MT2Io and MT1Ie of the multiple memory groups MG arranged along the Z direction are commonly connected to word line WLIo2e1; the gates (gate electrodes) of the multiple memory cell transistors MT3Io and MT0Ie of the multiple memory cells MG arranged along the Z direction are commonly connected to word line WLIo3e0; and the gates (gate electrodes) of the multiple memory cell transistors MT0Oo of the multiple memory groups MG arranged along the Z direction are also commonly connected to word line WLIo2e1. The gates (gate electrodes) of the memory cell transistors MT1Oo and MT2Oe of the multiple memory groups MG arranged along the Z direction are commonly connected to the word line WLOo0e3. The gates (gate electrodes) of the memory cell transistors MT2Oo and MT1Oe of the multiple memory groups MG arranged along the Z direction are commonly connected to the word line WLOo1e2. The gates (gate electrodes) of the memory cell transistors MT2Oo and MT1Oe of the multiple memory groups MG arranged along the Z direction are commonly connected to the word line WLOo2e1. The gates (gate electrodes) of the memory cell transistors MT3Oo and MT0Oe of the multiple memory groups MG arranged along the Z direction are commonly connected to the word line WLOo3e0.

[0071] like Figure 3As shown, the drains of the selection transistors ST1 of multiple memory groups MG arranged along the Z direction are commonly connected to the bit lines BL corresponding to the multiple memory groups MG via bit line contacts CBL. For example, the drains of the selection transistors ST1Ie and ST1Oe of the nth memory group MGe are connected to the bit line BL2n, and the drains of the selection transistors ST1Io and ST1Oo of the nth memory group MGo are connected to the bit line BL2n+1.

[0072] The source of the selection transistor ST4 of the multiple memory groups MG arranged along the Z direction is connected to the source line post SLP (source line contact plug, conductive layer 45). Figure 4 , Figure 5 The sources of the selection transistors ST4Ie and ST4Oe for the memory group MGe included in the nth semiconductor layer 31 are commonly connected to the source line CELSRC on the bit line BL2n+1 side. Similarly, the sources of the selection transistors ST4Io and ST4Oo for the memory group MGo included in the nth semiconductor layer 31 are commonly connected to the source line CELSRC on the bit line BL2n side.

[0073] Additionally, the gate electrodes of the multiple memory groups MG arranged along the Z direction, namely the selection transistors ST1 and ST2, and the selection transistors ST3 and ST4, are connected via the selection gate post SGP (selection gate line contact plug, conductive layer 37). Figure 4 , Figure 5They are all connected to different select gate lines SG. For example, the gate electrodes of the select transistors ST1Oe and ST2Oe of memory group MGe, which are respectively included in the multiple wiring layers 31 arranged along the Z direction, are all connected to select gate line SG2. The gate electrodes of the select transistors ST4Oe and ST3Oe of memory group MGo, which are respectively included in the multiple wiring layers 31 arranged along the Z direction, are all connected to select gate line SG3. The gate electrodes of the select transistors ST1Ie and ST1Oe of memory group MGe, and the gate electrodes of the select transistors ST4Io and ST3Io of memory group MGe, which are respectively included in the multiple wiring layers 31 arranged along the Z direction, are all connected to select gate line SG4. The gate electrodes of the select transistors ST4Ie and ST3Ie of memory group MGe, and the gate electrodes of the select transistors ST1Io and ST2Io of memory group MGo, which are respectively included in the multiple wiring layers 31 arranged along the Z direction, are all connected to select gate line SG5. The gate electrodes of the selection transistors ST1Oo and ST2Oo of the memory group MGo, which are respectively included in the multiple wiring layers 31 arranged along the Z direction, are commonly connected to the selection gate line SG7. The gate electrodes of the selection transistors ST4Oo and ST3Oo of the memory group MGo, which are respectively included in the multiple wiring layers 31 arranged along the Z direction, are commonly connected to the selection gate line SG6.

[0074] In one embodiment of the non-volatile semiconductor memory device 1, Figure 3 The multiple memory groups MG shown, arranged along the Z direction, are also arranged along the X and Y directions. For example, a non-volatile semiconductor memory device 1 of one embodiment will... Figure 3 The multiple memory groups MG arranged along the Z direction shown are configured as a single memory ridge, while... Figure 7 As shown, it includes a first memory configuration MR (first MR) and a second memory configuration MR (second MR) arranged adjacent to the first memory configuration MR1 along the X direction, details of which will be described below.

[0075] like Figures 1-3As shown, in one embodiment of the non-volatile semiconductor memory device 1, bit line BL0 (first bit line) is arranged to extend along the Y direction (second direction) intersecting the X direction (first direction). Bit line BL1 (second bit line) extends along the Y direction (second direction) and is arranged parallel to bit line BL0 on the opposite side of bit line BL0 in the X direction. Source line CELSRC (first source line) and source line CELSRC (second source line) arranged on the bit line BL0 side are arranged to extend along the Z direction (third direction) intersecting the X and Y directions. Source line CELSRC (second source line) is arranged parallel to source line CELSRC (first source line) and is arranged on the opposite side of source line CELSRC (first source line) in the X direction. The memory group MGe (first semiconductor layer) is disposed extending along the X direction, and the memory group MGo (second semiconductor layer) is disposed at a position after the memory group MGe is translated in the second direction, extending along the X direction. The memory string MSIe (first memory string) contained in the memory group MGe is disposed on the first side of the memory group MGe, and includes a selection transistor ST1Ie (first selection transistor) electrically connected to the bit line BL0, a selection transistor ST4Ie (second selection transistor) electrically connected to the source line CELSRC disposed on the bit line BL1 side, and memory cell transistors MT0Ie to MT3Ie electrically connected between the selection transistor ST1Ie and the selection transistor ST4Ie. The memory string MSOe (second memory string) contained in memory group MGe is located on the second side of memory group MGe, and includes a selection transistor ST1Oe (third selection transistor) electrically connected to bit line BL0, a selection transistor ST4Oe (fourth selection transistor) electrically connected to the source line CELSRC located on bit line BL1, and memory cell transistors MT0Oe to MT3Oe electrically connected between selection transistors ST1Oe and ST4Oe. The memory string MSIo (third memory string) contained in memory group MGo is located on the first side of memory group MGo, and includes a selection transistor ST1Io (fifth selection transistor) electrically connected to bit line BL1, a selection transistor ST4Io (sixth selection transistor) electrically connected to the source line CELSRC located on bit line BL0, and memory cell transistors MT0Io to MT3Io electrically connected between selection transistors ST1Io and ST4Io.The memory string MSOo (4th memory string) is located on the 2nd side of the memory group MGo, and includes a selection transistor ST1Oo (7th selection transistor) electrically connected to the bit line BL0, a selection transistor ST4Oo (8th selection transistor) electrically connected to the source line CELSRC located on the bit line BL0, and memory cell transistors MT0Oo to MT3Oo electrically connected between the selection transistors ST1Oo and ST4Oo. The gate electrodes of the selection transistors ST1Ie and ST4Io are electrically connected to the selection gate line SG4 (1st selection gate line), and the gate electrodes of the selection transistors ST4Ie and ST1Io are electrically connected to the selection gate line SG5 (2nd selection gate line).

[0076] <3. Planar layout of memory cell region, select gate region, source region, and stepped contact region>

[0077] Figure 4 This is an example of a top view showing the memory cell region MTA, the select gate region SGEA, the source region CELEA, and the stepped contact region SCDEA corresponding to the even bit line BL (even) of the memory cell array 18. Figure 5 This is an example of a top view showing the memory cell region MTA, the select gate region SGOA, the source region CELOA, and the stepped contact region SCDOA corresponding to the odd bit line BL(odd) of the memory cell array 18. Figure 4 From Figure 3 An example of the layout diagram from bit line BL0 to memory cell MT1. Figure 5 From Figure 3 An example of the layout diagram from bit line BL1 to memory cell MT3. Furthermore, Figure 4 and Figure 5 The configuration of the memory cell array 18 shown is an example, and the configuration of the memory cell array 18 is not limited to... Figure 4 and Figure 5 The structure shown is sometimes omitted. Figures 1-3 Description of identical or similar structures.

[0078] like Figure 4 and Figure 5 As shown, a memory trench MTR is disposed between two semiconductor layers 31 arranged along the Y direction. An insulating layer (not shown) is embedded in the memory trench MTR.

[0079] In the memory cell region MTA, an insulating layer 32 is provided on the side of the semiconductor layer 31. The insulating layer 32 functions as an etch stop layer when forming the insulating layer 36 (tunnel insulating film) and the charge accumulation layer 35 described below.

[0080] In the memory cell region MTA, multiple word line pillars (WLPs) and multiple select gate pillars (SGPs) are provided in a manner that separates the memory trench MTR. Each word line pillar (WLP) and select gate pillar (SGP) includes a conductive layer 33 extending along the Z-direction and an insulating layer 34 in contact with the side of the conductive layer 33. The conductive layer 33 functions as a contact plug (CWL). The insulating layer 34 functions as a barrier insulating film for the memory cell transistor (MT).

[0081] In the Y direction, a charge storage layer 35 and an insulating layer 36 are disposed between the word line pillar WLP and the select gate pillar SGP and the semiconductor layer 31, separating the insulating layer 32. The insulating layer 36 functions as a tunnel insulating film. More specifically, in the XY plane, one side of the charge storage layer 35 along the X direction contacts the insulating layer 34 of the word line pillar WLP and the select gate pillar SGP, while the other sides (the other side along the X direction and the two sides along the Y direction) contact the insulating layer 36. Furthermore, a portion of the side of the insulating layer 36 contacts the semiconductor layer 31 and the insulating layer 32.

[0082] Therefore, between the conductive layer 33 and the semiconductor layer 31, an insulating layer 34, a charge storage layer 35, and an insulating layer 36 are sequentially formed from the conductive layer 33 toward the semiconductor layer 31. The region containing a portion of the semiconductor layer 31, a portion of the conductive layer 33, a portion of the insulating layer 34, the charge storage layer 35, and the insulating layer 36 (also described as the intersection region of the semiconductor layer 31 and the word line post WLP or the semiconductor layer 31 and the select gate post SGP) functions as a memory cell transistor MT or a select transistor ST.

[0083] like Figure 4 As shown, in a semiconductor layer 31 connected to a conductive layer 39 that functions as an even bit line BL (even), the semiconductor layer 31 is disposed with... Figure 4 The intersection area of ​​the word line pillars WLP on the lower side of the paper serves as the memory cell transistors MT1 to MT3 of the memory string MSIe. The semiconductor layer 31 and the transistors MT1 to MT3 are located on the lower side of the paper. Figure 4 The cross region of the select gate pillar SGP on the lower side of the paper functions as the select transistors ST4 and ST3 for the memory string MSIe. The semiconductor layer 31 and the... Figure 4 The intersection area of ​​the word line pillars WLP on the upper side of the paper serves as the memory cell transistors MT1 to MT3 of the memory string MSOe. The semiconductor layer 31 and the transistors MT1 to MT3 are located on the upper side of the paper. Figure 4 The cross region of the select gate pillar SGP on the upper side of the paper functions as the select transistors ST4 and ST3 for the memory string MSOe. Similarly, in ( Figure 4 In another semiconductor layer 31 connected to the source line CELSRC (in the middle), semiconductor layer 31 is disposed with... Figure 4 The intersection area of ​​the word line pillars WLP on the lower side of the paper functions as the memory cell transistors MT0 to MT2 of the memory string MSOo. The semiconductor layer 31 and the... Figure 4 The cross region of the select gate pillar SGP on the lower side of the paper functions as the select transistors ST1 and ST2 of the memory string MSOo. The semiconductor layer 31 and the... Figure 4 The intersection area of ​​the word line pillars WLP on the upper side of the paper serves as the memory cell transistors MT0 to MT2 of the memory string MSIo. The semiconductor layer 31 and the... Figure 4 The cross region of the select gate pillar SGP on the upper side of the paper serves as the select transistors ST1 and ST2 for the memory string MSIo.

[0084] like Figure 5 As shown, in ( Figure 5 In a semiconductor layer 31 connected to the source line CELSRC, the semiconductor layer 31 is disposed in... Figure 5 The intersection area of ​​the word line pillars WLP on the lower side of the paper serves as the memory cell transistors MT1 to MT3 of the memory string MSIe. The semiconductor layer 31 and the transistors MT1 to MT3 are located on the lower side of the paper. Figure 5 The cross region of the select gate pillar SGP on the lower side of the paper functions as the select transistors ST1 and ST2 for the memory string MSIe. The semiconductor layer 31 and the... Figure 5 The intersection area of ​​the word line pillars WLP on the upper side of the paper serves as the memory cell transistors MT0 to MT3 of the memory string MSOe. The semiconductor layer 31 and the... Figure 5 The intersection region of the select gate pillar SGP on the upper side of the paper functions as the select transistors ST4 and ST3 for the memory string MSOe. Similarly, in another semiconductor layer 31 connected to the conductive layer 47 which functions as the odd bit line BL (odd), the semiconductor layer 31 is disposed with... Figure 5 The intersection area of ​​the word line pillars WLP on the lower side of the paper functions as the memory cell transistors MT0 to MT3 of the memory string MSOo. The semiconductor layer 31 and the... Figure 5 The cross region of the select gate pillar SGP on the lower side of the paper functions as the select transistors ST1 and ST2 of the memory string MSOo. The semiconductor layer 31 and the... Figure 5 The intersection area of ​​the word line pillars WLP on the upper side of the paper serves as the memory cell transistors MT1 to MT3 of the memory string MSIo. The semiconductor layer 31 and the transistors MT1 to MT3 are located on the upper side of the paper. Figure 5 The cross region of the select gate pillar SGP on the upper side of the paper serves as the select transistors ST1 and ST2 for the memory string MSIo.

[0085] exist Figure 4The source line region CELEA shown is Figure 5 In the source line region CELOA shown, the semiconductor layer 31 is surrounded by an insulating layer 32, and a conductive layer 45 is disposed therethrough the semiconductor layer 31. The conductive layer 45 is the source line post SLP. The conductive layer 45 functions as a source line contact plug and is electrically connected to the source line CELSRC. Figure 4 In the example shown, the semiconductor layer 31 has a circular shape in the connection region with the conductive layer 45. Furthermore, the shape of the semiconductor layer 31 in the connection region with the conductive layer 45 is arbitrary. For example, the shape of the connection region can also be polygonal. The connection region only needs to have a shape that ensures sufficient margin in the XY plane to prevent the source post SLP holes through the semiconductor layer 31 from not being exposed due to manufacturing deviations, etc., when processing the holes.

[0086] like Figure 4 As shown, in the stepped contact area SCDEA, a conductive layer 40 and an insulating layer 44 are provided, penetrating the first portion of the conductive layer 39. The conductive layer 40 functions as a contact plug CBL. The insulating layer 44 functions as a dummy post HR. The conductive layer 40 is electrically connected to any one of the first portions of the conductive layers 39 stacked along the Z direction. An insulating layer 40i is formed between the non-electrically connected conductive layers 39 and the conductive layer 40. The insulating layer 40i includes insulating layers 41, 42, and 43. The insulating layer 41 is provided in contact with the side surface (hereinafter also referred to as the "outer surface") of the conductive layer 40. The insulating layer 42 is provided in contact with a portion of the outer surface of the insulating layer 41. The insulating layer 43 is provided in contact with the outer surface of the insulating layer 42.

[0087] like Figure 5 As shown, in the stepped contact area SCDOA, a conductive layer 49 penetrating the first portion of the conductive layer 47 and an insulating layer 44 are provided. The conductive layer 49 functions as a contact plug CBL. The insulating layer 44 and... Figure 4 Similarly, it functions as a dummy pillar HR. The conductive layer 49 is electrically connected to any one of the first portions of the conductive layers 47 stacked along the Z direction. Insulating layers 43, 42, and 41 are provided between the unconnected conductive layers 47 and 49. The insulating layer 41 is provided in contact with the side surface (hereinafter also referred to as the "outer surface") of the conductive layer 49. The insulating layer 42 is provided in contact with a portion of the outer surface of the insulating layer 41. The insulating layer 43 is provided in contact with the outer surface of the insulating layer 42.

[0088] Conductive layers 39 and 47 use conductive materials. These conductive materials can be, for example, metallic materials or semiconductors such as Si with added impurities. Semiconductors such as Si with added impurities can be polycrystalline silicon with added phosphorus (P). Conductive layers 40 and 49 also use conductive materials. These conductive materials can also be, for example, metallic materials, and more specifically, W and TiN can be used.

[0089] <4. End face structure of the cut section in the stepped joint area>

[0090] Figure 6 yes Figure 4 An example of a cross-sectional view along A1-A2 of the stepped contact region SCDEA region of the memory cell array 18 shown. Figure 6 The cut-off end face structure shown is one example; the cut-off end face structure of the memory cell array 18 of a non-volatile semiconductor memory device according to one embodiment is not limited to this. Figure 6 The example shown. Sometimes the symbol is omitted. Figures 1-5 Description of identical or similar structures.

[0091] Figure 6 The diagram shows a stepped configuration for the conductive layer 39, which functions as the even-numbered bit line BL. For example... Figure 6 As shown, an insulating layer 51 is formed on a semiconductor substrate 50. The insulating layer 51 is made of, for example, silicon oxide (SiO2). The insulating layer 51 contains transistors (not shown) and multiple wiring layers (not shown) formed on the semiconductor substrate 50. A memory cell array 18 is formed on the insulating layer 51.

[0092] A plurality of conductive layers 60 extending in the X direction are formed near the upper surface of the insulating layer 51. The conductive layers 60 function, for example, as wiring connecting the bit line BL to each wiring. The conductive layers 60 are made of, for example, a metallic material or a semiconductor with added impurities.

[0093] An insulating layer 52 is provided on the insulating layer 51. The insulating layer 52 functions as an etch stop layer when machining memory trenches (MT) and holes for various contact plugs. The insulating layer 52 can be any insulating material that provides a sufficient etch selectivity relative to the insulating layer 53 provided above it. For example, silicon nitride (SiN), metal oxides, or aluminum oxide (Al2O3) can be used for the insulating layer 52.

[0094] An insulating layer 53 is disposed on the insulating layer 52. For example, the insulating layer 53 is made of SiO2. On the insulating layer 53, for example, nine conductive layers 39 are deposited between the insulating layers 53. That is, on the insulating layer 52, for example, nine insulating layers 53 and nine conductive layers 39 are alternately deposited. The conductive layers 39 and the semiconductor layer 31 ( Figure 4 , Figure 5 ) are formed in the same layer. That is, on the insulating layer 53, insulating layers 53 are interposed between each other and for example, nine semiconductor layers 31 are stacked. Figure 4 , Figure 5 Furthermore, the number of semiconductor layer 31 and conductive layer 39 stacked is arbitrary.

[0095] An insulating layer 54 is formed on the uppermost conductive layer 39. The insulating layer 54 may be, for example, SiO2.

[0096] Multiple holes HL1 are provided, penetrating the insulating layer 54 and reaching any one of the stacked conductive layers 39 on their bottom surface. Each conductive layer 39 has one or more holes HL1. The number of holes HL1 is greater than or equal to the number of conductive layers 39. Figure 6 The diagram shows holes HL1, HL1, HL1, HL1, HL1, HL1, and ...

[0097] An insulating layer 43 is provided on a portion of the side surface and bottom surface of the hole HL1. The insulating layer 43 is, for example, made of SiN. In addition, an insulating layer 42 is provided inside the hole HL1, with its side surface in contact with the insulating layer 43. The insulating layer 42 is, for example, made of SiO2.

[0098] A through-hole HL1 is provided with a hole HL2 whose bottom surface reaches the conductive layer 60. An insulating layer 41 is provided on a portion of the side surface of the hole HL2. A conductive layer 40 is provided inside the hole HL2. Here, the conductive layer 40 is a layer that connects multiple layers, and therefore functions as a HU (wiring) layer. In one embodiment, the conductive layer 40 functions as a contact plug CBL for the bit line BL.

[0099] Near the bottom surface of hole HL1, a portion of insulating layer 43 and insulating layer 41 in the same layer are removed. A connecting portion 57 protruding laterally is provided in conductive layer 40. The bottom surface of connecting portion 57 is connected to conductive layer 39. That is, the bottom surface of conductive layer 40 is electrically connected to conductive layer 60, and is electrically connected to conductive layer 39 (bit line BL) of any layer via the protruding connecting portion 57. For example, the height of the upper surface of connecting portion 57 is lower than the bottom surface of the conductive layer 39 above it.

[0100] The conductive layer 40 is connected to the conductive layer 511 and to each bit line BL via the conductive plug 521. In this way, each bit line BL is connected to the contact plug CBL. Figure 4Only the connection between bit line BL0 and conductive layer 39 is shown, but similarly to bit line BL0, other bit lines BL2, BL4, and BL6 are also connected to conductive layer 39 via their respective conductive layers and conductive plugs. For example... Figure 6 As shown, for example, the conductive layer 39, which is the fourth layer from the top, is electrically connected to the bit line BL6 via the conductive layer 40, conductive layer 511, and conductive plug 521, which function as contact plugs CBL. Similarly, the conductive layer 39, which is the fourth layer from the top, is electrically connected to the bit line BL4, the conductive layer 39, which is the sixth layer from the top, is electrically connected to the bit line BL2, and the conductive layer 39, which is the seventh layer from the top, is electrically connected to the bit line BL0. Furthermore, Figure 6 The diagram shows holes HL1, HL1, HL1, HL1, HL1, HL1, and ...

[0101] <5. Structure of the memory cell region, select gate region, source region, and stepped contact region>

[0102] Figure 7 It means Figure 4 and Figure 5 The diagram shows the configuration of the select gate line, bit line, and source line of the non-volatile semiconductor memory device 1. Figure 7 The configuration shown is an example; the configuration of the memory cell array 18 of a non-volatile semiconductor memory device in one embodiment is not limited to... Figure 7 The example shown. Sometimes the symbol is omitted. Figures 1-6 Description of identical or similar structures.

[0103] like Figure 7 As shown, the first memory configuration MR (first MR) and the second memory configuration MR (second MR) include the source region CELEA on the even bit line BL (even), the select gate region SGEA on the even bit line BL (even), the memory cell region MTA of the memory cell array 18, the select gate region SGOA on the odd bit line BL (odd), and the source region CELOA on the odd bit line BL (odd).

[0104] The first memory configuration MR (1st MR) and the second memory configuration MR (2nd MR) are arranged symmetrically, for example, with respect to the stepped contact area SCDOA corresponding to the odd bit line BL (odd). Alternatively, the first memory configuration MR (1st MR) and the second memory configuration MR (2nd MR) are arranged symmetrically, for example, with respect to the stepped contact area SCDEA corresponding to the even bit line BL (even). In the memory cell array 18 of one embodiment, the configuration of symmetrically arranging the first memory configuration MR (1st MR) and the second memory configuration MR (2nd MR) is repeatedly arranged in the X and Y directions.

[0105] In the first memory configuration MR (1st MR), in the source region CELEA, for example, the source line CELSRC is electrically connected to memory groups MG01 and MG05 via the source line post SLP. In the select gate regions SGEA and SGOA, the select gate line SG (not shown) is electrically connected to the gate electrode of each select transistor ST via the select gate line post SGP. In the memory cell region MTA, for example, the word line WLIo0e3 is electrically connected to the gate electrode of memory cell transistor MT0Io and memory cell transistor MT3Ie via the word line post WLP, and the word line WLOo3e0 is electrically connected to the gate electrode of memory cell transistor MT0Oe and memory cell transistor MT3Oo via the word line post WLP.

[0106] For example, in the stepped contact region SCDEA corresponding to the even bit line BL, the bit line BLPE formed by the conductive layer 39 is connected to the conductive layer 39 (e.g., via the contact plug CBL4) via the contact plug CBL4. Figure 6 All memory groups MGe (including memory groups MGe0 and MGe4) are electrically connected to the fourth conductive layer 39 (counting from top to bottom). Additionally, the bit line BLPE formed by another conductive layer 39 is connected via a contact plug CBL0 to a component disposed in that other conductive layer 39 (e.g., ...). Figure 6 All memory groups MGe are electrically connected in the conductive layer 39 (the 6th layer from top to bottom).

[0107] For example, in the stepped contact region SCDOA corresponding to the odd bit line BL(odd), the bit line BLPE formed by another conductive layer 39 is connected via a contact plug CBL1 to the contact provided in the other conductive layer 39 (e.g., Figure 6 The conductive layer 39 shown is the third layer from the top, and all memory groups MGo (including memory group MGo1 and memory group MGo5) are electrically connected. Furthermore, bit lines BLPE formed by these different conductive layers 39 are connected via contact plugs CBL5 to the conductive layers 39 (e.g., ...). Figure 6All memory groups MGo are electrically connected in the conductive layer 39 (the fifth layer from top to bottom).

[0108] <6. Summary of Write Operation>

[0109] right Figure 2 and Figure 3 The operation method of the shown memory cell array 18 will be explained. When the number of semiconductor layers 31 is set to k, the region separated by the memory trench MTR (each memory region MR) contains k memory groups MG stacked along the Z direction.

[0110] The following explanation uses the case where the number of semiconductor layers 31, k, is 12. In this case, a 12-layer memory group MG (memory string pair) is stacked. Furthermore, in the 12-layer memory group MG (memory string pair), the memory strings MS arranged at the same position in the Y direction are electrically connected to the same select gate line SG. For example, in the 12-layer memory group MG (memory string pair), the memory strings MSIe and MSIo arranged at the same position in the Y direction are electrically connected to the same select gate line SG. In other words, in the 12-layer memory group MG (memory string pair), the memory strings MSIe and MSIo arranged at the same position in the Y direction belong to the same string component SU.

[0111] For example, in one embodiment of a non-volatile semiconductor memory device 1, a program loop is repeatedly executed during a write operation. The program loop includes an EVEN programming operation, an ODD programming operation, and a verification operation. The EVEN programming operation and the ODD programming operation are performed by injecting electrons into the charge accumulation layer of a selected memory cell transistor MT, thereby raising the threshold voltage of the selected memory cell transistor MT. Alternatively, the EVEN programming operation and the ODD programming operation are performed by preventing electron injection into the charge accumulation layer, thereby maintaining the threshold voltage of the selected memory cell transistor MT. The verification operation is performed by reading using a verification voltage following the EVEN programming operation and the ODD programming operation to confirm whether the threshold voltage of the selected memory cell transistor MT has reached a target level. The selected memory cell transistor MT is prevented from being written to after the threshold voltage reaches the target level.

[0112] In one embodiment of the non-volatile semiconductor memory device 1, the threshold voltage of the selected memory cell transistor MT is raised to a target level by repeatedly executing a program loop that includes the EVEN programming operation, the ODD programming operation, and the verification operation as described above.

[0113] Electrons accumulated in the charge accumulation layer sometimes accumulate in an unstable state. Therefore, it is possible that, from the point when the programming operation ends, electrons accumulated in the charge accumulation layer of the memory cell transistor MT may be released from the charge accumulation layer over time. If electrons are released from the charge accumulation layer, the threshold voltage of the memory cell transistor MT decreases. Therefore, in the read operation performed after the write operation is completed, a read voltage lower than the verification voltage is used to address this potential decrease in the threshold voltage of the memory cell transistor over time. Furthermore, the read operation may also include a verification operation. In another embodiment, each operation of the non-volatile semiconductor memory device 1 is included in a separate operation method. More specifically, the write operation of the non-volatile semiconductor memory device 1 is included in a write operation method, the read operation of the non-volatile semiconductor memory device 1 is included in a read operation method, the erase operation of the non-volatile semiconductor memory device 1 is included in an erase operation method, and the verification operation of the non-volatile semiconductor memory device 1 is included in a verification operation method.

[0114] <6-1. An example of a write operation>

[0115] Figure 8 This is a timing diagram illustrating the write operation in the memory cell array 18 of a non-volatile semiconductor memory device 1 according to one embodiment. Figure 8 The timing diagram shown is an example of a timing diagram representing the time variation of the voltage applied to various circuit components. Figure 8 It is merely a schematic timing diagram used to represent the voltage applied to various circuit components. Figure 8 The timing diagram shown may not accurately depict, for example, the voltage supplied to the word line or the potential changes of the select gate line SG. Figure 8 The timing diagram shown is an example; the timing diagram of one embodiment of a non-volatile semiconductor memory device is not limited to... Figure 8 The example shown. Sometimes the symbol is omitted. Figures 1 to 7 Description of identical or similar structures.

[0116] In the following description, we focus on memory strings MSIe and MSIo within each semiconductor layer 31. Semiconductor layer 31 is called a channel layer, and the potential of the channel layer is called the channel potential. The word line WL connected to the selected memory cell transistor MT in each memory string MS is called the select word line SEL-WL, and the word line connected to the other memory cell transistor MTs is called the non-select word line USEL-WL. Figure 8In this configuration, the select word line SEL-WL is represented by SEL in WL, and the non-select word line USEL-WL is represented by USEL in WL. The select word line SEL-WL and the non-select word line USEL-WL are supplied commonly (common across all semiconductor layers). In one embodiment, the bit line BL electrically connected to the memory string containing the memory cell transistor MT (the memory cell transistor MT that has been written with data (threshold voltage)) in the memory string of each semiconductor layer 31 is called a bit line programming (Program) BL. The bit line BL electrically connected to the memory string containing memory cell transistor MT other than the memory cell transistor MT that has been written with data (threshold voltage) is called a bit line inhibit BL.

[0117] like Figure 8 As shown, in one embodiment of the write operation, firstly, the sequencer 15 performs an EVEN programming operation on the memory cell transistor MT contained in the memory string MSIe. That is, in the EVEN programming operation, the threshold voltage of the memory cell transistor MT contained in the memory string MS, which is electrically connected to the even bit line BL (even), is raised.

[0118] like Figure 8 As shown, during the EVEN programming operation, the sequencer 15 sends a signal that turns the selection transistors ST1Ie and ST2Ie in the memory string MSIe, and the selection transistors ST4Io and ST3Io in the memory string MSIo, on or off according to their voltage relationship with the bit line BL (e.g., a signal sent to the even-numbered selection gate line SG4). For example, the signal sent to the even-numbered selection gate line SG4 includes the voltage VSG. That is, during the EVEN programming operation, the sequencer 15 supplies the voltage VSG to the even-numbered selection gate line SG (even) connected to the gates of the selection transistors ST1Ie and ST2Ie in the memory string MSIe, and the selection transistors ST4Io and ST3Io in the memory string MSIo. At this time, the sequencer 15 sends a signal that turns the selection transistors ST3Ie and ST4Ie in the memory string MSIe, and the selection transistors ST1Io and ST2Io in the memory string MSIo off regardless of the voltage of the bit line BL (e.g., a signal sent to the odd-numbered selection gate line SG5). In addition, different voltages (Voltage VPGM, Voltage VPASS) are supplied to the select word line SEL-WL and the non-select word line USEL-WL.

[0119] Furthermore, the sequencer 15 supplies low (L) voltages to the bit line programming BL (even), bit line programming BL (odd), bit line disable BL (odd), and control signal STB, and high (H) voltages to the source line CELSRC and bit line disable BL (even). As a result, in the memory string MSIe connected to the bit line programming BL (even), the select transistors ST3 and ST4 on the BL side are turned on, applying the low level of bit line programming BL (even) to the channel of the memory string MSIe.

[0120] On the other hand, in the memory string MSIe connected to the bit line disable BL (even number), the select transistors ST1 and ST2 on the BL side are disconnected, and the channel of the memory string MSIe becomes floating. As a result, the channel of the memory string MSIe is boosted.

[0121] As a result, in the EVEN programming operation, the threshold voltage of the memory cell transistor MT, which is electrically connected to the even bit line BL (even) and selected by the select word line SEL-WL, can be increased in the non-volatile semiconductor memory device 1 of one embodiment.

[0122] like Figure 8 As shown, in the ODD programming operation following the EVEN programming operation, the sequencer 15 performs the ODD programming operation for the memory cell transistors MT contained in the memory string MSIo. The sequencer 15 sends a signal (e.g., a signal sent to the odd-numbered select gate line SG5) that turns the select transistors ST1Io and ST2Io contained in the memory string MSIo, and the select transistors ST4Ie and ST3Ie contained in the memory string MSIe, on or off according to their relationship with the voltage of the bit line BL. That is, in the ODD programming operation, the sequencer 15 supplies a voltage VSG to the odd-numbered select gate line SG(odd) connected to the gates of the select transistors ST1Ie and ST2Ie contained in the memory string MSIo, and the select transistors ST4Io and ST3Io contained in the memory string MSIe. At this time, sequencer 15 sends a signal that turns off the selection transistors ST3Io and ST4Io in memory string MSIo, and the selection transistors ST1Ie and ST2Ie in memory string MSIe, regardless of the voltage of bit line BL (for example, a signal sent to even-numbered select gate line SG4). Additionally, different voltages (voltage VPGM, voltage VPASS) are supplied to the select word line SEL-WL and the non-select word line USEL-WL.

[0123] Furthermore, the sequencer 15 supplies low (L) voltages to the bit line programming BL (odd), bit line programming BL (even), bit line disable BL (even), and control signal STB, and high (H) voltages to the source line CELSRC and bit line disable BL (odd). As a result, in the memory string MSIo connected to the bit line programming BL (odd), the select transistors ST1 and ST2 on the BL side are turned on, applying the low level of bit line programming BL (odd) to the channel of the memory string MSIo.

[0124] On the other hand, in the memory string MSIo connected to the bit line disable BL (odd number), the select transistors ST1 and ST2 on the BL side are disconnected, and the channels of the memory string MSIo become floating. As a result, the channels of the memory string MSIo are boosted.

[0125] As a result, in the ODD programming operation, the threshold voltage of the memory cell transistor MT, which is electrically connected to the odd bit line BL (odd) and selected by the select word line SEL-WL, can be increased in one embodiment of the non-volatile semiconductor memory device 1.

[0126] Next, as Figure 8 As shown, in one embodiment of the write operation, in order to verify the result of the programming operation, the sequencer 15 performs a verification operation (a first verification operation) for all memory cell transistors MT. In the first verification operation of the non-volatile semiconductor memory device 1 in one embodiment, the sequencer 15 sends a signal to turn on the selection transistors ST1Io, ST2Io, ST3Io, and ST4Io contained in the memory string MSIo, and the selection transistors ST1Ie, ST2Ie, ST3Ie, and ST4Ie contained in the memory string MSIe. The turn-on signal includes, for example, the voltage VSG_READ.

[0127] Furthermore, the sequencer 15 supplies different voltages (VOCG and VREAD) to the select word lines SEL-WL and the non-select word lines USEL-WL. Moreover, the sequencer 15 supplies high (H) voltages to the bit line programming lines BL (even) and BL (odd), and low (L) voltages to the source line CELSRC, bit line disable BL (even), and bit line disable BL (odd).

[0128] Furthermore, the sequencer 15 supplies a low (L) voltage to the channels of the memory cell transistors MT in the memory string MSIe and the memory cell transistors MT in the memory string MSIo, so that the channel potentials of the memory cell transistors MT in the memory string MSIe and the memory cell transistors MT in the memory string MSIo are low (L) levels. Then, the sequencer 15 supplies a high voltage to the control signal STB, switching it from a low level. When the control signal STB changes from a low level to a high level, the control signal STB is activated.

[0129] One embodiment of the non-volatile semiconductor memory device 1 can verify the results of the programming operation on the memory cell transistor MT during a verification operation (a single verification operation).

[0130] In one embodiment of the non-volatile semiconductor memory device 1, the period during which the EVEN programming operation is performed is sometimes referred to as the "first operation period", the period during which the ODD programming operation is performed is sometimes referred to as the "second operation period", and the period during which the verification operation is performed is sometimes referred to as the "third operation period".

[0131] Additionally, in one embodiment of the non-volatile semiconductor memory device 1, the high-level voltage is sometimes referred to as the "first voltage" or the "sixth voltage." The high-level voltage is, for example, 2.2V. The low-level voltage is sometimes referred to as the "second voltage." The low-level voltage is, for example, 0V. The voltage VSG is sometimes referred to as the "third voltage." The voltage VSG is, for example, 3V. The voltage VPGM is sometimes referred to as the "fourth voltage." The voltage VPGM is, for example, 24V. The voltage VPASS is sometimes referred to as the "fifth voltage." The voltage VPASS is, for example, 9V. The voltage VSG_READ is sometimes referred to as the "seventh voltage." The voltage supplied to the bit line programming BL is sometimes referred to as the "eighth voltage." The eighth voltage is greater than the second voltage. The voltage VCG is sometimes referred to as the "ninth voltage." The voltage VREAD is sometimes referred to as the "tenth voltage." The tenth voltage is greater than the ninth voltage. Furthermore, the voltage VCG is sometimes a negative voltage.

[0132] Here, the programming operations for a comparative example (a conventional three-dimensional NAND flash memory with the memory string extending horizontally) are explained. For example, in Figure 2 and Figure 3 In the non-volatile semiconductor memory device 1 of one embodiment shown, the bit line BL (even number) electrically connected to the memory group MGe is provided on the opposite side of the bit line BL (odd number) electrically connected to the memory group MGo in the X direction. On the other hand, in the comparative example of the three-dimensional NAND flash memory, the bit line BL (even number) electrically connected to the memory group MGe is provided on the same side of the bit line BL (odd number) electrically connected to the memory group MGo in the X direction, and the memory group MGe and the memory group MGo are connected to a common bit line BL.

[0133] In the comparative example of the three-dimensional NAND flash memory, when programming is performed on the memory cell transistor MT contained in the memory bank MGe, the selection transistor ST1 of the memory string MSIe and the selection transistor ST2 of the memory string MSOe, or the selection transistor ST2 of the memory string MSIe and the selection transistor ST1 of the memory string MSOe, are turned on. As a result, the memory bank MGo adjacent to the memory bank MGe is in a slightly selected state (half-selected state). Here, the memory bank MGo adjacent to the memory bank MGe is a memory string that is not programmed. The memory bank MGo adjacent to the memory bank MGe is connected to the common bit line BL, therefore, the memory bank MGo in the half-selected state is supplied with current based on the voltage supplied to the bit line BL. The memory bank MGo in the half-selected state cannot sufficiently cut off this current. In other words, the memory bank MGo in the half-selected state is not electrically disconnected from the bit line BL. As a result, during the programming operation of the memory cell transistor MT contained in memory group MGe, even if the channel of memory group MGo adjacent to memory group MGe is supplied with voltage, the channel of memory group MGo adjacent to memory group MGe is not sufficiently boosted. Therefore, it is possible to accidentally write to the memory cell transistor MT contained in memory group MGo adjacent to memory group MGe, which is not performing a programming operation.

[0134] On the other hand, in one embodiment of the non-volatile semiconductor memory device 1, when programming is performed on the memory cell transistor MT included in the memory string MSIe, the selection transistors ST1 and ST2 of the memory string MSIe are turned on. Therefore, the selection transistors ST3 and ST4 of the memory string MSIo, which share the selection gate line SG with the selection transistors ST1 and ST2 of the memory string MSIe and are adjacent to the memory string MSIe, are also turned on. As a result, the memory string MSIo, which is adjacent to the memory string MSIe, is also selected. As described above, in one embodiment of the non-volatile semiconductor memory device 1, the memory string MSIe and the memory string MSIo are connected to different bit lines BL (BL (even), BL (odd)). Even when the memory string MSIe is selected, the memory string MSIo is selected, but a low-level voltage can be supplied to the bit line BL (odd). As a result, the current based on the voltage supplied to the bit line BL does not flow through the memory string MSIo, which is not being programmed. Therefore, when a voltage is supplied to the channel of the memory string MSIo, the channel of the memory string MSIo is sufficiently boosted. In one embodiment of the non-volatile semiconductor memory device 1, the memory string does not become half-selected. As a result, in one embodiment of the non-volatile semiconductor memory device 1, erroneous writing to the memory cell transistors MT contained in the memory string MSIo, where no programming operation is performed, is suppressed.

[0135] <6-2. Examples during the first action>

[0136] Return to Figure 8 Continuing the explanation. Sequencer 15 ( Figure 1 Apply (supply) voltages to the select word line SEL-WL, the non-select word line USEL-WL, the source line CELSRC, the bit line programming BL (even), the bit line disable BL (even), the select gate line SG4, the channel of the memory string MSIe, the bit line programming BL (odd), the bit line disable BL (odd), the select gate line SG5, the channel of the memory string MSIo, and the control signal STB.

[0137] Specifically, the sequencer 15 controls the voltage generation circuit 17 ( Figure 1 ), Column decoder 22 ( Figure 1 ), Line decoder 19 ( Figure 1 ) and sensing amplifier module 20 ( Figure 1The voltage generation circuit 17, column decoder 22, row decoder 19 or sense amplifier module 20 apply (supply) voltage to the select word line SEL-WL, non-select word line USEL-WL, source line CELSRC, bit line programming BL (even), bit line disable BL (even), select gate line SG4, memory string MSIe channel, bit line programming BL (odd), bit line disable BL (odd), select gate line SG5, memory string MSIo channel and control signal STB.

[0138] Use sequencer 15 to execute the EVEN programming action. The execution period of the EVEN programming action is the first action period.

[0139] At the start of the first operation, sequencer 15 supplies a low (Low, L) voltage to the select word lines SEL-WL, non-select word lines USEL-WL, source line CELSRC, bit line programming BL (even), bit line disable BL (even), select gate line SG4, the channel of memory string MSIe, bit line programming BL (odd), bit line disable BL (odd), select gate line SG5, the channel of memory string MSIo, and control signal STB. The low voltage is, for example, voltage VSS.

[0140] The voltages applied to each signal line during the first operation, from time t00 to time t01, are explained. The select word line SEL-WL, the non-select word line USEL-WL, the bit line programming BL (even), the select gate line SG4, the channel of the memory cell transistor MT in the memory string MSIe, the bit line programming BL (odd), the bit line disable BL (odd), the select gate line SG5, the channel of the memory cell transistor MT in the memory string MSIo, and the control signal STB are supplied with low (Low, L) voltages. The source line CELSRC and the bit line disable BL (even) are switched from low voltage to high (High, H) voltages.

[0141] The voltages applied to each signal line during the first operation period from time t01 to time t02 are explained. The select word line SEL-WL is supplied with voltage VPASS after being switched from a low level, and then with voltage VPGM. Additionally, after being supplied with voltage VPGM, the select word line SEL-WL is supplied with voltage VPASS. The non-select word line USEL-WL is supplied with voltage VPASS after being switched from a low level. The source line CELSRC and the bit line disable BL (even) are supplied with a high level. The bit line programming BL (even), bit line programming BL (odd), bit line disable BL (odd), select gate line SG5, and control signal STB are supplied with low level voltages. The select gate line SG4 is supplied with voltage VSG after being switched from a low level. At this time, the selection transistors ST1Ie and ST2Ie in the memory string MSIe, and the selection transistors ST4Io and ST3Io in the memory string MSIo, are either ON or OFF depending on their relationship with the voltage of the bit line BL. The selection transistors ST3Ie and ST4Ie in the memory string MSIe, and the selection transistors ST1Io and ST2Io in the memory string MSIo, are OFF. A low-level voltage is supplied to the channel of the memory cell transistor MT in the memory string MSIe connected to the even-numbered bit line programming BL, making the channel potential of the memory cell transistor MT in the even-numbered bit line programming BL low. The channel potentials of the memory cell transistor MT in the memory string MSIe connected to the bit line disable (BL, even number) and the memory string MSIo rise to voltage VPASS, thus boosting the channel voltages of the memory cell transistor MT in the memory string MSIe connected to the bit line disable (BL, even number) and the memory string MSIo. In the memory string MSIe connected to the bit line programmable (BL, even number), the gate electrode of the memory cell transistor MT connected to the select word line SEL-WL is supplied with voltage VPGM. Therefore, voltage VPGM is applied between the low-level channel and the gate, causing the threshold voltage of the memory cell transistor MT in the memory string MSIe connected to the bit line programmable (BL, even number) to rise.

[0142] The voltages applied to each signal line during the first operation, from time t02 to time t03, are explained. The select word line SEL-WL is supplied with a low-level voltage after switching from voltage VPASS. The non-select word line USEL-WL is supplied with a low-level voltage after switching from voltage VPASS. The source line CELSRC and the bit line disable BL (even) are supplied with a high-level voltage. The bit line programming BL (even), bit line programming BL (odd), bit line disable BL (odd), select gate line SG5, and control signal STB are supplied with low-level voltages. The select gate line SG4 is supplied with voltage VSG. At this time, the select transistors ST1Ie and ST2Ie in the memory string MSIe, and the select transistors ST4Io and ST3Io in the memory string MSIo are either ON or OFF depending on their relationship with the voltage of the bit line BL; the select transistors ST3Ie and ST4Ie in the memory string MSIe, and the select transistors ST1Io and ST2Io in the memory string MSIo are OFF. The channel potential of the memory cell transistor MT connected to the even-numbered bit line programming BL (BL) memory string MSIe is low. The channel potential of the memory cell transistor MT connected to the even-numbered bit line disable BL (BL) memory string MSIe, and the channel potential of the memory cell transistor MT connected to the even-numbered bit line MSIo, simultaneously decrease to a low level along with the voltage of the word line WL from the voltage VPASS. The gate electrode of the memory cell transistor MT connected to the even-numbered bit line programming BL (BL) memory string MSIe is supplied with a low-level voltage, and the memory cell transistor MT connected to the even-numbered bit line programming BL (BL) memory string MSIe is in an off state. Therefore, the memory cell transistor MT connected to the even-numbered bit line programming BL (BL) memory string MSIe retains the risen threshold voltage.

[0143] The voltages applied to each signal line after time t03 during the first operation are explained. The select word line SEL-WL, the non-select word line USEL-WL, the bit line programming BL (even), the channel of the memory cell transistor MT in the memory string MSIe, the bit line programming BL (odd), the bit line disable BL (odd), the select gate line SG5, the channel of the memory cell transistor MT in the memory string MSIo, and the control signal STB are supplied with low (Low, L) voltages. The bit line disable BL (even) is switched from a high voltage to a low voltage. The select gate line SG4 is switched from a voltage VSG to a low voltage. At this time, the select transistors ST1Ie and ST2Ie in the memory string MSIe, the select transistors ST4Io and ST3Io in the memory string MSIo, the select transistors ST3Ie and ST4Ie in the memory string MSIe, and the select transistors ST1Io and ST2Io in the memory string MSIo are in the OFF state.

[0144] As explained above, the first operation period ends. During the first operation period (during the EVEN programming operation), the non-volatile semiconductor memory device 1 of one embodiment raises the threshold voltage of the memory cell transistor MT, which is electrically connected to the even bit line BL (even) and selected by the select word line SEL-WL. The memory cell transistor MT selected by the select word line SEL-WL can retain the raised threshold voltage.

[0145] <6-3. Examples during the second action>

[0146] During the second action, sequencer 15 ( Figure 1 Similar to the first operation, the control voltage generation circuit 17 ( Figure 1 ), Column decoder 22 ( Figure 1 ), Line decoder 19 ( Figure 1 ) and sensing amplifier module 20 ( Figure 1 The voltage generation circuit 17, column decoder 22, row decoder 19 or sense amplifier module 20 apply (supply) voltage to the select word line SEL-WL, non-select word line USEL-WL, source line CELSRC, bit line programming BL (even), bit line disable BL (even), select gate line SG4, memory string MSIe channel, bit line programming BL (odd), bit line disable BL (odd), select gate line SG5, memory string MSIo channel and control signal STB.

[0147] Using sequencer 15, the ODD programming action is executed after the EVEN programming action. The execution period of the ODD programming action is the second action period.

[0148] When the second operation begins after the first operation, the sequencer 15, in the same manner as in the first operation, supplies low (Low, L) voltages to the select word line SEL-WL, the non-select word line USEL-WL, the source line CELSRC, the bit line programming BL (even), the bit line disable BL (even), the select gate line SG4, the channel of the memory string MSIe, the bit line programming BL (odd), the bit line disable BL (odd), the select gate line SG5, the channel of the memory string MSIo, and the control signal STB.

[0149] The voltages applied to each signal line during the second operation, from time t10 to time t11, are explained. The select word lines SEL-WL, non-select word lines USEL-WL, bit line programming BL (even), bit line disable BL (even), select gate line SG4, the channel of the memory cell transistor MT in the memory string MSIe, bit line programming BL (odd), select gate line SG5, the channel of the memory cell transistor MT in the memory string MSIo, and the control signal STB are supplied with a low-level voltage. The source line CELSRC is supplied with a high-level voltage. The bit line disable BL (odd) is switched from a low-level voltage to a high (High, H) level voltage.

[0150] The voltages applied to each signal line during the second operation, from time t11 to time t12, are explained. The select word line SEL-WL is supplied with voltage VPASS after being switched from a low level, and then with voltage VPGM. Similarly, after being supplied with voltage VPGM, the select word line SEL-WL is supplied with voltage VPASS. The non-select word line USEL-WL is supplied with voltage VPASS after being switched from a low level. The source line CELSRC and the bit line disable BL (odd) are supplied with a high level. The bit line programming BL (even), bit line disable BL (even), select gate line SG4, bit line programming BL (odd), and control signal STB are supplied with low level voltages. The select gate line SG5 is supplied with voltage VSG after being switched from a low level. At this time, the selection transistors ST1Io and ST2Io in the memory string MSIo, and the selection transistors ST4Ie and ST3Ie in the memory string MSIe, are either ON or OFF depending on their relationship with the voltage of the bit line BL. The selection transistors ST3Io and ST4Io in the memory string MSIo, and the selection transistors ST1Ie and ST2Ie in the memory string MSIe, are OFF. A low-level voltage is supplied to the channel of the memory cell transistor MT connected to the bit line programming BL (odd number), making the channel potential of the memory cell transistor MT connected to the bit line programming BL (odd number) of the memory string MSIo low. The channel potentials of the memory cell transistor MT in the memory string MSIo connected to the bit line disable (odd number) and the memory string MSIe rise to voltage VPASS, thus boosting the voltage of the channels of the memory cell transistor MT in the memory string MSIo connected to the bit line disable (odd number) and the memory string MSIe. In the memory string MSIo connected to the bit line programmable (odd number), the gate electrode of the memory cell transistor MT connected to the select word line SEL-WL is supplied with voltage VPGM. Therefore, voltage VPGM is applied between the low-level channel and the gate, causing the threshold voltage of the memory cell transistor MT in the memory string MSIo connected to the bit line programmable (odd number) to rise.

[0151] The voltages applied to each signal line during the second operation, from time t12 to time t13, are explained. The select word line SEL-WL is supplied with a low-level voltage after switching from the VPASS voltage. The non-select word line USEL-WL is supplied with a low-level voltage after switching from the VPASS voltage. The source line CELSRC and the bit line disable BL (odd) are supplied with a high-level voltage. The bit line programming BL (even), bit line disable BL (even), select gate line SG4, bit line programming BL (odd), and control signal STB are supplied with a low-level voltage. The select gate line SG5 is supplied with the voltage VSG. At this time, the selection transistors ST1Io and ST2Io in memory string MSIo, and the selection transistors ST4Ie and ST3Ie in memory string MSIe, are either ON or OFF depending on their relationship with the voltage of bit line BL. The selection transistors ST3Io and ST4Io in memory string MSIo, and the selection transistors ST1Ie and ST2Ie in memory string MSIe, are OFF. The channel potential of the memory cell transistor MT in memory string MSIo connected to bit line programming BL (odd number) is low. The channel potential of the memory cell transistor MT in memory string MSIo connected to bit line disable BL (odd number), and the channel potential of the memory cell transistor MT in memory string MSIe, decrease simultaneously with the voltage of word line WL from voltage VPASS to a low level. When the gate electrode of the memory cell transistor MT connected to the bit-line programmed memory string MSIo (odd number) is supplied with a low-level voltage, the memory cell transistor MT connected to the bit-line programmed memory string MSIo (odd number) is in the off state. Therefore, the memory cell transistor MT connected to the bit-line programmed memory string MSIo (odd number) retains the risen threshold voltage.

[0152] The voltages applied to each signal line after time t13 during the second operation are explained. The select word line SEL-WL, the non-select word line USEL-WL, the bit line programming BL (even), the bit line disable BL (even), the select gate line SG4, the channel of the memory cell transistor MT in the memory string MSIe, the bit line programming BL (odd), the channel of the memory cell transistor MT in the memory string MSIo, and the control signal STB are supplied with low (Low, L) voltages. The bit line disable BL (odd) is switched from a high voltage to a low voltage. The select gate line SG5 is switched from a voltage VSG to a low voltage. At this time, the select transistors ST1Io and ST2Io in the memory string MSIo, the select transistors ST4Ie and ST3Ie in the memory string MSIe, the select transistors ST3Io and ST4Io in the memory string MSIo, and the select transistors ST1Ie and ST2Ie in the memory string MSIe are in the OFF state.

[0153] As explained above, the second operation period ends. During the second operation period (during the ODD programming operation), the non-volatile semiconductor memory device 1 of one embodiment raises the threshold voltage of the memory cell transistor MT, which is electrically connected to the odd bit line BL (odd) and selected by the select word line SEL-WL. The memory cell transistor MT selected by the select word line SEL-WL can retain the raised threshold voltage.

[0154] <6-4. Examples during the third action>

[0155] During the third action, sequencer 15 ( Figure 1 Similar to the second operation, the control voltage generation circuit 17 ( Figure 1 ), Column decoder 22 ( Figure 1 ), Line decoder 19 ( Figure 1 ) and sensing amplifier module 20 ( Figure 1 The voltage generation circuit 17, column decoder 22, row decoder 19 or sense amplifier module 20 apply (supply) voltage to the select word line SEL-WL, non-select word line USEL-WL, source line CELSRC, bit line programming BL (even), bit line disable BL (even), select gate line SG4, memory string MSIe channel, bit line programming BL (odd), bit line disable BL (odd), select gate line SG5, memory string MSIo channel and control signal STB.

[0156] Using sequencer 15, a verification action is performed after the ODD programming action. The period for performing one verification action is the third action period.

[0157] When the third operation begins after the second operation, the sequencer 15, in the same manner as in the second operation, supplies low (Low, L) voltages to the select word line SEL-WL, the non-select word line USEL-WL, the source line CELSRC, the bit line programming BL (even), the bit line disable BL (even), the select gate line SG4, the channel of the memory string MSIe, the bit line programming BL (odd), the bit line disable BL (odd), the select gate line SG5, the channel of the memory string MSIo, and the control signal STB.

[0158] The voltages applied to each signal line during the third operation, from time t20 to time t23, are explained. The select word line SEL-WL is switched from a low voltage to a voltage VCG. The non-select word line USEL-WL is switched from a low voltage to a voltage VREAD. The source line CELSRC, bit line disable BL (even), the channel of the memory cell transistor MT in the memory string MSIe, the bit line disable BL (odd), and the channel of the memory cell transistor MT in the memory string MSIo are supplied with low voltages. The bit line programming BL (even) and bit line programming BL (odd) are switched from low voltages to a high (High, H) voltage. The select gate line SG4 and select gate line SG5 are switched from low voltages to a voltage VSG_READ. At this time, the selection transistors ST1Ie and ST2Ie contained in the memory string MSIe, the selection transistors ST3Io and ST4Io contained in the memory string MSIo, the selection transistors ST1Io and ST2Io contained in the memory string MSIo, and the selection transistors ST4Ie and ST3Ie contained in the memory string MSIe are in the ON state.

[0159] During the third operation, from time t20 to time t21, the control signal STB is supplied with a low-level voltage. From time t21 to time t22 during the third operation, the control signal STB changes from a low-level voltage to a high-level voltage. During the third operation, from time t21 to time t22, the select word line SEL-WL is supplied with voltage VCG, and the control signal STB is activated when it changes from a low-level voltage to a high-level voltage. Here, voltage VCG is an arbitrary readout voltage. As a result, based on the arbitrary readout voltage VCG, the threshold voltage stored in the memory cell transistor MT of the memory string MS selected by the select word line SEL-WL is read out. The threshold voltage read from the memory cell transistor MT of the memory string MS selected by the select word line SEL-WL is transmitted to the latch circuits (latch circuits ADL, BDL, CDL, XDL) in the sense amplifier module 20. The sense amplifier module 20 determines whether the threshold voltage read based on the arbitrary readout voltage VCG is "0" or "1". The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store the read threshold voltage. Then, during the third operation period, from time t22 to time t23, the control signal STB changes from a high voltage to a low voltage. When the control signal STB changes from a high voltage to a low voltage, the control signal STB is deactivated.

[0160] The voltages applied to each signal line during the third operation period from time t23 to time t24, and after time t24, are explained. The select word line SEL-WL is supplied with a low-level voltage after switching from voltage VCG. The non-select word line USEL-WL is supplied with a low-level voltage after switching from voltage VREAD. The source line CELSRC, bit line disable BL (even), the channel of the memory cell transistor MT in the memory string MSIe, the bit line disable BL (odd), the channel of the memory cell transistor MT in the memory string MSIo, and the control signal STB are supplied with low (Low, L) level voltages. The bit line programming BL (even) and bit line programming BL (odd) are supplied with low-level voltages after switching from high-level voltages. The select gate line SG4 and select gate line SG5 are supplied with low-level voltages after switching from voltage VSG_READ. At this time, the selection transistors ST1Io and ST2Io contained in the memory string MSIo, the selection transistors ST4Ie and ST3Ie contained in the memory string MSIe, the selection transistors ST3Io and ST4Io contained in the memory string MSIo, and the selection transistors ST1Ie and ST2Ie contained in the memory string MSIe are in the OFF state.

[0161] As explained above, the third operation period ends. During the third operation period (the verification operation period), the non-volatile semiconductor memory device 1 of one embodiment can read the threshold voltage stored in the memory cell transistor MT of the memory string MS selected by the select word line SEL-WL, and verify the result of the programming operation.

[0162] <7. Circuit configuration of the sense amplifier assembly>

[0163] Next, an example of the circuit configuration of the sense amplifier component SAU will be described. Figure 9 This is an example of the circuit configuration of the sense amplifier component SAU. Furthermore, Figure 9 The circuit configuration of the sense amplifier component SAU shown is an example, and the circuit configuration of the sense amplifier component SAU of the non-volatile semiconductor memory device in one embodiment is not limited to... Figure 9 The example shown. Sometimes the symbol is omitted. Figures 1 to 8 Description of identical or similar structures.

[0164] The sensing amplifier module 20 includes multiple sensing amplifier components (SAUs) associated with bit lines BL1 to BLm (where m is a natural number greater than 2). Figure 9 The circuit configuration of one selected sensing amplifier component SAU is shown in the figure.

[0165] The sense amplifier component SAU can, for example, temporarily store data corresponding to the threshold voltage read to the corresponding bit line BL. Additionally, the sense amplifier component SAU can use the temporarily stored data to perform logical operations. The non-volatile semiconductor memory device 1 can use the sense amplifier module 20 (sense amplifier component SAU) to perform a readout operation according to one embodiment, as detailed below.

[0166] like Figure 9 As shown, the sense amplifier assembly SAU includes a sense amplifier section SA and latch circuits SDL, ADL, BDL, CDL, and XDL. The sense amplifier section SA and the latch circuits SDL, ADL, BDL, CDL, and XDL are connected via a bus LBUS in a manner that enables them to transmit and receive data with each other.

[0167] In a readout operation, the sensing amplifier section SA senses the data (threshold voltage) read to the corresponding bit line BL and determines whether the data corresponding to the read threshold voltage is "0" or "1". The sensing amplifier section SA includes, for example, a p-channel MOS (Metal Oxide Semiconductor) transistor 120, n-channel MOS transistors 121-128, and a capacitor 129.

[0168] One end of transistor 120 is connected to the power supply line, and its gate is connected to node INV within the latch circuit SDL. One end of transistor 121 is connected to the other end of transistor 120, and its other end is connected to node COM. A control signal BLX is input to the gate of transistor 121. One end of transistor 122 is connected to node COM, and a control signal BLC is input to its gate. Transistor 123 is a high-voltage MOS transistor; one end of transistor 123 is connected to the other end of transistor 122, and its other end is connected to the corresponding bit line BL. A control signal BLS is input to the gate of transistor 123.

[0169] One end of transistor 124 is connected to node COM, and the other end is connected to node SRC. The gate of transistor 124 is connected to node INV. One end of transistor 125 is connected to the other end of transistor 120, and the other end is connected to node SEN. A control signal HLL is input to the gate of transistor 125. One end of transistor 126 is connected to node SEN, and the other end is connected to node COM. A control signal XXL is input to the gate of transistor 126.

[0170] One end of transistor 127 is grounded, and its gate is connected to node SEN. One end of transistor 128 is connected to the other end of transistor 127, and the other end of transistor 128 is connected to bus LBUS. A control signal STB is input to the gate of transistor 128. One end of capacitor 129 is connected to node SEN, and a clock signal CLK is input to the other end of capacitor 129.

[0171] The control signals BLX, BLC, BLS, HLL, XXL, and STB described above are generated, for example, by the sequencer 15. Additionally, the internal power supply voltage of the non-volatile semiconductor memory device 1, i.e., voltage VDD, is applied to the power line connected to one end of the transistor 120, and the ground voltage of the non-volatile semiconductor memory device 1, i.e., voltage VSS, is applied to the node SRC.

[0172] The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store the read data. The latch circuit XDL, for example, is connected to the data register 21 and is used to sense the input and output of data between the amplifier component SAU and the input / output circuit 10.

[0173] The latch circuit SDL includes, for example, inverters 130 and 131, and n-channel MOS transistors 132 and 133. The input node of inverter 130 is connected to node LAT, and the output node of inverter 130 is connected to node INV. The input node of inverter 131 is connected to node INV, and the output node of inverter 131 is connected to node LAT. One end of transistor 132 is connected to node INV, and the other end of transistor 132 is connected to the bus LBUS, with a control signal STI input to its gate. One end of transistor 133 is connected to node LAT, and the other end of transistor 133 is connected to the bus LBUS, with a control signal STL input to its gate. For example, data stored at node LAT is equivalent to data stored in the latch circuit SDL, and data stored at node INV is equivalent to the inverted data stored at node LAT. The circuit configurations of latch circuits ADL, BDL, CDL, and XDL are the same as those of, for example, the latch circuit SDL, and therefore are omitted from description.

[0174] In the sensing amplifier module 20 described above, each sensing amplifier component SAU determines the time point at which the data corresponding to the threshold voltage of the bit line BL is read out based on the time point at which the control signal STB is activated. In one embodiment, "the sequencer 15 activates the control signal STB" corresponds to the sequencer 15 changing the control signal STB from the "L" level to the "H" level.

[0175] Furthermore, the configuration of the sense amplifier module 20 in one embodiment is not limited to this. For example, in the sense amplifier assembly SAU, the transistor 128 whose gate is input with the control signal STB may also include a p-channel MOS transistor. In this case, "the sequencer 15 activates the control signal STB" corresponds to the sequencer 15 changing the control signal STB from an "H" level to an "L" level.

[0176] Furthermore, the number of latching circuits in the sense amplifier assembly (SAU) can be designed to be arbitrary. In this case, the number of latching circuits is designed, for example, based on the number of bits of data stored in one memory cell transistor (MT). Alternatively, multiple bit lines (BL) can be connected to a single sense amplifier assembly (SAU) via a selector.

[0177] <8. Threshold distribution of memory cell transistors>

[0178] Next, an example of the threshold distribution of the memory cell transistor MT will be explained. Figure 10 This is a threshold distribution diagram representing an example of the threshold distribution of a memory cell transistor MT. Furthermore, Figure 10The threshold distribution of the memory cell transistor MT shown is an example, and the threshold distribution of the memory cell transistor MT in one embodiment of a non-volatile semiconductor memory device is not limited to... Figure 10 The example shown. Sometimes the symbol is omitted. Figures 1-9 Description of identical or similar structures.

[0179] One embodiment of the non-volatile semiconductor memory device 1 uses, for example, a TLC (Triple-Level Cell) method in which one memory cell transistor MT stores 3 bits of data as the writing method of the memory cell transistor MT.

[0180] Figure 10 These represent an example of the threshold distribution of the memory cell transistor MT, the allocation of 3 bits of data, the readout voltage, and the verification voltage in a TLC method. Figure 3 The vertical axis of the threshold distribution shown corresponds to the number of memory cell transistors MT, and the horizontal axis corresponds to the threshold voltage Vth of the memory cell transistor MT.

[0181] In TLC, multiple memory cell transistors MT, such as Figure 3 As shown, eight threshold distributions are formed. These eight threshold distributions (write levels) are named "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level in ascending order of threshold voltage. Three distinct 3-bit data bits are assigned to each of the "ER" level, "A" level, "B" level, "C" level, "D" level, "E" level, "F" level, and "G" level, as shown below.

[0182] “ER” level: 111 (“Lower bit / Middle bit / Higher bit”) data “A” level: 011 data “B” level: 001 data “C” level: 000 data “D” level: 010 data “E” level: 110 data “F” level: 100 data “G” level: 101 data

[0183] The verification voltage used in the write operation is set between adjacent threshold distributions. Specifically, verification voltages AV, BV, CV, DV, EV, FV, and GV are set corresponding to the "A", "B", "C", "D", "E", "F", and "G" levels, respectively.

[0184] For example, the verification voltage AV is set between the maximum threshold voltage in the "ER" level and the minimum threshold voltage in the "A" level. When the verification voltage AV is applied to the memory cell transistor MT, the memory cell transistor MT with threshold voltages contained in the "ER" level is turned on, and the memory cell transistor MT with threshold voltages contained in the threshold distribution above the "A" level is turned off.

[0185] Additionally, other verification voltages, such as BV, CV, DV, EV, FV, and GV, are set in the same way as verification voltage AV. Verification voltage BV is set between the "A" and "B" levels, verification voltage CV is set between the "B" and "C" levels, verification voltage DV is set between the "C" and "D" levels, verification voltage EV is set between the "D" and "E" levels, verification voltage FV is set between the "E" and "F" levels, and verification voltage GV is set between the "F" and "G" levels.

[0186] For example, the verification voltage AV can be set to 0.8V, the verification voltage BV to 1.6V, the verification voltage CV to 2.4V, the verification voltage DV to 3.1V, the verification voltage EV to 3.8V, the verification voltage FV to 4.6V, and the verification voltage GV to 5.6V. However, the verification voltages AV, BV, CV, DV, EV, FV, and GV are not limited to the examples shown here. The verification voltages AV, BV, CV, DV, EV, FV, and GV can also be appropriately set in stages within the range of 0V to 7.0V.

[0187] Alternatively, the readout voltage used in each readout operation can be set between adjacent threshold distributions. For example, the readout voltage AR used to determine whether the threshold voltage of the memory cell transistor MT is contained in the "ER" level or above the "A" level is set between the maximum threshold voltage in the "ER" level and the minimum threshold voltage in the "A" level.

[0188] Other readout voltages BR, CR, DR, ER, FR, and GR can be set in the same way as readout voltage AR. For example, readout voltage BR is set between the "A" and "B" levels, readout voltage CR is set between the "B" and "C" levels, readout voltage DR is set between the "C" and "D" levels, readout voltage ER is set between the "D" and "E" levels, readout voltage FR is set between the "E" and "F" levels, and readout voltage GR is set between the "F" and "G" levels.

[0189] Furthermore, the readout voltage VREAD is set to a voltage higher than the maximum threshold voltage of the highest threshold distribution (e.g., "G" level). The memory cell transistor MT, with the readout voltage VREAD applied to its gate, becomes ON regardless of the stored data (threshold voltage).

[0190] Furthermore, the verification voltages AV, BV, CV, DV, EV, FV, and GV are set, for example, to be higher than the readout voltages AR, BR, CR, DR, ER, FR, and GR, respectively. In other words, the verification voltages AV, BV, CV, DV, EV, FV, and GV are set near the lower end of the threshold distributions for "A," "B," "C," "D," "E," "F," and "G" levels, respectively.

[0191] For example, when applying the data allocation described above, during the read operation, the lower-level bit page data (lower page data) is determined based on the read results using read voltages AR and ER. The middle-level bit page data (middle page data) is determined based on the read results using read voltages BR, DR, and FR. The upper-level bit page data (upper page data) is determined based on the read results using read voltages CR and GR. In this way, the lower-level page data, middle-level page data, and upper-level page data are determined through 2, 3, and 2 read operations respectively; therefore, this data allocation is called "2-3-2 encoding".

[0192] Furthermore, the number of bits corresponding to the data (threshold voltage) stored in one memory cell transistor MT and the allocation of data for the threshold distribution of the memory cell transistor MT described above are examples only and are not limited to the examples shown here. For example, two bits or more of data can also be stored in one memory cell transistor MT. In addition, each readout voltage and readout pass voltage can be set to the same voltage value in each mode, or they can be set to different voltage values.

[0193] <9. An example of the operation of a sensing amplifier module>

[0194] Figure 11 This is a diagram illustrating an example of the verification operation of the sense amplifier module 20 included in a non-volatile semiconductor memory device 1 according to one embodiment. Figure 12 and Figure 13 This is a diagram illustrating an example of the programming operation of the sense amplifier module 20 included in a non-volatile semiconductor memory device 1 according to one embodiment. Figure 14 This is a diagram illustrating an example of the verification operation of a non-volatile semiconductor memory device 1 according to one embodiment. Figure 15 and Figure 16This diagram illustrates an example of the programming operation of a non-volatile semiconductor memory device 1 according to one embodiment. The operation example of the sense amplifier module 20 according to one embodiment is not limited to... Figures 11-16 The structure shown. In Figures 11-16 In the description, sometimes the terms "and" are omitted. Figures 1-10 Description of identical or similar structures.

[0195] like Figures 11-13 As shown, the sensing amplifier module 20 includes, for example, sensing amplifier components SAU0 to SAU7. Sensing amplifier components SAU0 to SAU7 are associated with bit lines BL0 to BL7, respectively. The circuit configuration of each sensing amplifier component SAU0 to SAU7 is similar to... Figure 9 The circuit configuration of the SAU sensing amplifier component shown is the same.

[0196] like Figure 11 As shown, during the verification operation, each sense amplifier component SAU0 to SAU7, for example, treats all memory cell transistors MT electrically connected to bit lines BL0 to BL7 as the operation target (0 in the figure). During the verification operation, each sense amplifier component SAU0 to SAU7 senses the data (threshold voltage) read from all memory cell transistors MT electrically connected to the corresponding bit line BL, and determines whether the data corresponding to the read threshold voltage is "0" or "1". The latch circuits SDL, ADL, BDL, CDL, and XDL temporarily store the data corresponding to the read threshold voltage.

[0197] For example, using Figure 14 The current paths of memory cell transistor MT1, electrically connected to bit line BL (even number), and memory cell transistor MT2, electrically connected to bit line BL (odd number), in memory string MSIo during the verification operation are explained. References are also provided as appropriate. Figure 8 The timing diagram shown.

[0198] like Figure 8 As shown, during the verification action (during the third action), from time t20 to time t23, the word line SEL-WL (word line WLIo2e1) is selected. Figure 14 The supplied voltage VCG, non-selected word lines USEL-WL (word lines WLIo0e3, WLIo1e2, WLIo3e0, WLOo0e3, WLOo1e2, WLOo2e1 and WLOo3e0) Figure 14The selected gate line SG4 and selected gate line SG5 are supplied with the voltage VSG_READ. The source line CELSRC, bit line disable BL (even), the channel of the memory cell transistor MT in memory string MSIe, bit line disable BL (odd), and the channel of the memory cell transistor MT in memory string MSIo are supplied with a low-level voltage. Bit line programming BL (even) (bit line (even)) Figure 14 Bitline programming BL(odd) (bitline(odd)) Figure 14 A high-level voltage is supplied.

[0199] As a result, the selection transistors ST1 and ST2, and ST4 and ST3 contained in the memory string MSIe, are turned on, and the current ( Figure 14 (arrow) Programming from bit line BL(even) (bit line BL(even)) ( Figure 14 The current flows to the source line CWLSRC. In the memory string MSIe electrically connected to the bit line BL (even), the data (threshold voltage) stored in the memory cell transistor MT1 connected to the select word line SEL-WL (word line WLIo2e1) is read out. Figure 14 The sensing amplifier component SAU senses data from the bit line BL (even number) connected to the bit line. Figure 14 The memory string MSIo contains a memory cell transistor MT2 that reads data (threshold voltage) and determines whether the data corresponding to the read threshold voltage is "0" or "1". Then, the latch circuits SDL, ADL, BDL, CDL and XDL temporarily store the data corresponding to the read threshold voltage.

[0200] In the same manner, the selection transistors ST3 and ST4 contained in the memory string MSIo, and the selection transistors ST1 and ST2 contained in the memory string MSIo, are turned on, and the current ( Figure 14 (arrow) Programming from bit line BL(odd) (bit line BL(odd)) Figure 14 The data (threshold voltage) stored in the memory cell transistor MT2 of the memory string MSIo, selected by the word line SEL-WL (word line WLIo2e1) and electrically connected to the bit line BL (odd number), is read out via the flow to the source line CWLSRC. Figure 14 The sensing amplifier component SAU senses from the bit line BL (odd number) connected to the bit line (). Figure 14The memory string MSIo contains a memory cell transistor MT2 that reads data (threshold voltage) and determines whether the data corresponding to the read threshold voltage is "0" or "1". Then, the latch circuits SDL, ADL, BDL, CDL and XDL temporarily store the data corresponding to the read threshold voltage.

[0201] On the other hand, in the programming operation, the even-numbered sense amplifier components SAU0, SAU2, SAU4, and SAU6 operate at different times than the odd-numbered sense amplifier components SAU1, SAU3, SAU5, and SAU7.

[0202] For example, such as Figure 12 and Figure 13 As shown, the even-numbered sense amplifier components SAU0, SAU2, SAU4, and SAU6 operate alternately with the odd-numbered sense amplifier components SAU1, SAU3, SAU5, and SAU7.

[0203] Specifically, such as Figure 12 As shown, during the EVEN programming operation (during the first operation), the memory cell transistor MT electrically connected to the even-numbered bit lines BL0, BL2, BL4, and BL6 corresponding to the even-numbered sense amplifier components SAU0, SAU2, SAU4, and SAU6 becomes the target of the operation (marked as 0 in the figure), while the memory cell transistor MT electrically connected to the odd-numbered bit lines BL1, BL3, BL5, and BL7 corresponding to the odd-numbered sense amplifier components SAU1, SAU3, SAU5, and SAU7 does not become the target of the operation (marked as × in the figure).

[0204] For example, using Figure 15 The current paths of memory cell transistor MT1, electrically connected to bit line BL (even number), and memory cell transistor MT2, electrically connected to bit line BL (odd number), within the memory string MSIe, are explained during the EVEN programming operation (during the first operation). References are also provided as appropriate. Figure 8 The timing diagram shown.

[0205] like Figure 8 As shown, during the EVEN programming action (during the first action), from time t01 to time t02, the word line SEL-WL (word line WLIo2e1) is selected. Figure 15 The supplied voltage VPGM, non-selected word lines USEL-WL (word lines WLIo0e3, WLIo1e2, WLIo3e0, WLOo0e3, WLOo1e2, WLOo2e1 and WLOo3e0) Figure 15The source line CELSRC and the bit line BL (even) are supplied with a high-level voltage. Bit line programming BL (even) (bit line (even)) Figure 15 Bitline programming BL(odd) (bitline(odd)) Figure 15 When the bit line is disabled (BL, odd number), the select gate line SG5 is supplied with a low-level voltage. The select gate line SG4 is supplied with the voltage VSG.

[0206] As a result, selection transistors ST1 and ST2 in the memory string MSIe become ON, while selection transistors ST4 and ST3 become OFF, and the current ( Figure 15 (arrow) Programming from bit line BL(even) (bit line BL(even)) ( Figure 15 The current flows to the vicinity of the select transistor ST3 contained in the memory string MSIe. On the other hand, the select transistors ST3 and ST4 contained in the memory string MSIo are in the ON state, and the select transistors ST1 and ST2 contained in the memory string MSIo are in the OFF state, so the current flows almost no from the bit line programming BL(odd) (bit line BL(odd)) Figure 15 )) Flow. Connected to bitline programming BL(even) (bitline BL(even)) ( Figure 15 The channel potentials of the memory cell transistors MT3, MT2, and MT0 in the MSIe memory string become low. This is achieved when the bit line programming BL (even number) is electrically connected to the bit line BL (even number). Figure 15 In the memory string MSIe, the gate electrode of the memory cell transistor MT1, which is connected to the select word line SEL-WL (word line WLIo2e1), is supplied with voltage VPGM. As a result, voltage VPGM is supplied to the gate electrode of the memory cell transistor MT1 connected to the bit line programming BL (even number) (bit line BL (even number)). Figure 15 A voltage VPGM is applied between the memory cell transistor MT1 contained in the memory string MSIe and the low-level channel to program the required data (threshold voltage) in the memory cell transistor MT1 of the memory string MSIe.

[0207] Use sequencer 15 ( Figure 1 Following the EVEN programming action (during the first action), the verification action (during the third action) is executed. At this time, the electrical connection is... Figure 12 The memory cell transistors MT of the even-numbered bit lines BL0, BL2, BL4, and BL6 corresponding to the even-numbered sense amplifier components SAU0, SAU2, SAU4, and SAU6 shown become the objects of the verification operation.

[0208] In addition, such as Figure 13As shown, in the ODD programming operation (during the second operation) following the EVEN programming operation (during the first operation), the memory cell transistor MT electrically connected to the odd-numbered bit lines BL1, BL3, BL5, BL7 corresponding to the odd-numbered sense amplifier components SAU1, SAU3, SAU5, SAU7 becomes the target of operation (0 in the figure), while the memory cell transistor MT electrically connected to the even-numbered bit lines BL0, BL2, BL4, BL6 corresponding to the even-numbered sense amplifier components SAU0, SAU2, SAU4, SAU6 does not become the target of operation (× in the figure).

[0209] For example, using Figure 16 The current paths of memory cell transistor MT2, electrically connected to bit line BL (odd number), and memory cell transistor MT1, electrically connected to bit line BL (even number), within the memory string MSIo, are explained during the ODD programming operation (during the second operation). References are also provided as appropriate. Figure 8 The timing diagram shown.

[0210] like Figure 8 As shown, during the ODD programming action (during the second action), from time t21 to time t22, word line SEL-WL (word line WLIo2e1) is selected. Figure 16 The supplied voltage VPGM, non-selected word lines USEL-WL (word lines WLIo0e3, WLIo1e2, WLIo3e0, WLOo0e3, WLOo1e2, WLOo2e1 and WLOo3e0) Figure 16 The source line CELSRC and the bit line BL (odd) are supplied with a high-level voltage. The bit line is programmed with BL (odd) (bit line (odd)) Figure 16 Bitline programming BL(even) (bitline(even)) Figure 16 When the bit line is disabled (BL, even number), the select gate line SG4 is supplied with a low-level voltage. The select gate line SG5 is supplied with the voltage VSG.

[0211] As a result, selection transistors ST1 and ST2 in the memory string MSIo become ON, while selection transistors ST4 and ST3 become OFF, and the current ( Figure 16 (arrow) Programming from bit line BL(odd) (bit line BL(odd)) Figure 16The current flows to the vicinity of the selection transistor ST0 contained in the memory string MSIo. On the other hand, the selection transistors ST3 and ST4 contained in the memory string MSIe are in the ON state, and the selection transistors ST1 and ST2 contained in the memory string MSIe are in the OFF state, with almost no current flowing from the bit line programming BL (even number) (bit line BL (even number)) Figure 16 )) Flow. Connected to bitline programming BL(odd) (bitline BL(odd) () Figure 16 The channel potentials of the memory cell transistors MT3, MT1, and MT0 in the MSIo memory string become low. This is achieved when the bit line programming BL (odd number) is electrically connected to the bit line BL (odd number). Figure 16 In the memory string MSIo, the gate electrode of the memory cell transistor MT2, which is connected to the select word line SEL-WL (word line WLIo2e1), is supplied with voltage VPGM. As a result, the voltage VPGM is supplied to the gate electrode of the memory cell transistor MT2, which is electrically connected to the bit line programming BL(odd) (bit line BL(odd)). Figure 16 A voltage VPGM is applied between the memory cell transistor MT2 in the memory string MSIo and the low-level channel to program the required data (threshold voltage) in the memory cell transistor MT2 of the memory string MSIo.

[0212] Use sequencer 15 ( Figure 1 Following the ODD programming action (during the second action), the verification action (during the third action) is performed. At this time, the electrical connection is... Figure 13 The memory cell transistors MT corresponding to the odd-numbered bit lines BL1, BL3, BL5, and BL7 of the odd-numbered sense amplifier components SAU1, SAU3, SAU5, and SAU7 shown become the objects of the verification operation.

[0213] Alternatively, during the first operation, the odd-numbered sensing amplifier component becomes the target of the operation, while the even-numbered sensing amplifier component does not become the target of the operation. During the second operation, the even-numbered sensing amplifier component becomes the target of the operation (0 in the figure), while the odd-numbered sensing amplifier component does not become the target of the operation.

[0214] <Other Implementation Methods>

[0215] In the described embodiment, describing the application or supply of a voltage includes both controlling the application or supply of the voltage and actually applying or supplying the voltage. Furthermore, applying or supplying a voltage may also include, for example, applying or supplying a voltage of 0V.

[0216] In this specification, "connection" means electrical connection, except where other components are in between.

[0217] The foregoing has described several embodiments of the non-volatile semiconductor memory device of this disclosure. However, these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in many other ways, or can be implemented by appropriate combinations without departing from the spirit of the invention, and various omissions, substitutions, and modifications can be made. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

[0218] [Explanation of Symbols]

[0219] 1: Non-volatile semiconductor memory devices

[0220] 2: External controller

[0221] 3: Memory System

[0222] 10: Input / output circuit

[0223] 11: Logic control circuit

[0224] 12: Status Register

[0225] 13: Address Register

[0226] 14: Instruction Register

[0227] 15: Sequencer

[0228] 16: Busy Circuit

[0229] 17: Voltage generation circuit

[0230] 18: Memory Cell Array

[0231] 19: Line Decoder

[0232] 20: Sensing Amplifier Module

[0233] 21: Data Register

[0234] 22: Column Decoder

[0235] 31: Semiconductor layer

[0236] 32: Insulation layer

[0237] 33: Conductive layer

[0238] 34: Insulation layer

[0239] 35: Charge Accumulation Layer

[0240] 36: Insulation layer

[0241] 37: Conductive layer

[0242] 39: Conductive layer

[0243] 40: Conductive layer

[0244] 40i: Insulation layer

[0245] 41: Insulation layer

[0246] 42: Insulation layer

[0247] 43: Insulation layer

[0248] 44: Insulation layer

[0249] 45: Conductive layer

[0250] 47: Conductive layer

[0251] 49: Conductive layer

[0252] 50: Semiconductor substrate

[0253] 51: Insulation layer

[0254] 52: Insulation layer

[0255] 53: Insulation layer

[0256] 54: Insulation layer

[0257] 57: Connecting part

[0258] 60: Conductive layer

[0259] 120: Transistor

[0260] 121: Transistor

[0261] 122: Transistor

[0262] 123: Transistor

[0263] 124: Transistor

[0264] 125: Transistor

[0265] 126: Transistor

[0266] 127: Transistor

[0267] 128: Transistor

[0268] 129: Capacitor

[0269] 130: Inverter

[0270] 131: Inverter

[0271] 132: Transistor

[0272] 133: Transistor

[0273] 190A: Select Gate Decoder

[0274] 190B: Select Gate Decoder

[0275] 190C: Select Gate Decoder

[0276] 190D: Select Gate Decoder

[0277] 190E: Select Gate Decoder

[0278] 190F: Select Gate Decoder

[0279] 190G: Select Gate Decoder

[0280] 190H: Select Gate Decoder

[0281] 190I: Select Gate Decoder

[0282] 190J: Select Gate Decoder

[0283] 511: Conductive layer

[0284] 521: Conductive plug.

Claims

1. A non-volatile semiconductor memory device, comprising: The first line extends along the second direction, which intersects the first direction; The second bit line is disposed parallel to the first bit line on the opposite side of the first bit line in the first direction and extends along the second direction; The first source line is disposed in a third direction that intersects the first direction and the second direction, and extends along the third direction; The second source line is disposed parallel to the first source line on the opposite side of the first source line in the first direction and extends along the third direction; A first semiconductor layer extends along the first direction; The second semiconductor layer is disposed parallel to the first semiconductor layer in the second direction and extends along the first direction; The first memory string is disposed on the first side of the first semiconductor layer and includes a first selection transistor connected to the first bit line, a second selection transistor connected to the first source line, and a plurality of first memory cell transistors connected between the first selection transistor and the second selection transistor. The second memory string is disposed on a second side opposite to the first semiconductor layer and the first side of the first semiconductor layer, and includes a third selection transistor connected to the first bit line, a fourth selection transistor connected to the first source line, and a plurality of second memory cell transistors connected between the third selection transistor and the fourth selection transistor; The third memory string is disposed on the first side of the second semiconductor layer and is disposed opposite to the first memory string. It includes a fifth selection transistor connected to the second bit line, a sixth selection transistor connected to the second source line, and a plurality of third memory cell transistors connected between the fifth selection transistor and the sixth selection transistor. The fourth memory string is disposed on the second side of the second semiconductor layer opposite to the first side, and includes a seventh selection transistor connected to the second bit line, an eighth selection transistor connected to the second source line, and a plurality of fourth memory cell transistors connected between the seventh selection transistor and the eighth selection transistor. The first selection gate line is electrically connected to the gate electrode of the first selection transistor and the gate electrode of the sixth selection transistor; and The second selection gate line is electrically connected to the gate electrode of the second selection transistor and the gate electrode of the fifth selection transistor; and The first bit line and the second bit line are located on opposite sides of the first semiconductor layer and the second semiconductor layer, respectively, in the first direction, and on opposite sides of the first memory string, the second memory string, the third memory string and the fourth memory string.

2. The non-volatile semiconductor memory device according to claim 1, wherein... From an overhead view, The first bit line and the first source line are arranged on the same side in the first direction. The second bit line and the second source line are disposed on the same side in the first direction, and are disposed on the opposite side of the first bit line and the first source line in the first direction.

3. The non-volatile semiconductor memory device according to claim 1, wherein... In cross-section, the layer containing a portion of the first bit line is different from the layer containing a portion of the second bit line.

4. The non-volatile semiconductor memory device according to claim 1, wherein the non-volatile semiconductor memory device comprises: The first word line is disposed in the third direction, extends along the third direction, and is commonly disposed for each of the plurality of first memory cell transistors and each of the plurality of third memory cell transistors; and The second word line is disposed in the third direction, extends along the third direction, and is commonly disposed for each of the plurality of the second memory cell transistors and each of the plurality of the fourth memory cell transistors.

5. The non-volatile semiconductor memory device according to claim 4, wherein... The non-volatile semiconductor memory device has a controller. The controller is capable of controlling the first selected gate line and the second selected gate line at different times.

6. The non-volatile semiconductor memory device according to claim 5, wherein... The controller is During the first action, After supplying a second voltage, less than the first voltage, to the first bit line and the second bit line, A third voltage, greater than the first voltage, is supplied to the first selection gate line for the first selection transistor and the sixth selection transistor, causing the first selection transistor and the sixth selection transistor to be turned on or off. A second voltage, causing the second selection transistor and the fifth selection transistor to be turned off, is supplied to the second selection gate line. A fourth voltage, greater than the third voltage, is supplied to the first word line. A fifth voltage, greater than the third voltage and less than the fourth voltage, is supplied to the second word line. During the second action following the first action, After supplying the first voltage to the second bit line, and then supplying the second voltage to the first bit line, The third voltage is supplied to the second selection gate line for the second and fifth selection transistors to turn them on or off. The second voltage is supplied to the first selection gate line to turn off the first and sixth selection transistors. The fifth voltage is supplied to the first word line and the second word line. During both the first and second actions, A sixth voltage, greater than the second voltage, is supplied to both the first source line and the second source line.

7. The non-volatile semiconductor memory device according to claim 6, wherein... During the third action following the second action, the controller... The second voltage is supplied to the first source line, the second source line, and the second bit line. A seventh voltage, different from the third voltage, is supplied to both the first selected gate line and the second selected gate line. A third voltage, which is greater than the second voltage and different from the first voltage, is supplied to the first bit line. A ninth voltage, different from the fourth and fifth voltages, is supplied to the first word line. A 10th voltage, which is different from the 4th and 5th voltages and is greater than the 9th voltage, is supplied to the 2nd word line.

8. The non-volatile semiconductor memory device according to claim 5, wherein The controller is During the first action, After supplying a first voltage to the first bit line and a second voltage lower than the first voltage to the second bit line, A third voltage is supplied to the first selection gate line for the first and sixth selection transistors to turn them on or off. A second voltage, causing the second and fifth selection transistors to turn off, is supplied to the second selection gate line. A fifth voltage, greater than the third voltage, is supplied to the first and second word lines. During the second action following the first action, After supplying the second voltage to the second bit line and the first bit line, A third voltage is supplied to the second selection gate line for the second and fifth selection transistors to turn them on or off. A second voltage, which turns off the first and sixth selection transistors, is supplied to the first selection gate line. A fourth voltage, greater than the fifth voltage, is supplied to the second word line. The fifth voltage is supplied to the first word line. During both the first and second actions, A sixth voltage, greater than the second voltage, is supplied to both the first source line and the second source line.

9. The non-volatile semiconductor memory device according to claim 8, wherein During the third action following the second action, the controller... The second voltage is supplied to the first source line, the second source line, and the first bit line. A seventh voltage, different from the third voltage, is supplied to both the first selected gate line and the second selected gate line. A second voltage, which is greater than the second voltage and different from the first voltage, is supplied to the second bit line. A ninth voltage, different from the fourth and fifth voltages, is supplied to the second word line. A 10th voltage, which is different from the 4th and 5th voltages and is greater than the 9th voltage, is supplied to the 1st word line.

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