Internal fec encoding system and method

Abstract

Embodiments of the present disclosure relate to inner FEC encoding systems and methods. The present invention relates to communication systems and methods. According to certain embodiments, FEC data streams from a plurality of FEC data channels are received. First stage interleaving and inner encoding are performed on the FEC data streams to generate inner encoded data streams. Second stage interleaving processing is performed to interleave the inner encoded data streams. There are other embodiments.

Description

[0001] Cross-reference to related applications

[0002] This application claims U.S. Patent Application No. 17 / 205,881, filed March 18, 2021, entitled “INNER FEC ENCODING SYSTEMS AND METHODS”. This invention relates to U.S. Patent Application No. 16 / 818,864, filed March 13, 2020, entitled “SYSTEMS AND METHODS FOR INTERLEAVED HAMMING ENCODING AND DECODING”, which is commonly owned and incorporated herein by reference for all purposes. Technical Field

[0003] This invention relates to data communication systems and technologies. Background Technology

[0004] Over the past few decades, the use of communication networks has surged. In the early days of the Internet, popular applications were limited to email, bulletin boards, and most text-based web browsing, with relatively small amounts of data transmitted. Today, the Internet and mobile applications require massive amounts of bandwidth to transmit photos, videos, music, and other multimedia files. For example, social networks like Facebook process over 500TB of data daily. This high demand for data storage and transmission necessitates improvements to existing data communication systems to meet these needs. New data centers are constantly being built, while existing data centers are being expanded and upgraded.

[0005] Data communication rates can be increased in various ways, such as through error correction. For example, Reed-Solomon codes have been used in traditional communication systems. Unfortunately, existing technologies are insufficient, and improved systems and methods are needed. Summary of the Invention

[0006] This invention relates to communication systems and methods. According to a particular embodiment, FEC data streams from multiple FEC data channels are received. A first-stage interleaving and internal coding are performed on the FEC data streams to generate an internally coded data stream. A second-stage interleaving process is then performed to interleave the internally coded data streams. Other embodiments are also available.

[0007] According to an embodiment, the present invention provides a communication device including an interface for receiving FEC data streams from two or more FEC data channels. The FEC data streams include a first FEC data stream and a second FEC data stream. The device further includes a first interleaver configured to interleave the first FEC data stream and generate a first interleaved stream. The device also includes an encoder configured to process the first interleaved stream and generate a first soft-decodeable stream. The device further includes a second interleaver configured to interleave the first soft-decodeable stream and generate an outgoing data stream. The second interleaver may include M lines corresponding to an interleaving depth of N. The M lines may include a first delay line and a second delay line. The first delay line may include N-1 delay units. The second delay line may include N-2 delay units. The device also includes a mapper configured to map the outgoing data stream for transmission on the communication channel.

[0008] According to another embodiment, the present invention provides a communication device including a first convolutional interleaver configured to generate a first interleaved stream based on a first FEC data stream. The device further includes a first Hamming encoder configured to encode the first interleaved stream and generate a first Hamming codeword stream. The device also includes a second convolutional interleaver configured to generate a second interleaved stream based on a second FEC data stream. The device further includes a second Hamming encoder configured to encode the second interleaved stream and generate a second Hamming codeword stream. The device also includes a Hamming codeword interleaver configured to generate an outgoing data stream by interleaving at least the first and second Hamming codeword streams. The Hamming codeword interleaver may include a first memory configured to interleave the first and second Hamming codeword streams to generate the outgoing data stream. The first memory may include a memory having N rows and M columns. The Hamming codeword interleaver is configured to write the first Hamming codeword stream row by row. The outgoing data stream is generated by reading the first memory column by column.

[0009] According to another embodiment, the present invention provides a communication device including a communication interface coupled to a communication channel for receiving input data signals. The device further includes a soft sequence detector configured to generate a log-likelihood ratio (LLR) value associated with the input data signal. The device also includes a deinterleaver configured to deinterleave the input data signal and accordingly assign LLR values ​​to an internal soft forward error correction (SFEC) process to generate a deinterleaved data stream. The device further includes an internal SFEC decoder configured to process the deinterleaved data stream.

[0010] It should be understood that embodiments of the present invention offer many advantages over conventional techniques. In particular, by interleaving symbols with soft FEC coding, embodiments of the present invention provide effective error correction, especially in the presence of associated errors (e.g., ISI). In various embodiments, the internal interleaving mechanism according to the present invention is used in conjunction with other coding and interleaving techniques such as Hamming codeword interleaving, thereby achieving a high level of performance.

[0011] Embodiments of the present invention can be implemented in conjunction with existing systems and processes. For example, the encoding and interleaving mechanism according to the present invention can be implemented using existing manufacturing equipment and processes. Furthermore, the internal SFEC and interleaving mechanism and method are compatible with existing systems and equipment, and therefore can be easily applied to a wide range of applications. Other advantages also exist.

[0012] These and other advantages are achieved by the present invention within the context of known technologies. However, a further understanding of the nature and advantages of the invention can be achieved by referring to the latter part of the specification and the accompanying drawings. Attached Figure Description

[0013] The figures below are merely illustrative and should not unduly limit the scope of the claims herein. Many other variations, modifications, and substitutions will be recognized by those skilled in the art. It should also be understood that the embodiments and implementations described herein are for illustrative purposes only, and various modifications or changes thereto will be suggested to those skilled in the art and will be included within the spirit and scope of the method and the appended claims.

[0014] Figure 1 This is a simplified block diagram illustrating a communication system according to an embodiment of the present invention.

[0015] Figure 2 This is a simplified block diagram illustrating a dual-channel transmitter according to an embodiment of the present invention.

[0016] Figure 3 This is a simplified diagram illustrating a four-channel transmitter according to an embodiment of the present invention.

[0017] Figure 4A -4C is a simplified diagram illustrating the interlacing technique according to an embodiment of the present invention.

[0018] Figure 5 This is a simplified block diagram illustrating a column-based interleaving mechanism according to an embodiment of the present invention.

[0019] Figure 6 This is a simplified diagram illustrating the Hamming code interleaving process according to an embodiment of the present invention.

[0020] Figure 7 This is a simplified diagram illustrating a four-channel Hamming codeword interleaving mechanism according to an embodiment of the present invention.

[0021] Figure 8 This is a simplified diagram illustrating a two-channel Hamming codeword interleaving mechanism according to an embodiment of the present invention. Detailed Implementation

[0022] This invention relates to communication systems and methods. According to a particular embodiment, FEC data streams from multiple FEC data channels are received. A first-stage interleaving and internal coding are performed on the FEC data streams to generate an internally coded data stream. A second-stage interleaving process is then performed to interleave the internally coded data streams. Other embodiments are also available.

[0023] Error correction and its encoding mechanisms are important aspects of data communication. For example, soft forward error correction (SFEC) and interleaving techniques are described in U.S. Patent Application No. 16 / 818,864, which is incorporated herein by reference. Depending on the implementation, the SFEC mechanism can be implemented in various ways, such as single parity check and Hamming codewords. It should be understood that the term "SFEC" refers to softly decodable code used for encoding.

[0024] In communication systems, different types of noise exist. For example, equalization techniques are commonly used to remove link noise. Some noise is correlated (e.g., "memory" errors), such as inter-symbol interference (ISI), and can be removed using soft sequence detectors. It should be understood that embodiments of the present invention provide an interleaving technique implemented in conjunction with a soft sequence detector.

[0025] In certain embodiments, the present invention provides a system that incorporates a soft sequence detector for an equalized partial response channel to utilize SFEC (or variations thereof). For example, the soft sequence detector may be a grid-based processor (e.g., SOVA, BCJR, MAX-LOG-MAP) for pulse amplitude modulation (PAM) (e.g., PAM4 / PAM6 / PAM8 on a 1+αD partial response channel). For instance, the soft sequence detector in an exemplary receiver generates reliability (e.g., log-likelihood ratio or LLR) as input to the SFEC decoder.

[0026] It should be understood that one of the challenges introduced by the sequence detection mechanism is that errors (and corresponding reliability) at its output are correlated, which degrades the performance of low-complexity FEC decoders. It should be understood that a suitable interleaving mechanism is used to achieve excellent end-to-end performance. More specifically, interleaving mechanisms are implemented on multiple SFEC codewords in the transmitter, and deinterleaving mechanisms are implemented in the receiver. It should be understood that the interleaving mechanism according to embodiments of the invention can decorrelate the LLR without requiring a complex FEC decoder, increasing end-to-end latency to a minimum and minimizing performance degradation.

[0027] The following description is presented to enable those skilled in the art to make and use the invention and incorporate it into a particular application context. Various modifications and uses in different applications will be apparent to those skilled in the art, and the general principles defined herein can be applied to a wide range of embodiments. Therefore, the invention is not intended to be limited to the presented embodiments, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0028] In the following detailed description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without being limited to these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the invention.

[0029] The reader's attention is directed to all papers and documents submitted concurrently with this specification and made publicly available for examination together with this specification, the contents of which are incorporated herein by reference. All features disclosed in this specification (including any appended claims, abstracts, and drawings) may be replaced by alternative features for the same, equivalent, or similar purposes, unless otherwise expressly stated. Therefore, unless otherwise expressly stated, each disclosed feature is merely one example of an equivalent or similar feature in a general series.

[0030] Furthermore, no element in the claims that expressly refers to "means for..." or "steps for..." performing a specific function should be construed as the "means" or "steps" provision in paragraph 6 of 35 U.S.SC § 112. In particular, the use of "steps for..." or "actions for..." in the claims is not intended to invoke the provisions of paragraph 6 of 35 U.S.SC § 112.

[0031] Please note that if used, the labels left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are for convenience only and do not imply any particular fixed direction. Rather, they are used to reflect the relative position and / or orientation between the various parts of an object.

[0032] Figure 1 This is a simplified block diagram illustrating a communication system according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. As an example, the communication system 100 includes a transmitter 110 and a receiver 120 connected via a communication channel 130. For example, the communication channel 130 may be an optical communication link and uses PAM communication. Depending on the implementation, the communication channel 130 may be implemented using a high-speed wired connection or other types of links.

[0033] Transmitter 110 includes an FEC encoder 101. For example, the FEC encoder 101 can be implemented using an SFEC encoder (e.g., with soft-decodeable code), and the FEC encoder 101 may include a block interleaver (…). Figure 2 (as shown) or convolutional interleaver ( Figure 3 As shown, the output of FEC encoder 101 is interleaved at box 102 as part of the encoding process. Figure 4A -C to Figure 8 (As shown in the diagram). For example, internal codeword interleaver 102 produces an output consisting of time-interleaved internal codewords. A detailed description of the internal codeword interleaving mechanism will be provided below. Block 103 includes a mapper that transforms consecutive bit pairs into PAM4 symbols (optionally using precoding). In various embodiments, block 103 also includes transmit digital signal processing (TX DSP) that warps the transmitted PAM4 sequence (i.e., the mapper output) to pre-compensate for line impairments. The output of block 103 is processed in transmit interface block 104. For example, block 104 includes various components (e.g., modulators, drivers, etc.) for transmitting data to receiver 120 via communication link 130.

[0034] Receiver 120 first processes the data received from communication link 130 using receiver (Rx) interface block 111. For example, block 111 includes various components performing initial processing, such as termination circuitry, equalizers, and variable gain amplifiers (VGAs). In various embodiments, block 111 performs timing recovery, and it may include equalization and attenuation mitigation. For example, block 111 induces a partial response channel at the soft sequence detector input. Soft sequence detector 112 is configured to generate an LLR for each received unit interval (UI). Block 113 includes a deinterleaver that reorders the LLRs from the soft sequence detector output. For example, the soft internal FEC decoder assumes that the LLRs are independently and identically distributed at their inputs. Block 114 includes an internal FEC decoder. For example, the parameters of the internal codeword deinterleaver at block 113 depend on the selection of the internal SFEC in block 114.

[0035] Figure 2This is a simplified block diagram illustrating a dual-channel transmitter according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art. As shown, transmitter 200 includes two 25G FEC channels with their respective data streams. A first FEC channel is coupled to AM-locked block 201; a second FEC channel is coupled to AM block 202. For example, AM-locked blocks 201 and 202 are configured to align the incoming data streams, and their output data blocks (e.g., even and odd blocks) are encoded by an SFEC encoder to form a single data stream destined for block 203. In various embodiments, SFEC is configured with one encoder per physical channel; the encoding process appends a PAM4 parity symbol to every 20 UI payloads. For example, each SFEC codeword corresponds to 21 PAM4 UIs. Block 203 includes an SFEC codeword interleaver as shown. For example, a single codeword interleaver at block 203 is configured to interleave the combined data streams. In various implementations where multiple sequence detectors exist in the receiver, the transmitter includes multiple codeword interleavers, each configured for each physical data channel in the transmitter.

[0036] Figure 3 This is a simplified diagram illustrating a four-channel transmitter according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art. Transmitter 300 includes four 25G FEC channels (e.g., configured as physical channels), each channel having its own convolutional interleaver and Hamming encoder. For example, each FEC channel applies Hamming encoding; block 380 combines the Hamming-encoded outputs of multiple FEC channels to form a physical channel (e.g., four for 100G physical channels, or two for 50G physical channels). In a particular embodiment, each Hamming codeword comprises 128 bits (i.e., 64 UI for PAM4). The data from these four 25G FEC channels is interleaved by Hamming codeword interleaver 380, as shown. The output of block 380 is processed by a Gray mapper in block 390 to prepare data for PAM4 communication.

[0037] Figure 4A -4C is a simplified diagram illustrating the interlacing technique according to embodiments of the present invention. These diagrams are merely illustrative and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art. For example, Figure 4A The interleaving technique shown in -4C illustrates the convolutional interleaving of codewords.

[0038] like Figure 4AAs shown, a convolutional interleaver is used to interleave the SFEC-encoded data stream 21 ways. For example, each codeword includes multiple PAM symbols (e.g., 2 bits of data for a PAM4 implementation). More specifically, there are 21 UI codewords (by c0, c1, ..., c...). 20 (This indicates that) is written to 21 delay lines (i.e., Figure 4A Each "D" in the diagram represents a delay unit. Simultaneously, 21 UIs are read from the 21 delay lines for transmission via the communication channel. For example, line c0 includes 20 delay units, line c1 includes 19 delay units, and c... 20 Excluding delay units, and correspondingly producing the output of the interleaving mechanism. The maximum delay among all delay lines defines the depth of the codeword interleaver. Figure 4A The interleaving mechanism in the code comprises 21 delay lines with a depth of 21. It should be understood that the interleaver's latency, area, and power consumption increase linearly with the interleaving depth. Simultaneously, the resilience to associated errors also increases with the interleaving depth.

[0039] Figure 4B An interleaving mechanism specifically configured for internal error correction, characterized by a depth of 7, is shown. It should be noted that the interleaving from c0 to c... 20 The diagram shows 21 lines, but they are grouped. For example, lines c0 to c6 are in the first group at depth 7, and lines c7 to c... 13 Located in the second group at depth 7, line c 14 To c 20 It is located in the third group. Figure 4C An interleaving mechanism characterized by a depth of 10 is shown, which is specifically configured for internal error correction, where lines c0 to c... 20 They were grouped.

[0040] Figure 5 This is a simplified block diagram illustrating a column-based interleaving mechanism according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Many variations, substitutions, and modifications will be recognized by those skilled in the art. As an example, Figure 2 203 in the middle can be used Figure 5 This is implemented using a column-based mechanism, as shown. Figure 5 As shown, there are N rows of data. This is achieved by writing codeword data line by line and interleaving at predetermined positions (e.g., C). n To C n＋N－1 Interleaving is performed by reading data column by column (corresponding to the interleaving positions for the N rows of data). As an example, Figure 5The interleaving mechanism shown can be implemented using various types of memory and registers. In various embodiments, SFEC codewords (indexed according to their generation order) are written to rows of a two-dimensional memory. N is the depth of the interleaver (in SFEC codewords), and M is the offset between codeword boundaries in consecutive rows of the interleaver structure (e.g., in PAM4 UI). For example, for each column, each SFEC codeword intersecting that column is read out as 2 bits (i.e., 1 PAM4 UI). When M=0, the interleaver simplifies to a standard block interleaver. In various embodiments, M is chosen to minimize end-to-end latency such that M·N≅21, where 21 is the length of the SFEC codeword in UI. It is understood that the advantage of setting M·N≅21 is that codewords “arrive” at the receiver at a regular rate, which simplifies hardware implementation. In contrast, when M=0, all N codewords will arrive substantially simultaneously, thus requiring simultaneous decoding to minimize end-to-end latency, which necessitates additional hardware. Depending on the implementation, Figure 4A The interleaving mechanism shown in -C (e.g., convolutional interleaving) provides superior performance compared to... Figure 6 The interleaving mechanism shown has some advantages. Among other features, the convolutional interleaver can be configured within a smaller region for a fixed interleaving depth, which also minimizes power consumption. Typically, the deinterleaver consumes more power than the interleaver because it handles multi-bit resolution LLR. Additionally, SFEC codeword arrival times are smoothed. However, the synchronization of the convolutional deinterleaver switches requires knowledge of the codeword boundaries, which increases the complexity of initial locking to the codeword boundaries in the receiver, but has little impact on power, performance, or end-to-end delay (if any).

[0041] Figure 6 This is a simplified diagram illustrating the Hamming codeword interleaving process according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. As an example, Figure 6 The interleaving mechanism shown includes 64 lines configured in depth-4 groups (i.e., c0 to c...). 63 ), and performs convolutional interleaving. In a particular embodiment, FEC channels 0 / 1 / 2 / 3 provide Hamming codeword input to the convolutional interleaver in a cyclic order, where lines c0 to c 63 This corresponds to 64 UIs from a single Hamming codeword. The use of a convolutional interleaver scheme minimizes the storage required for the receiver deinterleaver. Furthermore, the convolutional interleaver smooths codeword arrival time.

[0042] Figure 7This is a simplified diagram illustrating a four-channel Hamming codeword interleaving mechanism according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. As an example, the Hamming codeword interleaver is implemented similarly to the SFEC interleaver described above, with certain differences. For example, the interleaving depth N is an integer multiple of the number of FEC channels that combine to form the physical channel. Performance and latency are measured in terms of N. The codeword from FEC channel i is written to the interleaver row with row index i (mod p) by indexing the FEC channel that forms the physical channel by i, i∈{0,1,…,p-1}. Figure 7 In this process, four 25G FEC channels are mapped to 100G physical channels, where N=4 and M=16 (Note: N·M=64, the number of UIs in the Hamming codeword).

[0043] Figure 8 This is a simplified diagram illustrating a two-channel Hamming codeword interleaving mechanism according to an embodiment of the present invention. This diagram is merely an example and should not unduly limit the scope of the claims. Those skilled in the art will recognize many variations, substitutions, and modifications. As an example, a 50G physical channel is mapped from two 25G FEC channels, where N=4 and M=16 (note: N·M=64, the number of UIs in the Hamming codeword). It should be understood that, depending on the implementation, the Hamming codewords can be interleaved in many ways, as described in U.S. Patent Application No. 16 / 818,864.

[0044] While the foregoing is a complete description of specific embodiments, various modifications, alternative constructions, and equivalents may be used. Therefore, the foregoing description and illustrations should not be construed as limiting the scope of the invention as defined by the appended claims.

Claims

1. A communication device for transmitting data via an optical communication link in a communication system, comprising: A plurality of first interleavers, each first interleaver being configured to: (i) receive an FEC data stream from a corresponding forward error correction (FEC) data channel, and (ii) interleave the FEC data stream to generate an interleaved stream; Multiple encoders are configured to receive the interleaved stream from a respective first interleaver among the multiple first interleavers and encode the interleaved stream to generate an encoded interleaved stream containing soft-decodeable code corresponding to the interleaved stream; The second interleaver is configured to interleave the encoded interleaved streams previously encoded by the plurality of encoders and generate an outgoing data stream including the internal codewords of the time interleaving of the encoded interleaved streams. The second interleaver is also configured to apply different delays to the encoded interleaved streams received by the second interleaver by applying delays to corresponding encoded interleaved streams in a set of encoded interleaved streams, wherein the corresponding delay applied to the corresponding stream is different from the delay applied to each other encoded interleaved stream in the set of encoded interleaved streams, in order to reduce the waiting time associated with the second interleaver simultaneously receiving the encoded interleaved streams. as well as A mapper is configured to map the outgoing data stream into symbols for transmission over the optical communication link.

2. The communication device according to claim 1, wherein the encoder comprises a Hamming encoder.

3. The communication device of claim 1, wherein the encoder includes a parity encoder configured to add parity symbols to the interleaved stream.

4. The communication device of claim 1, wherein the mapper includes a Gray mapper configured for PAM4 communication.

5. The communication device according to claim 1, wherein the second interleaver includes M lines corresponding to an interleaving depth of N, the M lines including a first delay line and a second delay line, the first delay line including N-1 delay units, the second delay line including N-2 delay units, wherein N is 21.

6. The communication device according to claim 1, wherein the second interleaver includes M lines corresponding to an interleaving depth of N, the M lines including a first delay line and a second delay line, the first delay line including N-1 delay units, the second delay line including N-2 delay units, wherein N is 4.

7. The communication device according to claim 1, wherein the second interleaver includes M lines corresponding to an interleaving depth of N, the M lines including a first delay line and a second delay line, the first delay line including N-1 delay units, the second delay line including N-2 delay units, wherein N is 7.

8. The communication device according to claim 1, wherein the second interleaver includes M lines corresponding to an interleaving depth of N, the M lines including a first delay line and a second delay line, the first delay line including N-1 delay units, the second delay line including N-2 delay units, wherein N is 10.

Images