A double-sided heat dissipation power module with high short-circuit current tolerance

Abstract

The present invention discloses a double-sided heat dissipation power module with high short-circuit current tolerance, belonging to the technical field of power electronic devices. It includes two AC power terminals, DC positive / negative power terminals, a number of power semiconductor chips, two DBC substrates and a number of metal gaskets. The power module of the half-bridge structure is internally divided into a first / second commutation loop and decoupling is achieved, and the short-circuit current adopts a winding current path and a narrow conductive metal copper layer. By replacing the bonding wire with a metal gasket that realizes double-sided heat dissipation, the purpose of electrical connection between the upper and lower DBC substrates is achieved at the same time, thereby reducing the parasitic inductance of the commutation loop and suppressing voltage overshoot. The short-circuit current path adopts a narrow copper layer, and is laid out using the principle of increasing the mutual inductance of the same-direction current, which greatly increases the inductance of the short-circuit loop and suppresses the rise rate and peak value of the short-circuit current. The module can greatly improve the short-circuit current tolerance without affecting the normal operation of the power device, and ensure the reliability and stability of the device.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronic devices, and in particular relates to a double-sided heat dissipation power module with high short-circuit current tolerance. Background Art

[0002] Power electronic power devices and their devices are widely used in the fields of renewable energy power generation, transportation, aerospace, chemical industry, etc. They are an important means to efficiently convert energy, achieve energy conservation and environmental protection, and improve people's quality of life. As the core of power electronic devices, power devices are also the components with the highest failure rate, accounting for about one-third of the total failures, and temperature factors have the greatest impact on the reliability of power electronic power devices and systems. Especially when a short-circuit fault occurs, the device is directly connected to the extremely high bus voltage, and a large current flows through the device. The chip will generate a lot of heat within a few microseconds, causing aging or failure. Taking the short-circuit thermoelectric simulation of SiC MOSFET as an example, the maximum junction temperature inside the device can reach 1200℃ before failure.

[0003] In order to improve the tolerance of devices under short-circuit conditions, it is generally considered to increase the loop impedance and suppress the current rise rate. Under the traditional configuration, the commutation loop coincides with a type of short-circuit fault loop. If the loop impedance, such as parasitic inductance, is increased, then during normal commutation, the high di / dt generated by the active semiconductor chip switch will generate a spike voltage ΔV=L·di / dt on the parasitic inductance. The spike voltage at the emitter or source will cause fluctuations in the drive voltage, which will seriously affect the life of the base or gate. If the voltage overshoot is too large, it may even cause the collector-emitter or drain-source breakdown of the active semiconductor chip. Therefore, improving the short-circuit current tolerance is inconsistent with reducing the voltage overshoot.

[0004] Most of the existing power devices currently reduce the loop impedance as much as possible to obtain a good voltage waveform, but they are helpless against short-circuit faults. This phenomenon is particularly common in double-sided heat dissipation module structures. Through three-dimensional spatial layout, the loop inductance can be greatly reduced, but at the same time, the tolerance to short-circuit faults is also deteriorated. Currently, there are also topological structures with dual AC power terminals, but the decoupling of the power commutation loop is not achieved, and the tolerance to short-circuit faults is not improved. In power module design, parallel layout and small loop principles are widely used, but the purpose is to offset the magnetic field and reduce inductance, and there is no protection against short-circuit faults.

[0005] In addition, the current conventional layout modules generally have heat dissipation problems. For the sake of device reliability, additional heat dissipation measures such as water cooling are often required, which restricts the further improvement of power density. Double-sided heat dissipation modules dissipate heat on both sides simultaneously, greatly improving the heat dissipation efficiency, but most double-sided heat dissipation modules use a single-sided layout of power chips, and conduct heat to the other side through a heat-conducting medium, resulting in a large thermal coupling between power chips.

[0006] In summary, the existing power device design cannot achieve both "improving short-circuit tolerance" and "reducing voltage overshoot", and most tend to reduce the circuit inductance, allowing the short-circuit tolerance to deteriorate, which poses hidden dangers to device applications. In addition, most double-sided heat dissipation modules do not really take advantage of the double-sided structure, which affects the further improvement of heat dissipation efficiency. Summary of the invention

[0007] In view of the above problems, the present invention provides a double-sided heat dissipation power module with high short-circuit tolerance, which utilizes a clever layout to greatly improve the suppression effect on short-circuit current without affecting the normal commutation of power devices, thereby providing sufficient margin for short-circuit protection.

[0008] In order to achieve the above object, the present invention adopts the following technical solution:

[0009] A double-sided heat dissipation power module with high short-circuit current tolerance, comprising a power terminal, an active semiconductor chip, a passive semiconductor chip, an upper DBC substrate, a lower DBC substrate, and a metal gasket;

[0010] The power terminals include a DC positive power terminal, a DC negative power terminal, a first AC power terminal, and a second AC power terminal; wherein the DC positive power terminal is close to the second AC power terminal, and the DC negative power terminal is close to the first AC power terminal;

[0011] The active semiconductor chip includes an upper bridge arm active semiconductor chip and a lower bridge arm active semiconductor chip, and the passive semiconductor chip includes an upper bridge arm passive semiconductor chip and a lower bridge arm passive semiconductor chip;

[0012] The upper DBC substrate and the lower DBC substrate are placed opposite to each other, and include an inner metal layer, an insulating layer and an outer metal layer, wherein the insulating layer is located between the inner metal layer and the outer metal layer, and the outer metal layer is used for heat dissipation; the inner metal layer of the upper DBC substrate includes an upper first metal part, an upper second metal part, an upper third metal part and an upper fourth metal part, and the four parts are independent and unconnected; the inner metal layer of the lower DBC substrate includes a lower first metal part, a lower second metal part, a lower third metal part and a lower fourth metal part, and the four parts are independent and unconnected; the upper first metal part of the upper DBC substrate is welded with an upper bridge arm active semiconductor chip, an upper bridge arm passive semiconductor chip and a DC positive power terminal, and the upper fourth metal part is welded with a DC negative power terminal; the lower first metal part of the lower DBC substrate is welded with a lower bridge arm active semiconductor chip, the lower second metal part is welded with a lower bridge arm passive semiconductor chip, the lower third metal part is welded with a second AC power terminal, and the lower fourth metal part is welded with a first AC power terminal;

[0013] The metal gasket includes a main metal gasket and a secondary metal gasket, the main metal gasket includes a first main metal gasket, a second main metal gasket, a third main metal gasket, and a fourth main metal gasket, and the secondary metal gasket includes a first metal gasket, a second metal gasket, a third metal gasket, and a fourth metal gasket; the first main metal gasket is installed on the upper bridge arm active semiconductor chip, the second main metal gasket is installed on the upper bridge arm passive semiconductor chip, the third main metal gasket is installed on the lower bridge arm active semiconductor chip, and the fourth main metal gasket is installed on the lower bridge arm passive semiconductor chip; the first metal gasket, the second metal gasket, the third metal gasket, and the fourth metal gasket are respectively installed on the lower second metal part, the lower fourth metal part, the lower first metal part, and the lower third metal part of the lower DBC substrate;

[0014] The collector or drain of the upper bridge arm active semiconductor chip and the cathode of the upper bridge arm passive semiconductor chip are electrically connected to the DC positive power terminal through the upper first metal part of the upper DBC substrate; the emitter or source of the upper bridge arm active semiconductor chip is connected to the lower second metal part of the lower DBC substrate through the first main metal gasket to achieve electrical connection with the cathode of the lower bridge arm passive semiconductor chip; the anode of the upper bridge arm passive semiconductor chip is connected to the lower first metal part of the lower DBC substrate through the second main metal gasket to achieve electrical connection with the collector or drain of the lower bridge arm active semiconductor chip; the emitter or source of the lower bridge arm active semiconductor chip and the anode of the lower bridge arm passive semiconductor chip are connected to the upper fourth metal part of the upper DBC substrate through the third main metal gasket and the fourth main metal gasket respectively, and are electrically connected to the DC negative power terminal through the upper fourth metal part;

[0015] The two ends of the upper third metal part of the upper DBC substrate are electrically connected to the first metal pad and the second metal pad respectively, and the two ends of the upper second metal part are electrically connected to the third metal pad and the fourth metal pad respectively.

[0016] As a preferred embodiment of the present invention, the upper third metal part and the upper second metal part of the upper DBC substrate are parallel and close elongated copper layers; one end of the upper third metal part is connected to the second metal gasket, and the other end is connected to the first metal gasket; one end of the upper second metal part is connected to the third metal gasket, and the other end is connected to the fourth metal gasket; the first metal gasket and the fourth metal gasket are used to transmit the short-circuit current of the lower DBC substrate into a pair of parallel and close elongated copper layers on the upper DBC substrate, and then the third metal gasket and the second metal gasket transmit the short-circuit current into the lower DBC substrate.

[0017] As a preferred embodiment of the present invention, the design method of the parallel and close elongated copper layers is:

[0018] Determine the rated voltage level, rated current level, and current rise rate parameters of the double-sided heat dissipation power module to be designed; determine the copper thickness according to the typical value of the DBC substrate, determine the minimum copper width according to the rated current level, and determine the minimum insulation spacing according to the rated voltage level; estimate the parasitic inductance of the short-circuit current loop based on 5 to 10 times the expected parasitic inductance of the commutation loop of the double-sided heat dissipation power module; use the finite element analysis method to establish the relationship between the parasitic inductance and the length of the parallel slender copper layer for iterative optimization.

[0019] As a preferred embodiment of the present invention, the upper third metal part and the upper second metal part of the upper DBC substrate are spiral structures.

[0020] As a preferred embodiment of the present invention, the short-circuit current flows through the upper third metal portion and the upper second metal portion of the upper DBC substrate in the same direction.

[0021] As a preferred embodiment of the present invention, the upper first metal part and the upper fourth metal part of the upper DBC substrate are wide rectangular copper layers, which are arranged on both sides of the upper third metal part and the upper second metal part; the current path width of the rectangular structure is 2-20 times the current path width of the upper third metal part and the upper second metal part.

[0022] As a preferred embodiment of the present invention, the lower third metal part and the lower fourth metal part of the lower DBC substrate are slender copper layer structures, one end of the lower third metal part is welded with a fourth metal gasket, and the other end is welded with a second AC power terminal; one end of the lower fourth metal part is welded with a second metal gasket, and the other end is welded with a first AC power terminal.

[0023] As a preferred embodiment of the present invention, the lower first metal part of the lower DBC substrate includes a wide rectangular copper layer and a slender copper layer, the lower bridge arm active semiconductor chip is welded on one end of the wide rectangular copper layer, and the end is connected to one end of the slender copper layer, a third metal gasket is welded on the other end of the slender copper layer, and the second main metal gasket is connected to the other end of the wide rectangular copper layer; the slender copper layer of the lower first metal part is parallel and close to the lower fourth metal part.

[0024] As a preferred embodiment of the present invention, the lower second metal part of the lower DBC substrate includes a wide rectangular copper layer and a slender copper layer, the first main metal gasket is connected to one end of the wide rectangular copper layer, and the end is connected to one end of the slender copper layer, the other end of the slender copper layer is welded with a first metal gasket, and the lower bridge arm passive semiconductor chip is welded to the other end of the wide rectangular copper layer; the slender copper layer of the lower second metal part is parallel and close to the lower third metal part.

[0025] As a preferred embodiment of the present invention, the double-sided heat dissipation power module includes a first commutation circuit and a second commutation circuit;

[0026] The first commutation loop is composed of the DC positive power terminal, the upper bridge arm active semiconductor chip, the lower bridge arm passive semiconductor chip and the DC negative power terminal, and the second commutation loop is composed of the DC positive power terminal, the upper bridge arm passive semiconductor chip, the lower bridge arm active semiconductor chip and the DC negative power terminal.

[0027] As a preferred embodiment of the present invention, the first AC power terminal and the second AC power terminal are connected to a metal busbar or a protection element outside the power module; the protection element includes but is not limited to a fuse and a positive temperature coefficient thermistor.

[0028] The short-circuit current flows through the DC positive power terminal, the upper bridge arm active semiconductor chip, the first main metal gasket, the first metal gasket, the second metal gasket, and the first AC power terminal. The first AC power terminal is connected to the second AC power terminal through an external metal busbar or a protection element. The short-circuit current continues to flow through the second AC power terminal through the fourth metal gasket, the third metal gasket, the lower bridge arm active semiconductor chip, the third main metal gasket, and the DC negative power terminal.

[0029] As a preferred embodiment of the present invention, the active semiconductor chip and the passive semiconductor chip can be composed of a single or multiple parallel connections, and the materials include but are not limited to silicon, silicon carbide or gallium nitride; the metal gasket can be composed of a single or multiple parallel connections, and the materials include but are not limited to molybdenum; the materials of the power terminal, the metal busbar, the first metal layer and the second metal layer of the substrate include but are not limited to copper;

[0030] As a preferred embodiment of the present invention, the gap between the upper and lower DBC substrates is an insulating sealing layer, and the sealing material includes but is not limited to silicone or epoxy resin.

[0031] As a preferred embodiment of the present invention, the active semiconductor chip is an insulated gate bipolar transistor IGBT, a metal oxide field effect transistor MOSFET, a thyristor or a bipolar junction transistor BJT; and the passive semiconductor chip is a diode.

[0032] Compared with the prior art, the advantages of the present invention are:

[0033] (1) The power device layout design proposed in the present invention makes full use of the principle of increased mutual inductance of current in the same direction, greatly increases the parasitic inductance of the short-circuit loop, suppresses the rising rate and peak value of the short-circuit current, and leaves sufficient margin for short-circuit fault protection; while the normal parasitic inductance of the commutation loop is not affected.

[0034] (2) The power device layout design proposed in the present invention uses metal gaskets to achieve electrical connection and thermal coupling between the upper and lower substrates, eliminates the bonding wire structure, increases the current capacity and reduces parasitic parameters, reduces the voltage overshoot when the device is turned off, and solves the failure problem caused by bonding wire aging.

[0035] (3) The power device layout design proposed in the present invention not only adopts double-sided heat dissipation, but also places the upper and lower bridge arm power chips on the upper and lower substrates, further reducing the coupling during heat dissipation of the power chips and enhancing the heat dissipation capability. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 It is a three-dimensional diagram of an optional embodiment of the double-sided heat dissipation power module proposed by the present invention.

[0037] Figure 2 A bottom DBC stereogram of an optional embodiment of a double-sided heat dissipation power module proposed by the present invention.

[0038] Figure 3 It is a three-dimensional diagram of the upper DBC of an optional embodiment of the double-sided heat dissipation power module proposed by the present invention.

[0039] Figure 4 It is a right side view of an optional embodiment of the double-sided heat dissipation power module proposed by the present invention.

[0040] Figure 5 This is a flow chart for designing a thin and narrow copper layer for a double-sided heat dissipation power module proposed by the present invention.

[0041] Figure 6 This is a corresponding relationship diagram between the inductance and the copper layer length of an optional embodiment of the double-sided heat dissipation power module proposed by the present invention.

[0042] Figure 7 This is the first commutation circuit of an optional embodiment of the double-sided heat dissipation power module proposed by the present invention.

[0043] Figure 8 This is a second commutation circuit of an optional embodiment of the double-sided heat dissipation power module proposed by the present invention.

[0044] Fig. 9 This is a short-circuit current loop of an optional embodiment of the double-sided heat dissipation power module proposed by the present invention.

[0045] Fig.10 Schematic diagram of parasitic parameters when current flows through an isolated wire.

[0046] Fig.11 Schematic diagram of parasitic parameters when current in the same direction flows through parallel wires.

[0047] Fig.12Schematic diagram of parasitic parameters when reverse current flows through parallel wires.

[0048] Among them, 101 is a third main metal pad, 102 is a lower bridge arm active semiconductor chip, 103 is a lower DBC substrate inner metal layer, 103-1 is a lower first metal part, 103-2 is a lower second metal part, 103-3 is a lower third metal part, 103-4 is a lower fourth metal part, 104 is a lower DBC substrate insulating layer, 105 is a second AC power terminal, 106 is a first AC power terminal, 107 is a lower bridge arm passive semiconductor chip, 108 is a fourth main metal pad, 109 is a lower bridge arm active semiconductor chip driving emitter or source terminal, 110 is a lower bridge arm active semiconductor chip driving base or gate terminal, 111 is a third metal pad, 112 is a second metal pad, 113 is a fourth metal pad, 114 is a 14 first main metal gasket, 115 lower DBC substrate outer metal layer; 201 second main metal gasket, 202 upper bridge arm passive semiconductor chip, 203 upper DBC substrate insulating layer, 204 DC negative power terminal, 205 DC positive power terminal, 206 upper bridge arm active semiconductor chip, 207 first main metal gasket, 208 upper DBC substrate inner metal layer, 208-1 upper first metal part, 208-2 upper second metal part, 208-3 upper third metal part, 208-4 upper fourth metal part, 209 upper bridge arm active semiconductor chip driving emitter or source terminal, 210 upper bridge arm active semiconductor chip driving base or gate terminal, 211 upper DBC substrate outer metal layer. DETAILED DESCRIPTION

[0049] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0050] It should be noted that the present embodiment and description are only used to explain the present invention and are not intended to limit the present invention. In addition, the present embodiment and its features may be combined with each other without conflict.

[0051] Figure 1-Figure 4 A double-sided heat dissipation module configuration with high short-circuit current tolerance is provided in an embodiment of the present disclosure, which mainly includes a DC positive power terminal 205, a DC negative power terminal 204, a first AC power terminal 106, a second AC power terminal 105, an upper bridge arm active semiconductor chip 206, a lower bridge arm active semiconductor chip 102, an upper bridge arm passive semiconductor chip 202, a lower bridge arm passive semiconductor chip 107, an upper DBC substrate, a lower DBC substrate, and a metal gasket.

[0052] Among them, the active semiconductor chip has three ports: a control electrode port, a collector or drain port, and an emitter or source port, which form electrical connections with the substrate, metal pads or bonding wires;

[0053] The passive semiconductor chip has two ports: a cathode port and an anode port, which form electrical connections with the substrate and the metal pad;

[0054] The lower bridge arm active semiconductor chip driving emitter or source terminal 109, the lower bridge arm active semiconductor chip driving base or gate terminal 110 are electrically connected to the control electrode port of the lower bridge arm active semiconductor chip 102, and the upper bridge arm active semiconductor chip driving emitter or source terminal 209, the upper bridge arm active semiconductor chip driving base or gate terminal 210 are electrically connected to the control electrode port of the upper bridge arm active semiconductor chip. The upper DBC substrate includes an inner metal layer 208, an insulating layer 203 and an outer metal layer 211; the lower DBC substrate also includes an inner metal layer 103, an insulating layer 104 and an outer metal layer 115, the insulating layer is located between the inner metal layer and the outer metal layer, and the outer metal layer is used for heat dissipation; the metal gasket includes a first main metal gasket 207, a second main metal gasket 201, a third main metal gasket 101, a fourth main metal gasket 108, a first metal gasket 114, a second metal gasket 112, a third metal gasket 111, and a fourth metal gasket 113.

[0055] like Figure 3 As shown, the inner metal layer 208 of the upper DBC substrate includes an upper first metal portion 208-1, an upper second metal portion 208-2, an upper third metal portion 208-3, and an upper fourth metal portion 208-4, and the four portions are independent and not connected; Figure 2 As shown, the inner metal layer 103 of the lower DBC substrate includes a lower first metal part 103-1, a lower second metal part 103-2, a lower third metal part 103-3, and a lower fourth metal part 103-4, and the four parts are independent and not connected; the upper first metal part 208-1 of the upper DBC substrate is welded with an upper bridge arm active semiconductor chip 206, an upper bridge arm passive semiconductor chip 202 and a DC positive power terminal 205, and the upper fourth metal part 208-4 is welded with a DC negative power terminal 204; the lower first metal part 103-1 of the lower DBC substrate is welded with a lower bridge arm active semiconductor chip 102, the lower second metal part 103-2 is welded with a lower bridge arm passive semiconductor chip 107, the lower third metal part 103-3 is welded with a second AC power terminal 105, and the lower fourth metal part 103-4 is welded with a first AC power terminal 106;

[0056] The metal gasket includes a main metal gasket and a secondary metal gasket, the main metal gasket includes a first main metal gasket 207, a second main metal gasket 201, a third main metal gasket 101, and a fourth main metal gasket 108, and the secondary metal gasket includes a first metal gasket 114, a second metal gasket 112, a third metal gasket 111, and a fourth metal gasket 113; the first main metal gasket 207 is installed on the upper bridge arm active semiconductor chip 206, and the second main metal gasket 201 is installed on the upper bridge arm passive semiconductor chip On the chip 202, the third main metal gasket 101 is installed on the lower bridge arm active semiconductor chip 102, and the fourth main metal gasket 108 is installed on the lower bridge arm passive semiconductor chip 107; the first metal gasket 114, the second metal gasket 112, the third metal gasket 111, and the fourth metal gasket 113 are respectively installed on the lower second metal part 103-2, the lower fourth metal part 103-4, the lower first metal part 103-1, and the lower third metal part 103-3 of the lower DBC substrate.

[0057] In a specific implementation of the present invention, the active semiconductor chip type is IGBT or MOSFET or thyristor or BJT, which can be a single chip or multiple chips connected in parallel; the passive semiconductor chip can be a diode, which can be a single chip or multiple chips connected in parallel.

[0058] The DC positive power terminal 205 in this configuration is electrically connected to the collector or drain of the upper bridge arm active semiconductor chip 206 and the cathode of the upper bridge arm passive semiconductor chip 202 through the upper first metal part 208-1 of the upper DBC substrate; the emitter or source of the upper bridge arm active semiconductor chip 202 and the anode of the upper bridge arm passive semiconductor chip 206 are electrically connected to the lower second metal part 103-2 and the lower first metal part 103-2 of the lower DBC substrate through the first main metal pad 207 and the second main metal pad 201 respectively. The other end of the wide lower DBC substrate lower layer second metal part 103-2 is electrically connected to the cathode of the lower bridge arm passive semiconductor chip 107, and the other end of the wide lower DBC substrate lower layer first metal part 103-1 is electrically connected to the collector or drain of the lower bridge arm active semiconductor chip 102; the DC negative power terminal 204 is electrically connected to the third main metal pad 101 and the fourth main metal pad 108 through the upper DBC substrate upper layer fourth metal part 208-4, and the third main metal pad 101 The other side is connected to the emitter or source of the lower bridge arm active semiconductor chip 102, and the other side of the fourth main metal pad 108 is connected to the anode of the lower bridge arm passive semiconductor chip 107; the lower layer second metal part 103-2 of the lower DBC substrate is electrically connected to the upper layer third metal part 208-3 of the upper DBC substrate through the first metal pad 114, and the elongated copper layer of the upper third metal part 208-3 is electrically connected to the lower layer fourth metal part 103-4 of the lower DBC substrate through the second metal pad 112 after making a circle, and the lower The other end of the fourth metal part 103-4 of the lower DBC substrate is connected to the first AC power terminal 205; the fourth metal part 103-1 of the lower DBC substrate is electrically connected to the second metal part 208-2 of the upper DBC substrate through the third metal gasket 111, and the elongated copper layer of the second metal part 208-2 of the upper DBC substrate is electrically connected to the third metal part 103-3 of the lower DBC substrate through the fourth metal gasket 113 after a circle, and the other end of the third metal part 103-3 of the lower DBC substrate is connected to the second AC power terminal 105. The first AC power terminal 106 and the second AC power terminal 105 are arranged on both sides of the module. Among them, the slender copper layers of the second metal part 208-2 and the third part 208-3 of the upper DBC substrate are parallel and close to each other; the slender copper layer areas of the first metal part 103-1 and the fourth part 103-4 of the lower DBC substrate are parallel and close to each other, and the slender copper layer areas of the second part 103-2 and the third part 103-3 are parallel and close to each other.In a specific implementation of the present invention, the lower first metal part 103-1 of the lower DBC substrate includes a wide rectangular copper layer and a slender copper layer, the lower bridge arm active semiconductor chip 102 is welded on one end of the wide rectangular copper layer, and the end is connected to one end of the slender copper layer, the other end of the slender copper layer is welded with a third metal gasket 111, and the second main metal gasket 201 is connected to the other end of the wide rectangular copper layer; the slender copper layer of the lower first metal part 103-1 is parallel and close to the lower fourth metal part 103-4.

[0059] The lower second metal part 103-2 of the lower DBC substrate includes a wide rectangular copper layer and a slender copper layer, the first main metal gasket 207 is connected to one end of the wide rectangular copper layer, and the end is connected to one end of the slender copper layer, the other end of the slender copper layer is welded with a first metal gasket 114, and the lower bridge arm passive semiconductor chip 107 is welded to the other end of the wide rectangular copper layer; the slender copper layer of the lower second metal part 103-2 is parallel and close to the lower third metal part 103-3.

[0060] The upper third metal part 208-3 and the upper second metal part 208-2 of the upper DBC substrate are parallel and close elongated copper layers; one end B of the upper third metal part 208-3 is connected to the second metal gasket 112, and the other end D is connected to the first metal gasket 114; one end A of the upper second metal part 208-2 is connected to the third metal gasket 111, and the other end C is connected to the fourth metal gasket 113; the first metal gasket 114 and the fourth metal gasket 113 are used to transmit the short-circuit current of the lower DBC substrate to a pair of parallel and close elongated copper layers on the upper DBC substrate, and then the third metal gasket 111 and the second metal gasket 112 transmit the short-circuit current to the lower DBC substrate.

[0061] like Figure 5 As shown, the design process of the parallel elongated copper layers formed by the upper third metal portion 208-3 and the upper second metal portion 208-2 of the upper DBC substrate is:

[0062] Step 1, determining the rated voltage level, rated current level, and current rise rate parameters of the double-sided heat dissipation power module to be designed;

[0063] Step 2, determine the copper thickness according to the typical value of the DBC substrate, determine the minimum copper width according to the rated current level, and determine the minimum insulation spacing according to the rated voltage level;

[0064] Step 3, estimating the parasitic inductance of the short-circuit current loop based on 5 to 10 times the expected parasitic inductance of the commutation loop of the double-sided heat dissipation power module;

[0065] Step 4: Use a finite element analysis method (such as finite element analysis software Q3D) to establish a relationship between the parasitic inductance and the length of the parallel elongated copper layers for iterative optimization.

[0066] Taking the 800V150A power module in the embodiment of the present invention as an example, the typical thickness of the metal layer in the DBC is 0.3mm, and the width of the copper layer is 2mm at the 150A current level. With the assistance of insulating media such as silicone, a spacing of 1mm can meet the 800V insulation requirements. In the absence of a special layout, the parasitic inductance of the commutation circuit is about 20 to 30nH, and the estimated design parasitic inductance of the short-circuit circuit is about 300nH. In the finite element analysis software Q3D, side-by-side copper layers with a thickness of 0.3mm, a width of 2mm, and a spacing of 1mm are established, and the parasitic reactance at a frequency of 10MHz is extracted at different copper layer lengths. The relationship between the inductance and the copper layer length is shown as follows. Figure 6 As shown. The copper layer length corresponding to the parasitic inductance of 300nH is about 170mm. In the embodiment of the present invention, a spiral structure is used to improve space utilization. The longitudinal wiring length is about 30mm, and the transverse wiring length is about 20mm. Considering other line impedances, it is estimated that one circle can meet the design requirements. Therefore, the upper third metal part 208-3 and the upper second metal part 208-2 of the upper DBC substrate are a one-circle spiral structure, and the short-circuit current flows through the upper third metal part 208-3 and the upper second metal part 208-2 of the upper DBC substrate in the same direction.

[0067] like Figure 7 The figure shows the first commutation loop of the power device of the present invention when it is operating normally, wherein the long dashed line is the current path in the upper DBC substrate, the dotted line is the current path in the lower DBC substrate, and the dashed circle is the connection between the upper and lower DBC substrates completed by the current passing through the metal gasket. The commutation current flows through the DC positive power terminal 205, the upper bridge arm active semiconductor chip 206, the first main metal gasket 207, the lower bridge arm passive semiconductor chip 107, the fourth main metal gasket 108 and the DC negative power terminal 204.

[0068] like Figure 8 The figure shows the second commutation loop of the power device of the present invention when it is operating normally, wherein the long dashed line is the current path in the upper DBC substrate, the dotted line is the current path in the lower DBC substrate, and the dashed circle is the connection between the upper and lower DBC substrates completed by the current passing through the metal gasket. The commutation current flows through the DC positive power terminal 205, the upper bridge arm passive semiconductor chip 202, the second main metal gasket 201, the lower bridge arm active semiconductor chip 102, the third main metal gasket 101 and the DC negative power terminal 204.

[0069] The first commutation circuit and the second commutation circuit are not electrically connected inside the module. When the power device operates normally, the load current is output through the first commutation circuit and the first AC power terminal 106 in sequence, and flows into the second commutation circuit in sequence through the second AC power terminal 105 and the second commutation circuit.

[0070] like Fig. 9 The figure shows the short-circuit current loop when a short-circuit fault occurs in the present invention, wherein the long dashed line is the current path in the upper DBC substrate, the dotted line is the current path in the lower DBC substrate, and the dashed circle is the current passing through the metal gasket to complete the connection between the upper and lower DBC substrates. The short-circuit current flows through the DC positive power terminal 205, the upper bridge arm active semiconductor chip 206, the first main metal gasket 207, the first metal gasket 114, the second metal gasket 112, the first AC power terminal 106, and the first AC power terminal 106 is connected to the second AC power terminal 105 through an external metal busbar or a protection element. The short-circuit current flows through the second AC power terminal 105 through the fourth metal gasket 113, the third metal gasket 111, the lower bridge arm active semiconductor chip 102, the third main metal gasket 101 and the DC negative power terminal 204.

[0071] Since the power terminals, metal gaskets, and metal copper layers of the DBC substrate in the power device all have parasitic inductance, the first commutation loop and the second commutation loop in the present invention use a relatively close current path and a wide conductive metal copper layer, which have a lower parasitic inductance and do not affect the normal operation and voltage overshoot of the power device; the short-circuit current loop uses a winding current path and a narrow conductive metal copper layer, and the layout fully utilizes the principle of increased mutual inductance of current in the same direction, has a higher parasitic inductance, and suppresses the short-circuit current rise rate and peak value.

[0072] The first main metal pad 207 is electrically connected to the third metal part 208-3 of the upper DBC substrate through the lower second metal part 103-2 of the upper DBC substrate with a narrower width by the first metal pad 114, and after a circle, it is electrically connected to the lower fourth metal part 103-4 of the lower DBC substrate through the second metal pad 112, and then reaches the vicinity of the lower bridge arm passive semiconductor chip to realize electrical connection with the first AC power terminal;

[0073] The collector or drain of the lower bridge arm active semiconductor chip is electrically connected to the upper second metal part 103-2 of the upper DBC substrate through the upper first metal part 208-1 of the narrower upper DBC substrate by the third metal gasket 111, and after making a circle, it is electrically connected to the upper third metal part 208-3 of the lower DBC substrate through the fourth metal gasket 113, and is electrically connected to the second AC power terminal near the upper bridge arm active semiconductor chip. The routing is as close to and parallel to the metal layer connected to the first AC power terminal as possible.

[0074] The parasitic inductance of the first commutation loop includes the DC positive power terminal 205 itself, the upper first metal part 208-1 from the DC positive power terminal 205 to the collector or drain of the upper bridge arm active semiconductor chip 206, the first main metal pad 207 itself, the lower second metal part 103-2 from the first main metal pad 207 to the cathode of the lower bridge arm passive chip 107, the fourth main metal pad 108 itself, the upper fourth metal part 208-4 from the fourth main metal pad 108 to the DC negative power terminal 204, and the parasitic inductance and mutual inductance of the DC negative power terminal 204 itself;

[0075] The parasitic inductance of the second commutation loop includes the DC positive power terminal 205 itself, the upper first metal part 208-1 from the DC positive power terminal 205 to the cathode of the upper bridge arm passive semiconductor chip 202, the second main metal gasket 201 itself, the lower first metal part 103-1 from the second main metal gasket 201 to the collector or drain of the lower bridge arm active chip 102, the third main metal gasket 101 itself, the upper fourth metal part 208-4 from the third main metal gasket 101 to the DC negative power terminal 204, and the parasitic inductance and mutual inductance of the DC negative power terminal 204 itself; the first commutation loop and the second commutation loop reduce the loop impedance as much as possible by eliminating bonding wires, double-sided layout and other methods.

[0076] The parasitic inductance of the short-circuit current loop includes the DC positive power terminal 205 itself, the upper first metal part 208-1 from the DC positive power terminal 205 to the collector or drain of the upper bridge arm active semiconductor chip 206, the first main metal pad 207 itself, the lower second metal part 103-2 from the first main metal pad 207 to the first metal pad 114, the first metal pad 114 itself, the upper third metal part 208-3 from the first metal pad 114 to the second metal pad 112, the second metal pad 112 itself, the lower fourth metal part 103-4 from the second metal pad 112 to the first AC power terminal 106, the first AC power terminal 106 itself, the electrical connection part between the first AC power terminal 106 and the second AC power terminal 105, the second AC power terminal 105 itself, the second AC power terminal 105 to the fourth metal pad The lower third metal part 103-3 between the chips 113, the fourth metal gasket 113 itself, the upper second metal part 208-2 between the fourth metal gasket 113 and the third metal gasket 111, the third metal gasket 111 itself, the lower first metal part 103-1 from the third metal gasket 111 to the collector or drain of the lower bridge arm active semiconductor chip 102, the third main metal gasket 101 itself, the upper fourth metal part 208-4 from the third main metal gasket 101 to the DC negative power terminal 204, and the parasitic inductance and mutual inductance of the DC negative power terminal 204 itself; compared with the first and second commutation loops, the short-circuit current loop includes the first and second AC power terminals and the narrow copper layer to reach the two components, and by making full use of the side-by-side routing of the mutual inductance, the parasitic inductance value can be increased by 5 to 10 times, effectively reducing the rising rate and amplitude of the short-circuit fault current.

[0077] Under the structure of the optional embodiment of this figure, the inductance value of the first commutation loop extracted by Q3D is 29nH, the inductance value of the second commutation loop is 44nH, the inductance value of the short-circuit current loop is 320nH, and the parasitic inductance value of the short-circuit current loop is 8 to 10 times that of the commutation loop, which will greatly suppress the short-circuit current rise rate and peak value. A metal busbar connection is required between the first AC power terminal 106 and the second AC power terminal 105, and protective elements such as fuses and positive temperature coefficient resistors can be connected in series when necessary to further enhance the short-circuit current tolerance.

[0078] In order to better illustrate the advantages of the structural layout using its own mutual inductance, such as Fig.10 As shown, the cross-sectional area is 1mm 2 , a 20mm long copper wire, the parasitic inductance L extracted in Q3D is 13.1nH; Fig.11 As shown, copper wires of the same specification are placed side by side with a spacing of 1mm and the same direction of current is passed. The extracted self-inductance L1 is 12.9nH and the mutual inductance M12 is 8.4nH, the total parasitic inductance L1+M 12 is 21.3nH; Fig.12 As shown, copper wires of the same specification are placed side by side with a spacing of 1mm and a reverse current is passed through. The extracted self-inductance L1 is 12.9nH and the mutual inductance M 12 is -8.4nH, the total parasitic inductance L1+M 12 Compared with the traditional module design, this embodiment not only has a longer short-circuit current path to increase the short-circuit loop impedance, but also makes full use of the principle of increasing the mutual inductance of the same-direction current to increase the short-circuit loop impedance by more than 60%.

[0079] In a specific implementation of the present invention, the materials of the active semiconductor chip and the passive semiconductor chip include but are not limited to silicon, silicon carbide or gallium nitride; the materials of the power terminal, the metal busbar, the inner metal layer and the outer metal layer of the DBC substrate include but are not limited to copper; the material of the metal gasket includes but is not limited to molybdenum; the insulating sealing material between the upper and lower DBC substrates includes but is not limited to silicone or epoxy resin.

[0080] In the description of the present invention, a series of terms describing directions, such as "upper", "lower", "left", "right", "inner", "outer", etc., all represent directions or positional relationships based on the drawings.

[0081] The above description is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. All deformations directly derived or associated with the technical scope disclosed in the present disclosure by any technician familiar with the technical field should be included in the protection scope of the present disclosure.

Claims

1. A double-sided heat dissipation power module with high short-circuit current tolerance, characterized in that: It includes a power terminal, an active semiconductor chip, a passive semiconductor chip, an upper DBC substrate, a lower DBC substrate, and a metal gasket; The power terminals include a DC positive power terminal (205), a DC negative power terminal (204), a first AC power terminal (106), and a second AC power terminal (105); wherein the DC positive power terminal (205) is close to the second AC power terminal (105), and the DC negative power terminal (204) is close to the first AC power terminal (106); The active semiconductor chip comprises an upper bridge arm active semiconductor chip (206) and a lower bridge arm active semiconductor chip (102), and the passive semiconductor chip comprises an upper bridge arm passive semiconductor chip (202) and a lower bridge arm passive semiconductor chip (107); The upper DBC substrate and the lower DBC substrate are placed opposite to each other, and include an inner metal layer, an insulating layer and an outer metal layer, wherein the insulating layer is located between the inner metal layer and the outer metal layer, and the outer metal layer is used for heat dissipation; the inner metal layer (208) of the upper DBC substrate includes an upper first metal part (208-1), an upper second metal part (208-2), an upper third metal part (208-3), and an upper fourth metal part (208-4), and the four parts are independent and unconnected; the inner metal layer (103) of the lower DBC substrate includes a lower first metal part (103-1), a lower second metal part (103-2), a lower third metal part (103-3), and a lower fourth metal part (103-4), and the four parts are independent and unconnected; The upper first metal part (208-1) of the upper DBC substrate is welded with an upper bridge arm active semiconductor chip (206), an upper bridge arm passive semiconductor chip (202) and a DC positive power terminal (205), and the upper fourth metal part (208-4) is welded with a DC negative power terminal (204); the lower first metal part (103-1) of the lower DBC substrate is welded with a lower bridge arm active semiconductor chip (102), the lower second metal part (103-2) is welded with a lower bridge arm passive semiconductor chip (107), the lower third metal part (103-3) is welded with a second AC power terminal (105), and the lower fourth metal part (103-4) is welded with a first AC power terminal (106); The metal gasket comprises a main metal gasket and a secondary metal gasket, the main metal gasket comprises a first main metal gasket (207), a second main metal gasket (201), a third main metal gasket (101), and a fourth main metal gasket (108), and the secondary metal gasket comprises a first metal gasket (114), a second metal gasket (112), a third metal gasket (111), and a fourth metal gasket (113); the first main metal gasket (207) is mounted on the upper bridge arm active semiconductor chip (206), and the second main metal gasket (201) is mounted on the upper bridge arm passive semiconductor chip ( 202), the third main metal gasket (101) is mounted on the lower bridge arm active semiconductor chip (102), and the fourth main metal gasket (108) is mounted on the lower bridge arm passive semiconductor chip (107); the first metal gasket (114), the second metal gasket (112), the third metal gasket (111), and the fourth metal gasket (113) are respectively mounted on the lower second metal part (103-2), the lower fourth metal part (103-4), the lower first metal part (103-1), and the lower third metal part (103-3) of the lower DBC substrate; The collector or drain of the upper bridge arm active semiconductor chip (206) and the cathode of the upper bridge arm passive semiconductor chip (202) are electrically connected to the DC positive power terminal (205) through the upper first metal part (208-1) of the upper DBC substrate; the emitter or source of the upper bridge arm active semiconductor chip (206) is connected to the lower second metal part (103-2) of the lower DBC substrate through the first main metal pad (207) to achieve electrical connection with the cathode of the lower bridge arm passive semiconductor chip (107); the anode of the upper bridge arm passive semiconductor chip (202) is connected to the lower second metal part (103-2) of the lower DBC substrate through the second ... The metal gasket (201) is connected to the lower first metal part (103-1) of the lower DBC substrate to realize electrical connection with the collector or drain of the lower bridge arm active semiconductor chip (102); the emitter or source of the lower bridge arm active semiconductor chip (102) and the anode of the lower bridge arm passive semiconductor chip (107) are connected to the upper fourth metal part (208-4) of the upper DBC substrate through the third main metal gasket (101) and the fourth main metal gasket (108), respectively, and are electrically connected to the DC negative power terminal (204) through the upper fourth metal part (208-4); The two ends of the upper third metal part (208-3) of the upper DBC substrate are respectively electrically connected to the first metal pad (114) and the second metal pad (112), and the two ends of the upper second metal part (208-2) are respectively electrically connected to the third metal pad (111) and the fourth metal pad (113); The upper third metal part (208-3) and the upper second metal part (208-2) of the upper DBC substrate are parallel and close elongated copper layers; one end of the upper third metal part (208-3) is connected to the second metal gasket (112), and the other end is connected to the first metal gasket (114); one end of the upper second metal part (208-2) is connected to the third metal gasket (111), and the other end is connected to the fourth metal gasket (113); the first metal gasket (114) and the fourth metal gasket (113) are used to transmit the short-circuit current of the lower DBC substrate to a pair of parallel and close elongated copper layers on the upper DBC substrate, and then the third metal gasket (111) and the second metal gasket (112) transmit the short-circuit current to the lower DBC substrate; the short-circuit current flows in the same direction through the upper third metal part (208-3) and the upper second metal part (208-2) of the upper DBC substrate.

2. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1, characterized in that: The design method of the parallel and close elongated copper layers is as follows: Determine the rated voltage level, rated current level, and current rise rate parameters of the double-sided heat dissipation power module to be designed; determine the copper thickness according to the typical value of the DBC substrate, determine the minimum copper width according to the rated current level, and determine the minimum insulation spacing according to the rated voltage level; estimate the parasitic inductance of the short-circuit current loop based on 5 to 10 times the expected parasitic inductance of the commutation loop of the double-sided heat dissipation power module; use the finite element analysis method to establish the relationship between the parasitic inductance and the length of the parallel slender copper layer for iterative optimization.

3. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1, characterized in that: The upper third metal part (208-3) and the upper second metal part (208-2) of the upper DBC substrate are spiral structures.

4. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1, characterized in that: The upper first metal part (208-1) and the upper fourth metal part (208-4) of the upper DBC substrate are wide rectangular copper layers, which are arranged on both sides of the upper third metal part (208-3) and the upper second metal part (208-2); the current path width of the rectangular structure is 2-20 times the current path width of the upper third metal part (208-3) and the upper second metal part (208-2).

5. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1, characterized in that: The lower third metal part (103-3) and the lower fourth metal part (103-4) of the lower DBC substrate are elongated copper layer structures; one end of the lower third metal part (103-3) is welded with a fourth metal gasket (113), and the other end is welded with a second AC power terminal (105); one end of the lower fourth metal part (103-4) is welded with a second metal gasket (112), and the other end is welded with a first AC power terminal (106).

6. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1 or 5, characterized in that: The lower first metal part (103-1) of the lower DBC substrate comprises a wide rectangular copper layer and a slender copper layer, the lower bridge arm active semiconductor chip (102) is welded to one end of the wide rectangular copper layer, and the end is connected to one end of the slender copper layer, the other end of the slender copper layer is welded with a third metal gasket (111), and the second main metal gasket (201) is connected to the other end of the wide rectangular copper layer; the slender copper layer of the lower first metal part (103-1) is parallel to and close to the lower fourth metal part (103-4).

7. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1 or 5, characterized in that: The lower second metal part (103-2) of the lower DBC substrate comprises a wide rectangular copper layer and a slender copper layer, the first main metal pad (207) is connected to one end of the wide rectangular copper layer, and the end is connected to one end of the slender copper layer, the other end of the slender copper layer is welded with a first metal pad (114), and the lower bridge arm passive semiconductor chip (107) is welded to the other end of the wide rectangular copper layer; the slender copper layer of the lower second metal part (103-2) is parallel to and close to the lower third metal part (103-3).

8. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1, characterized in that: The double-sided heat dissipation power module comprises a first commutation circuit and a second commutation circuit; The first commutation loop is composed of the DC positive power terminal (205), the upper bridge arm active semiconductor chip (206), the lower bridge arm passive semiconductor chip (107) and the DC negative power terminal (204), and the second commutation loop is composed of the DC positive power terminal (205), the upper bridge arm passive semiconductor chip (202), the lower bridge arm active semiconductor chip (102) and the DC negative power terminal (204).

9. The double-sided heat dissipation power module with high short-circuit current tolerance according to claim 1, characterized in that: The first AC power terminal (106) and the second AC power terminal (105) are connected to a metal busbar or a protective element outside the power module; the short-circuit current flows through the DC positive power terminal (205), the upper bridge arm active semiconductor chip (206), the first main metal gasket (207), the first metal gasket (114), the second metal gasket (112), and the first AC power terminal (106); the first AC power terminal (106) is connected to the second AC power terminal (105) through the external metal busbar or the protective element; the short-circuit current continues to flow through the second AC power terminal (105) through the fourth metal gasket (113), the third metal gasket (111), the lower bridge arm active semiconductor chip (102), the third main metal gasket (101), and the DC negative power terminal (204).

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