Folded cascaded operational amplifiers, amplifier circuits and their operation methods

Abstract

A first embodiment relates to an amplifier circuit including a positive bias circuit having a driving PMOS biased in subthreshold mode, a negative bias circuit having a driving NMOS biased in subthreshold mode, and an amplification circuit coupled to the bias circuit. The amplification circuit includes a first stage having a first boost stage, a second stage having a second boost stage, and a resistive element coupled between the first and second stages. A second embodiment relates to a folded cascaded operational amplifier, wherein the value of the resistive element is selected to place at least one of the driving MOS in subthreshold mode. A third embodiment relates to an integrated circuit having a resistive region adjacent to a first boost region and a second boost region, the resistive region including a resistive element directly connected to the driving PMOS and the driving NMOS. Embodiments of this application also relate to a folded cascaded operational amplifier and a method of operating the amplifier circuit.

Description

Technical Field

[0001] This disclosure relates to a folded cascaded operational amplifier, an amplifier circuit, an integrated circuit implementing the amplifier circuit, and a method of operating the same. Background Technology

[0002] An operational amplifier (op-amp) is a high-gain electronic voltage amplifier circuit with differential inputs and one or more outputs. The output potential produced by an op-amp is typically thousands of times larger than the potential difference between its input terminals. Op-amps can be used in various amplification modes, including but not limited to linear amplification, nonlinear amplification, and / or frequency-dependent amplification. Furthermore, op-amps are used as building blocks in a wide range of applications in both analog and digital circuits. Moreover, because op-amps can be tuned for specific operations using external components, they are well-suited for custom operation. For example, the gain, input, output, impedance, and bandwidth of an op-amp can be customized using external components.

[0003] Operational amplifiers can be implemented in integrated circuits with specific configurations of active and / or passive electronics. For example, operational amplifiers can be fabricated within an integrated circuit using transistor networks configured for high-gain conversion. Such operational amplifiers can be used for on-chip amplification, noise reduction, and other signal processing operations for weak signals. For instance, operational amplifiers in integrated circuits can be used to filter and amplify signals input to processing and / or logic circuits within the integrated circuit. Operational amplifiers in integrated circuits can utilize BJT and / or CMOS technologies and can be cascaded to adjust gain, operating frequency, and signal phase.

[0004] The disclosed systems, apparatuses, and methods for operational amplifiers and integrated circuits are designed to address one or more problems or challenges in the prior art. Summary of the Invention

[0005] According to one aspect of an embodiment of this application, an amplifier circuit is provided, comprising: a positive bias circuit coupled to a power supply node and including a driving PMOS, the driving PMOS being used for biasing in a subthreshold region; a negative bias circuit coupled to a ground node and including a driving NMOS, the driving NMOS being used for biasing in a subthreshold region; and an amplification circuit (280) coupled to the positive bias circuit and the negative bias circuit. The amplification circuit includes: a first stage including a PMOS transistor and a first boost stage, one of the PMOS transistors being coupled to the driving PMOS; a second stage including an NMOS transistor and a second boost stage, one of the NMOS transistors being coupled to the driving NMOS; a resistive element coupled between the first stage and the second stage; and an output node connected to the first stage and the second stage.

[0006] According to another aspect of the embodiments of this application, a folded cascaded operational amplifier is provided, comprising: a positive bias circuit coupled to a power supply node and including a driving PMOS; a negative bias circuit coupled to a ground node and including a driving NMOS; a differential input circuit coupled to the positive bias circuit and the negative bias circuit; and an amplification circuit coupled to the positive bias circuit and the negative bias circuit. The amplification circuit includes: a first stage coupled to the driving PMOS; a second stage coupled to the driving NMOS; and a resistive element coupled between the first stage and the second stage, the resistive element being directly connected to the gates of the driving PMOS and the driving NMOS, wherein the value of the resistive element is selected to place at least one of the driving PMOS or the driving NMOS in the subthreshold region.

[0007] According to another aspect of the embodiments of this application, a method for operating an amplifier circuit is provided, comprising: configuring a first transistor of the amplifier circuit to operate in a saturation region, the first transistor being directly connected to a driving PMOS transistor connected to a power supply node; configuring a second transistor of the amplifier circuit to operate in a saturation region, the second transistor being directly connected to a driving NMOS transistor coupled to a ground node, the PMOS transistor being connected to the second transistor via a resistive element; supplying power to the amplifier circuit with a power supply voltage proportional to the sum of the voltage drop of the driving PMOS transistor, the voltage drop of the resistive element (270), and the voltage drop of the driving NMOS transistor, the power supply voltage being at least twice the sum of the threshold voltage of the first transistor and the overdrive voltage of the first transistor; inputting an input signal at a differential input circuit of the amplifier circuit, the differential input circuit including an NMOS transistor and a PMOS transistor; and receiving an output signal proportionally from the output node of the amplifier, the output signal being the input signal multiplied by the gain of the amplifier circuit. Attached Figure Description

[0008] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the components may be arbitrarily increased or decreased.

[0009] Figure 1 A circuit diagram of a duty cycle corrector (DCC) with a synchronous input clock is shown according to some embodiments of the present disclosure.

[0010] Figure 2 A circuit diagram of an exemplary operational amplifier according to some embodiments of the present disclosure is shown.

[0011] Figure 3A A circuit diagram illustrating an exemplary configuration of a driving transistor using a resistor according to some embodiments of the present disclosure is shown.

[0012] Figure 3BA circuit diagram illustrating an exemplary configuration of a driving transistor using a transistor according to some embodiments of the present disclosure is shown.

[0013] Figure 3C A circuit diagram illustrating an exemplary configuration of a driving transistor using a diode according to some embodiments of the present disclosure is shown.

[0014] Figure 4A A circuit diagram illustrating an exemplary configuration of an operational amplifier using a variable resistor according to some embodiments of the present disclosure is shown.

[0015] Figure 4B A circuit diagram illustrating an exemplary configuration of an operational amplifier using transistors according to some embodiments of the present disclosure is shown.

[0016] Figure 5A A circuit diagram of a first exemplary boost stage according to some embodiments of the present disclosure is shown.

[0017] Figure 5B A circuit diagram of a second exemplary boost stage according to some embodiments of the present disclosure is shown.

[0018] Figure 6A A circuit diagram of an exemplary boost stage using a resistive load is shown according to some embodiments of the present disclosure.

[0019] Figure 6B A circuit diagram of an exemplary boost stage using an inductive load is shown according to some embodiments of the present disclosure.

[0020] Figure 6C A circuit diagram of an exemplary boost stage using an active load is shown according to some embodiments of the present disclosure.

[0021] Figure 6D A circuit diagram of an exemplary boost stage using an active PMOS diode load is shown according to some embodiments of the present disclosure.

[0022] Figure 6E A circuit diagram of an exemplary boost stage using an active NMOS diode load is shown according to some embodiments of the present disclosure.

[0023] Figure 7 A circuit diagram is shown for a first exemplary amplifier with active load and resistive coupling for subthreshold bias, according to some embodiments of the present disclosure.

[0024] Figure 8 A circuit diagram of a second exemplary amplifier using a coupling resistor for subthreshold bias is shown according to some embodiments of the present disclosure.

[0025] Figure 9A An exemplary schematic diagram showing a first layout plan view of an integrated circuit according to some embodiments of the present disclosure.

[0026] Figure 9B An exemplary schematic diagram showing a second layout plan view of an integrated circuit according to some embodiments of the present disclosure.

[0027] Figure 10 A flowchart illustrating an exemplary method of operation of an amplifier circuit according to some embodiments of the present disclosure is provided. Detailed Implementation

[0028] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements will be described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein can be interpreted accordingly.

[0030] Furthermore, connectivity terms such as “connection,” “coupling,” “joining,” and “attachment” may be used herein for descriptive convenience to describe connections that are electrical, electromagnetic, radio frequency, or ultrasonic. Additionally, connectivity terms may indicate general electrical or magnetic communication between components. These connectivity terms may indicate a direct connection (i.e., two components connected without any intermediate elements) or an indirect connection (i.e., two components connected via one or more intermediate elements).

[0031] Figure 1A circuit diagram of a duty cycle corrector (DCC) 100 with a synchronous input clock is shown according to some embodiments of the present disclosure. In some embodiments, the DCC 100 can be configured to adjust the clock duty cycle to a selected percentage. For example, the DCC 100 can be configured to adjust the clock duty cycle to modify the clock signal used for double data rate (DDR), half-rate clock data recovery (CDR), and / or delay-locked loop (DLL). In some embodiments, the DCC 100 can be used in applications using multiphase clocks, MUX / DEMUX circuitry, or other circuitry with fixed rise edge requirements. The DCC 100 can be used in analog, semi-digital, and / or digital applications.

[0032] The DCC 100 includes a clock input CLK_IN 114, which can be connected to external input circuitry to transmit input signals to be modified and / or corrected. The DCC 100 also includes differential inputs for signals CKP 102 and CKN 104. Figure 1 In this embodiment, signals CKP 102 and CKN 104 are generated by operational amplifiers in DCC 100. In such an embodiment, as further discussed below, CKP 102 is generated by inverter 126 and CKN 104 is generated by inverter 128. Furthermore, CKP 102 and CKN 104 can be used as feedback signals. Therefore, as... Figure 1 As shown, inputs CKP 102 and CKN 104 are connected to amplifier 200, and the amplifier is connected to power node PWD_DCC 106. Combined Figure 2 Further discussion on amplifier 200.

[0033] like Figure 1 As shown, the output of amplifier 200 is coupled to a first control stage 108. The first control stage 108 includes a first coupled CMOS transistor 108A, a second coupled CMOS transistor 108C, and a first connection node 108B. The first coupled CMOS transistor 108A is connected to the output of amplifier 200, the first connection node 108B is connected to a first reset control signal RSTB1 110, and the second coupled transistor 108C is connected to a first connection control signal tie0 112. Figure 1 In this configuration, when the output of amplifier 200 and the input of signal tie0 112 are connected to the drain / source of the first coupled CMOS transistor 108A and the second coupled CMOS transistor 108C, signal RSTB1 110 is coupled to the first connection node 108B. Furthermore, the first coupled CMOS transistor 108A and the second coupled CMOS transistor 108C can be coupled together through their respective gates.

[0034] DCC 100 includes a second control stage 122, configured similarly to the first control stage 108 described above. In some embodiments, such as Figure 1 As shown, the second control stage 122 includes a third coupled CMOS transistor 122A, a fourth coupled CMOS transistor 122C, and a second connection node 122B. The third coupled CMOS transistor 122A is coupled to a control node 116. Although not shown, the control node 116 may be coupled to the output of another amplifier, similar to amplifier 200. However, in other embodiments, the control node 116 may be connected to another circuit and / or electronic device. The second connection node 122B is coupled to a second reset control signal RSTB2 118, and the fourth coupled CMOS transistor 122C is coupled to receive a second connection control signal tie1 120. Similar to the connections in the first control stage 108, the inputs of the control node 116 and the signal tie1 120 are connected to the drain / source nodes of the third coupled CMOS transistor 122A and the fourth coupled CMOS transistor 122C, while the signal RSTB2 118 is connected to the second connection node 122B.

[0035] The DCC 100 also includes a correction stage 124 coupled to the inputs of the first control stage 108, the second control stage 122, and the signal CLK_IN 114. The correction stage 124 includes a first PMOS transistor 124A, a second PMOS transistor 124B, a first NMOS transistor 124C, and a second NMOS transistor 124D. (The text repeats itself here.) Figure 1 As shown, transistors 124A and 124D are coupled in series. Also as... Figure 1 As shown, the first PMOS transistor 124A is coupled to a power node, which in some embodiments may be the same node as PWD_DCC 106. The second NMOS transistor 124D is connected to a ground node. The gate of the first PMOS transistor 124A is coupled to the drain / source of the first coupled CMOS transistor 108A and the second coupled CMOS transistor 108C. The gate of the first NMOS transistor 124C is coupled to the drain / source of the third coupled CMOS transistor 122A and the fourth coupled CMOS transistor 122C. Furthermore, the gates of the second PMOS transistor 124B and the first NMOS transistor 124C are shorted, as shown... Figure 1 As shown, and the gate is shorted to receive the signal CLK_IN 114. (As...) Figure 1As shown, the second PMOS transistor 124B and the first NMOS transistor 124C provide the output of the correction stage 124. For example, the drain / source nodes of the second PMOS transistor 124B and the first NMOS transistor 124C provide the output of the correction stage 124. This configuration of the correction stage 124 can operate as a buffer and / or charge pump to modify the CLK_IN 114 signal. The correction stage 124 can also be configured as an integrator and / or corrector for CLK_IN 114.

[0036] The output of correction stage 124 is coupled to a series of inverters that generate the output signal CLK_OUT 136. For example, as... Figure 1 As shown, the output of correction stage 124 (with the drain / source node of a transistor with a shorted gate) is connected to first inverter 126. The output of first inverter 126 can provide a differential output. In some embodiments, the output of first inverter 126 can be used as feedback by routing to CKP 102. First inverter 126 is connected in series with second inverter 128. The output of second inverter 128 can also be used as series feedback routed to CKP.

[0037] DCC 100 also includes a third inverter 130 connected in series with the second inverter 128. However, unlike the first inverter 126 and the second inverter 128, the output of the third inverter 130 is the output of DCC 100.

[0038] In some embodiments, inverters 126, 128, and 130 can be configured to also provide gain and / or attenuation. Furthermore, in some embodiments, inverters 126, 128, and 130 can be implemented using amplifiers similar to amplifier 200, which will combine... Figure 2 Further discussion.

[0039] Figure 2 A circuit diagram illustrating an exemplary embodiment of an amplifier 200 according to some embodiments of the present disclosure is shown. (As in conjunction with...) Figure 1 In some embodiments discussed, amplifier 200 is part of DCC 100. For example, amplifier 200 may be used to receive a differential clock signal for duty cycle modification and / or correction. However, amplifier 200 may be used for other applications unrelated to DCC 100. For example, amplifier 200 may be used as a differential amplifier, an inverting amplifier (e.g., Figure 1 The first inverter 126 in the circuit) and the non-inverting amplifier. In some embodiments, such as Figure 2 As shown, amplifier 200 is configured as a folded cascaded amplifier. However, in other embodiments, the elements of amplifier 200 may be reconfigured to have a non-folded cascaded configuration.

[0040] Amplifier 200 includes a positive bias circuit 210 and a negative bias circuit 230. Amplifier 200 also includes a differential input circuit 220. Amplifier 200 also includes a first stage 250 and a second stage 260, which together form an amplifier circuit 280 that provides differential amplification in amplifier 200.

[0041] The positive bias circuit 210 can provide voltage and / or current for the operation of amplifier 200. For example... Figure 2 As shown, the forward bias circuit 210 includes a plurality of PMOS transistors. However, in other embodiments, the forward bias circuit 210 may have alternative transistors, such as BJT transistors and / or NMOS transistors.

[0042] The transistors in the forward bias circuit 210 include a first bias PMOS transistor 211, a second bias PMOS transistor 213, and a driving PMOS transistor 212. (See below for details.) Figure 3A , Figure 3B and Figure 7 Further discussion reveals that the driving PMOS transistor 212 can be configured to be biased in the subthreshold region. The threshold voltage of the driving PMOS transistor 212 can be determined by the MOSFET threshold voltage equation, such as... Where V t It is the threshold voltage, V FB It is the flat-band voltage of the transistor. It is the surface potential, ∈ s It is the relative permittivity, q is the elementary charge, and N is the relative permittivity. a It is the doping concentration, V SB It is source-bulk substrate bias, C ox It is the effective capacitance. The size, doping characteristics, and processing of the driving PMOS transistor 212 can be selected to enable the driving PMOS transistor 212 to operate in the subthreshold region when the amplifier 200 is turned on. In some embodiments, for example, the W / D and C of the PMOS transistor 212 ox Doping and V FB It was selected for subthreshold operation in amplifier 200.

[0043] like Figure 2 As shown, the gates of the first bias PMOS transistor 211, the second bias PMOS transistor 213, and the driving PMOS transistor 212 are directly connected. Furthermore, the first bias PMOS transistor 211, the second bias PMOS transistor 213, and the driving PMOS transistor 212 in the positive bias circuit 210 are connected to a power node 214 that provides a voltage and / or current source. For example, in some embodiments, the power node 214 may be connected to PWD_DCC 106 (…). Figure 1The same nodes. The first bias PMOS transistor 211, the second bias PMOS transistor 213, and the drive PMOS transistor 212 in the positive bias circuit 210 are also connected to other stages or devices in the amplifier 200. For example, the first bias PMOS transistor 211 and the drive PMOS transistor 212 may be connected to the differential input circuit 220 and the first stage 250.

[0044] Figure 2 An embodiment of a forward bias circuit 210 with three PMOS transistors is shown. Other embodiments, not shown, may use alternative configurations of transistors in the forward bias circuit 210. For example, the forward bias circuit 210 may include four or more transistors, which may include CMOS or BJT transistors. Alternatively or additionally, the forward bias circuit 210 may include alternative three-terminal devices, such as vacuum tubes or other semiconductor devices.

[0045] Similar to the positive bias circuit 210, the negative bias circuit 230 includes transistors directly connected to the differential input circuit 220. However, instead of being connected to the first stage 250, the transistors in the negative bias circuit 230 are also connected to the second stage 260. Furthermore, the transistors in the negative bias circuit 230 include multiple NMOS transistors. However, in other embodiments, the negative bias circuit 230 may have alternative transistors. For example, the negative bias circuit 230 may include four or more transistors, which may include CMOS and BJT transistors. Alternatively or additionally, the negative bias circuit 230 may alternatively include three-terminal devices, such as vacuum tubes or other semiconductor devices.

[0046] The transistors in the negative bias circuit 230 include a driving NMOS transistor 232, a first bias NMOS transistor 231, and a second bias NMOS transistor 233. Similar to the driving PMOS transistor 212, the driving NMOS transistor 232 can be configured to be biased in the subthreshold region. For example, the size, oxide, doping, and bias circuitry of the driving NMOS transistor 232 can be selected for biasing in the subthreshold region when the amplifier 200 is turned on or operating. In some embodiments, for example, the W / D and C of the NMOS transistor 232... ox Doping and V FB It was selected for subthreshold operation in amplifier 200.

[0047] like Figure 2As shown, the gates of the driving NMOS transistor 232, the first bias NMOS transistor 231, and the second bias NMOS transistor 233 are shorted. Furthermore, the transistors in the negative bias circuit 230 are connected to ground node 234. In some embodiments, ground node 234 may be the same node as the ground node in DCC 100. The driving NMOS transistor 232, the first bias NMOS transistor 231, and the second bias NMOS transistor 233 are also connected to other stages or transistors in the amplifier 200. For example, some transistors in the negative bias circuit 230 may be connected to the differential input circuit 220 and the second stage 260.

[0048] The differential input circuit 220 includes a plurality of transistors connected to either the first amplifier input VIP 202 or the second amplifier input VIN 204. In some embodiments, VIP 202 and VIN 204 may be connected to external components. For example, VIP 202 and VIN 204 may be coupled to a capacitor and / or a resistor and receive an input signal. In some embodiments, such as Figure 1 As shown, the inputs of amplifier 200, VIP 202 and VIN 204, receive signals CKP 102 and CKN 104, respectively.

[0049] like Figure 2 As shown, the transistors in the differential input circuit 220 include both NMOS and PMOS transistors. For example, the differential input circuit 220 includes NMOS transistors 222A and 222B and PMOS transistors 224A and 224B. NMOS transistors 222A and 222B can be matched transistors. That is, NMOS transistors 222A and 222B can have the same size, C ox The NMOS transistors 222A and 222B can be configured to operate in the same bias region and under similar voltage and current conditions. However, in other embodiments, the NMOS transistors 222A and 222B can be independent and configured with different W / D or different bias circuit configurations.

[0050] Similar to the NMOS portion of the differential input circuit 220, PMOS transistors 224A and 224B can also be matched transistors. For example, PMOS transistors 224A and 224B can have the same dimensions, C ox The PMOS transistors 224A and 224B are doped and biased. Furthermore, the PMOS transistors 224A and 224B can be configured to operate in the same or similar bias regions. However, in other embodiments, the PMOS transistors 224A and 224B can be independent and configured with different W / D or different bias circuit configurations.

[0051] like Figure 2 As shown, the gate of each of NMOS transistor 222A and PMOS transistor 224A is coupled to VIP 202. Conversely, the gate of each of NMOS transistor 222B and PMOS transistor 224B is coupled to VIN 204. The resulting differential input configuration enables the reception of differential signals to be amplified. For example, in some embodiments, VIP 202 and VIN 204 may correspond to signals from DCC 100 (… Figure 1 CKP 102 and CKN 104. In such an embodiment, the differential input circuit 220 may be connected to the input and / or feedback in DCC 100.

[0052] Furthermore, the drain / source terminals of the transistors in the differential input circuit 220 are directly connected to other components of the amplifier 200. For example, NMOS transistor 222A is directly connected to drive PMOS transistor 212 and NMOS transistor 222B. Conversely, NMOS transistor 222B is directly connected to the PMOS transistor in the positive bias circuit 210. Both PMOS transistors 224A and 224B are directly connected to the first bias PMOS transistor 211 in the positive bias circuit 210, while PMOS transistor 224A is directly connected to drive NMOS transistor 232 and the first bias NMOS transistor 231 in the negative bias circuit 230.

[0053] Figure 2 The diagram shows a configuration of a differential input circuit 220 with two NMOS and two PMOS transistors. However, other configurations are possible for the differential input circuit 220. For example, the differential input circuit 220 can be implemented using BJT transistors. Alternatively or additionally, the differential input circuit 220 can be implemented using other three-terminal devices. Furthermore, instead of four transistors, the differential input circuit 220 can have different arrangements, including more transistors, unpaired transistors, and / or a mixture of transistor types. Furthermore, the differential input circuit 220 can be connected to other components in the amplifier 200 to enable the capture of the differential input to be amplified. For example, as... Figure 2 As shown, the differential input circuit 220 is coupled to the positive bias circuit 210 and the negative bias circuit 230.

[0054] The first stage 250 is coupled to the positive bias circuit 210 and the second stage 260 via a resistor element 270. The first stage 250 includes a PMOS transistor 254, which includes a first PMOS transistor 254A and a second PMOS transistor 254B. In some embodiments, the first PMOS transistor 254A and the second PMOS transistor 254B are of the same size, C... oxMatching transistors for doping and biasing circuitry. In other embodiments, the first PMOS transistor 254A and the second PMOS transistor 254B are independent transistors. The first stage 250 also includes a first boost stage 252. Figure 2 As shown, the first boost stage 252 is connected to the gate of PMOS transistor 254. Furthermore, the drain / source node of PMOS transistor 254A is connected in series with and to the gate of driving PMOS transistor 212. PMOS transistor 254B is directly connected between the drain / source of NMOS transistor 222B (which is coupled to VIN204) and the output node 282 of amplifier 200.

[0055] In addition to being connected to PMOS transistor 254, the first boost stage 252 can also be directly connected to the transistors in the forward bias circuit 210. For example, the first boost stage 252 is also connected to the drain / source of the driving PMOS transistor 212 and to the drain / source of the second bias PMOS transistor 213 in the forward bias circuit 210. Furthermore, the first boost stage 252 can be directly connected to the respective gates of the first PMOS transistor 254A and the second PMOS transistor 254B.

[0056] The second stage 260 has a configuration similar to the first stage 250. However, instead of being coupled to the positive bias circuit 210, the second stage 260 is coupled to the negative bias circuit 230. Furthermore, instead of having a PMOS transistor 254, the second stage 260 has an NMOS transistor 264. The second stage 260 includes the NMOS transistor 264, which includes a first NMOS transistor 264A and a second NMOS transistor 264B. The second stage 260 also includes a second boost stage 262. Similar to the first boost stage 252, the second boost stage 262 can be connected to the gate of the NMOS transistor 264. Furthermore, the drain / source of the NMOS transistor 264A is connected in series with the gates of the driving NMOS transistor 232 and the driving NMOS transistor 232. The NMOS transistor 264B is directly connected to the drain / source of the second bias NMOS transistor 233 in the negative bias circuit 230 and the PMOS transistor 254B. The shared node between the PMOS transistor 254B and the NMOS transistor 264B generates the output node 282.

[0057] In addition to being connected to NMOS transistor 264, the second boost stage 262 is also directly connected to the transistor in the negative bias circuit 230. The second boost stage 262 is also connected to the drain / source of the driving NMOS transistor 232 and the drain / source of the second bias NMOS transistor 233 in the negative bias circuit 230.

[0058] like Figure 2As shown, the first stage 250 is connected to the second stage 260 via a resistor element 270. Specifically, the drain / source of the PMOS transistor 254A is directly connected to the resistor element 270, and the resistor element is connected to the drain / source of the NMOS transistor 264A. Furthermore, the resistor element 270 is also connected to the gates of the driving PMOS transistor 212 and the driving NMOS transistor 232. Specifically, as... Figure 2 As shown, resistor 270 is connected to the gates of PMOS transistor 254A and driving PMOS transistor 212 at the same node. Therefore, the gate of driving PMOS transistor 212 is directly connected to the first terminal of resistor 270. Specifically, in some embodiments, the gate of driving NMOS transistor 232 is directly connected to the second terminal of resistor 270. Furthermore, resistor 270 is connected to the gates of NMOS transistor 264A and driving NMOS transistor 232 at the same node, which is different from the node connected to driving PMOS transistor 212.

[0059] Resistor element 270 in Figure 2 As shown, as a two-terminal element, it can include a resistor, capacitor, or inductor (or any combination thereof). However, in some embodiments, the resistive element 270 can include different types of devices. For example, the resistive element 270 can include a three-terminal device, such as a transistor or a controlled diode. For example, the resistive element 270 can include a transistor biased in transistor mode. In such embodiments, the resistive element 270 can be coupled to receive a control signal that allows selection of a specific resistance required for the operation of the amplifier 200. For example, in some embodiments, the resistive element 270 can be dynamically configured based on the operation of other elements in the amplifier 200. Furthermore, in some embodiments, such as in combination with... Figure 4B Further discussion reveals that the resistive element 270 includes a PMOS transistor, a resistor, and an NMOS transistor, wherein the PMOS transistor is connected in series with the resistor, and the resistor is connected in series with the NMOS transistor.

[0060] Figure 2The diagram shows a resistor element 270 that enables amplifier 200 to be configured for self-biased gain boost operation. For example, resistor element 270 can be selected to place each of the driving PMOS transistor 212 and the driving NMOS transistor 232 into subthreshold region operation. Therefore, in some embodiments, the value of resistor element 270 can be selected to set the gate voltage of the driving NMOS transistor 232 to operate in the subthreshold region, and to set the gate voltage of the driving PMOS transistor 212 to operate in the subthreshold region. By appropriately selecting the values ​​of the transistors and resistor element 270 in amplifier 200, one or more transistors in amplifier 200 can operate in the subthreshold region. This configuration provides several advantages to amplifier 200. For example, amplifier 200 requires a lower supply voltage (or Vdd) by operating in the subthreshold region compared to other amplifiers. Furthermore, amplifier 200 achieves higher DC gain by operating in the subthreshold region compared to other amplifiers. In particular, using a gain boost stage in amplifier 200 enables higher DC gain than other amplifiers.

[0061] In addition to the increased DC gain, amplifier 200 (such as Figure 2 (As shown) This also provides other operational advantages. For example, amplifier 200 reduces the number of external bias voltages compared to other folded cascaded amplifiers. Folded cascaded configurations require a large number of external bias voltages. This requirement leads to several limitations, especially when the amplifier is manufactured in an integrated circuit. For example, having multiple bias voltages results in area and power overhead, as well as sensitivity to crosstalk between bias lines and / or noise. Given the relationship between amplifier gain and noise sensitivity, the gain of other folded cascaded amplifiers is limited by practical considerations of signal-to-noise ratio (SNR). The configuration of amplifier 200 addresses these issues by providing a low-voltage (e.g., less than 2.5V), self-biased, and gain-boosting amplifier. The use of a resistive element 270 between the first stage 250 and the second stage 260 (each with its own boost stage) allows the transistors to operate in the subthreshold region, increasing amplifier gain and reducing the number of external bias lines, which translates to a smaller footprint, lower noise, and lower power consumption.

[0062] Furthermore, the detailed configuration of amplifier 200 can modify the gain spectrum compared to other operational amplifiers. By placing the driving NMOS transistor 232 and driving PMOS transistor 212 in the subthreshold region using the resistive element 270, the dynamic range of amplifier 200 can be improved, resulting in strong gain at both low and high input or output voltages. For example, the configuration shown for amplifier 200 produces greater gain at low input voltages (e.g., less than 100 mV), but also exhibits high gain for high input voltages (e.g., above 500 mV).

[0063] In addition to improved operational performance, the configuration of amplifier 200 also improves manufacturing requirements. For example, as combined with Figure 9A and Figure 9B Further discussion Figure 2 The circuitry and stage configurations shown allow for the configuration of specific regions with a smaller footprint, simpler wiring, and lower power consumption. Furthermore, the amplifier 200 is a versatile design and can be used across multiple technology nodes. For example, the amplifier 200 can be implemented in various manufacturing processes, including 3nm, 5nm, 7nm, 10nm, 16nm, and 20nm processes.

[0064] The operational and manufacturing advantages offered by amplifier 200 make it a good candidate for operational amplifiers in digital and / or analog circuits. For example, amplifier 200 can improve operation and / or facilitate the manufacture of DCC 100.

[0065] Figure 3A A circuit diagram is shown of an exemplary configuration 300 in which a resistor is implemented as a driving transistor of a resistive element 270 according to some embodiments of the present disclosure. In configuration 300, the resistive element 270 is implemented as a resistor 302. Figure 3A As shown, resistor 302 is used as a resistive element to create amplifier circuit 280. Figure 2 The circuit consists of a branch where the gate of the driving PMOS transistor 212 is coupled to one end of resistor 302, and the gate of the driving NMOS transistor 232 is coupled to one end of resistor 302. Furthermore, resistor 302 is also connected to transistors in the first stage 250 and the second stage 260. Specifically, one end of resistor 302 is coupled to PMOS transistor 254A, and the other end of resistor 302 is coupled to NMOS transistor 264A.

[0066] The configuration 300 using resistor 302 effectively reduces the gate-source voltages of both the driving NMOS transistor 232 and the driving PMOS transistor 212, allowing both to operate in the subthreshold region. That is, adding resistor 302 to the branch of amplifier circuit 280 results in a lower gate-source voltage in the driving transistors; such a lower voltage facilitates subthreshold operation and allows self-biasing. Therefore, appropriately selecting the value of resistor 302 can produce the advantages of amplifier 200 as described above.

[0067] Figure 3B A circuit diagram is shown of an exemplary configuration 350 of a drive transistor that implements a resistive element 270 according to some embodiments of the present disclosure. In configuration 350, the resistive element 270 is implemented as a transistor 304. Figure 3BAs shown, in some embodiments, transistor 304 is a PMOS device. However, in other embodiments, transistor 304 may be an NMOS device or a BJT device. Transistor 304 can be used as a controlled variable resistor. For example, the Vb applied to the gate of transistor 304 can be selected to put transistor 304 into a resistive or transistor operating mode. The equivalent resistance can be selected to place the driving PMOS transistor 212 and the driving NMOS transistor 232 in the subthreshold region. Amplifier circuit 280 is created using transistor 304 as a resistive element. Figure 2 The branch of the transistor 304 has a gate that drives the PMOS transistor 212, which is coupled to the source of the transistor 304, while the gate that drives the NMOS transistor 232 is coupled to the drain of the transistor 304. Furthermore, the transistor 304 is also connected to transistors in the first stage 250 and the second stage 260. Specifically, the source of the transistor 304 is coupled to the PMOS transistor 254A, and the drain of the transistor 304 is coupled to the NMOS transistor 264A.

[0068] In configuration 350, the bias condition of transistor 304 can be selected to reduce the gate-source voltages driving NMOS transistor 232 and PMOS transistor 212, allowing both to operate in the subthreshold region. That is, the combination of transistor 304 and the Vb applied to transistor operation yields an adjusted gate-source voltage in the driving transistor, which facilitates subthreshold operation and allows self-biasing. Therefore, appropriately selecting the value and bias of transistor 304 yields the advantages of amplifier 200 as described above.

[0069] Figure 3C A circuit diagram is shown of an exemplary configuration 380 of a drive transistor in which a diode is implemented as a resistive element 270 according to some embodiments of the present disclosure. In configuration 380, the resistive element 270 is implemented as a diode 306. Diode 306 may be a standard diode connected to a selected diode voltage drop required for forward bias and resistive operation. However, in other embodiments, diode 306 may be configured for reverse bias and the breakdown voltage may be selected for the equivalent resistance. In some embodiments, diode 306 may be implemented using a Zener diode and / or a Schottky diode. The equivalent resistance of diode 306 may be selected to place the drive PMOS transistor 212 and the drive NMOS transistor 232 in the subthreshold region. An amplifier circuit 280 is created using diode 306 as a resistive element. Figure 2The diode 306 is a branch in which the gate of the driving PMOS transistor 212 is coupled to one end of the diode 306, and the gate of the driving NMOS transistor 232 is coupled to the other end of the diode 306. Furthermore, the diode 306 is also connected to transistors in the first stage 250 and the second stage 260. Specifically, one end of the diode 306 is coupled to PMOS transistor 254A, and the other end of the diode 306 is coupled to NMOS transistor 264A.

[0070] In configuration 380, the bias conditions of diode 306 can be selected to reduce the gate-source voltages of both the driving NMOS transistor 232 and the driving PMOS transistor 212, allowing both to operate in the subthreshold region. That is, the combination of diode 306 with a sufficiently selected equivalent resistance (forward or reverse mode) yields an adjusted gate-source voltage in the driving transistors, which facilitates subthreshold operation and allows self-biasing. Therefore, appropriately selecting the parameters of diode 306 can achieve the advantages of amplifier 200 as described above.

[0071] Figure 4A A circuit diagram is shown of an exemplary configuration 400 of an amplifier 200 using variable resistors according to some embodiments of the present disclosure. In configuration 400, the resistive element 270 is implemented by a series of variable and fixed resistors. Such a configuration facilitates the selection of sufficient resistance values ​​to obtain subthreshold bias for driving the PMOS transistor 212 and the NMOS transistor 232.

[0072] In configuration 400, the resistive element 270 is implemented by a first variable resistor 402, a fixed resistor 404, and a second variable resistor 406. This configuration allows for more precise control of gain and power consumption by increasing and decreasing the gate-source voltage (Vgs) of the driving PMOS transistor 212 and the driving NMOS transistor 232 through precise selection of the operating mode of the driving transistors. Furthermore, using a variable resistor as part of the resistive element 270 increases the output and common-mode range of the amplifier 200.

[0073] The ability to precisely control the gate-source voltages of the driving PMOS transistor 212 and the driving NMOS transistor 232 allows Vgs to be selected based on the output voltage (VO) at the output node 282. To place the driving PMOS transistor 212 and the driving NMOS transistor 232 in the subthreshold region, configuration 400 allows Vgs to be adjusted based on VO. For example, as combined with... Figure 4BFurther discussion suggests that the signal from VO can be used as feedback control to dynamically adjust the values ​​of the first variable resistor 402 and the second variable resistor 406. Thus, as VO increases at output node 282, the first variable resistor 402 and the second variable resistor 406 can be modified to increase Vgs, avoiding saturation or transistor operation and keeping the transistor in the subthreshold region. Conversely, as VO decreases, the first variable resistor 402 and the second variable resistor 406 can be adjusted to decrease Vgs, also avoiding saturation or transistor operation and keeping the device in the subthreshold region.

[0074] In some embodiments, the first variable resistor 402 and the second variable resistor 406 can be implemented using transistors similar to transistor 422 (e.g., in combination). Figure 4B (To be discussed further). However, in other embodiments, the first variable resistor 402 and the second variable resistor 406 can be implemented with alternative devices that allow control of their resistance values.

[0075] Figure 4B A circuit diagram is shown of an exemplary configuration 450 of an operational amplifier 200 using transistors as variable resistors according to some embodiments of the present disclosure. In configuration 450, the resistive element 270 is implemented using a PMOS transistor 422, a resistor 404, and an NMOS transistor 426. Configuration 450 illustrates an implementation of configuration 400, in which the variable resistor is implemented using transistors. Therefore, in some embodiments, as... Figure 4B As shown, the first variable resistor 402 and the second variable resistor 406 ( Figure 4A The configuration 450 is implemented using PMOS transistor 422 and NMOS transistor 426, respectively. Configuration 450 uses a combination of PMOS and NMOS transistors to facilitate the fabrication of resistive element 270 and create a self-biased bias based on VO at output node 282. However, other configurations may also use only NMOS or PMOS transistors, or different types of devices (e.g., BJTs).

[0076] In configuration 450, the gates of PMOS transistor 422 and NMOS transistor 426 are directly connected to output node 282. This configuration generates feedback through PMOS transistor 422 and NMOS transistor 426. Using configuration 450, when the amplifier 200 output VO is low, the resistance of PMOS transistor 422 decreases, while the resistance of NMOS transistor 426 increases. Furthermore, as the resistance of NMOS transistor 426 increases, the Vgs of NMOS transistor 232 / NMOS transistor 233 further decreases. The overdrive voltage (Vov) of NMOS transistor 233, defined as the gate-source voltage (Vgs) exceeding the threshold voltage, also decreases. This type of feedback in resistive element 270 enables precise control of gain and dynamic, self-bias adjustment to maintain target DC gain and dynamic range.

[0077] The PMOS transistor 422 and NMOS transistor 426 in configuration 450 can be implemented using finFETs. For example, the PMOS transistor 422 can be implemented using three parallel-coupled finFETs, each finFET having L = 8n and M = 24, where L defines the transistor length based on the selected process node, and M defines the transistor type. Similarly, the NMOS transistor 426 can be implemented using three parallel-coupled finFETs, each finFET having L = 8n and M = 24. In such an embodiment, the value of resistor 404 can be in the kiloohm range. For example, resistor 404 can be between 1 and 100 kΩ. For example, resistor 404 can have a value of 1.8 kΩ.

[0078] Figure 5A An exemplary circuit diagram of a first boost stage 252 according to some embodiments of the present disclosure is shown. The first boost stage 252 provides additional gain to amplifier 200. Figure 2 As shown, the first boost stage 252 can be in the first stage 250 ( Figure 2 )Inside.

[0079] The first boost stage 252 includes a first input substage 512. The first input substage 512 includes input PMOS transistors 506A and 506B. One of the source / drain nodes of PMOS transistors 506A and 506B is directly connected to and coupled to a power supply node 214. The opposite source / drain nodes of PMOS transistors 506A and 506B are connected to a first output VOPN 506 and a second output VOPP 508. The gates of PMOS transistors 506A and 506B are coupled to a first input VPP 502 and a second input VPN 504. In some embodiments, the inputs of the PMOS transistors within the first input substage 512 may be matched, having the same size, bias, and operation. However, in other embodiments, the input PMOS transistors within the first input substage 512 may be independent.

[0080] The first boost stage 252 also includes a first loading substage 510. The first loading substage 510 includes PMOS transistors 506A and 506B connected to the first input substage 512 and NMOS transistors 507A and 507B connected to the ground node 234. For example, the first input substage 512 may include PMOS transistors 506A and 506B coupled to the power supply node 214. Furthermore, the gates of the NMOS transistors 507A and 507B are shorted and they may be connected to the input node VB1. Figure 3B Similarly, the input of node VB1 can be selected to place NMOS transistors 507A and 507B in the transistor region as an active load. The effective impedance value of the loaded substage 510 can be selected based on the desired gain, SNR, dynamic range, or a combination of these parameters. However, Figure 5A The first loading sublevel 510 embodiment is one option, and is described below in conjunction with... Figures 6A-6E Alternative embodiments are discussed.

[0081] Figure 5B An exemplary circuit diagram of a second boost stage 262 according to some embodiments of the present disclosure is shown. The second boost stage 262 provides additional gain to amplifier 200. Figure 2 As shown, the second boost stage 262 can be installed in the first stage 260 ( Figure 2 )Inside.

[0082] The second boost stage 262 includes a second input substage 532. The second input substage 532 includes input NMOS transistors 533A and 533B. These are one of the source / drain nodes of the input. The NMOS transistors 533A and 533B within the second input substage 532 are directly connected and coupled to ground node 234. Figure 2For example, the second input substage 532 may be coupled to the drain / source node of each NMOS transistor 264, wherein the second loaded substage is coupled to the gate node of each NMOS transistor 533A and 533B. Additionally, NMOS transistors 533A and 533B are coupled to ground node 234.

[0083] The opposite source / drain nodes of input NMOS transistors 533A and 533B are connected to the first output VONP 526 and the second output VONN 528. The gates of NMOS transistors 533A and 533B are coupled to the first input VNP 522 and the second input VNN 524. In some embodiments, the input NMOS transistors within the second input substage 532 may be matched, having the same size, bias, and operation. However, in other embodiments, the input NMOS transistors within the second input substage 532 may be independent.

[0084] The second boost stage 262 also includes a second loading substage 530. The second loading substage 530 includes NMOS transistors 533A and 533B connected to the second input substage 532 and PMOS transistors 531A and 531B connected to the power node 214. Furthermore, the gates of the PMOS transistors 531A and 531B in the second loading substage 530 are shorted, and they can be connected to the input node VB2. (As in...) Figure 3B The input of VB2, as discussed, can be used to place PMOS transistors 531A and 531B in the transistor region and serve as an active load. The effective impedance value of the second loaded substage 530 can be selected based on the desired gain, SNR, dynamic range, or a combination of these parameters.

[0085] Figures 6A-6E The diagram illustrates exemplary boost stages using different loading devices. Depending on the application, integrated circuit area constraints, or power targets, designers can choose different loading mechanisms or devices for the boost stage.

[0086] Figure 6A A circuit diagram of an exemplary boost stage 252A using a resistive load according to some embodiments of this disclosure is shown. Figure 6A In the boost stage 252A, the loading substage uses a passive load with a loading resistor 642. Although the loading resistor 642 is shown as a single resistor, it can comprise a network of passive resistors.

[0087] Figure 6B A circuit diagram of an exemplary boost stage 252B using an inductive load, according to some embodiments of the present disclosure, is shown. Figure 6BIn the boost stage 252B, the loading substage uses a passive load with a loading inductor 644. Although the loading inductor 644 is shown as a single inductor, it may include a network of inductors and / or capacitors having the equivalent impedance required for the loading substage. In some embodiments, the boost stage 252B may combine a resistor 642 or an inductor 644, or a combination thereof. Figure 6A and Figure 6B Examples of implementations.

[0088] Figure 6C A circuit diagram of an exemplary boost stage 252C using an active load, according to some embodiments of this disclosure, is shown. Figure 6C In the boost stage 252C, the load substage uses an active load with a load transistor 646. Although the load transistor 646 is shown as a single device, it can include a transistor network. For example, Figure 6C A possible implementation of the boost stage 252C is a first loaded substage 510 using back-to-back transistors. Similarly, other embodiments may include transistor networks coupled in parallel, in series, or a combination of parallel and series.

[0089] Figure 6D A circuit diagram of an exemplary boost stage 252D using an active PMOS diode load according to some embodiments of the present disclosure is shown. Figure 6D In the boost stage 252D, the load substage uses an active load with a PMOS diode 648. Although the PMOS diode 648 is shown as a single MOS device with a shorted gate, the PMOS diode 648 may include a transistor or a standard diode (non-CMOS) or a Zener diode and / or a Schottky diode.

[0090] Figure 6E A circuit diagram of an exemplary boost stage 252E using an active NMOS diode load according to some embodiments of the present disclosure is shown. Figure 6E In this design, the loading substage uses an active load with an NMOS diode 650. Although the NMOS diode 650 is shown as a single MOS device with a shorted gate, the NMOS diode 650 may include a transistor or a standard diode (non-CMOS), including, for example, a Zener diode and / or a Schottky diode.

[0091] Figure 7A circuit diagram of a first exemplary amplifier 700 for subthreshold biasing, with active load and resistive coupling according to some embodiments of the present disclosure, is shown. Amplifier 700 embodies a possible implementation of amplifier 200. Like amplifier 200, amplifier 700 also includes differential input circuitry 220, positive bias circuitry 210, negative bias circuitry 230, amplification circuitry 280 (including a first stage 250 and a second stage 260), and a resistive element 270 between the first stage 250 and the second stage 260. However, in amplifier 700, the first boost stage 252 (within the first stage 250) is used... Figure 5A The boost stage shown is implemented using the second boost stage 262 (within the second stage 260). Figure 5B The boost stage shown is implemented using resistor 302 ( ). Figure 3A This was achieved.

[0092] like Figure 7 As shown, the resulting circuit includes multiple direct connections between different transistors in amplifier 700. For example, as Figure 7 As shown, one end of resistor 270 is directly connected to the gate of the transistor (e.g., PMOS transistor 254A) in the first stage 250, the gate of the driving PMOS transistor 212, and the gate of the loading transistor (e.g., the transistor in the loading substage 530) in the second boost stage. The other end of resistor 270 is directly connected to the gate of the transistor (e.g., NMOS transistor 264A) in the second stage 260, the gate of the driving NMOS transistor 232, and also to the gate of the loading transistor (e.g., the transistor in the loading substage 510) in the first boost stage. Furthermore, the gate of PMOS transistor 254A is directly connected to the drain / source node of the transistor in the first boost stage 252. Additionally, the gate of NMOS transistor 264A is directly connected to the drain / source node of the transistor in the second boost stage 262. Therefore, amplifier 700 can be configured such that the gate of the driving PMOS transistor 212 is directly connected to the first terminal of resistor 270, and the gate of the driving NMOS transistor 232 is directly connected to the second terminal of resistor 270. In this configuration, the first terminal of the resistor element 270 is directly connected to the second loading sub-stage 530, and the second terminal of the resistor element 270 is directly connected to the first loading sub-stage 510.

[0093] Figure 7 The connections between the transistors in the first input substage 512 and the second input substage 532 and other components of the amplifier 700 are also shown. For example, as... Figure 7As shown, the gate of the first input substage 512 is connected to the drain / source node of the positive bias circuit 210. The gate of the second input substage 532 is connected to the drain / source node of the negative bias circuit 230. Furthermore, the gate of the PMOS transistor 254B is directly connected to the drain / source node of the transistor in the first boost stage 252. Additionally, the gate of the NMOS transistor 264B is directly connected to the drain / source node of the transistor in the second boost stage 262.

[0094] Amplifier 700 illustrates an implementation of amplifier 200, wherein the boost substage uses an active load and the resistive element 270 uses a passive load. This type of implementation can be used to improve control of the boost stage while minimizing power and area expenditure for coupling between the first stage 250 and the second stage 260.

[0095] Figure 8 A circuit diagram of a second exemplary amplifier 800 using coupling resistors for subthreshold biasing according to some embodiments of the present disclosure is shown. Amplifier 800 embodies an alternative implementation of amplifier 200, which does not use a boost stage and places coupling resistor elements between stages at different nodes. By using resistive elements to couple the stages of the amplifier circuit, amplifier 800 still places the driving NMOS transistor 232 in the subthreshold region. However, the use of a boost stage between different components of the stage is avoided and footprint and / or power consumption are minimized. However, this implementation may result in a narrower dynamic range.

[0096] Amplifier 800 is similar to amplifier 200, including a positive bias circuit 210, a negative bias circuit 230, and a differential input circuit 220. However, amplifier 800 has a stage without a boost stage, and does not have a first stage 250 and a second stage 260. Amplifier 800 has a first stage 810 including a PMOS transistor 812 and a coupled NMOS transistor 814. The PMOS transistor 812 includes PMOS transistor 812A (which may be similar to PMOS transistor 254A) and PMOS transistor 812B (which may be similar to PMOS transistor 254B). However, instead of having a first boost stage 252, the first stage 810 includes a coupled NMOS transistor 814. The source / drain nodes of the coupled NMOS transistor 814 are connected to a power supply node 214 and a resistive element 830, respectively. Furthermore, the gate of the coupled NMOS transistor 814 is coupled to drive PMOS transistors 212 and 812A.

[0097] Amplifier 800 also has a second stage 820 including an NMOS transistor 822 and a coupled PMOS transistor 824. The NMOS transistor 822 includes NMOS transistor 822A (which may be similar to NMOS transistor 264A) and NMOS transistor 822B (which may be similar to NMOS transistor 264B). However, instead of having a second boost stage 262, the second stage 820 includes the coupled PMOS transistor 824. The source / drain nodes of the coupled PMOS transistor 824 are connected to ground node 234 and resistive element 830, respectively. Furthermore, the gate of the coupled PMOS transistor 824 is coupled to drive NMOS transistors 232 and 822A.

[0098] Unlike the first stage 250 and the second stage 260, which are coupled via resistor element 270 and output node 282, the first stage 810 and the second stage 820 are coupled via resistor element 830, output node 282, and other direct connections between the stage components. For example, as... Figure 8 As shown, NMOS transistor 822A and PMOS transistor 824A are directly connected (without resistor element 270 in amplifier 200). Furthermore, the gates of PMOS transistor 812 are directly connected to each other (without a boost stage) and they are connected to the drain / source node of NMOS transistor 822A. Similarly, the gates of NMOS transistor 822 are directly connected to each other (without a boost stage) and their gates are connected to the drain / source node of PMOS transistor 812A.

[0099] Additionally, the first stage 810 and the second stage 820 are connected via a resistor element 830. Resistor element 830 connects and couples the NMOS transistor 814 and the PMOS transistor 824. Resistor element 830 is also directly connected to the gate 232 of the driving NMOS transistor. This configuration provides bias for the driving NMOS transistor 232 in the threshold region. By appropriately selecting resistor element 830, the driving NMOS transistor 232 can be positioned in the subthreshold region. Resistor element 830 can be selected from the elements discussed above for resistor element 270. That is, resistor element 830 can be implemented using passive, active, or combined loads. For example, resistor element 830 can simply be a resistor (see...). Figure 3A Resistor element 830 can be implemented using either an inductor or a transistor. However, it can also be implemented using a transistor (see [link to implementation]). Figure 3B Furthermore, the resistor element 830 can also be implemented using a diode (see...). Figure 3C ).

[0100] The bias configuration in amplifier 800 provides at least part of the above combination. Figure 2The advantages discussed are that amplifier 800 also operates the drive transistors in the subthreshold region. For example, amplifier 800 also achieves a larger DC gain than conventional amplifiers and has the potential to operate over a wider range of output voltages. Amplifier 800 can also be fabricated in a smaller area (because it has fewer transistors) and can be used in applications requiring lower power consumption. Circuit designers can combine embodiments of amplifiers 200, 700, and 800 based on gain, power, and area conditions and / or application-specific constraints.

[0101] Figure 9A This diagram illustrates an exemplary first layout planar view 900 of an integrated circuit according to some embodiments of the present disclosure. The first planar view 900 may be used to implement amplifier 200, amplifier 700, and / or amplifier 800. The first planar view 900 includes a positive bias region 902. In some embodiments, the positive bias region 902 may include elements of a positive bias circuit 210. Additionally, the positive bias region 902 may also include elements of a differential input circuit 220, such as PMOS transistors 224A and 224B. In such an embodiment, the positive bias region 902 includes a driving PMOS transistor 212. The first planar view 900 also includes a negative bias region 908. In some embodiments, the negative bias region 908 may include elements of a negative bias circuit 230. In such an embodiment, the negative bias region 908 includes a driving NMOS transistor 232. Furthermore, the negative bias region 908 may also include elements of the differential input circuit 220, such as NMOS transistors 222A and 222B.

[0102] The first planar view 900 also includes an input region 905, which includes a p-input region 904 and an n-input region 906. The input region 905 may include elements of the differential input circuit 220. For example, the p-input region 904 may include a PMOS transistor 224, and the n-input region 906 may include an NMOS transistor 222.

[0103] The first planar view 900 also includes a first boost region 910 and a second boost region 912. In some embodiments, the first boost region 910 may include elements of the first stage 250. In other embodiments, the first boost region 910 may include only elements of the first boost stage 252 (e.g., excluding the PMOS transistor 254). In some embodiments, the second boost region 912 may include elements of the second stage 260. In other embodiments, the second boost region 912 may include only elements of the second boost stage 262 (e.g., excluding the NMOS transistor 264).

[0104] The first planar view 900 also includes a resistor region 914, which may include a resistive element 270. Alternatively or additionally, the resistor region 914 may include a resistive element 830. For example, the resistor region 914 may include a resistor 302, a transistor 304, or a diode 306. Figures 3A-3C Furthermore, resistor region 914 can be connected between first boost region 910 and second boost region 912.

[0105] First plan view 900 shows possible configurations of different zones of amplifiers 200, 700, or 800. For example... Figure 9A As shown, input region 905 is located between positive bias region 902 and negative bias region 908. Specifically, when p-input region 904 is adjacent to and in contact with positive bias region 902, n-input region 906 is adjacent to and in contact with negative bias region 908. Furthermore, p-input region 904 and n-input region 906 are adjacent to, in contact with, and / or adjacent to each other.

[0106] Furthermore, in the first plan view 900, the first boost region 910 is adjacent, in contact with, and / or near the positive bias region 902 and the p-input region 904 on the same side as the first boost region 910. The first boost region 912 is adjacent, in contact with, and / or near the negative bias region 908 and the n-input region 906 on the same side as the second boost region 912. Additionally, the first boost region 910 and the second boost region 912 are adjacent, in contact with, and / or near each other on a different side from the other adjacent, adjacent, or contacting regions in the first plan view 900.

[0107] In the first plan view 900, the resistor region 914 is adjacent, in contact with, and / or near the first boost region 910 and the second boost region 912 on the same side of the resistor region 914. Furthermore, as shown in the first plan view 900, the resistor region 914 may be adjacent only to the first boost region 910 and the second boost region 912, and separated from the input region 905, the positive bias region 902, and the negative bias region 908.

[0108] Therefore, as Figure 9A As shown, the integrated circuit implementing the disclosed amplifier can be arranged such that the positive bias region 902 is adjacent to the first boost stage 910 and the p-input region 904. Furthermore, the negative bias region 908 is adjacent to the second boost stage 912 and the n-input region 906. Additionally, or alternatively, the resistor region 914 is adjacent to the first boost stage region 910 and the second boost stage region 912.

[0109] Figure 9B An exemplary schematic diagram of a second layout plan view 920 of an integrated circuit according to some embodiments of the present disclosure is shown. The second plan view 920 may be used to implement amplifiers 200, 700 and / or 800.

[0110] Similar to the first planar view 900, the second planar view 920 includes a positive bias region 902, a negative bias region 908, and an input region 905 including a p-input region 904 and an n-input region 906. However, unlike the first planar view 900, the second planar view 920 combines the boost regions into a single boost region 915. While the first planar view 900 has a first boost region 910 and a second boost region 912, the second planar view 920 has a single boost region 915, which can combine elements of the first stage 250 and the second stage 260. Alternatively, the boost region 915 may include only elements of the first boost stage 252 and the second boost stage 262.

[0111] In the boost region 915, the boost elements are combined to create a different organization for the second planar layout 920. In the second planar layout 920, the boost region 915 is surrounded by other regions. For example, the boost region 915 is adjacent to the input region 905 on one side. On another side, the boost region 915 is adjacent to the resistor region 914. On a third side, the boost region is adjacent to, near, and / or in contact with the positive bias region 902. And on a fourth side opposite to the third side, the boost region 915 is adjacent to, near, and / or in contact with the negative bias region 908. Furthermore, in the second planar layout 920, in addition to the input region 905, the resistor region 914 is also adjacent to, in contact with, and / or near the positive bias region 902 and the negative bias region 908.

[0112] Other elements in the second plan view 920 have a similar arrangement to those in the first plan view 900. For example, input region 905 is disposed between positive bias region 902 and negative bias region 908, wherein p-input region 904 is adjacent, in contact with and / or adjacent to positive bias region 902, and n-input region 906 is adjacent, in contact with and / or adjacent to negative bias region 908.

[0113] Figure 10 A flowchart illustrating an exemplary method of operation 1000 for an amplifier circuit according to some embodiments of the present disclosure is provided. In some embodiments, the disclosed amplifiers 200, 700, and / or 800 may be operated based on method 1000. For example, when an input signal is input at the first amplifier input VIP 202 and / or the second amplifier input VIN 204, the transistors in amplifier 200 may be biased, connected, and / or operated based on method 1000 to provide gain at output node 282.

[0114] Method 1000 may begin at step 1002. In step 1002, one or more PMOS transistors within the p-type wide-swing cascaded current mirror of the amplifier circuit are configured to operate in the saturation region. For example, in step 1002, the first PMOS transistor 254A may be biased in the saturation region. The PMOS transistor biased in the saturation region in step 1002 may be connected to the amplifier's drive transistor. For example, in step 1002, PMOS transistor 254A may be biased to operate in the saturation region while it is directly connected to the drive PMOS transistor 212.

[0115] In step 1004, one or more NMOS transistors within the n-type wide-swing cascaded current mirror of the amplifier circuit are configured to operate in the saturation region. For example, in step 1004, the first NMOS transistor 264A can be biased to operate in the saturation region. The NMOS transistor biased in the saturation region in step 1004 can be connected to the transistor driving the amplifier. For example, in step 1004, NMOS transistor 264A can be biased to operate in the saturation region while it is directly connected to the driving NMOS transistor 232.

[0116] In step 1006, the driving NMOS transistor 232 and the driving PMOS transistor 212 are configured to operate in the subthreshold region. As described above... Figure 2 Further described, a resistor element can couple an NMOS transistor to a PMOS transistor in an amplifier circuit. For example, in amplifier 200, resistor element 270 connects a first NMOS transistor 264A and a first PMOS transistor 254A. This configuration enables the driving NMOS transistor 232 and the driving PMOS transistor 212 to operate in the subthreshold region. Without resistor element 270, both the driving NMOS transistor 232 and the driving PMOS transistor 212 cannot operate in the subthreshold region because their gates would be connected together. However, resistor element 270 can be used to decouple the gates of the driving NMOS transistor 232 and the driving PMOS transistor 212, enabling the configuration of the driving NMOS transistor 232 and the driving PMOS transistor 212 to operate in the subthreshold region.

[0117] In step 1008, a power supply voltage can be used to power the amplifier circuit. For example, amplifier 200 can be powered by inputting a power supply voltage at power node 214. The power supply voltage can be selected based on the configuration of the transistors in the amplifier, the desired current, and the bias of the transistors in steps 1002 and 1004. For example, in some embodiments, the power supply voltage applied to the power node of the amplifier can be proportional to the sum of the voltage drops in the driving transistors and the resistive elements. The power supply voltage for power amplifier 200 can also (or alternatively) be proportional to the sum of the voltage drops on driving NMOS transistor 232, resistive element 270, and driving PMOS transistor 212. Furthermore, in some embodiments, the selected power supply voltage (VDD) can be equal to the sum of the voltage drops (Vgs_232) on driving NMOS transistor 232, resistive element 270 (Vr_270), and driving PMOS transistor 212 (Vgs_212). Therefore, in some embodiments, VDD = Vgs_232 + Vr_270 + Vgs_212. Furthermore, Vr_270 can be set based on the current driving the NMOS transistor 232, the resistive element 270, and the PMOS transistor 212, such as Vr_270 = I*R, where I is the current and R is the equivalent resistance of the resistive element 270.

[0118] Furthermore, the power supply voltage (VDD) in step 1008 can be selected based on the threshold voltage of the transistors in the amplifier circuit and the overdrive condition. For example, in some embodiments, the power supply voltage (VDD) can be selected as at least twice the sum of the threshold voltage (Vt) of the transistors in the p-type and n-type wide-swing cascaded current mirrors and the overdrive voltage (ΔV) of the transistor biased in the saturation region. Therefore, for such an embodiment, in step 1006, VDD ≥ 2*(Vt + ΔV).

[0119] Steps 1002-1008 of method 1000 configure a self-biased amplifier without external bias and without any degradation in its AC performance. This method allows the use of amplifier circuitry with enhanced gain that maintains a wide dynamic range.

[0120] In step 1010, a signal can be input to the differential input circuit of the amplifier circuit. For example, in step 1010, a signal can be input to the differential input circuit 220 of amplifier 200. Figure 1 As shown, the differential inputs of amplifier 200 can be signal CKP 102 and signal CKN 104.

[0121] The input signal is amplified by the amplifier circuit. Based on the configuration settings in steps 1002-1008, the amplifier circuit generates an amplified output. Therefore, in step 1012, the amplifier circuit can generate an output based on the differential input signal at the output node. For example, in step 1012, amplifier 200 can generate an output at output node 282. (As in conjunction with...) Figure 1 The output generated by amplifier 200 can be used as a control signal in DCC.

[0122] The gain generated by the amplifier circuit in step 1012 is based on a boost gain stage and an input gain stage. The input gain stage can be based on the configuration of the differential input circuit 220. For example, the input gain stage can be based on the transconductance of the transistors in the differential circuit 220. In some embodiments, the input gain stage in amplifier 200 can be proportional to the transconductance of NMOS transistor 222 and PMOS transistor 224. The boost gain stage can be based on the configuration of the amplifier circuit. For example, the boost gain stage can be based on the transconductance and output resistance of amplifier circuit 280. In some embodiments, the boost gain stage in amplifier circuit 280 can be based on the configuration of a first boost stage 252 and a second boost stage 262. The boost gain stage can be proportional to the transconductance of the first input substage 512, the first loading substage 510, the second loading substage 530, the second input substage 532, and the output resistance of the amplifier stage. In some embodiments, the overall gain of the amplifier circuit can be determined based on the gain of the first boost stage 252 (Avp, based on the transconductance of the first input substage 512) and the gain of the second boost stage (Avn, proportional to the transconductance of the second input substage 532). The gains in these stages then determine the equivalent resistance (R250) of the first stage 250 and the equivalent resistance (R260) of the second stage 260. Specifically:

[0123] R250=g_213-254B*r_254B(r_213 / r_222B)*Avp,

[0124] Where (i) g_213-254B is the combined transconductance of the second bias PMOS transistor 213 and the second PMOS transistor 254B, (ii) r_254B is the output resistance of the second PMOS transistor 254B, (iii) r_213 is the output resistance 213 of the second bias PMOS transistor, (iv) r_222B is the output resistance of the NMOS transistor 222B, and (v) Avp is the gain of the first boost stage 252. Furthermore,

[0125] R260=g233_264B*r_264B(r_233 / r_224B)*Avn,

[0126] Where (i) g233_264B is the combined transconductance of the second bias NMOS transistor 233 and the second NMOS transistor 264B, (ii) r_264B is the output resistance of the second NMOS transistor 264B, (iii) r_233 is the output resistance of the second bias NMOS transistor 233, (iv) r_224B is the output resistance of the PMOS transistor 224B, and (v) Avn is the gain of the second boost stage 262.

[0127] The equivalent resistors R250 and R260 of the boost stage determine the total gain of the amplifier circuit, defined as follows:

[0128] Av=(g_222+g_224)(R250 / R260),

[0129] Where (i)g_222 is the transconductance of NMOS transistor 222, and (ii)g_224 is the transconductance of PMOS transistor 224. Therefore, in step 1012, the amplifier circuit can generate an output proportional to Av and the differential input signal. In some embodiments, the amplifier circuit generates an output equal to Vout = Av * Vin by multiplying the input signal by Av.

[0130] In some embodiments, method 1000 may include the step of adjusting an operating mode. For example, in step 1014, the voltage drop in the driving transistor may be reduced to adjust the power supply. In step 1008, the power supply voltage is determined based on the threshold voltage, overdrive voltage, and voltage drop. For example, these voltages may be adjusted to reduce the power supply voltage for low-power operation. Thus, in step 1014, the amplifier circuit can initiate a low-voltage application by reducing the power supply voltage. For example, the driving NMOS transistor 232 may be rebiased to have a lower voltage drop at the driving NMOS transistor 232. Alternatively or additionally, step 1014 of method 1000 may include reducing the overdrive voltage to operate under low-voltage applications and increasing the output swing. Thus, method 1000 is capable of adjusting bias rules and selecting current in a wide-swing cascaded current mirror to control the power supply voltage and adjust for different operating modes.

[0131] The disclosed amplifier, circuit configuration, and bias conditions improve amplifier operation and address other design challenges. Furthermore, the disclosed configuration facilitates integrated circuit fabrication by, for example, minimizing the external bias required for the operational amplifier.

[0132] For example, the disclosed amplifiers 200, 700, and / or 800 facilitate the operation and configuration of operational amplifiers by reducing the amount of external bias voltage required for the operating circuitry. The disclosed configuration of amplifiers with positive bias circuitry, negative bias circuitry, and amplifier circuitry (with multiple stages and resistive elements) addresses the drawbacks of conventional amplifiers. Conventional operational amplifiers (especially folded cascaded amplifiers) can utilize large amounts of external bias voltage. Such large amounts of external bias voltage can lead to performance and manufacturing problems. For example, amplifiers with external voltage require a larger manufacturing area and consume more power (leading to overheating problems). Furthermore, amplifiers with large amounts of external voltage can suffer from performance issues because they are more susceptible to noise, crosstalk, and are highly sensitive to bias point and bias variations. The disclosed embodiments overcome these problems through a self-biasing configuration in which resistive elements self-bias the transistors, resulting in fewer bias nodes than alternative methods. Furthermore, the disclosed embodiments allow for transistor self-biasing without degrading AC performance or requiring an increase in supply voltage.

[0133] Specifically, the disclosed embodiments facilitate the self-biasing of transistors in the circuit by utilizing resistive elements in the gain boost stage of a self-biased operational amplifier. The disclosed embodiments employ resistive elements (active or passive) connected to the gain boost stage and the driving transistor. This configuration facilitates the self-biasing of both the driving and boost transistors. Furthermore, as combined with... Figure 2 As discussed, resistive elements (such as resistive element 270) can be selected and coupled between gain boost stages to place the drive transistors in the subthreshold region. The subthreshold operating region of the drive transistors achieves high DC gain without degrading AC performance and while minimizing power consumption. The disclosed embodiments offer several advantages for both the operation and fabrication of operational amplifiers (and particularly folded cascaded amplifiers). For example, selecting resistive elements between boost stages enables certain transistors of amplifiers 200, 700, or 800 to operate in the subthreshold region, which reduces power requirements. Furthermore, by operating in the subthreshold region, the amplifiers of the disclosed embodiments achieve increased DC gain.

[0134] In addition to the increased DC gain, the disclosed embodiments offer other operational advantages. For example, the disclosed embodiments facilitate the fabrication of integrated circuits in a smaller area with lower power consumption. Furthermore, the disclosed amplifier circuitry improves amplifier stability and noise sensitivity because, while conventional folded cascaded amplifiers have limited signal-to-noise ratio (SNR)—partly due to the required bias conditions—the disclosed self-biased configuration minimizes noise sources.

[0135] Therefore, the disclosed embodiments and circuit configurations provide a low-voltage, self-biased, and gain-boosting amplifier. Using resistive elements to self-bias the transistor and operate in the subthreshold region improves amplifier gain, reduces the number of external bias lines, minimizes potential noise, and improves power consumption characteristics.

[0136] Furthermore, the disclosed embodiments offer a wider operating range. By including resistive elements for self-biasing and subthreshold region operation, the disclosed embodiments improve the amplifier's dynamic range, providing strong gain at both low and high output voltages. Other amplifiers have Gaussian gain, peaking at the average output voltage but exhibiting low (or even attenuated) gain at low or high output voltages. For example, other amplifiers might have peak gain around VO = 350mV but lower gain at low output voltages (e.g., VO = 100mV) or high output voltages (e.g., VO = 650mV). In contrast, the disclosed embodiments and amplifier configurations achieve better amplification range with high gain at the extremes of the output voltage. For example, the disclosed embodiments achieve greater gain at both low (e.g., VO = 100mV) and high (e.g., VO = 650mV) output voltages. Consistent with some disclosed configurations, the amplifier achieves a 20dB–30dB gain improvement at the edges of the output voltage range compared to other amplifiers.

[0137] Furthermore, the disclosed configuration can be applied to different technologies. For example, embodiments of the disclosed amplifier can be implemented in various manufacturing processes, including 3nm, 5nm, 7nm, 10nm, 16nm, and 20nm processes.

[0138] At least for these reasons, the advantages of the disclosed embodiments result in operational amplifiers with improved performance, simpler configuration, and / or simpler manufacturing.

[0139] It should be understood that this document does not need to discuss all advantages, no particular advantage is necessary for all embodiments or instances, and other embodiments or instances may provide different advantages.

[0140] According to one aspect of this disclosure, the amplifier circuit includes a positive bias circuit coupled to a power supply node and having a driving PMOS for biasing in the subthreshold region. The circuit also includes a negative bias circuit coupled to a ground node and having a driving NMOS for biasing in the subthreshold region. The circuit further includes an amplification circuit coupled to the positive and negative bias circuits. The amplification circuit includes a first stage having a PMOS transistor and a first boost stage, wherein one of the PMOS transistors is coupled to the driving PMOS. The amplification circuit also includes a second stage comprising an NMOS transistor and a second boost stage, wherein one of the matching NMOS transistors is coupled to the driving NMOS. The amplification circuit also includes a resistive element coupled between the first and second stages and an output node connected to both the first and second stages.

[0141] In the amplifier circuit described above, the gate of the driving PMOS is directly connected to the first terminal of the resistive element.

[0142] In the amplifier circuit described above, the gate of the driving NMOS is directly connected to the second terminal of the resistive element, which is different from the first terminal.

[0143] In the amplifier circuit described above, the first boost stage is directly connected to the corresponding gate of the PMOS transistor.

[0144] In the amplifier circuit described above, the resistive elements include transistors in a bipolar junction configuration.

[0145] In the amplifier circuit described above, the value of the resistor element is selected to set the gate voltage driving the NMOS to operate in the subthreshold region and to set the gate voltage driving the PMOS to operate in the subthreshold region.

[0146] In the amplifier circuit described above, the resistive element includes: a PMOS transistor; a resistor; and an NMOS transistor; the PMOS transistor is connected in series with the resistor; and the resistor is connected in series with the NMOS transistor.

[0147] The amplifier circuit described above also includes a differential input circuit coupled to the positive bias circuit and the negative bias circuit. The differential input circuit includes two N-input matching transistors and two P-input matching transistors.

[0148] The amplifier circuit described above is disposed in an integrated circuit, wherein: the positive bias circuit is adjacent to the first boost stage and the P-input matching transistor; the negative bias circuit is adjacent to the second boost stage and the N-input matching transistor; and the resistive element is adjacent to the first boost stage and the second boost stage.

[0149] According to another aspect of this disclosure, the folded cascaded operational amplifier includes a positive bias circuit coupled to a power supply node and including a driving PMOS. The folded cascade also includes a negative bias circuit coupled to a ground node and including a driving NMOS, and a differential input circuit coupled to the positive and negative bias circuits. The folded cascade also includes an amplification circuit coupled to the positive and negative bias circuits. The amplification circuit has a first stage coupled to the driving PMOS, a second stage coupled to the driving NMOS, and a resistive element coupled between the first and second stages, the resistive element being directly connected to the gates of the driving PMOS and the driving NMOS. In the folded cascade, the value of the resistive element is selected to place at least one of the driving PMOS or the driving NMOS in the subthreshold region.

[0150] In the above-mentioned folded cascaded operational amplifier, the first stage includes a first input substage, a PMOS transistor, and a first loading substage. The first input substage is coupled to the drain / source node of each of the PMOS transistors, the first loading substage is coupled to the gate node of each of the PMOS transistors, and the PMOS transistors are coupled to the driving PMOS transistor.

[0151] In the above-described folded cascaded operational amplifier, the first loaded substage includes at least one of a resistor or an inductor.

[0152] In the above-mentioned folded cascaded operational amplifier, the first loaded substage includes at least one of a MOS transistor or a MOS diode.

[0153] In the aforementioned folded cascaded operational amplifier, the first input substage includes two boost transistors coupled to the power supply node.

[0154] In the above-mentioned folded cascaded operational amplifier, the second stage includes a second input substage, an NMOS transistor, and a second loading substage. The second input substage is coupled to the drain / source node of each of the NMOS transistors, and the second loading substage is coupled to the gate node of each of the NMOS transistors. The NMOS transistors are coupled to the driving NMOS transistor.

[0155] In the above-described folded cascaded operational amplifier, the second input substage includes two boost transistors coupled to a ground node; and the second loading substage includes a PMOS transistor coupled to a power supply node.

[0156] In the above-mentioned folded cascaded operational amplifier, the gate of the driving PMOS is directly connected to the first terminal of the resistive element; the gate of the driving NMOS is directly connected to the second terminal of the resistive element, the second terminal being different from the first terminal, wherein: the first terminal is directly connected to the second loading substage; and the second terminal is directly connected to the first loading substage.

[0157] According to another aspect of this disclosure, the integrated circuit includes a positive bias region having a driving PMOS for operation in the subthreshold region and a negative bias region having a driving NMOS for operation in the subthreshold region. The integrated circuit further includes: an input region disposed between and adjacent to the positive bias region and the negative bias region; a first boost region adjacent to the input region and the positive bias region, the first boost region including a PMOS transistor; and a second boost region adjacent to the input region and the negative bias region, the second boost region including an NMOS transistor. The integrated circuit also includes a resistor region adjacent to the first boost region and the second boost region, the resistor region including resistive elements directly connected to the driving PMOS and the driving NMOS.

[0158] According to another aspect of this disclosure, a method of operating an amplifier circuit includes: configuring a first transistor of the amplifier circuit to operate in a saturation region, the first transistor being directly connected to a driving PMOS transistor connected to a power supply node; configuring a second transistor of the amplifier circuit to operate in a saturation region, the second transistor being directly connected to a driving NMOS transistor coupled to a ground node, the PMOS transistor being connected to the second transistor via a resistive element; supplying power to the amplifier circuit with a power supply voltage proportional to the sum of the voltage drop of the driving PMOS transistor, the voltage drop of the resistive element (270), and the voltage drop of the driving NMOS transistor, the power supply voltage being at least twice the sum of the threshold voltage of the first transistor and the overdrive voltage of the first transistor; inputting an input signal at a differential input circuit of the amplifier circuit, the differential input circuit including an NMOS transistor and a PMOS transistor; and receiving an output signal from the output node of the amplifier, the output signal being the input signal multiplied by the gain of the amplifier circuit.

[0159] In the above method, the operation further includes starting a low-voltage application with increased output swing by reducing the power supply voltage to reduce the voltage drop of the driving NMOS; the power supply voltage is equal to the sum of the voltage drop of the driving PMOS transistor, the voltage drop of the resistive element, and the voltage drop of the driving NMOS; the driving NMOS and the driving PMOS have the same current; and the first transistor is a PMOS transistor and the second transistor is an NMOS transistor.

[0160] In the above method, the resistive element includes at least one of a PMOS transistor, a resistor, and an NMOS transistor; the gain at the output of the amplifier circuit is proportional to the transconductance of the differential input stage and the transconductance of the amplification circuit within the amplifier circuit.

[0161] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

[0162] Furthermore, while illustrative embodiments have been described herein, their scope includes any and all embodiments having equivalent elements, modifications, omissions, combinations (e.g., aspects across various embodiments), alterations, and / or changes, as understood by those skilled in the art based on this disclosure. For example, the number and orientation of components shown in the exemplary system may be modified. Additionally, with respect to the exemplary methods illustrated in the drawings, the order and sequence of steps may be modified, and steps may be added or removed.

[0163] Therefore, the above description is for illustrative purposes only. It is not exhaustive and is not limited to the precise forms or embodiments disclosed. Modifications and adaptations will be apparent to those skilled in the art in light of the specification and practice of the disclosed embodiments.

[0164] The claims should be interpreted broadly based on the language used in them, and not limited to the examples described herein, which will be interpreted as non-exclusive. Furthermore, the steps of the disclosed method may be modified in any way, including by reordering steps and / or inserting or deleting steps.

Claims

1. An amplifier circuit, comprising: A positive bias circuit, coupled to a power node, includes a driving PMOS for biasing in the subthreshold region; A negative bias circuit, coupled to a ground node, includes a driving NMOS for biasing in the subthreshold region; as well as An amplifier circuit is coupled to the positive bias circuit and the negative bias circuit, the amplifier circuit comprising: The first stage includes a PMOS transistor and a first boost stage, wherein one of the PMOS transistors is coupled to the driving PMOS. The second stage includes an NMOS transistor and a second boost stage, one of the NMOS transistors being coupled to the driving NMOS. A resistive element is coupled between the first stage and the second stage; and The output node connects to both the first and second levels.

2. The amplifier circuit of claim 1, wherein, The gate of the driving PMOS is directly connected to the first terminal of the resistive element.

3. The amplifier circuit according to claim 2, wherein, The gate of the driving NMOS is directly connected to the second terminal of the resistive element, which is different from the first terminal.

4. The amplifier circuit according to claim 1, wherein, The first boost stage is directly connected to the corresponding gate of the PMOS transistor.

5. The amplifier circuit according to claim 1, wherein, The resistive element includes a transistor in a triode mode.

6. The amplifier circuit according to claim 1, wherein, The value of the resistor element is selected to set the gate voltage of the driving NMOS to operate in the subthreshold region and to set the gate voltage of the driving PMOS to operate in the subthreshold region.

7. The amplifier circuit according to claim 1, wherein: The resistive element includes: PMOS transistor; Resistors; and NMOS transistor; The PMOS transistor is connected in series with the resistor; and The resistor is connected in series with the NMOS transistor.

8. The amplifier circuit of claim 1 further includes a differential input circuit coupled to the positive bias circuit and the negative bias circuit, the differential input circuit including two N-input matched transistors and two P-input matched transistors.

9. The amplifier circuit according to claim 8, disposed in an integrated circuit, wherein: The positive bias circuit is located adjacent to the first boost stage and the P-input matching transistor; The negative bias circuit is adjacent to the second boost stage and the N-input matched transistor; and The resistive element is adjacent to the first boost stage and the second boost stage.

10. A folded cascaded operational amplifier, comprising: A positive bias circuit, coupled to the power node, includes a driving PMOS; A negative bias circuit, coupled to a ground node, includes a driver NMOS; A differential input circuit is coupled to the positive bias circuit and the negative bias circuit; as well as An amplifier circuit, coupled to the positive bias circuit and the negative bias circuit, the amplifier circuit comprising: The first stage is coupled to the driving PMOS; The second stage is coupled to the driving NMOS; and A resistive element is coupled between the first stage and the second stage, and the resistive element is directly connected to the gate of the driving PMOS and the driving NMOS. The value of the resistor element is selected to place at least one of the driving PMOS or the driving NMOS in the subthreshold region. The first stage includes a first input substage, a PMOS transistor, and a first loading substage. The first input substage is coupled to the drain / source node of each of the PMOS transistors, and the first loading substage is coupled to the gate node of each of the PMOS transistors. The PMOS transistors are coupled to the driving PMOS.

11. The folded cascaded operational amplifier according to claim 10, wherein, One of the PMOS transistors is coupled to the resistive element.

12. The folded cascaded operational amplifier according to claim 11, wherein, The first loading substage includes at least one of a resistor or an inductor.

13. The folded cascaded operational amplifier according to claim 11, wherein, The first loading substage includes at least one of a MOS transistor or a MOS diode.

14. The folded cascaded operational amplifier according to claim 11, wherein, The first input substage includes two boost transistors coupled to the power node.

15. The folded cascaded operational amplifier according to claim 11, wherein, The second stage includes a second input substage, an NMOS transistor, and a second loading substage. The second input substage is coupled to the drain / source node of each of the NMOS transistors, and the second loading substage is coupled to the gate node of each of the NMOS transistors. The NMOS transistors are coupled to the driving NMOS.

16. The folded cascaded operational amplifier according to claim 15, wherein: The second input substage includes two boost transistors coupled to the ground node; and the second load substage includes a PMOS transistor coupled to the power node.

17. The folded cascaded operational amplifier according to claim 15, wherein: The gate of the driving PMOS is directly connected to the first terminal of the resistive element; The gate of the driving NMOS is directly connected to the second terminal of the resistive element, and the second terminal is different from the first terminal. in: The first terminal is directly connected to the second loading sub-stage; and The second terminal is directly connected to the first loading sub-stage.

18. A method of operating an amplifier circuit, comprising: The first transistor of the amplifier circuit is configured to operate in the saturation region, one of the first transistors is directly connected to a drive PMOS transistor connected to a power supply node, and a first boost stage is connected between the first transistors. The second transistor of the amplifier circuit is configured to operate in the saturation region, one of the second transistors is directly connected to a driving NMOS transistor coupled to a ground node, and a second boost stage is connected between the second transistors, wherein the first transistor is connected to the second transistor via a resistive element; The amplifier circuit is powered by a power supply voltage that is proportional to the sum of the voltage drop of the driving PMOS transistor, the voltage drop of the resistive element (270), and the voltage drop of the driving NMOS, wherein the power supply voltage is at least twice the sum of the threshold voltage of the first transistor and the overdrive voltage of the first transistor. An input signal is input at the differential input circuit of the amplifier circuit, the differential input circuit including an NMOS transistor and a PMOS transistor; as well as An output signal is received from the output node of the amplifier, the output signal being the input signal multiplied by the gain of the amplifier circuit, wherein the gain of the amplifier circuit is based on the configuration of the differential input circuit, the configuration of the first boost stage, and the configuration of the second boost stage.

19. The method of claim 18, wherein: The operation also includes enabling a low-voltage application with increased output swing by reducing the power supply voltage to reduce the voltage drop across the driving NMOS. The power supply voltage is equal to the sum of the voltage drop of the driving PMOS transistor, the voltage drop of the resistive element, and the voltage drop of the driving NMOS transistor; The driving NMOS and the driving PMOS have the same current; and The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor.

20. The method of claim 19, wherein: The resistive element includes at least one of a PMOS transistor, a resistor, and an NMOS transistor; The gain at the output of the amplifier circuit is proportional to the transconductance of the differential input circuit and the transconductance of the amplification circuit within the amplifier circuit.

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