Control method of flash memory controller, flash memory controller, and storage device

Abstract

The present application provides a control method of a flash memory controller, a flash memory controller and a storage device. In the control method, after receiving a deallocation command from a host device, the flash memory controller updates a valid page count table, a detailed valid page count table and / or a region valid page count table according to the deallocation command, so that the flash memory controller can effectively and quickly determine whether any region does not have any valid data, and thus the flash memory controller can suggest the host device to transmit a reset command to reset the region.

Description

Technical Field

[0001] This invention relates to flash memory, and more particularly to flash memory controllers and related control methods. Background Technology

[0002] In the Non-volatile Memory Express (NVMe) specification, a zoned namespace is standardized. However, since the aforementioned zoned namespace and each zone within it are viewed purely from the host device's perspective, how to provide an effective memory management method to correctly and quickly process the host device's commands appropriately is an important issue. Summary of the Invention

[0003] Therefore, one of the objectives of this invention is to provide a flash memory controller capable of effectively managing flash memory modules according to deallocate commands from a host device, in order to solve the above-mentioned problems.

[0004] According to an embodiment of the present invention, a control method for a flash memory controller is provided, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising a plurality of blocks, and the control method comprises: receiving a setting command from a host device, wherein the setting command configures at least a portion of the flash memory module as a partition namespace, the partition namespace logically comprising a plurality of regions, the host device performing a region-based data write operation on the partition namespace, each region having the same size, the plurality of logical addresses corresponding to each region being contiguous, and the plurality of logical addresses not overlapping between the plurality of regions; writing data of a first region to a plurality of first blocks; and establishing a region-block mapping table, wherein... The region-block mapping table contains information about a first region and its corresponding plurality of first blocks; after data is written to the plurality of first blocks, a valid page count table is established or updated; at least one deallocation command is received from the host device, wherein each deallocation command contains a logical address range to be deallocated; the valid page count table is updated according to the at least one deallocation command to generate an updated valid page count table; the updated valid page count table is used to determine whether the multiple valid page counts of all the plurality of first blocks corresponding to the first region are zero; and if the multiple valid page counts of all the plurality of first blocks corresponding to the first region are zero, the host device is advised to transmit a reset command, wherein the reset command is used to reset the first region.

[0005] According to an embodiment of the present invention, a flash memory controller is provided, wherein the flash memory controller is used to access a flash memory module, the flash memory module including a plurality of blocks, and the flash memory controller includes a read memory for storing program code, a microprocessor for executing the program code to control access to the flash memory module, and a buffer memory. The microprocessor is used to: receive a setup command from a host device, wherein the setup command configures at least a portion of the flash memory module as a partition namespace, the partition namespace logically including a plurality of regions, the host device performing a region-based data write operation on the partition namespace, each region having the same size, the plurality of logical addresses corresponding to each region being contiguous, and the plurality of logical addresses not overlapping between the plurality of regions; write data from a first region to a plurality of first blocks; establish a region-block mapping table, wherein the region-block mapping table contains information about the first region and the corresponding plurality of first blocks; and in After data is written to multiple first blocks, a valid page count table is established or updated; at least one deallocation command is received from the host device, wherein each deallocation command contains a logical address range to be deallocated; the valid page count table is updated according to the at least one deallocation command to generate an updated valid page count table; the updated valid page count table is used to determine whether the multiple valid page counts of all multiple first blocks corresponding to the first region are zero; and if the multiple valid page counts of all multiple first blocks corresponding to the first region are zero, the host device is advised to transmit a reset command, wherein the reset command is used to reset the first region.

[0006] According to an embodiment of the present invention, a storage device is provided comprising a flash memory module and a flash memory controller. The flash memory module includes multiple blocks, and the flash memory controller is used to operate the flash memory module. During operation of the storage device, the flash memory controller receives a configuration command from a host device, wherein the configuration command configures at least a portion of the flash memory module as a partition namespace, the partition namespace logically including multiple regions, the host device performs a region-based data write operation on the partition namespace, each region having the same size, the logical addresses corresponding to each region being contiguous, and the logical addresses not overlapping between multiple regions; the flash memory controller writes data from a first region to multiple first blocks and establishes a region-block mapping table, the region-block mapping table containing information about the first region and the corresponding multiple first blocks. Information; After the data is written to multiple first blocks, the flash memory controller establishes or updates a valid page count table; the flash memory controller receives at least one deallocation command from the host device, and each deallocation command contains a logical address range to be deallocated; the flash memory controller updates the valid page count table according to the at least one deallocation command to generate an updated valid page count table; the flash memory controller determines, according to the updated valid page count table, whether the multiple valid page counts corresponding to all multiple first blocks of the first region are zero; and if the multiple valid page counts corresponding to all multiple first blocks of the first region are zero, the flash memory controller suggests that the host device send a reset command, and the reset command is used to reset the first region.

[0007] In summary, in the control method of the flash memory controller of the present invention, by establishing a valid page count table, a detailed valid page count table, and / or a region valid page count table based on the deallocation command from the host device, the flash memory controller can effectively and quickly determine whether any region does not have any valid data, so that the flash memory controller can suggest the host device to send a reset command to reset the region. Attached Figure Description

[0008] Figure 1 This is a schematic diagram of an electronic device according to an embodiment of the present invention.

[0009] Figure 2 This is a schematic diagram of a flash memory controller in a storage device according to an embodiment of the present invention.

[0010] Figure 3 This is a schematic diagram of a block in a flash memory module according to an embodiment of the present invention.

[0011] Figure 4This is a schematic diagram of a flash memory module that includes general storage space and partition namespaces.

[0012] Figure 5 This is a diagram illustrating a partitioned namespace that has been divided into multiple regions.

[0013] Figure 6 This is a flowchart illustrating the writing of data from a host device to a partition namespace according to an embodiment of the present invention.

[0014] Figure 7 This is a schematic diagram of the region data of the block being written into the flash memory module.

[0015] Figure 8 This is a schematic diagram of a logic-to-entity address mapping table according to an embodiment of the present invention.

[0016] Figure 9 This is a schematic diagram of an effective page count table according to an embodiment of the present invention.

[0017] Figure 10 This is a flowchart of a control method for a flash memory controller according to an embodiment of the present invention.

[0018] Figure 11 This is a flowchart illustrating the writing of data from a host device to a partition namespace according to another embodiment of the present invention.

[0019] Figure 12 This is a diagram illustrating a partitioned namespace that has been divided into multiple regions.

[0020] Figure 13 This is a schematic diagram of a logical-to-entity address mapping table and a shared block table according to an embodiment of the present invention.

[0021] Figure 14 This is a schematic diagram of an effective page count table according to an embodiment of the present invention.

[0022] Figure 15 This is a schematic diagram of a detailed valid page count table according to an embodiment of the present invention.

[0023] Figure 16 This is a flowchart of a control method for a flash memory controller according to an embodiment of the present invention.

[0024] Figure 17 This is a schematic diagram of a region effective page count table according to an embodiment of the present invention.

[0025] Figure 18 This is a flowchart of a control method for a flash memory controller according to an embodiment of the present invention.

[0026] Figure 19This is a schematic diagram of a region effective page mapping table according to an embodiment of the present invention.

[0027] Figure 20 This is a schematic diagram of an updated region valid page mapping table according to an embodiment of the present invention.

[0028] Figure 21 This is a flowchart of a control method for a flash memory controller according to an embodiment of the present invention.

[0029] [Symbol Explanation]

[0030] 100: Electronic devices

[0031] 110: Main unit

[0032] 120_1~120_N: Storage device

[0033] 122: Flash memory controller

[0034] 124: Flash memory module

[0035] 212: Microprocessor

[0036] 212C: Program Code

[0037] 212M: Read-Only Memory

[0038] 214: Control Logic

[0039] 216: Buffer memory

[0040] 218: Interface Logic

[0041] 232: Encoder

[0042] 234: Decoder

[0043] 240: Dynamic Random Access Memory

[0044] 200, B3, B7, B8, B12, B99, B6: Blocks

[0045] 202: Floating gate transistor

[0046] BL1~BL3: Bitline

[0047] WL0, WL1, WL2, WL4, WL5, WL6: Character lines

[0048] 410_1, 410_2: Partition namespace

[0049] 420_1, 420_2: General storage space

[0050] 600~608, 1000~1008, 1100~1106, 1600~1608, 1800~1810, 2100~2108: Steps

[0051] 800, 1300: Logical to physical address mapping table

[0052] 900, 1400: Valid page count table

[0053] 1330: Shared Block Table

[0054] 1500: Detailed valid page count table

[0055] 1700: Region Valid Page Count Table

[0056] 1900: Region Valid Page Mapping Table Detailed Implementation

[0057] Figure 1 This is a schematic diagram of an electronic device 100 according to an embodiment of the present invention. Figure 1 As shown, the electronic device 100 may include a host device 110 and multiple storage devices 120_1 to 120_N. Each storage device (e.g., storage device 120_1) may include a flash memory controller 122 and a flash memory module 124. In this embodiment, each storage device 120_1 to 120_N may be a solid-state drive (SSD) or any storage device with a flash memory module. The host device 110 may be a central processing unit (CPU) or other electronic devices or components that can access the storage devices 120_1 to 120_N. The electronic device 100 may be a server, a personal computer, a laptop computer, or any portable electronic device. It should be noted that although... Figure 1 Storage devices 120_1 to 120_N are illustrated, but in some embodiments, electronic device 100 may have only a single storage device 120_1.

[0058] Figure 2 This is a schematic diagram of a storage device 120_1 according to an embodiment of the present invention. Figure 2As shown, the flash memory controller 122 may include a microprocessor 212, a read-only memory (ROM) 212M, control logic 214, a buffer memory 216, and interface logic 218. The ROM 212M can be used to store program code 212C, and the microprocessor 212 can be used to execute program code 212C to control the access of the flash memory module 124. The control logic 214 may include an encoder 232 and a decoder 234. The encoder 232 can be used to encode the data written to the flash memory module 124 to generate a corresponding check code (i.e., an error correction code (ECC)), and the decoder 234 can be used to decode the data read from the flash memory module 124.

[0059] In a typical configuration, flash memory module 124 may include multiple flash memory chips, and each flash memory chip may include multiple blocks. Flash memory controller 122 may perform a block-based erase operation on flash memory module 124. Furthermore, a block may record a specific number of pages, and flash memory controller 122 may perform a page-based write operation on flash memory module 124. In this embodiment, flash memory module 124 may be a 3D-NAND type flash memory module.

[0060] In practice, by executing program code 212C through microprocessor 212, flash memory controller 122 can perform many control operations using its internal components. For example, flash memory controller 122 can use control logic 214 to control access to flash memory module 124 (especially access to at least one block or at least one page), use buffer memory 216 to perform necessary buffering operations, and use interface logic 218 to communicate with host device 110. Buffer memory 216 can be implemented using random access memory (RAM), for example, buffer memory 216 can be static random access memory (SRAM), but the present invention is not limited thereto. In addition, the flash memory controller 122 may be coupled to the dynamic random access memory (DRAM) 240. It should be noted that the DRAM 240 may be included in the flash memory controller 122. For example, the DRAM 240 and the flash memory controller 122 may coexist in the same package.

[0061] In one embodiment, storage device 120_1 may conform to the non-volatile memory express (NVMe) specification. That is, interface logic 218 may conform to a specific communication specification, such as the Peripheral Component Interconnect (PCI) specification or the Peripheral Component Interconnect Express (PCIe) specification, and may communicate according to that specific communication specification. For example, interface logic 218 may communicate with host device 110 via a connector.

[0062] Figure 3 This is a schematic diagram of block 200 in flash memory module 124 according to an embodiment of the present invention, wherein flash memory module 124 may be a 3D NAND gate type flash memory module. Figure 3 As shown, block 200 may contain multiple memory cells, such as Figure 3 The floating gate transistor 202 or other charge trapping component shown, in a 3D NAND gate flash memory architecture, can be transmitted through multiple bit lines. Figure 3Only bit lines BL1 to BL3 and multiple word lines are shown in the diagram. Figure 3 The text only shows character lines WL0 to WL2 and character lines WL4 to WL6 to form the character line. Figure 3 Taking the topmost plane as an example, all floating gate transistors on word line WL0 form at least one page, all floating gate transistors on word line WL1 form at least another page, and all floating gate transistors on word line WL2 form at least another page, and so on. Furthermore, the definition between word lines WL0 and pages (e.g., logic pages) can vary depending on the flash memory's writing method. Specifically, when storing data using a single-level cell (SLC) architecture, all floating-gate transistors on word lines WL0 correspond to a single logic page; when storing data using a multi-level cell (MLC) architecture, all floating-gate transistors on word lines WL0 correspond to two logic pages; when storing data using a triple-level cell (TLC) architecture, all floating-gate transistors on word lines WL0 correspond to three logic pages; and when storing data using a quad-level cell (QLC) architecture, all floating-gate transistors on word lines WL0 correspond to four logic pages. The 3D NAND gate flash memory architecture and the relationship between word lines and pages are well known to those skilled in the art, and for the sake of brevity, the relevant details will not be repeated here.

[0063] In this embodiment, the host device 110 can configure at least a portion of the flash memory module 124 as a zoned namespace by transmitting a settling command set (such as a zoned namespace command set). Please refer to [reference needed]. Figure 4The host device 110 can transmit a set of configuration commands to the flash memory controller 122, so that the flash memory module 124 has at least one partition namespace (in this embodiment, partition namespaces 410_1 and 410_2 are used as examples) and at least one general storage space (in this embodiment, general storage spaces 420_1 and 420_2 are used as examples). Partition namespace 410_1 can be divided into multiple zones for access, and the host device 110 must perform a data write operation based on a logical block address (LBA) in partition namespace 410_1. A logical block address (referred to as a logical address) can represent a 512-byte data entry or a 4-kilobyte (KB) data entry, and the host device 110 needs to write data continuously into a zone. Specifically, please refer to... Figure 5 The partition namespace 410_1 can be divided into multiple regions (e.g., region Z0 to region Z3). The logical addresses in each region must be contiguous, and there must be no overlapping logical addresses between regions (i.e., a logical address can only exist in one region). For example, if the size of each region is "x" logical addresses and the starting logical address of region Z3 is logical address LBA_k, then region Z3 is used to store data using logical addresses LBA_k, logical address LBA_(k+1), logical address LBA_(k+2), logical address LBA_(k+3)... and logical address LBA_(k+x-1). In one embodiment, the logical addresses of adjacent regions can also be contiguous. For example, region Z0 is used to store data using logical addresses LBA_1 to LBA_2000, region Z1 is used to store data using logical addresses LBA_2001 to LBA_4000, region Z2 is used to store data using logical addresses LBA_4001 to LBA_6000, and region Z3 is used to store data using logical addresses LBA_6001 to LBA_8000, and so on. Furthermore, the amount of data corresponding to a logical address can be determined by the host device 110. For example, the amount of data corresponding to a logical address can be 4 kilobytes.

[0064] Furthermore, when data is written to each region, the data is written in the order of its multiple logical addresses. In detail, the flash memory controller 122 can set a writepoint based on the data already written to control the data writing sequence. Assuming region Z1 is used to store data using logical addresses LBA_2001 to LBA_4000, after host device 110 transmits data corresponding to logical addresses LBA_2001 to LBA_2051 to flash memory controller 122, flash memory controller 122 can set the write point to the next logical address LBA_2052. If host device 110 subsequently transmits data belonging to the same region but without logical address LBA_2052 (for example, host device 110 transmits data with logical address LBA_3000), then flash memory controller 122 can refuse the data write operation and send a write failure message back to host device 110. In other words, flash memory controller 122 will only allow the data write operation if the logical address of the received data is the same as the logical address indicated by the write point. Furthermore, if data is written alternately in multiple regions, each region can have its own write point.

[0065] Furthermore, the Non-volatile Memory Host Controller Interface Specification provides a deallocate command, which is transmitted from host device 110 to request the deletion of data corresponding to a logical address range. The Non-volatile Memory Host Controller Interface Specification also indicates that a flash memory controller can recommend host device 110 to perform a reset command to control a region from a full state to an empty state. Therefore, the following embodiments are proposed so that flash memory controller 122 can effectively and correctly recommend host device 110 to perform a reset command.

[0066] Figure 6This is a flowchart illustrating the writing of data from host device 110 to partition namespace 410_1 according to an embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is greater than the size of each physical block in flash memory module 124, and the amount of data corresponding to each region is not an integer multiple of the size of each physical block in flash memory module 124. In step 600, the process begins, and the host device 110 and storage device 120_1 are powered on and an initialization operation is completed. The host device 110 sets basic settings (e.g., the size of each region, the number of regions, and the logical block address size) for at least a portion of the storage regions of storage device 120_1 using a partition namespace command set. In step 602, the host device 110 transmits a write command and corresponding data to flash memory controller 122, wherein the data is data corresponding to one or more regions, such as data corresponding to one or more regions in flash memory module 124. Figure 5 The data at logical addresses LBA_k to LBA_(k+x-1) in region Z3 is shown. In step 604, the flash memory controller 122 selects at least one block (e.g., a blank block, i.e., a spare block) from the flash memory module 124 and sequentially writes the data from the host device 110 into the at least one block. Since the size of the region set by the host device 110 is difficult to match with the size of the physical block, after the host device 110 transmits the write command to all logical addresses in region Z3, the data to be written by the host device 110 usually cannot completely fill the storage space of the physical block. In other words, the data storage capacity corresponding to a region is usually not an integer multiple of the size of the physical block used to store the data written by the host device 110. In step 606, after writing data to the last block and completing the data writing process, the flash memory controller 122 writes invalid data to the remaining pages of the last block, or simply leaves the remaining pages blank. It should be noted that each block typically reserves multiple pages to store system management information, including a write schedule, an entity-to-logic mapping table, error correction code check bits, and redundant array of independent disks parity (RAID parity), etc. The aforementioned remaining pages represent the pages remaining after system management information and the data to be stored by the host device 110 have been written to the last block.

[0067] For example, please refer to Figure 7Assume that the amount of data corresponding to each region is between two and three blocks in the flash memory module 124. In response to a write command transmitted by the host device 110 for region Z1, the flash memory controller 122 can sequentially write the data of region Z1 to blocks B3, B7, and B8. It should be noted that, in one embodiment, the write command transmitted by the host device 110 for region Z1 may include the starting logical address of region Z1, and the flash memory controller 122 can map the starting logical address of region Z1 to the starting physical storage space (e.g., the first physical page) of physical block B3, and store the data corresponding to the starting logical address of region Z1 in the starting physical storage space (e.g., the first physical page) of physical block B3. Blocks B3, B7, and B8 each contain pages P1 to PM, and from the first page P1 of block B3 to the last page PM of block B3, the data in region Z1 is written sequentially according to the logical address. After the data in block B3 is written, the write operation continues from the first page P1 of block B7 to the last page PM of block B7. It should be noted that even if the host device 110 continues to write to the logical address in region Z1, the flash memory controller 122 can still select discontinuous blocks B3 and B7 to store data that is contiguous in the logical address. After the data in block B7 is written, the data continues to be written to the first page P1 of block B8 until the end of the data in block Z1. In addition, the remaining pages of block B8 remain blank or contain invalid data written to them. Similarly, the flash memory controller 122 can sequentially write the data in region Z3 to blocks B12, B99, and B6, where blocks B12, B99, and B6 each contain pages P1 to PM, and from the first page P1 of block B12 to the last page PM of block B12. The data in region Z3 is written sequentially according to the logical address. After the data in block B12 is written, data continues to be written from the first page P1 of block B99 to the last page PM of block B99. Similarly, after the data in block B99 is written, data continues to be written from the first page P1 of block B6 until the data in block Z3 ​​ends. Furthermore, the remaining pages of block B6 remain blank or contain invalid data. It should be noted that the flash memory controller 122 may not establish a logical page-to-physical page mapping for physical pages storing invalid data. The flash memory controller 122 typically sets physical blocks with blank physical pages or physical blocks with invalid data as the last part of each region. In other words, the flash memory controller 122 stores the data corresponding to the last logical address of the region into physical blocks with blank pages or invalid data.

[0068] In step 608, the flash memory controller 122 establishes or updates a logical-to-physical (L2P) address mapping table to record the mapping relationship between logical addresses and physical addresses for subsequent data reading in the partition namespace 410_1. Figure 8 This is a schematic diagram of a logical-to-entity address mapping table 800 according to an embodiment of the present invention. The logical-to-entity address mapping table 800 may contain two fields, one field recording the starting logical address of a region, and the other field recording the entity block address of the block. Please refer to the accompanying documentation. Figure 7 as well as Figure 8 Since the data of region Z1 is written sequentially to blocks B3, B7, and B8, and the data of region Z3 is written sequentially to blocks B12, B99, and B6, the logical-to-physical address mapping table 800 records the starting logical address Z1_LBA_S of region Z1, the physical block address PBA3 of block B3, the physical block address PBA7 of block B7, and the physical block address PBA8 of block B8, and also records the starting logical address Z3_LBA_S of region Z3, the physical block address PBA12 of block B12, the physical block address PBA99 of block B99, and the physical block address PBA6 of block B6. For example, suppose region Z1 is used to store data with logical addresses LBA_2001 to LBA_4000, and region Z3 is used to store data with logical addresses LBA_6001 to LBA_8000. The starting logical address Z1_LBA_S of region Z1 is logical address LBA_2001, and the starting logical address Z3_LBA_S of region Z3 is logical address LBA_6001. It should be noted that as long as the same purpose is achieved, the steps in the flowchart for writing data from host device 110 to partition namespace 410_1 do not need to be performed in a fixed order. For example, step 608 can be performed after step 602, which is understandable to those skilled in the art under the teachings of this invention. It should be noted that in this embodiment, each entity block corresponds to only a single region. For example, blocks B3, B7, and B8 correspond to only region Z1, and blocks B12, B99, and B6 correspond to only region Z3. In other words, a single block stores data in only a single region. For example, blocks B3, B7, and B8 store data corresponding to region Z1, and blocks B12, B99, and B6 store data corresponding to region Z3.

[0069] It is important to note that Figure 8The logical-to-entity address mapping table 800 shown is for illustrative purposes only, and the present invention is not limited thereto. In other embodiments of the present invention, the logical-to-entity address mapping table may contain each logical address and its corresponding entity address, or the logical-to-entity address mapping table may contain multiple entity addresses and their corresponding logical address ranges.

[0070] In addition, the flash memory controller 122 can establish a valid page count table, which records the number of valid pages in a block, where valid pages represent data that is not old data (that is, the flash memory module 124 does not have other data with the same logical address used to update old data). Figure 9 This is a schematic diagram of an effective page count table 900 according to an embodiment of the present invention. Figure 9 As shown, assuming the effective page count table 900 contains real-time information after the data in regions Z1 and Z3 has been completely written to the flash memory module 12, the effective page counts for physical blocks B3, B7, and B8 corresponding to region Z1 are "128", "128", and "60", respectively, and the effective page counts for physical blocks B12, B99, and B6 corresponding to region Z3 are "128", "128", and "60", respectively. In one embodiment, the effective page count table 900 is temporarily stored in the buffer memory 216.

[0071] Next, if the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate data corresponding to a logical address range, the microprocessor 212 updates the logical-to-physical address mapping table to remove information for that logical address range, so that the data corresponding to that logical address range can be considered invalid data. For example, the logical-to-physical address mapping table is updated to remove the corresponding physical address for that logical address range, or the logical-to-physical address mapping table is updated to indicate that the logical address range does not have a corresponding physical address. Afterward, the microprocessor 212 updates the valid page count table 900 based on the page number corresponding to that logical address range. For example, if the deallocation command from the host device 110 indicates a logical address range corresponding to 30 pages of data within block B3, the valid page count table 900 is updated so that the valid page count for block B3 becomes "98".

[0072] Furthermore, the microprocessor 212 can check the valid page count table 900 and a zone-block mapping table to determine whether any zone contains no valid data. The zone-block mapping table may contain information about each zone and its corresponding physical block. Figure 7As an example, region Z1 corresponds to blocks B3, B7, and B8, and region Z3 corresponds to blocks B12, B99, and B6. In one embodiment, a logical-to-physical address mapping table 800 can serve as this region-block mapping table. Specifically, if the microprocessor 212 detects that blocks B3, B7, and B8 corresponding to region Z1 do not contain valid data (i.e., the valid page count of each block B3, B7, and B8 is equal to 0), the microprocessor 212 can proactively notify the host device 110 to suggest that the host device 110 perform a reset command to control region Z1 from a full state to an empty state. Only after receiving the reset command can the microprocessor 212 erase blocks B3, B7, and B8 and set blocks B3, B7, and B8 as spare blocks (e.g., blank blocks) for storing other data.

[0073] In one embodiment, the flash memory controller 122 may further include multiple registers, each register storing a reset zone recommended attribute for a region. This reset zone recommended attribute indicates whether the flash memory controller 122 detects that there is no valid data in the region. Specifically, if the microprocessor 212 detects that there is no valid data in blocks B3, B7, and B8 corresponding to region Z1, the microprocessor 212 can set the register corresponding to region Z1 to "1". Once the host device 110 detects that the register corresponding to region Z1 has a value of "1", the host device 110 may consider whether to send a reset command to the flash memory controller 122.

[0074] In another embodiment, if the microprocessor 212 detects that there is no valid data in blocks B3, B7 and B8 corresponding to region Z1, the flash memory controller 122 may proactively transmit a zone descriptor changed event to the host device 110 for region Z1, so as to suggest that the host device 110 transmit a reset command to reset the region.

[0075] Figure 10 This is a flowchart of a control method for a flash memory controller 122 according to an embodiment of the present invention. Please refer to the above description. Figures 6-9 An example of this is described in the following process.

[0076] In step 1000, the process begins.

[0077] In step 1002, the flash memory controller determines whether it has received a deallocation command from the host device. If yes, proceed to step 1004; otherwise, return to step 1002.

[0078] In step 1004, the flash memory controller updates the logic to the physical address mapping table and the valid page count table.

[0079] In step 1006, the flash memory controller refers to the valid page count table to determine whether any region does not contain any valid data. If so, proceed to step 1008; otherwise, return to step 1002.

[0080] In step 1008, the flash memory controller recommends that the host device resend a reset command to reset the area that does not contain valid data.

[0081] Figure 11 This is a flowchart illustrating the writing of data from host device 110 to partition namespace 410_1 according to another embodiment of the present invention. In this embodiment, it is assumed that the amount of data corresponding to each region is greater than the size of each block in flash memory module 124, and the amount of data corresponding to each region is not an integer multiple of the size of each block in flash memory module 124. In step 1100, the process begins by powering on host device 110 and storage device 120_1 and completing initialization operations. Host device 110 sets storage device 120_1 to have basic settings (e.g., the size of each region, the number of regions, and the logical block address size) using a partition namespace command set. In step 1102, host device 110 transmits a write command and corresponding data to flash memory controller 122, wherein the data corresponds to data in one or more regions (e.g., corresponding to...). Figure 5 The data in region Z3 shown is located at logical addresses LBA_k to LBA_(k+x-1). In step 1104, the flash memory controller 122 selects at least one block from the flash memory module 124 (e.g., a blank block, i.e., a spare block), or selects at least one blank block or at least one shared block to sequentially write data from the host device 110 to these blocks. For example, please refer to... Figure 12Assuming the data volume corresponding to each region is between two and three blocks in the flash memory module 124, and the flash memory controller 122 can sequentially write the data of region Z1 into blocks B3, B7, and B8, where block B3 records the first part of the data Z1_0 of region Z1, block B7 records the second part of the data Z1_1 of region Z1, and block Z8 records the third part of the data Z1_2 of region Z1. In this embodiment, since all the data stored in blocks B3 and B7 is data from region Z1, and only a portion of the pages in region B8 store data from region Z1, in order to utilize the remaining pages in block B8, the microprocessor 212 can set block B8 as a shared block. That is, the remaining pages in block B8 can be used to store data from other regions.

[0082] Please refer to Figure 12 The flash memory controller 122 prepares to write the data of region Z3 to the partition namespace 410_1. Since there is a spare space in the shared block B8, the microprocessor 212 can select the blank block B12, the blank block B99, and the shared block B8 to store the data in region Z3. Specifically, the flash memory controller 122 sequentially writes the data of region Z3 to blocks B12, B99, and B8, where block B12 records the first part of the data Z3_0 of region Z3, block B99 records the second part of the data Z3_1 of region Z3, and block B8 records the third part of the data Z3_2 of region Z3. In this embodiment, all data stored in blocks B12 and B99 are data from region Z3, while block B8 records the third part of data Z1_2 from region Z1 and the third part of data Z3_2 from region Z3. It's important to note that for ease of management, to reduce the complexity of establishing the logical-to-physical address mapping table through the flash memory controller 122, the flash memory controller 122 does not store the first data of any region in a shared block. Instead, the flash memory controller 122 stores the first data of each region in an exclusive block (such as blocks B3 and B12). These exclusive blocks only store data belonging to the same region, hence they are called exclusive blocks. The last data of any region (the data corresponding to the last logical address of that region) is stored in a shared block (e.g., block B8), and the last data of another region is also stored in this shared block. In this embodiment, the shared block stores data from multiple regions; in other words, the shared block stores the last data from multiple regions, while the exclusive block stores data from only a single region.

[0083] In step 1106, the flash memory controller 122 establishes or updates a logical-to-physical address mapping table to record the mapping relationship between logical addresses and physical addresses, and establishes a shared block table for subsequent data reading of the partition namespace 410_1. Figure 13 This is a schematic diagram of a logical-to-entity address mapping table 1300 and a shared block table 1330 according to an embodiment of the present invention. The logical-to-entity address mapping table 1300 may include two fields, one field recording the logical address and the other field recording the entity address of the block. Please refer to the accompanying diagram. Figure 12 as well as Figure 13 Since the data of region Z1 is written sequentially to blocks B3, B7, and B8, and the data of region Z3 is written sequentially to blocks B12, B99, and B8, the logical-to-physical address mapping table 1300 records the starting logical address Z1_LBA_S of region Z1, the physical block address PBA3 of block B3, the logical address (Z1_LBA_S+y) of region Z1, the physical block address PBA7 of block B7, the logical address (Z1_LBA_S+2*y) of region Z1, and the physical block address PBA8 of block B8. The logical address (Z1_LBA_S+y) can be used as the first logical address of the data written to block B7 (that is, the first logical address of the second part of data Z1_1), and the logical address (Z1_LBA_S+2*y) can be used as the first logical address of the data written to block B8 (that is, the first logical address of the third part of data Z1_2).

[0084] Similarly, the logical-to-physical address mapping table 1300 records the starting logical address Z3_LBA_S of region Z3, the physical block address PBA12 of block B12, the logical address (Z3_LBA_S+y) of region Z3, the physical block address PBA99 of block B99, the logical address (Z3_LBA_S+2*y) of region Z3, and the physical block address PBA8 of block B8. The logical address (Z3_LBA_S+y) can be used as the first logical address of the data written to block B99 (that is, the first logical address of the second part of data Z3_1, which corresponds to the logical address of the first page P1 of block B99), and the logical address (Z3_LBA_S+2*y) can be used as the first logical address of the data written to block B8 (that is, the first logical address of the third part of data Z3_2). It should be noted that the "y" mentioned above can represent the number of data entries from host device 110 with different logical addresses that can be stored in a block. It is important to note that after host device 110 sets the region size and number of regions, the starting logical address of each region and the starting logical address of each sub-region are determined, such as starting logical address Z1_LBA_S, logical address (Z1_LBA_S+y), logical address (Z1_LBA_S+2*y), starting logical address Z3_LBA_S, logical address (Z3_LBA_S+y), and logical address (Z3_LBA_S+2*y). Therefore, the logical-to-physical address mapping table 1300 can be further simplified to have only one column, that is, only one column for the physical block address, and the logical address column can be represented by the entries in this table, without actually storing the starting logical addresses of multiple sub-regions.

[0085] Furthermore, the shared block table 1330 may contain two fields, one field recording the logical address, and the other field recording the entity block address and entity page address corresponding to the logical address. Figure 13In the shared block table 1330, the first logical address (Z1_LBA_S+2*y) of the third part of data Z1_2 in region Z1, the corresponding entity block address PBA8, and the entity page address P1 are recorded. That is, the data corresponding to the first logical address in the third part of data Z1_2 is written to the first page P1 of block B8. Similarly, the first logical address (Z3_LBA_S+2*y) of the third part of data Z3_2 in region Z3, the corresponding entity block address PBA8, and the entity page address P61 are recorded. In other words, the data corresponding to the first logical address in the third part of data Z3_2 is written to the sixty-first page P61 of block B8. It should be noted that the above assumes that each page in the block can only store data with a single logical address; however, the actual situation can be adjusted depending on how many data entries with different logical addresses can be stored on a single page.

[0086] Furthermore, it should be noted that during the writing of data in regions Z1 and Z3, the write operation may not begin writing data in region Z3 only after all data in region Z1 has been written to the partition namespace 410_1. In other words, the flash memory controller 122 may need to start writing data in region Z3 to the partition namespace 410_1 before the data in region Z1 has been completely written. Therefore, in another embodiment of the present invention, the shared block table 1330 may additionally include a completion indicator field, which is used to indicate whether the data in a region has been completely written to the shared block. The microprocessor 212 can refer to the completion indicator corresponding to region Z1 to determine whether the data in region Z3 can be written to block B8.

[0087] It is important to note that Figure 13 The logical-to-entity address mapping table 1300 and the shared block table 1330 shown are for illustrative purposes only. In other embodiments of the present invention, the logical-to-entity address mapping table 1300 and the shared block table 1330 may contain each logical address and its corresponding entity address, or the logical-to-entity address mapping table 1300 and the shared block table 1330 may contain multiple entity addresses and their corresponding logical address ranges.

[0088] In addition, the flash memory controller 122 can establish a valid page count table, which records the number of valid pages in the block, where valid pages represent data that is not old data (that is, the flash memory module 124 does not have other data with the same logical address used to update old data). Figure 14 This is a schematic diagram of an effective page count table 1400 according to an embodiment of the present invention. Figure 14As shown, assume that the effective page count table 1400 contains real-time information after the data in region Z1 has been completely written to the flash memory module 124, but the data in region Z3 has not yet been completely written to block B8. The effective page counts for blocks B3, B7, and B8 corresponding to region Z1 are "128", "128", and "86", respectively, and the effective page counts for blocks B12, B99, and B8 corresponding to region Z3 are "128", "128", and "86", respectively. The third portion of data Z1_2 in region Z1 has 60 pages in block B8, and the third portion of data Z3_2 in region Z3 temporarily has 26 pages in block B8. In one embodiment, the effective page count table 1400 is temporarily stored in the buffer memory 126.

[0089] In addition, each shared block has a detailed valid page count table, which clearly indicates the valid page count of the area. Figure 15 This is a schematic diagram of a detailed valid page count table 1500 according to an embodiment of the present invention, wherein the detailed valid page count table 1500 provides... Figures 12-14 Use the shared block B8. For example... Figure 15 As shown, the detailed valid page count table 1500 has four fields: zone number, starting physical page address, full information, and valid page count. The starting physical page address field records the starting physical page address for each zone; for example, page P1 corresponding to the third part of data Z1_2 in zone Z1 and page P61 corresponding to the third part of data Z3_2 in zone Z3. The full information field records whether all data in the zone has been completely written to block B8. In this example, the data in zone Z1 has been completely written to the flash memory module 124, while the data in zone Z3 has not yet been completely written to block B8. The valid page count field records the current valid page count for each zone; for example, the valid page count for the third part of data Z1_2 in zone Z1 is "60", and the valid page count for the third part of data Z3_2 in zone Z3 is "26".

[0090] Next, if the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate data corresponding to a logical address range, the microprocessor 212 updates the logical-to-physical address mapping table to remove information for that logical address range, so that the data corresponding to that logical address range can be considered invalid data. For example, the logical-to-physical address mapping table is updated to remove the corresponding physical address for that logical address range, or the logical-to-physical address mapping table is updated to indicate that the logical address range does not have a corresponding physical address. Subsequently, the microprocessor 212 updates the effective page count table 1400 and / or the detailed effective page count table 1500 based on the page number corresponding to the logical address range. For example, if the deallocation command from the host device 110 indicates a logical address range corresponding to 30 pages of data within block B8, and the logical address range corresponds to region Z1, then the effective page count table 1400 is updated so that the effective page count of block B8 becomes "56", and the detailed effective page count table 1500 is updated so that the effective page count of the third part of the data Z1_2 in region Z1 becomes "30".

[0091] Furthermore, the microprocessor 212 can check the valid page count table 1400, the detailed valid page count table 1500, and a region-block mapping table to determine whether any region contains no valid data. The region-block mapping table may contain information about each region and its corresponding physical block. Figure 12 As an example, region Z1 corresponds to blocks B3, B7, and B8, and region Z3 corresponds to blocks B12, B99, and B8. In one embodiment, the logical-to-physical address mapping table 1300 can serve as the region-block mapping table. Specifically, if the microprocessor 212 detects that there is no valid data in blocks B3 and B7 corresponding to region Z1 (i.e., the valid page counts of blocks B3 and B7 are both equal to 0), and pages P1 to P60 in block B8 do not have valid data (i.e., the valid page count of the third part of data Z1_2 in region Z1 is equal to 0), and the detailed valid page count table 1500 indicates that all data in region Z1 has been completely written to the flash memory module 124, then the microprocessor 212 can proactively notify the host device 110 to suggest that it perform a reset command to control region Z1 from a full state to an empty state. Only after receiving the reset command can the microprocessor 212 erase blocks B3 and B7 and set them as spare blocks (i.e. blank blocks) for storing other data. Note that since block B8 contains data from region Z3, even if region Z1 is reset, block B8 cannot be released as a spare block.

[0092] It should be noted that, in order to avoid erroneously determining that a region does not contain any valid data, the microprocessor 212 may suggest that the host device 110 use only... Figure 15 The full information field shown indicates that a reset command will only be executed when all data in the region has been completely written to the flash memory module 124. Specifically, if the host device 110 sends one or more deallocation commands to deallocate the logical addresses corresponding to all written data in region Z3 (e.g., logical addresses corresponding to all pages in blocks B12 and B99 and 26 pages in block B8), but the full information field shown in Figure 15 indicates that all data in region Z3 has not yet been completely written to the flash memory module 124 (that is, it means that the remaining data in region Z3 can be written to block B8 after one cycle), then the microprocessor 212 should not suggest that the host device 100 execute a reset command to reset region Z3.

[0093] In one embodiment, the flash memory controller 122 may further include multiple registers, each register storing a reset region suggestion attribute for a region, and the reset region suggestion attribute indicating whether the flash memory controller 122 has detected no valid data in the region. In another embodiment, if the microprocessor 212 detects no valid data in blocks B3, B7, and B8 corresponding to region Z1, the flash memory controller 122 may proactively transmit a region descriptor change event to the host device 110 for region Z1, suggesting that the host device 110 transmit a reset command to reset the region.

[0094] Figure 16 This is a flowchart of a control method for a flash memory controller 122 according to an embodiment of the present invention. Please refer to the accompanying diagram. Figures 11-15 The process described in the above embodiments is as follows.

[0095] In step 1600, the process begins.

[0096] In step 1602, the flash memory controller determines whether it has received a deallocation command from the host device. If yes, proceed to step 1604; otherwise, return to step 1602.

[0097] In step 1604, the flash memory controller updates the logic to the physical address mapping table, the valid page count table, and / or the detailed valid page count table.

[0098] In step 1606, the flash memory controller refers to the valid page count table and the detailed valid page count table to determine whether any region does not contain any valid data. If yes, proceed to step 1608; otherwise, return to step 1602.

[0099] In step 1608, the flash memory controller suggests that the host device send a reset command to reset the area that does not contain valid data.

[0100] exist Figures 6-10 In the illustrated embodiment, each block corresponds to only a single region, and the microprocessor 212 checks the valid page count table 900 and a region-block mapping table to determine whether any region contains no valid data, in order to determine whether to recommend that the host device 110 send a reset command. Figures 11-16 In the illustrated embodiment, since one block can correspond to multiple regions, the microprocessor 212 checks the valid page count table 1400, the detailed valid page count table 1500, and a region-block mapping table to determine whether any region contains no valid data, in order to determine whether to recommend that the host device 110 send a reset command. In another embodiment, the microprocessor 212 may establish a region valid page count table based on the valid page count table 900 or based on the valid page count table 1400 and the detailed valid page count table 1500, in order to determine whether any region contains no valid data.

[0101] Figure 17 This is a schematic diagram of a region effective page count table 1700 according to an embodiment of the present invention. Figure 17 As shown, the region effective page count table 1700 contains information about the effective page count for each region. In this embodiment, the region effective page count table 1700 is updated immediately when the effective page count table 900 is updated, or when the effective page count table 1400 and / or the detailed effective page count table 1500 are updated. For example, if all data for each region is written to 282 pages of the flash memory module 124, and the effective page count table 900 is updated to reduce the effective page count corresponding to region Z1 due to a first deallocation command, then the region effective page count table 1700 is updated based on the updated effective page count. The page count table 900 is immediately updated (e.g., the effective page count for region Z1 is updated from "282" to "100"). Then, if the effective page count table 900 is further updated to reduce the effective page count corresponding to region Z1 due to a second deallocation command, the region effective page count table 1700 is immediately updated based on the updated effective page count table 900 (e.g., the effective page count for region Z1 is updated from "100" to "0"). After that, the microprocessor 212 can determine whether any region has no valid data based on the region effective page count table 1700 without referring to other tables (e.g., effective page count table 900 or effective page count table 1400).

[0102] Figure 18 This is a flowchart of a control method for a flash memory controller 122 according to an embodiment of the present invention. Please refer to the above description. Figure 17 An example of this process is described below.

[0103] In step 1800, the process begins.

[0104] In step 1802, the flash memory controller determines whether it has received a deallocation command from the host device. If yes, it proceeds to step 1804; otherwise, it returns to step 1802.

[0105] In step 1804, the flash memory controller updates the logic to the physical address mapping table, the valid page count table, and / or the detailed valid page count table.

[0106] In step 1806, the flash memory controller updates the region valid page count table based on the updated valid page count table and / or the updated detailed valid page count table.

[0107] In step 1808, the flash memory controller refers to the region valid page count table to determine whether any region does not contain any valid data. If so, proceed to step 1810; otherwise, return to step 1802.

[0108] In step 1810, the flash memory controller suggests that the host device send a reset command to reset the area that does not have valid data.

[0109] In the above embodiments, if the host device 110 transmits an erroneous deallocation command, the effective page count table 900, the effective page count table 1400, and the region effective page count table 1700 may contain errors. This will cause the microprocessor 212 to make an incorrect decision. For example, if the host device 110 transmits a first deallocation command indicating a first logical address range, and then transmits a second deallocation command indicating a second logical address range that partially overlaps with the first logical address range, the calculation of the effective page count may be incorrect. To solve this problem, the region effective page count table can be modified to have a deallocation command history field to record the status of each page. Specifically, please refer to... Figure 19 , Figure 19This is a schematic diagram of a region valid page mapping table 1900 according to an embodiment of the present invention. The region valid page mapping table 1900 may include a deallocation command history field, wherein the deallocation command history field may contain multiple bits, and each bit is used to indicate whether the data of a corresponding page is valid or invalid. For example, if a region has 282 pages, the deallocation command history field contains 282 bits, and each bit corresponds to a page. If the bit is equal to "1", it means that the data in the corresponding page is valid; and if the bit is equal to "0", it means that the data in the corresponding page is invalid. Figure 19 In the embodiment shown, since all data in regions Z1 to Z3 is rewritten to the flash memory module 124 and no deallocation command is received, the bits in the deallocation command history field are all equal to "1", and the effective page count for each region Z1 to Z3 is equal to "282".

[0110] Next, if the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate a logical address range, the microprocessor 212 can refer to the logical address range in the deallocation command to flip the corresponding bits in the deallocation command history field. Specifically, please refer to... Figure 20 If the flash memory controller 122 receives a deallocation command from the host device 110 to deallocate a logical address range corresponding to 100 pages, the microprocessor 212 can update the bit in the deallocation command history field corresponding to the 100 pages from "1" to "0".

[0111] It should be noted that the zone valid page mapping table 1900 can be updated based solely on the deallocation command from the host device 110, without referring to the valid page count table 900, the valid page count table 1400, and the detailed valid page count table 1500.

[0112] exist Figure 19 In the illustrated embodiment, the term "page" can refer to a physical page (e.g., 16 kilobytes) corresponding to a block or a logical address range (e.g., a logical block address, 4 kilobytes).

[0113] Figure 21 This is a flowchart of a control method for a flash memory controller 122 according to an embodiment of the present invention. Please refer to the above description. Figure 19 as well as Figure 20 An example of this process is described below.

[0114] In step 2100, the process begins.

[0115] In step 2102, the flash memory controller determines whether it has received a deallocation command from the host device. If yes, it proceeds to step 2104; otherwise, it returns to step 2102.

[0116] In step 2104, the flash memory controller updates the region valid page count table based on the logical address range of the deallocation command.

[0117] In step 2106, the flash memory controller refers to the region valid page count table to determine whether any region does not have any valid data. If so, proceed to step 2018; otherwise, return to step 2102.

[0118] In step 2108, the flash memory controller suggests that the host device send a reset command to reset the area that does not have valid data.

[0119] In summary, in the control method of the flash memory controller of the present invention, by establishing a valid page count table, a detailed valid page count table, and / or a region valid page count table based on the deallocation command from the host device, the flash memory controller can effectively and quickly determine whether any region does not have any valid data, so that the flash memory controller can suggest the host device to send a reset command to reset the region.

[0120] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made within the scope of the claims of the present invention should be included in the scope of the present invention.

Claims

1. A control method for a flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising a plurality of blocks, and the control method comprises: A host device receives a configuration command, wherein the configuration command configures at least a portion of the flash memory module as a partition namespace, the partition namespace logically containing multiple regions, the host device performs a region-based data write operation on the partition namespace, each region having the same size, multiple logical addresses corresponding to each region being consecutive, and the multiple logical addresses not overlapping between the multiple regions. Write data from a first region to multiple first blocks; Establish a region-block mapping table, wherein the region-block mapping table contains information about the first region and the corresponding multiple first blocks; After the data is written to the multiple first blocks, a valid page count table is created or updated; The host device receives at least one deallocation command, wherein each deallocation command contains a logical address range to be deallocated; The effective page count table is updated according to the at least one deassignment command to produce an updated effective page count table; Based on the updated valid page count table, determine whether the multiple valid page counts of all the multiple first blocks corresponding to the first region are zero; as well as If the multiple valid page counts for all of the multiple first blocks corresponding to the first region are zero, the host device is advised to send a reset command to reset the first region.

2. The control method as described in claim 1, characterized in that, If the valid page counts for all of the plurality of first blocks corresponding to the first region are zero, the step of recommending that the host device transmit the reset command includes: A reset region suggestion attribute corresponding to the first region is set from a first logical value to a second logical value, wherein the reset region suggestion attribute with the first logical value is used to indicate that not all data corresponding to the first region becomes invalid, the reset region suggestion attribute with the second logical value is used to indicate that all data corresponding to the first region becomes invalid, and the reset region suggestion attribute is read by the host device to determine whether to send the reset command to the flash memory controller.

3. The control method as described in claim 1, characterized in that, The valid page count table records each block and its corresponding valid page count.

4. The control method as described in claim 1, characterized in that, The valid page count table is a region valid page count table. The region valid page count table records multiple bits for each region, and each bit corresponds to a logical address range, which corresponds to a physical page or a logical address unit.

5. The control method as described in claim 4, characterized in that, For each bit in the valid page count table for that region, if the bit has a first logical value, it means that the data corresponding to that bit is valid; if the bit has a second logical value, it means that the data corresponding to that bit is invalid; and the step of determining whether the multiple valid page counts of all the multiple first blocks corresponding to the first region are zero based on the updated valid page count table includes: If all bits corresponding to the plurality of first regions are zero, then the multiple valid page counts of all the plurality of first blocks corresponding to the first regions are determined to be zero.

6. A flash memory controller, wherein the flash memory controller is used to access a flash memory module, the flash memory module comprising a plurality of blocks, and the flash memory controller comprises: A read-only memory used to store a program code; A microprocessor is used to execute the program code to control access to the flash memory module; as well as A buffer memory; The microprocessor is used for: A host device receives a configuration command, wherein the configuration command configures at least a portion of the flash memory module as a partition namespace, the partition namespace logically containing multiple regions, the host device performs a region-based data write operation on the partition namespace, each region having the same size, multiple logical addresses corresponding to each region being contiguous, and the multiple logical addresses not overlapping between the multiple regions. Write data from a first region to multiple first blocks; Establish a region-block mapping table, wherein the region-block mapping table contains information about the first region and the corresponding multiple first blocks; After the data is written to the multiple first blocks, a valid page count table is created or updated; The host device receives at least one deallocation command, wherein each deallocation command contains a logical address range to be deallocated; The effective page count table is updated according to the at least one deassignment command to produce an updated effective page count table; Based on the updated valid page count table, determine whether the multiple valid page counts of all the multiple first blocks corresponding to the first region are zero; as well as If the multiple valid page counts for all of the multiple first blocks corresponding to the first region are zero, the host device is advised to send a reset command to reset the first region.

7. The flash memory controller as described in claim 6, characterized in that, If the valid page counts for all of the plurality of first blocks corresponding to the first region are zero, the step of recommending that the host device transmit the reset command includes: A reset region suggestion attribute corresponding to the first region is set from a first logical value to a second logical value, wherein the reset region suggestion attribute having the first logical value is used to indicate that not all data corresponding to the first region becomes invalid, the reset region suggestion attribute having the second logical value is used to indicate that all data corresponding to the first region becomes invalid, and the reset region suggestion attribute is read by the host device to determine whether to send the reset command to the flash memory controller.

8. The flash memory controller as described in claim 6, characterized in that, The valid page count table records each block and its corresponding valid page count.

9. The flash memory controller as described in claim 6, characterized in that, The valid page count table is a region valid page count table. The region valid page count table records multiple bits for each region, and each bit corresponds to a logical address range, which corresponds to a physical page or a logical address unit.

10. The flash memory controller as described in claim 9, characterized in that, For each bit in the valid page count table for that region, if the bit has a first logical value, it means that the data corresponding to that bit is valid; if the bit has a second logical value, it means that the data corresponding to that bit is invalid; and the step of determining whether the multiple valid page counts of all the multiple first blocks corresponding to the first region are zero based on the updated valid page count table includes: If all bits corresponding to the first region are zero, then the valid page count of all the first blocks corresponding to the first region is zero.

11. A storage device comprising: A flash memory module, wherein the flash memory module comprises multiple blocks; and A flash memory controller for accessing the flash memory module; The flash memory controller receives a configuration command from a host device, which configures at least a portion of the flash memory module as a partition namespace, which logically contains multiple regions. The host device performs a region-based data write operation on the partition namespace. Each region has the same size, and the multiple logical addresses corresponding to each region are contiguous and do not overlap between the multiple regions. The flash memory controller writes data from a first region to multiple first blocks and establishes a region-block mapping table, which contains information about the first region and the corresponding multiple first blocks. And the flash memory controller establishes or updates a valid page count table after the data is written to the plurality of first blocks; as well as The flash memory controller receives at least one deallocation command from the host device, and each deallocation command contains a logical address range to be deallocated; the flash memory controller updates the valid page count table according to the at least one deallocation command to generate an updated valid page count table. The flash memory controller determines, based on the updated valid page count table, whether the multiple valid page counts corresponding to all of the multiple first blocks of the first region are zero; and if the multiple valid page counts corresponding to all of the multiple first blocks of the first region are zero, the flash memory controller suggests that the host device send a reset command, and the reset command is used to reset the first region.

12. The storage device as claimed in claim 11, characterized in that, If the multiple valid page counts of all the multiple first blocks corresponding to the first region are zero, the flash memory controller sets a reset region recommendation attribute corresponding to the first region from a first logical value to a second logical value, wherein the reset region recommendation attribute with the first logical value is used to indicate that not all the data corresponding to the first region becomes invalid, the reset region recommendation attribute with the second logical value is used to indicate that all the data corresponding to the first region becomes invalid, and the reset region recommendation attribute is read by the host device to determine whether to send the reset command to the flash memory controller.

13. The storage device as claimed in claim 11, characterized in that, The valid page count table records each block and its corresponding valid page count.

14. The storage device as claimed in claim 11, characterized in that, The valid page count table is a region valid page count table. The region valid page count table records multiple bits for each region, and each bit corresponds to a logical address range, which corresponds to a physical page or a logical address unit.

15. The storage device as claimed in claim 14, characterized in that, For each bit in the valid page count table of the region, if the bit has a first logic value, it means that the data corresponding to the bit is valid; if the bit has a second logic value, it means that the data corresponding to the bit is invalid; and if all bits corresponding to the first region are zero, the flash memory controller determines that the multiple valid page counts of all the multiple first blocks corresponding to the first region are zero.

Images