Package structure for multi-chip modules

Abstract

The present disclosure provides a package structure for a multi-chip module, comprising: a plurality of chips and a plurality of pins, wherein the plurality of chips comprises a plurality of types of interfaces, and each of the plurality of chips comprises at least one type of interface, at least two of the plurality of chips have one or more same types of interfaces, wherein the plurality of types of interfaces comprises interfaces for testing and calibration. The plurality of pins is used to connect the plurality of types of interfaces of the plurality of chips to devices outside the package structure. Wherein a first pin of the plurality of pins corresponds to at least two of the plurality of chips, and is used to connect the same type of interfaces included by the at least two chips to devices outside the package structure.

Description

Technical Field

[0001] This disclosure relates to the field of chip packaging technology, and more specifically to a packaging structure for a multi-chip module. Background Technology

[0002] With the rapid development of chip technology, the requirements for chips are constantly increasing, especially the requirements for chip cost. As we all know, the cost of chips is largely limited by chip size, and chip design and packaging are important influencing factors for chip size.

[0003] In recent years, to improve overall chip yield and reduce costs, technologies have emerged that package multiple small-sized chips or dies together. Designing a large chip as multiple smaller chips offers advantages such as simplified design, reduced losses due to design or manufacturing errors in large chips, and improved yield. However, this inevitably increases the workload associated with inter-chip interconnection and testing. These interconnections and testing also increase the size required for chip packaging. Therefore, reducing the overall size in multi-chip scenarios is a pressing technical problem that needs to be solved. Summary of the Invention

[0004] To address the technical problem of increased overall chip size caused by multi-chip connections and testing in existing technologies, this disclosure provides a packaging structure for multi-chip modules that shares the same pin for the same type of interface in multiple chips, thereby reducing the number of pins required for chip packaging, and thus reducing the overall chip area and cost.

[0005] At least one embodiment of this disclosure provides a package structure for a multi-chip module, comprising: a plurality of chips, the plurality of chips including multiple types of interfaces, and each of the plurality of chips including at least one type of interface, at least two of the plurality of chips having one or more of the same type of interface, wherein the multiple types of interfaces include interfaces for testing and calibration; and a plurality of pins for connecting the multiple types of interfaces of the plurality of chips to a device outside the package structure, wherein a first pin of the plurality of pins corresponds to at least two of the plurality of chips and is used to connect the same type of interfaces included in the at least two chips to a device outside the package structure.

[0006] For example, in a packaging structure provided in one embodiment of this disclosure, at least two chips are connected to a device outside the packaging structure via a first pin in a time-sharing manner, and the device outside the packaging structure can be one or more devices.

[0007] For example, in a packaging structure provided in one embodiment of this disclosure, for each of at least a portion of the chips among a plurality of chips, the chip further includes a first circuit, the first circuit being used to perform a preset operation on the chip in conjunction with devices outside the packaging structure.

[0008] For example, in the packaging structure provided in one embodiment of this disclosure, the first circuit is a calibration circuit, and the device outside the packaging structure is a calibration resistor. The calibration circuit, in conjunction with the calibration resistor, performs a calibration operation on the chip to adjust the equivalent resistance value of the chip's interface.

[0009] For example, in the packaging structure provided in one embodiment of this disclosure, the first pin connects at least two chips to the same calibration resistor in a time-sharing manner; when the first interfaces of different chips among multiple chips have the same type, each of the multiple chips connects to different calibration resistors with the same value simultaneously through a first pin, or multiple chips connect to the same calibration resistor in a time-sharing manner through only one first pin.

[0010] For example, in the packaging structure provided in one embodiment of this disclosure, when multiple chips are connected to the same calibration resistor through only one first pin in a time-sharing manner, the multiple first circuits corresponding to the multiple chips are connected to the same calibration resistor in a preset order and perform calibration operations in a preset order.

[0011] For example, in a packaging structure provided in one embodiment of this disclosure, the calibration circuit includes: an adjustable resistor for adjusting the equivalent resistance value of the corresponding interface of the chip according to a control signal; a comparator connected to the adjustable resistor and the calibration resistor for comparing the voltage value between the equivalent resistance value and the calibration resistor with a reference voltage signal to obtain a comparison result; and a controller for obtaining the comparison result when receiving an indication signal to perform a calibration operation, and generating a control signal according to the comparison result.

[0012] For example, in the packaging structure provided in one embodiment of this disclosure, the first circuit is a test circuit. The test circuit, in conjunction with external devices of the packaging structure, performs test operations on the chip to detect chip malfunctions.

[0013] For example, in a packaging structure provided in one embodiment of this disclosure, the test circuit includes: a multiplexer connected to a first interface and connected to multiple channels within the chip, used to receive multiple test signals from multiple channels when receiving an indication signal for performing a test operation, and to sequentially output the multiple test signals to a first device; wherein, when at least one of the multiple test signals cannot be received by the first device, it is determined that a chip corresponding to the test circuit is in a fault state.

[0014] For example, in a packaging structure provided in one embodiment of this disclosure, the first pin is a packaging ball.

[0015] The present disclosure provides at least one embodiment of a packaging structure for a multi-chip module in which, for the same type of interface, such as a test or calibration interface, among multiple chips, each interface shares the same pin, and each pin corresponds to at least one chip, thereby reducing the number of pins required for chip packaging, and thus reducing the overall chip area and lowering costs. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the accompanying drawings of the embodiments will be briefly described below. Obviously, the drawings described below only relate to some embodiments of this disclosure, and are not intended to limit this disclosure.

[0017] Figure 1 This is a schematic diagram of a packaging structure for a multi-chip module provided according to at least one embodiment of the present disclosure;

[0018] Figure 2A A schematic diagram of a first circuit is shown when the first circuit provided according to at least one embodiment of the present disclosure is a calibration circuit;

[0019] Figure 2B A schematic diagram shows calibration circuits in multiple chips connected to an external device via the same pin;

[0020] Figure 3A A schematic diagram of a first circuit is shown when the first circuit provided according to at least one embodiment of the present disclosure is a test circuit;

[0021] Figure 3B A schematic diagram is shown showing test circuits in a plurality of chips provided according to at least one embodiment of the present disclosure connected to a first device via the same pin. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this disclosure clearer, the technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this disclosure. All other embodiments obtained by those skilled in the art based on the described embodiments of this disclosure without creative effort are within the scope of protection of this disclosure.

[0023] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0024] At least one embodiment of this disclosure provides a package structure for a multi-chip module, comprising: a plurality of chips, the plurality of chips including multiple types of interfaces, and each of the plurality of chips including at least one type of interface, at least two of the plurality of chips having one or more of the same type of interface, wherein the multiple types of interfaces include interfaces for testing and calibration; and a plurality of pins for connecting the multiple types of interfaces of the plurality of chips to a device outside the package structure, wherein a first pin of the plurality of pins corresponds to at least two of the plurality of chips and is used to connect the same type of interfaces included in the at least two chips to a device outside the package structure.

[0025] The packaging structure for multi-chip modules disclosed herein allows for the sharing of a common pin for the same type of interface, such as a test or calibration interface, among multiple chips, with each pin corresponding to at least one chip. This reduces the number of pins required for chip packaging, thereby reducing the overall chip area and lowering costs.

[0026] At least one embodiment of this disclosure provides a package structure for a multi-chip module, comprising: a plurality of chips and a plurality of pins, wherein the plurality of chips include multiple types of interfaces, and each of the plurality of chips includes at least one type of interface, at least two of the plurality of chips have one or more of the same type of interface, wherein the multiple types of interfaces include interfaces for testing and calibration. The plurality of pins are used to connect the multiple types of interfaces of the plurality of chips to a device outside the package structure. A first pin of the plurality of pins corresponds to at least two of the plurality of chips and is used to connect the same type of interfaces included in the at least two chips to a device outside the package structure.

[0027] Figure 1A schematic diagram of a packaging structure for a multi-chip module provided according to an embodiment of the present disclosure is shown.

[0028] like Figure 1 As shown, the package structure 100 includes multiple chips 110 and multiple pins 120. The multiple chips include chips 111, 112, 113, and 114. The multiple pins include pins 121 and 122. Each of the multiple chips 110 includes a test interface and a calibration interface, wherein chip 111 has a test interface 131 and a calibration interface 141, chip 112 has a test interface 132 and a calibration interface 142, chip 113 has a test interface 133 and a calibration interface 143, and chip 114 has a test interface 134 and a calibration interface 144. The multiple test interfaces 131-134 are connected to pin 121, and the multiple calibration interfaces 141-144 are connected to pin 122. Pins 121 and 122 are both first pins among the multiple pins 120, and pins 121 and 122 are used to connect the multiple test interfaces 131-134 and the multiple calibration interfaces 141-144 to devices outside the package structure 100, respectively. Understandably, pins 121 and 122 can be considered as the “interface” between the package structure 100 and external devices.

[0029] Understandably, Figure 1 The diagram shows multiple chips 110, including four chips 111-114. The multiple chips 110 may also include more than four chips or fewer than four chips, such as two, three, five, or more. Correspondingly, the number of pins in the multiple pins 120 is related to the type of interface of the multiple chips 110; for example, the number of pins in the multiple pins 120 is equal to the number of interface types of the multiple chips 110. It is also understood that, although... Figure 1 Each chip 111-114 shown has a test interface and a calibration interface. In actual applications, chips may not necessarily have all types of interfaces. Interfaces of the same type can be connected to the same pin, or a separate interface can be set for each chip for all interface types.

[0030] Compared to existing technologies where each chip has one interface connected to one pin, such as Figure 1 The package structure 100 shown only requires one pin to be connected to for the same type of interface. Compared to four test interfaces or four calibration interfaces, which require four pins to be connected, the four test interfaces or four calibration interfaces in the package only require one pin to be connected, thus effectively reducing the number of pins by 75%.

[0031] Optionally, in the embodiments of this application, the first pin is a packaged ball. For example, pins 121 and 122 are both packaged balls.

[0032] Alternatively, depending on the packaging technology, the first pin can also be a metal strip, etc. For example, when using packaging technologies such as fan-out, 2D, 2.5D, and embedded multi-chip interconnect bridge, the first pin is a package ball, such as a BGA ball.

[0033] Optionally, at least two of the multiple chips are time-division connected to a device outside the package structure via a first pin, and the device outside the package structure can be one or more devices.

[0034] For example, chips 111 and 112 are connected to pin 121 via test interface 131 and test interface 132 respectively, thus enabling time-sharing connection to external test devices. Similarly, chips 111 and 112 are connected to pin 122 via calibration interface 141 and calibration interface 142 respectively, thus enabling time-sharing connection to external calibration resistors.

[0035] Optionally, for each of at least a portion of the chips, the chip further includes a first circuit for performing a preset operation on the chip in conjunction with devices outside the package structure.

[0036] For example, the first circuit is related to the type of interface. For instance, if chip 111 has a test interface 131 and a calibration interface 141, then the first circuit inside chip 111 includes both a test circuit and a calibration circuit. If chip 114 only has a test interface 134 and no calibration interface, then the first circuit inside chip 114 is a test circuit. Accordingly, different preset operations are performed on the chip depending on the type of the first circuit. For example, if the first circuit is a test circuit, then a test operation is performed on the chip; if the first circuit is a calibration circuit, then a calibration operation is required. When the first circuit includes both a test circuit and a calibration circuit, then both test and calibration operations are required on the chip.

[0037] The following descriptions address scenarios where the first circuit is a calibration circuit and a test circuit, respectively.

[0038] Figure 2A A schematic diagram of a first circuit is shown when the first circuit provided according to an embodiment of the present disclosure is a calibration circuit.

[0039] Figure 2A The calibration circuit 200 is located inside the chip, for example... Figure 1 The chips 111-114 shown can all include a calibration circuit 200. Figure 2A Taking the calibration circuit 200 as an example, which is set in the chip 112, the calibration circuit 200 is connected to pin 122 through the calibration interface 142 of the chip 112, and pin 122 is connected to the calibration resistor 260.

[0040] The calibration circuit 200 includes a comparator 210, an adjustable resistor 220, a protector 230, an optional Zener diode 240, and an optional controller 250.

[0041] Comparator 210, connected to adjustable resistor 220 and calibration resistor 260, is used to compare the voltage value between the equivalent resistance value and the calibration resistor with a reference voltage signal. One input of comparator 210 receives the reference voltage signal Vef, the other input is connected to protector 230, and the output of comparator 210 is connected to controller 250.

[0042] After the protector 230 is connected to the adjustable resistor 220, it is connected to the calibration interface 142 through the Zener diode 250.

[0043] The Zener diode 240 includes two diodes 241 and 242 connected in series. The anode of diode 241 is grounded, and the cathode of diode 241 is connected to the anode of diode 242. The cathode of diode 242 is connected to a positive DC voltage. Optionally, the calibration resistor 260 has a resistance of 50 ohms, 100 ohms, etc., and its resistance can be adjusted according to actual needs, such as 75 ohms, 150 ohms, etc.

[0044] The controller 250 is used to acquire a comparison result when it receives an indication signal for calibration, and to generate a control signal based on the comparison result. The indication signal may be issued by the processor of the chip 112. For example, when the controller 250 receives the indication signal from the processor, it sends a control signal to the adjustable resistor 220 based on the comparison result output by the comparator 210 to adjust the resistance value of the adjustable resistor 220.

[0045] In this embodiment, the calibration circuit 200, in conjunction with the calibration resistor 260, performs a calibration operation on the chip 112 to adjust the equivalent resistance value of the interface 142 of the chip 112. The controller 250 receives the comparison result from the comparator 210, which is a high level and a low level or the corresponding "1" and "0". When the output result is high, the resistance value of the adjustable resistor 220 is increased; when the comparison result is low, the resistance value of the adjustable resistor 220 is decreased. The controller 250 stops adjusting the resistance value of the variable circuit 220 when the comparison result received by the controller 250 continuously changes between high and low levels.

[0046] Figure 2B A schematic diagram shows the calibration circuitry in multiple chips connected to an external device via the same pin.

[0047] Figure 2B As shown in Figure 1 Chips 112 and 113 shown are connected via pin 122 to, for example Figure 2AThe calibration resistor 260 is shown. Chip 112 includes calibration circuit 200, and chip 113 includes calibration circuit 200'. Calibration circuit 200' may be the same as or different from calibration circuit 200.

[0048] Optionally, the first pin can connect at least two chips to the same calibration resistor in a time-sharing manner. When different chips among multiple chips have the same type of first interface, the multiple chips can be connected to the same calibration resistor in a time-sharing manner through only one first pin.

[0049] For example, pin 122 connects chips 112 and 113 to calibration resistor 260. Chips 112 and 113 are connected to pin 122 via calibration interfaces 142 and 143, respectively. Chips 112 and 113 are connected to calibration resistor 260 at different times. For example, chips 112 and 113 are connected to calibration resistor 260 in a preset order, or chip 112 notifies chip 113 whether calibration resistor 260 is available, or chip 112 is responsible for scheduling its own and chip 113's use of calibration resistor 260. Understandably, although... Figure 2B The example only shows two chips connected to the same calibration resistor, but more chips can also be connected to the same calibration resistor, and their time-sharing operation is similar to that in this embodiment.

[0050] Optionally, when multiple chips are connected to the same calibration resistor via a single first pin in a time-sharing manner, the multiple first circuits corresponding to the multiple chips are sequentially connected to the same calibration resistor according to a preset order and perform calibration operations in the preset order. For example, if chip 113 is connected before chip 112, the calibration circuit in chip 113 first completes the calibration operation of chip 113 in conjunction with calibration resistor 260. After the calibration operation of chip 113 is completed, the calibration circuit in chip 112 completes the calibration operation of chip 112 in conjunction with calibration resistor 260.

[0051] Alternatively, the same type of interface in multiple chips can be connected to different calibration resistors through different first pins. For example, chips 111 and 112 require a 50-ohm calibration resistor, while chips 113 and 114 require a 75-ohm calibration resistor. Chips 111 and 112 can be time-division multiplexed to connect to the same 50-ohm calibration resistor using the same pin, and chips 113 and 114 can be time-division multiplexed to connect to the same 75-ohm calibration resistor using the same pin. Thus, chips 111 or 112 and chips 113 or 114 can be simultaneously connected to their corresponding calibration resistors through different pins, allowing chips 111 and 114 to perform calibration operations simultaneously. This method can improve calibration efficiency when a large number of chips need to be calibrated.

[0052] Figure 3A A schematic diagram of a first circuit is shown when the first circuit provided according to an embodiment of the present disclosure is a test circuit.

[0053] exist Figure 3A In the test circuit 300, there are multiplexers 310 and optional Zener diodes 320.

[0054] Multiplexer 310 is connected to first interface 30 and multiple channels within the chip. Multiplexer 310 receives multiple test signals from multiple channels upon receiving an indication signal for a test operation, and sequentially outputs these test signals to first device 330. First device 330 is an external device within the package structure. If at least one test signal cannot be received by first device 330, it is determined that a chip corresponding to test circuit 300 is in a fault state.

[0055] Multiplexer 310 is optionally connected to first pin 31 via Zener diode 320, and first pin 31 is connected to first device 330. In this embodiment, first device 330 can be any test device that can confirm whether a test signal has been received, and is not limited here.

[0056] Taking the example of test circuit 300 being installed in chip 114, test circuit 300 can perform test operations on chip 114 in conjunction with the first device 330, thereby detecting faults in chip 114. It should be noted that... Figure 1 Each of the multiple chips 110 shown requires testing to determine if it is faulty; therefore, a test circuit must be included in each chip. This testing is typically used to check the internal signal paths of the chip for proper functioning and the chip's external connections for correctness.

[0057] For example, multiplexer 310 is connected to 8 channels, each of which can transmit signals / data bidirectionally, meaning each channel can input and output signals / data. During each test, the test signals of all 8 channels need to be tested sequentially, for example, a total of 8 status tests. If any test signal cannot be received by the first device 330, the chip currently being tested is determined to be in a faulty state.

[0058] Figure 3B A schematic diagram is shown showing test circuits in a plurality of chips provided according to embodiments of the present disclosure connected to a first device via the same pin.

[0059] Figure 3B by Figure 1Multiple chips 110 are used as an illustration. Chips 111-114 are connected to pin 121 via test interfaces 131-134, and then connected to the first device 330 via pin 121. Test circuits 350, 360, 370, and 380 in chips 111-114 can all be... Figure 3A The test circuit 300 shown in the figure can also be used, but other test circuits can also be used.

[0060] and Figure 2B Similar to the multiple calibration circuits in the circuit, test circuits 350, 360, 370, and 380 are connected to the first device 330 in a time-division manner, which is similar to the multiple calibration circuits. For example, test circuits 350-380 are connected to the first device 330 in a preset order and perform test operations sequentially. Or, chip 111 is responsible for the test operations of test circuits 350-380 in circuit chips 111-114.

[0061] Understandably, when at least one of the multiple chips includes multiple different types of first circuits, it is a combination of multiple first circuits. The relevant descriptions and references to the first circuits are descriptions of calibration circuits and test circuits, which will not be repeated here.

[0062] A unified address space can be used for all chips in the embodiments of this disclosure. This means that for each chip, the chip address is a part of the complete address space, so that the corresponding chip can be identified by decoding the address. The test and calibration operations described herein can be implemented using this unified address space. Optionally, a corresponding chip identifier can also be set for each chip, so that the chip performing the operation can be distinguished by the chip identifier.

[0063] According to embodiments of this disclosure, the processes described above can also be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program containing program code for performing the processes described above.

[0064] The method flowcharts and device block diagrams disclosed herein are merely illustrative examples and are not intended to require or imply that connections or arrangements must be made in the manner shown in the flowcharts and block diagrams. As those skilled in the art will recognize, these devices and equipment can be connected and arranged in any manner that achieves the desired purpose.

[0065] The scope of protection of this disclosure is not limited to the specific embodiments thereof, but should be determined by the scope of the claims. The accompanying drawings of the embodiments of this disclosure only relate to the structures involved in the embodiments; other structures can be referred to with common designs. Where there is no conflict, the embodiments of this disclosure and the features within them can be combined to obtain new embodiments.

Claims

1. A packaging structure for a multi-chip module, comprising: Multiple chips, the multiple chips including multiple types of interfaces, and each of the multiple chips including at least one type of interface, at least two of the multiple chips having one or more interfaces of the same type, wherein the multiple types of interfaces include interfaces for testing and calibration; and Multiple pins are provided for connecting the various types of interfaces of the multiple chips to a device outside the package structure, wherein a first pin of the multiple pins corresponds to at least two of the multiple chips and is used to connect the same type of interfaces included in the at least two chips to a device outside the package structure, wherein the multiple pins are package pins. In this configuration, at least two chips are connected in a time-division manner to devices outside the package structure via the first pin, and the devices outside the package structure can be one or more devices. Specifically, for each of at least a portion of the plurality of chips, the chip further includes a first circuit, which is used to perform a preset operation on the chip in conjunction with devices external to the package structure. When the first circuit is a calibration circuit, the device outside the package structure is a calibration resistor. The calibration circuit, in conjunction with the calibration resistor, performs a calibration operation on the chip to adjust the equivalent resistance value of the chip's interface. The first pin connects the at least two chips to the same calibration resistor in a time-sharing manner. When the first interfaces of different chips among the plurality of chips are of the same type, each of the plurality of chips is simultaneously connected to different calibration resistors with the same value through a first pin, or the plurality of chips are connected to the same calibration resistor through only one first pin in a time-sharing manner.

2. The packaging structure according to claim 1, wherein, When multiple chips are connected to the same calibration resistor via only one first pin in a time-sharing manner, the multiple first circuits corresponding to the multiple chips are connected to the same calibration resistor in a preset order and the calibration operation is performed in the preset order.

3. The packaging structure according to claim 1, wherein the calibration circuit comprises: An adjustable resistor is used to adjust the equivalent resistance value of the corresponding interface of the chip according to the control signal; A comparator, connected to the adjustable resistor and the calibration resistor, is used to compare the voltage value between the equivalent resistance value and the calibration resistor with a reference voltage signal to obtain a comparison result. and A controller is configured to acquire the comparison result upon receiving an indication signal for performing a calibration operation, and to generate the control signal based on the comparison result.

4. The packaging structure according to claim 1, wherein, When the first circuit is a test circuit, the test circuit, in conjunction with external devices of the package structure, performs test operations on the chip to detect any faults in the chip.

5. The packaging structure according to claim 4, wherein, The test circuit includes: A multiplexer, connected to a first interface and to multiple channels within the chip, is used to receive multiple test signals from the multiple channels when an instruction signal for performing a test operation is received, and to output the multiple test signals sequentially to the first device. If at least one of the multiple test signals cannot be received by the first device, it is determined that a chip corresponding to the test circuit is in a fault state.

6. The packaging structure according to claim 1, wherein, The first pin is a packaged ball.

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