Data transmission method and data processing circuit

Abstract

A data transmission method and a data processing circuit, the data processing circuit includes a memory to implement a buffer, and a control circuit to control the operation of the data processing circuit. When the data processing circuit receives input data, the data hot bits of the input data are used to address a plurality of data blocks, and after the data hot bits are parsed, the start address and data length of each data block are obtained and written into the buffer, thereby generating the effect of masking false data addresses. In addition, before writing the plurality of data blocks into the buffer, the data dependency between the data blocks can be confirmed by comparing the data hot bits of the data blocks.

Description

Technical Field

[0001] This disclosure proposes a data transmission technique, and in particular a data transmission method and related circuitry that reduces the data processing cycle by addressing effective data. Background Technology

[0002] In known data transmission techniques, the maximum input width limit of a circuit system's write buffer defines the boundary for data segmentation. One such maximum input width limit is the width of the transmission bus in the circuit system. For example, with a maximum input width of 64 bytes (128 bytes), the circuit system splits the data transmission process into two steps before reaching the maximum input width limit of the write buffer.

[0003] In known transmission methods, because the data transmission procedure must conform to the fixed access width of the slave device (the device receiving data), the circuit system must transmit data according to the fixed access width of the slave device. This means that data is written from the circuit system to the buffer and then to the slave device, transmitting a fixed amount of data. Therefore, due to the mechanism of the circuit system's write buffer, the system issues a chopping command during data transmission. The system can also generate dummy data when necessary, based on the actual data transmission situation, because the transmission process is limited by the fixed access width of the receiving slave device, to align with the maximum input width of the buffer and the fixed access width of the slave device.

[0004] Figure 1 This diagram illustrates an embodiment of creating dummy data in a known circuit system. Input data 100 is written to memory 10 in the circuit system, which acts as a buffer. The circuit system then transmits the data from the buffer to slave device 101. During data transmission, the data is limited by the boundaries defined by the maximum input width of the write buffer, the fixed access width of the slave device, and the width of the transmission bus. For example, the maximum input width of the write buffer could be 64 bytes, the fixed access width of the slave device could be 32 bytes, and the bus width could be 16 bytes.

[0005] During operation, the write buffer converts one push instruction into two pop instructions. The push instruction adds new data to the buffer, while the pop instruction retrieves data from the buffer. In this example, the memory addresses of slave device 101 are 0x40, 0x50, 0x60, and 0x70. During transmission, when pushing data to memory addresses 0x50 and 0x60, dummy data 103 is inserted into memory addresses 0x40 and 0x70 to align with the fixed access width of slave device 101. This dummy data is marked as "dum" in memory 10, allowing the push address to start from memory address 104 (0x40 in this example). In this example, after being input to memory 10 via bus 105, these four data entries will be retrieved from memory 10 using two pop instructions and then output, i.e., the data will be output to slave device 101.

[0006] When considering critical timing and hardware complexity, in known technologies, the data transmission process also needs to check the dependencies of data in the circuit system's buffer to ensure data correctness within the maximum input width limit of the buffer. A known method is to compare the address within the buffer with the input data based on the maximum input width of the buffer. A relevant schematic diagram can be found in the reference diagram. Figure 2 The diagram illustrates the process of checking data dependencies during data transmission.

[0007] For example, the data dependency check method is to check whether there is a data address that needs to be read before the data is written to the buffer by the instruction in the data processing circuit. If there is a data address that needs to be read in the data processing circuit, it means that the data at the corresponding data address in the buffer is old or incorrect, and it is necessary to wait for the data to be written to the buffer before reading the data in the buffer. Conversely, if the data processing circuit does not obtain the data address that needs to be read, it means that there is no dependency, and the data at the corresponding address can be read from the buffer.

[0008] according to Figure 2The diagram shows a buffer with a maximum input width of 64 bytes and a bus width of 16 bytes (in this example, the width is shown as 0x40 to 0x7f, and the data address range is 0x40 to 0x70). Therefore, when writing data, the input instruction must be divided into two or more write instructions. As shown in the diagram, the first instruction 201 writes a portion of the input data 121 to buffer addresses 0x50 and 0x60, followed by the second instruction 202, which writes the remaining portion of the input data 121 to address 0x70 in the buffer. In the circuit system, a data dependency check 203 is performed on the data under different instructions. If the data transmitted by different instructions is within the boundary of the data segmentation formed by the maximum input width of the buffer, a data dependency is confirmed; otherwise, if it exceeds this boundary, such as not being within buffer addresses 0x40 to 0x70, a data dependency is confirmed. During data buffering, data at buffer address 0x70 is temporarily stored only after the data at buffer address 0x50 has been output. However, when data dependencies are identified a large number of times, the inability of dependent data to operate simultaneously can have a significant impact on hardware performance.

[0009] In known technologies, data conflict checking in the write buffer is based on the boundary of the data segmentation formed by the maximum input width of the buffer. However, as the addresses of transmitted data become more concentrated and dense, the rate of data dependencies increases, further burdening hardware performance. Furthermore, since the size of the accessed data is fixed due to the slave device, when the data input to the buffer is not aligned to the fixed access width of the slave device, the buffer in the circuit system needs to generate spurious data. This mechanism also generates additional processing and degrades the efficiency of pushing data to the buffer.

[0010] In addition, known techniques only refer to data alignment to solve the problem of data conflict, but data with the same boundary does not necessarily indicate data dependency. Such judgment is not accurate enough, and checking data dependency will constantly confirm data boundaries, resulting in unnecessary procedures. Summary of the Invention

[0011] This disclosure proposes a data transmission method for use in a data processing circuit with a buffer. Specifically, hot-addressed data is used to separate the data into multiple data blocks due to the limitation of the maximum input width of the write buffer. Multiple write instructions are formed based on the multiple data blocks to write the input data to the data blocks separated from the buffer.

[0012] In the data transmission method, when receiving input data, multiple data blocks in the input data are addressed by data hot bits. Then, the data hot bits are parsed to obtain the start address and data length of each data block, and the data is written into the buffer accordingly.

[0013] Furthermore, before writing multiple data blocks into the buffer, the data dependencies between data blocks can be confirmed by comparing the data hot bits of each data block. If it is determined that there is no dependency between data blocks, they are directly written into the buffer; if it is determined that there is a dependency between data blocks, they need to wait to be written into the buffer before being read out.

[0014] Preferably, the input data is transmitted from the master device to the slave device through the data processing circuit. The slave device reads the input data from the buffer. The hot bit addressing mechanism used in the process is mainly based on the limitation of the data address in the data alignment buffer during the input data transmission process.

[0015] Thus, after the input data is written to the buffer, the slave device reads the data from the buffer based on the parsing information of the data hot bits, from which the start address of each data block is obtained, and then the data is obtained according to the data length, which produces the effect of masking the false data address.

[0016] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0017] Figure 1 A schematic diagram illustrating an example of creating fake data in a known circuit system;

[0018] Figure 2 The diagram illustrates the process of checking data dependencies during data transmission.

[0019] Figure 3 A schematic diagram illustrating an embodiment of a data processing circuit performing data transmission is shown;

[0020] Figure 4 This diagram illustrates the operation of the data hotspot in the data processing circuit.

[0021] Figure 5 Display a schematic diagram illustrating the operation of writing and reading data into the buffer; and

[0022] Figure 6 A flowchart illustrating an embodiment of the data transmission method is shown. Detailed Implementation

[0023] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions; this is stated beforehand. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention.

[0024] It should be understood that while terms such as "first," "second," and "third" may be used in this document to describe various components or signals, these components or signals should not be limited by these terms. These terms are primarily used to distinguish one component from another, or one signal from another. Furthermore, the term "or" as used herein should, as appropriate, include any combination of one or more of the associated listed items.

[0025] Unlike known technologies where various data verification procedures reduce the performance of data processing circuits and increase hardware burden during data access due to numerous limitations (such as data transmission being limited by the maximum input width of the write buffer defining the data segmentation boundary, the fixed access width of the slave device, and the width of the transmission bus), this disclosure presents a data transmission method and data processing circuit that can reduce the burden of data conflict handling. It proposes a data-hot-bit data conflict handling mechanism. Unlike known methods that require determining the start address and data length in memory (buffer) when storing data, the data-hot-bit method additionally records the address range of the data input to the data processing circuit in a different format in the buffer. It also updates the push instruction for accessing data in the buffer to a pop instruction, using the data-hot-bit to indicate a false data address, eliminating the need to actually generate false data to fit the smallest indivisible unit of received data in the receiving device (such as a slave device). This effectively reduces unnecessary data processing procedures and improves the performance of the data processing circuit.

[0026] The data transmission method disclosed in this disclosure proposes a low-cost, high-efficiency solution for handling data conflicts. The technical problem it addresses is that read and write instructions executed by the data processing circuit are frequently reprogrammed to achieve high efficiency. However, numerous read and write operations can cause data conflicts, necessitating additional data consistency handling to prevent them. The data transmission method proposed in this disclosure utilizes the aforementioned hot-bit mechanism to reduce the number of writes by addressing valid data and solves the problem of fixed access width alignment for specific types of objects (such as slave devices relative to the master device). Furthermore, the hot-bit technology also increases the write efficiency of the data processing circuit.

[0027] The width of the transmission bus can be defined as the total amount of data that can be transmitted per unit time (frequency x width, bytes / second). The data hot bits are several bits in the circuit implementing the data transmission method used to indicate each bus address, used to address the boundary between valid and false addresses in the bus (one data hot bit corresponds to the start address of a data block). For example, for data with a length of 3, the start address is 0x20 (the block data width is memory addresses 0x20 to 0x2f), the maximum input width of the buffer is 128 bytes, and the data width is 128 bits. Therefore, one bit of the data hot bit can indicate the valid data address 0x20 in the buffer of the data transmission procedure, another bit can indicate the valid data address 0x30, another bit can indicate the valid data address 0x40, and several bits can indicate invalid data addresses in this data transmission procedure, such as 0x70, 0x60, 0x50, 0x10, and 0x00.

[0028] Figure 3 The diagram illustrates an embodiment of the data transmission method proposed in this disclosure, showing a data processing circuit 33 for processing the data transmission procedure from the master device 31 to the slave device 32, including a procedure for checking for data conflicts, such as confirming the dependency between incoming and outgoing data. The data processing circuit 33 is controlled by a controller 331, which includes accessing and removing data written to a buffer 333 using push and pop instructions. The buffer 333 may be a buffer circuit implemented by a memory (such as SRAM) within the data processing circuit 33.

[0029] During data transmission, the master device 31 generates data, which is then transmitted to the data processing circuit 33 via the bus 34. In the data processing circuit 33, a write instruction is used to write the input data into the buffer 333. Then, the slave device 32 reads the data from the buffer 333 using a read instruction. During the reading process, the data processing circuit 33 verifies whether the data has been completely written to the specific address in the buffer 333, thus resolving data conflicts. If data dependencies are not checked, and the slave device 32 reads data from the buffer before it has been completely written, incorrect data may be read.

[0030] According to the above method, the controller 331 in the data processing circuit 33 will compare the data address in the buffer 333 to confirm the data dependency in the input data, determine whether there is a data conflict problem, and after confirming the dependency, the slave device 32 will read the data that has been checked from the buffer 333.

[0031] In the data transmission method, when input data is written to the buffer 333 of the data processing circuit 33, the controller 331 uses hot bits for addressing, that is, records the data address of the input data in a specific format, instead of determining whether to fill in dummy data based on information such as the start address and data length in the buffer 333 to align with the fixed access width of the receiving slave device 32. In one embodiment, addressing valid input data with hot bits can eliminate the problem of data conflicts. Then, a mask is used to block the data address that should have been written as dummy data, so that the data processing circuit 33 improves its operating efficiency by reducing the working cycle of writing dummy data.

[0032] According to an embodiment of the data transmission method using hot bits, Figure 4 This diagram illustrates how hot bits are used in data processing circuits to check for data conflicts.

[0033] The diagram illustrates a memory that implements a buffer in a data processing circuit. Within the buffer, write instructions may be divided into multiple parts due to the bus width. For example, the first instruction 401 in the diagram writes data at addresses 0x50 and 0x60 of input data 400 into the buffer, and the second instruction 402 writes input data 400 into buffer address 0x70. As an example, if the maximum input width of the buffer is 64 bytes and the bus width is 128 bits, four blocks need to be planned in the memory (such as SRAM in the data processing circuit). The first instruction 401 executes the first data transfer program, recording the address of the data transferred under the first instruction 401 in the first data hot bit (e.g., 4'b0110) 403. The second instruction 402 executes the second data transfer program, recording the address of the data transferred under the second instruction 402 in the second data hot bit (e.g., 4'b1000) 404.

[0034] Next, the data dependency checking circuit 405 in the data processing circuit checks the data dependency in the write buffer. For example, it compares the first hot data bit (e.g., 4'b0110) 403 with the second hot data bit (e.g., 4'b1000) 404 using an AND operation. By comparing the hot data bits, it confirms whether the address to be read (equivalent to the memory address in the slave device) already contains data. The comparison result will determine whether the transmitted data has no data dependency. For example, if the address to be read is 0x50, if there is data at the corresponding address in the buffer, the data is read; if there is no data at the corresponding address in the buffer, the data will only be read when there is data at that address.

[0035] If there is no data dependency, it means that the data are unrelated to each other. The data at the data address recorded in the second data hot bit 404 can be directly pushed to the buffer without needing to fill in any false data. This can reduce the number of data dependency judgments and improve the performance of the data processing circuit.

[0036] according to Figure 5 This diagram illustrates the operation of writing data to the buffer. When device 500 reads data from the buffer (data addresses 0x50 and 0x60 in this example), it masks the data addresses of the dummy data to be written (data addresses 0x40 and 0x70 in this example) using a hot bit method. This allows the data processing circuit to effectively reduce the number of processing steps when writing data to the slave device. For example, in the program that pushes input data 503 (data addresses 0x50 and 0x60) to the buffer (implemented by memory 50 in the diagram) via bus 507, because there is no need to write dummy data 501 (original data addresses 0x40 and 0x70), the push program, which originally required 4 write cycles, can be reduced to 2 working cycles.

[0037] In this example, the buffer addresses 0x40 to 0x70 represent the maximum input width of the buffer. During the data transmission process, when input data 503 is written into the buffer via bus 507, in addition to the transmission width of bus 507, the valid data is mainly determined by the fixed access width of the receiving slave device 500. The pop-up instruction reads data from the buffer (memory 50) based on the addressing information of the data hot bit 505. The relevant data processing circuit will distinguish the data address of the dummy data 501 that was originally to be filled in the buffer based on the addressing information of the valid data (valid address, such as 0x50 and 0x60 in this example) of the data hot bit 505. When writing to the slave device 500, the dummy data address (such as 0x40 and 0x70 in this example) is masked, so that the input data 503 can be successfully written into the memory of the slave device 500.

[0038] The data transmission procedure described above utilizes the mechanism of the data hot bit 505 to omit the writing cycle of generating and transmitting false data, thereby reducing the number of times data dependency checks are performed and increasing the efficiency of the data processing circuit.

[0039] Based on the above embodiments, the data transmission process can be summarized as follows: Figure 6 The flowchart shown is an example of a data transmission method.

[0040] The process begins with the master device generating data, which is then received by the data processing circuit (step S601). Following this, the data processing circuit checks the data dependencies between preceding and following data (step S603). In this step, a data hot bit is set, used to address the start address of each data block in the input data, which also includes the data length under the transmission format. The data processing circuit separates the data into multiple data blocks based on the maximum input width of the write buffer and generates multiple write instructions based on these blocks. For example, in step S605, the data processing circuit uses a push instruction to write each data block according to the maximum input width of the buffer. It is worth noting that the input data is transmitted from the master device to the slave device via the data processing circuit, and the data hot bit addressing mechanism is based on the limitation of data addresses in the data alignment buffer during input data transmission.

[0041] Subsequently, the slave device prepares to read data from the buffer by popping the command. The start address and length of each data (each data block) can be obtained by parsing the data hot bits. The data dependency is checked by comparing the data hot bits with the check circuit in the data processing circuit, thereby confirming the data dependency in the buffer (step S607).

[0042] Specifically, the data processing circuit checks whether there is a data address that needs to be read before writing data to the buffer. If there is a data address that needs to be read, it means that the data at the corresponding data address in the buffer is old, and it is necessary to wait for data to be written to the buffer before reading the data in the buffer. Conversely, if the data processing circuit has not obtained the data address that needs to be read, the data at the corresponding address can be read from the buffer.

[0043] In this way, the data processing circuit uses hot-addressed data to effectively address the input data, which can eliminate the problem of data conflict. Then, it uses a mask to block the data address that should have been written with false data, so that the data processing circuit improves its operating efficiency by reducing the working cycle of writing false data.

[0044] Afterwards, the slave device decodes the data to obtain the addressing information of the data hot bits (start address, data length). Data can then be read from the buffer based on the data hot bits. The start address of each data block in each data item can be obtained from the data hot bits. The data is then obtained based on the data length. The data hot bits create the effect of masking the false data address when writing to the slave device (step S609). If necessary, the data that has not been read needs to be filled in in order to align with the fixed access width in the slave device. For example, false data can be used to fill in the data blocks that need to be filled.

[0045] Thus, in addition to effectively improving system performance by reducing the processing of false data, the data transmission method also ensures that the data transmission process is not affected by data conflicts through data hot bits.

[0046] In summary, based on the data transmission method and data processing circuit described in the above embodiments, the method can be applied to a master-slave device architecture. The data processing circuit handles the data transmission and format conversion between the master and slave devices, such as in a computer system between all circuit elements that need to access memory data.

[0047] The data transmission method mainly adopts a hot-bit data processing mechanism. The data processing circuit uses the data transmission method to address valid data, replacing the traditional method that requires setting the start address and data length. This can effectively eliminate the problem of data conflict and also eliminate the need for the processing program that needs to fill in false data when the data is not aligned with the maximum input width of the buffer. This method still checks for data conflict in the circuit, which can improve its accuracy to the bus level. It can effectively reduce the number of data dependency processing steps and increase the efficiency of the data processing circuit in processing data.

[0048] The content disclosed above is only a preferred and feasible embodiment of the present invention, and is not intended to limit the scope of the patent application of the present invention. Therefore, all equivalent technical changes made using the contents of the present invention specification and drawings are included in the scope of the patent application of the present invention.

[0049] Explanation of reference numerals in the attached figures

[0050] 100: Input data

[0051] 10: Memory

[0052] 101: From the device

[0053] 103: Fake Data

[0054] 104: Starting Address

[0055] 105: Bus

[0056] 201: First Instruction

[0057] 202: Second Instruction

[0058] 121: Input Data

[0059] 203: Data Dependency Check

[0060] 31: Main unit

[0061] 32: From the device

[0062] 33: Data processing circuit

[0063] 331: Controller

[0064] 333: Buffer

[0065] 34: Bus

[0066] 401: First Instruction

[0067] 402: Second Instruction

[0068] 400: Input data

[0069] 403: First data hotspot

[0070] 404: Second data hotspot

[0071] 405: Data Dependency Check Circuit

[0072] 501: Fake Data

[0073] 503: Input data

[0074] 505: Data Hotspot

[0075] 50: Memory

[0076] 500: From the device

[0077] 507: Bus

[0078] Data transmission process in steps S601 to S609

Claims

1. A data transmission method, applied in a data processing circuit with a buffer, comprising: Receive input data; The input data is addressed using hot bits to specify the start address of multiple data blocks, with each hot bit corresponding to the start address of one data block; and Parse the hot bits of the data to obtain the start address and data length of each data block, and The data dependencies between data blocks are confirmed by comparing the hot bits of each data block, and multiple data blocks are written into the buffer accordingly.

2. The data transmission method as described in claim 1, wherein, If it is determined that there is no dependency between data blocks, they are written directly to the buffer; if it is determined that there is a dependency between data blocks, they must wait to be written to the buffer before being read out.

3. The data transmission method as described in claim 1, wherein the input data is separated into multiple data blocks according to the maximum input width limit of the write buffer, and multiple write instructions are formed according to the multiple data blocks for writing the input data to the buffer.

4. The data transmission method according to any one of claims 1 to 3, wherein the input data is transmitted from the master device to the slave device through the data processing circuit, and the slave device reads the input data from the buffer, and the hot bit addressing mechanism is based on the limitation of the data address in the data alignment buffer during the input data transmission process.

5. The data transmission method of claim 4, wherein the transmission of input data is limited by the boundary of the data segmentation defined by the maximum input width of the write buffer, the fixed access width of the slave device, and the width of the transmission bus.

6. The data transmission method as described in claim 5, wherein, After the input data is written to the buffer, the slave device reads the data from the buffer based on the parsing information of the data hot bits, from which the start address of each data block is obtained, and then the data is obtained according to the data length, which produces the effect of masking the false data address.

7. A data processing circuit, comprising: The memory serves as a buffer. as well as A controller is used to control the operation of data processing circuits. When the data processing circuit receives input data, it uses hot bits to address the start addresses of multiple data blocks in the input data. Each hot bit corresponds to the start address of a data block. After parsing the hot bits, it obtains the start address and data length of each data block. By comparing the hot bits of each data block, it confirms the data dependency between data blocks and writes multiple data blocks into the buffer accordingly.

8. The data processing circuit as described in claim 7, wherein, If it is determined that there is no dependency between data blocks, they are written directly to the buffer; if it is determined that there is a dependency between data blocks, they must wait to be written to the buffer before being read out.

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