Interface device and its damage detection method, display panel

Abstract

This application provides an interface device and a method for detecting its damage status, as well as a display panel. The interface device includes at least one differential port, at least one electrostatic discharge (ESD) protection module, and at least one port damage detection module. Each ESD protection module is connected to a corresponding differential port to provide ESD protection for the differential port. Each port damage detection module is connected to a corresponding differential port to detect and determine the damage status of the corresponding differential port. This interface device has good reliability and effectively reduces the risk of potential interface device failure.

Description

Technical Field

[0001] This invention relates to the field of electronic equipment technology, and in particular to an interface device and a method for detecting its damaged state, as well as a display panel. Background Technology

[0002] With the continuous improvement of display resolution, the amount of data transmitted has increased significantly. Traditional interfaces such as 8086, 8088, and TTL are no longer sufficient to meet the needs of high-speed and large-volume data transmission. Therefore, various industry brands have developed the Mobile Industry Processor Interface (MIPI) to meet the needs of high-speed data transmission in the mobile phone market.

[0003] Because high-speed transmission interfaces require faster switching response times for interface devices, such as the logic MOSFETs inside an Integrated Circuit Chip (IC), the nanometer manufacturing process for ICs must reduce parasitic resistance and capacitance to meet the high-speed switching response requirements of the logic MOSFETs. Therefore, high-speed MIPI interfaces are relatively less resistant to electrostatic discharge (ESD) compared to traditional interfaces. To prevent damage to the MIPI interface, IC manufacturers design ESD protection circuitry at the MIPI interface to protect the MIPI interface circuitry.

[0004] However, the ESD protection circuit within the MIPI interface is inevitably subject to micro-short circuit damage to the circuitry or pins due to excessive ESD energy or too many electrostatic discharges during the product manufacturing process. These micro-short circuit damages do not affect the normal operation of the chip, but the chip has lower reliability and potential failure risk during subsequent use. Summary of the Invention

[0005] This application provides an interface device and a method for detecting its damaged state, as well as a display panel, which aims to address the problem that existing chips have low reliability and potential failure risks during subsequent use.

[0006] To address the aforementioned technical problems, this application provides a technical solution: an interface device based on a mobile industry processor interface protocol. This interface device includes: at least one differential port, at least one electrostatic discharge (ESD) protection module, and at least one port damage detection module; wherein each ESD protection module is connected to a corresponding differential port to provide ESD protection for the differential port; and each port damage detection module is connected to a corresponding differential port to detect and determine the damage status of the corresponding differential port.

[0007] Each of the electrostatic discharge (ESD) protection modules includes: a negative polarity ESD protection unit, connected to the negative polarity voltage pin of the corresponding differential port, to provide ESD protection for the negative polarity voltage pin; each of the port damage detection modules includes: a negative polarity voltage pin damage detection unit, connected to the negative polarity voltage pin of the corresponding differential port, to detect and determine the damage status of the negative polarity voltage pin.

[0008] Each of the electrostatic discharge (ESD) protection modules includes: a positive polarity ESD protection unit, connected to the positive polarity voltage pin of the corresponding differential port, to provide ESD protection for the positive polarity voltage pin; each of the port damage detection modules includes: a positive polarity voltage pin damage detection unit, connected to the positive polarity voltage pin of the corresponding differential port, to detect and determine the damage status of the positive polarity voltage pin.

[0009] The negative polarity voltage pin damage detection unit or the positive polarity voltage pin damage detection unit includes:

[0010] Reference voltage generation circuit, used to output reference voltage;

[0011] A comparison circuit is connected to the reference voltage generation circuit and the negative or positive voltage pin of the differential port, respectively. When the interface device is powered on and in the port damage detection stage, the power consumption voltage on the negative or positive voltage pin is compared with the reference voltage, and the comparison result is output to determine the damage state of the differential port based on the comparison result.

[0012] The reference voltage generation circuit includes:

[0013] Multiple reference voltage generation units, wherein each reference voltage generation unit is used to generate a different reference voltage, and the comparison circuit is switchably connected to any of the reference voltage generation units to receive different reference voltages, so as to compare the power dissipation voltage on the negative voltage pin or the positive voltage pin with the different reference voltages to determine the damage level of the differential port.

[0014] Each of the reference voltage generating units includes: a plurality of resistors connected in series between the operating voltage and the ground voltage, wherein the connection node between any two adjacent resistors can be selected as the output node of the reference voltage generating unit to generate and output the corresponding reference voltage; and a first control switch connected between the output node of the reference voltage generating unit and the comparison circuit to switchably output the reference voltage generated by the reference voltage generating unit to the comparison circuit.

[0015] The negative voltage pin damage detection unit or the positive voltage pin damage detection unit further includes: a second control switch connected between the negative voltage pin or the positive voltage pin and the comparison circuit. When the interface device performs a port damage detection operation, the second control switch is turned on so that the comparison circuit compares the power consumption voltage on the negative voltage pin or the positive voltage pin with the reference voltage.

[0016] The interface further includes: a logic circuit connected to each of the port damage detection modules to summarize the comparison results of each of the port damage detection modules and determine whether the interface device meets the requirements.

[0017] Preferably, the logic circuit includes multiple logic gates to summarize the comparison results of each of the port damage detection modules;

[0018] Preferably, the plurality of logic gates includes an AND gate; or, the plurality of logic gates includes an AND gate and an OR gate; or, the plurality of logic gates includes an AND gate and a NOT gate; or, the plurality of logic gates includes an AND gate, a NOT gate, and an OR gate.

[0019] To address the aforementioned technical problems, another technical solution adopted in this application is: providing a method for detecting the damage status of an interface device, used for detecting the damage status of an interface device based on a mobile industry processor interface protocol, wherein the interface device includes a differential port; the differential port includes a negative voltage pin and a positive voltage pin; the detection method includes: outputting a reference voltage; when the interface device is powered on and in the port damage detection stage, comparing the power consumption voltage on the negative voltage pin or the positive voltage pin with the reference voltage, outputting a comparison result, and determining the damage status of the differential port based on the comparison result.

[0020] To address the aforementioned technical problems, another technical solution adopted in this application is to provide a display panel. This display panel includes the interface device based on the mobile industry processor interface protocol mentioned above.

[0021] The beneficial effects of the embodiments of this application, which differ from the prior art, are as follows: The interface device and its damage detection method and display panel provided in this application. This interface device based on the mobile industry processor interface protocol includes at least one differential port and at least one electrostatic discharge (ESD) protection module, with each ESD protection module connected to a corresponding differential port to provide ESD protection for the differential port and prevent ESD damage. Simultaneously, this interface device based on the mobile industry processor interface protocol further includes at least one port damage detection module, with each port damage detection module connected to a corresponding differential port. This allows the port damage detection module to detect and determine the damage state of the corresponding differential port, thereby assessing the micro-damage state caused by excessive ESD energy or excessive ESD discharge in the interface device. This enables the interception of interface devices with micro-damage states, effectively improving the reliability of the interface device and reducing the potential failure risk. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 A schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol provided in an embodiment of this application;

[0024] Figure 2 A schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol provided in the first specific embodiment of this application;

[0025] Figure 3 A schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol provided in the second specific embodiment of this application;

[0026] Figure 4 A schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol provided in the third specific embodiment of this application;

[0027] Figure 5 This is a schematic diagram of the structure of a reference voltage generation circuit provided in an embodiment of this application;

[0028] Figure 6 A schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol provided in the fourth specific embodiment of this application;

[0029] Figure 7A schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol provided in the fifth specific embodiment of this application;

[0030] Figure 8 A schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol provided in the sixth specific embodiment of this application;

[0031] Figure 9 A schematic diagram of the architecture of a logic circuit provided in an embodiment of this application;

[0032] Figure 10 A flowchart illustrating a method for detecting the damage status of an interface device based on a mobile industry processor interface protocol, provided in an embodiment of this application;

[0033] Figure 11 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application.

[0034] Explanation of reference numerals in the attached figures

[0035] Interface device 10; Differential port 1; Negative voltage pin DP; Positive voltage pin DN; Electrostatic discharge protection module 2; Negative electrostatic discharge protection unit 2a; Positive electrostatic discharge protection unit 2b; Damage detection module 3; Negative voltage pin damage detection unit 3a; Positive voltage pin damage detection unit 3b; Reference voltage generation circuit 31; Reference voltage generation unit 311; First resistor R1; Second resistor R2; First control switch 3111; Comparison circuit 32; Second control switch 33; Logic circuit 4; Logic gate 41. Detailed Implementation

[0036] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0037] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0038] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0039] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0040] Please see Figure 1 , Figure 1 This is a schematic diagram of the structure of an interface device based on a mobile industry processor interface protocol according to an embodiment of this application. In this embodiment, an interface device 10 based on a mobile industry processor interface protocol is provided. The interface device 10 may be a D-PHY interface device. The interface device 10 includes at least one differential port 1, at least one electrostatic discharge protection module 2, and at least one port damage detection module 3.

[0041] Among them, see Figure 2 , Figure 2 This is a schematic diagram of the interface device based on the mobile industry processor interface protocol provided in the first specific embodiment of this application; differential port 1 may be clock differential port 11 and / or data differential port 12 (see below). Figure 8 The number of clock differential ports 11 is one; the number of data differential ports 12 can be one, two, three, or four. In a specific embodiment, each differential port 1 includes a negative voltage pin DP and a positive voltage pin DN.

[0042] Please continue reading. Figure 1 Each electrostatic discharge (ESD) protection module 2 is connected to a corresponding differential port 1 to provide ESD protection for the differential port 1 and prevent it from being damaged by ESD. Furthermore, each differential port 1 is also connected to a corresponding port damage detection module 3 to detect and determine the damage state of the corresponding differential port 1. This allows for the assessment of the micro-damage state caused by excessive ESD energy or excessive ESD discharge in the interface device 10, enabling the interception of interface devices 10 that have caused micro-damage. This effectively improves the reliability of the interface device 10 and reduces the potential failure risk of the interface device 10.

[0043] In one specific embodiment, such as Figure 2 As shown, each electrostatic discharge (ESD) protection module 2 includes a negative polarity ESD protection unit 2a, which is connected to the negative polarity voltage pin DP of the corresponding differential port 1 to provide ESD protection for the negative polarity voltage pin DP and prevent ESD damage to the negative polarity voltage pin DP. In this specific embodiment, each port damage detection module 3 includes a negative polarity voltage pin damage detection unit 3a, which is connected to the negative polarity voltage pin DP of the corresponding differential port 1. The damage state of the negative polarity voltage pin DP is detected and determined by the negative polarity voltage pin damage detection unit 3a, thereby assessing the micro-damage state of the negative polarity voltage pin DP of the interface device 10 under conditions such as excessive ESD energy or excessive ESD discharge, effectively improving the reliability of the interface device 10 and reducing the potential failure risk of the interface device 10.

[0044] In the second specific embodiment, see Figure 3 , Figure 3 This is a schematic diagram of the interface device based on the mobile industry processor interface protocol provided in the second specific embodiment of this application. Each electrostatic discharge (ESD) protection module 2 further includes a positive polarity ESD protection unit 2b, which is connected to the positive polarity voltage pin DN of the corresponding differential port 1 to provide ESD protection for the positive polarity voltage pin DN and prevent ESD damage to the positive polarity voltage pin DN. In this specific embodiment, each port damage detection module 3 further includes a positive polarity voltage pin damage detection unit 3b, which is connected to the positive polarity voltage pin DN of the corresponding differential port 1 to detect and determine the damage state of the positive polarity voltage pin DN. This allows for the assessment of the micro-damage state of the positive polarity voltage pin DN of the interface device 10 under conditions such as excessive ESD energy or excessive ESD release, further improving the reliability of the interface device 10 and reducing the potential failure risk of the interface device 10.

[0045] See Figure 4 , Figure 4 This is a schematic diagram of the interface device based on the mobile industry processor interface protocol provided in the third specific embodiment of this application. The negative polarity voltage pin damage detection unit 3a (or positive polarity voltage pin damage detection unit 3b) includes a reference voltage generation circuit 31 and a comparison circuit 32.

[0046] The reference voltage generation circuit 31 is used to output a reference voltage. The comparison circuit 32 is connected to the reference voltage generation circuit 31 and the negative voltage pin DP (or positive voltage pin DN) of the differential port 1, respectively. When the interface device 10 is powered on and in the port damage detection stage, it compares the power consumption voltage on the negative voltage pin DP (or positive voltage pin DN) with the reference voltage, thereby outputting the comparison result.

[0047] In a specific embodiment, such as Figure 4 As shown, the comparison circuit 32 includes a comparator. The first input terminal of the comparator is connected to the reference voltage generation circuit 31, and the second input terminal of the comparator is connected to the negative voltage pin DP (or positive voltage pin DN) of the differential port 1. When the interface device 10 is powered on and in the port damage detection phase, the comparator compares the power consumption voltage on the negative voltage pin DP (or positive voltage pin DN) with the reference voltage and outputs the comparison result through the output terminal of the comparator. In a specific embodiment, the interface device 10 also includes a motherboard or processor (see below). Figure 8 The motherboard or processor is connected to the comparison circuit 32 to receive the comparison result and determine the damage status of the differential port 1 based on the comparison result.

[0048] Specifically, in response to a power consumption voltage higher than the reference voltage, comparator circuit 32 outputs a first-level signal; the motherboard or processor determines, based on the first-level signal, that the negative voltage pin DP (or positive voltage pin DN) of the corresponding differential port 1 is in good condition. In response to a power consumption voltage lower than the reference voltage, comparator circuit 32 outputs a second-level signal; the motherboard or processor determines, based on the second-level signal, that the negative voltage pin DP (or positive voltage pin DN) of the corresponding differential port 1 is damaged. The first-level signal is high, and the second-level signal is low.

[0049] See Figure 5 , Figure 5This is a schematic diagram of a reference voltage generation circuit provided in one embodiment of this application. During the detection of the damage status of the negative voltage pin DP or positive voltage pin DN of each differential port 1, the reference voltage can be preset or selected according to the actual situation. For example, the reference voltage generation circuit 31 may specifically include multiple reference voltage generation units 311; each reference voltage generation unit 311 is used to generate a different reference voltage. The comparator circuit 32 can be switched to any reference voltage generation unit 311 to receive the corresponding reference voltage. It can be understood that the comparator circuit 32 connected to different reference voltage generation units 311 receives different reference voltages, thereby realizing different selections of the reference voltage during the detection process.

[0050] In a specific embodiment, the comparison circuit 32 can be selectively connected to any reference voltage generation unit 311 to receive different reference voltages and compare the power consumption voltage on the negative voltage pin DP (or positive voltage pin DN) with the different reference voltages respectively to output multiple different comparison results. The motherboard or processor determines the damage level of the corresponding differential port 1 based on the corresponding comparison results, thereby determining whether the interface device 10 can enter the market, be returned to the factory for repair, or be scrapped based on the damage level. This effectively improves the reliability of the interface device 10, reduces the failure risk of the interface device 10, and ensures the functional reliability of the product throughout its life cycle.

[0051] For ease of understanding, the following example illustrates a reference voltage generation circuit 31 comprising four reference voltage generation units 311. The four reference voltage generation units 311 output reference voltages of 1.2V, 1.1V, 1.0V, and 0.9V, respectively. A comparator circuit 32 is switchably connected to the reference voltage generation unit 311 with an output reference voltage of 1.2V to receive the 1.2V reference voltage. When comparing the power consumption voltage with the 1.2V reference voltage, if the comparator circuit 32 detects that the power consumption voltage is higher than 1.2V, the output result indicates no damage. Comparator circuit 32, responding to a power consumption voltage below 1.2V, outputs a result indicating at least level four damage and can be switched to reference voltage generation unit 311 with an output reference voltage of 1.1V to receive the reference voltage 1.1V. For further comparison of the power consumption voltage and the reference voltage 1.1V, comparator circuit 32, responding to a power consumption voltage above 1.1V, outputs a result indicating level four damage; comparator circuit 32, responding to a power consumption voltage below 1.1V, outputs a result indicating at least level three damage and can be switched to reference voltage generation unit 311 with an output reference voltage of 1.0V to receive the reference voltage 1.0V. For further comparison of the power consumption voltage and the reference voltage 1.0V, comparator circuit 32, responding to a power consumption voltage above 1.0V, outputs a result indicating level three damage; comparator circuit 32, responding to a power consumption voltage below 1.0V, outputs a result indicating at least level two damage and can be switched to reference voltage generation unit 311 with an output reference voltage of 0.9V to receive the reference voltage 0.9V. For further comparison of the power consumption voltage with the reference voltage of 0.9V, the comparator circuit 32 outputs a result indicating a level 2 damage if the power consumption voltage is higher than 0.9V; and an output indicating a level 1 damage if the power consumption voltage is lower than 1.0V. The degree of damage increases from level 4 to level 1.

[0052] Among them, such as Figure 5 As shown, each reference voltage generating unit 311 includes several resistors and a first control switch 3111. Several circuits are connected in series between the operating voltage (VDDI) and the ground voltage (GND); and the connection node between any two adjacent resistors can be selected as the output node of the reference voltage generating unit 311 to generate a corresponding output reference voltage. In this embodiment, each reference voltage generating unit 311 is described using two resistors as an example.

[0053] The first control switch 3111 is connected between the output node of the reference voltage generation unit 311 and the comparison circuit 32, so as to turn on when a corresponding control signal is received, so as to output the reference voltage generated by the reference voltage generation unit 311 to the comparison circuit 32.

[0054] In one specific embodiment, such as Figure 5 As shown, each reference voltage generating unit 311 includes a first resistor R1, a second resistor R2, and a first control switch 3111. The first terminal of the first resistor R1 is connected to the operating voltage (VDDI), the second terminal of the first resistor R1 is connected to the first terminal of the second resistor R2, and the second terminal of the second resistor R2 is connected to ground voltage (GND). The first terminal of the first control switch 3111 is connected to the connection node between the first resistor R1 and the second resistor R2, and the second terminal of the first control switch 3111 is connected to the comparator circuit 32. The control terminal of the first control switch 3111 receives a control signal to turn on.

[0055] In a specific embodiment, the first resistor R1 in the first reference voltage generation unit 311 has a resistance of 13KΩ; the second resistor R2 has a resistance of 27KΩ; and the reference voltage output by the first reference voltage generation unit 311 is 1.2V. The first resistor R1 in the second reference voltage generation unit 311 has a resistance of 16KΩ; the second resistor R2 has a resistance of 24KΩ; and the reference voltage output by the second reference voltage generation unit 311 is 1.1V. The first resistor R1 in the third reference voltage generation unit 311 has a resistance of 18KΩ; the second resistor R2 has a resistance of 22KΩ; and the reference voltage output by the third reference voltage generation unit 311 is 1.0V. The first resistor R1 in the fourth reference voltage generation unit 311 has a resistance of 20KΩ; the second resistor R2 has a resistance of 20KΩ; and the reference voltage output by the fourth reference voltage generation unit 311 is 1.0V.

[0056] See Figure 6 , Figure 6 This is a schematic diagram of an interface device based on a mobile industry processor interface protocol provided in the fourth embodiment of this application. In this embodiment, the negative voltage pin damage detection unit 3a (or positive voltage pin damage detection unit 3b) further includes a second control switch 33. The second control switch 33 is connected between the negative voltage pin DP or the positive voltage pin DN and the comparator circuit 32. When the interface device 10 performs a port damage detection operation, the second control switch 33 is turned on, so that the comparator circuit 32 compares the power consumption voltage on the negative voltage pin DP or the positive voltage pin DN with the reference voltage.

[0057] Specifically, when the interface device 10 is powered on and in the port damage detection phase, the control terminal of the second control switch 33 receives a control signal to turn on, so that the comparison circuit 32 compares the power consumption voltage on the negative voltage pin DP or the positive voltage pin DN with the reference voltage.

[0058] In one embodiment, see Figure 7 , Figure 7This is a schematic diagram of the interface device based on the mobile industry processor interface protocol provided in the fifth specific embodiment of this application. To simplify the level signals output by the comparison circuit 32 of at least one port damage detection module 3, and to facilitate processing of these level signals by the motherboard or processor, the interface device 10 also includes a logic circuit 4. The logic circuit 4 is connected to each port damage detection module 3 to summarize the comparison results of each port damage detection module 3, and performs logic gate processing on the summarized comparison results of each port damage detection module 3 to finally output a level signal to the motherboard or processor for processing. Compared to the scheme of directly outputting the comparison results of each port damage detection module 3 to the motherboard or processor for processing, this greatly reduces the number of level signals received by the motherboard or processor, facilitating processing by the motherboard or processor to determine whether the interface device 10 meets the requirements.

[0059] Specifically, if the final signal level is high, then the interface device 10 is determined to meet the requirements. If the final signal level is low, then the interface device 10 is determined to not meet the requirements.

[0060] In one specific embodiment, see Figure 8 , Figure 8 This is a schematic diagram of the interface device based on the mobile industry processor interface protocol provided in the sixth specific embodiment of this application. The interface device 10 includes a clock differential port 11 and four data differential ports 12, five negative polarity electrostatic discharge protection units 2a; five positive polarity electrostatic discharge protection units 2b; five negative polarity voltage pin damage detection units 3a; and five positive polarity voltage pin damage detection units 3b.

[0061] Specifically, the negative voltage pin CKP of clock differential port 11 is connected to a negative electrostatic discharge (ESD) protection unit 2a and a negative voltage pin damage detection unit 3a, respectively; the positive voltage pin CKN of clock differential port 11 is connected to a positive ESD protection unit 2b and a positive voltage pin damage detection unit 3b, respectively. The negative voltage pin DP of each of the four data differential ports 12 is connected to a negative ESD protection unit 2a and a negative voltage pin damage detection unit 3a, respectively; the positive voltage pin DN of each data differential port 12 is connected to a positive ESD protection unit 2b and a positive voltage pin damage detection unit 3b, respectively.

[0062] In this specific embodiment, five negative voltage pin damage detection units 3a and five positive voltage pin damage detection units 3b respectively output level signals D1, D2, D3, D4, D5, D6, D7, D8, D9, and D10; the logic circuit 4 receives these 10 level signals and performs logic gate processing on these 10 level signals to finally output a level signal D0 to the motherboard or processor for processing.

[0063] For details, see Figure 9 , Figure 9 This is a schematic diagram of the logic circuit architecture provided in one embodiment of this application. The logic circuit 4 includes multiple logic gates 41, each logic gate 41 being connected to a comparison circuit 32 unit of a negative voltage pin damage detection unit 3a or a positive voltage pin damage detection unit 3b, to receive the level signal output by the corresponding comparison circuit 32; thereby summing the comparison results of each port damage detection module 3 through the multiple logic gates 41. Each of the multiple logic gates 41 is an AND gate, so that after the multiple level signals output by the multiple comparison circuits 32 are processed by the logic circuit 4, a single level signal is finally output, which is convenient for the motherboard or processor to process. Of course, in other embodiments, the multiple logic gates 41 include AND gates and NOT gates; or the multiple logic gates 41 include AND gates and OR gates; or the multiple logic gates 41 include AND gates, NOT gates, and OR gates.

[0064] The interface device 10 based on the mobile industry processor interface protocol provided in this application includes at least one differential port 1 and at least one electrostatic discharge (ESD) protection module 2. Each ESD protection module 2 is connected to a corresponding differential port 1 to provide ESD protection for the differential port 1 and prevent ESD loss. Simultaneously, each differential port 1 is further connected to a corresponding port damage detection module 3 to detect and determine the damage state of the corresponding differential port 1. This allows for the assessment of the micro-damage state caused by excessive ESD energy or excessive ESD discharge in the interface device 10, effectively improving the reliability of the interface device 10 and reducing the potential failure risk.

[0065] See Figure 10 , Figure 10 This is a flowchart illustrating a method for detecting the damage status of an interface device based on a mobile industry processor interface protocol, as provided in one embodiment of this application. The interface device is the interface device 10 provided in any of the above embodiments. The interface device 10 includes at least one differential port 1; each differential port 1 includes a negative voltage pin DP and a positive voltage pin DN.

[0066] The detection method includes:

[0067] Step S1: Output reference voltage.

[0068] Specifically, a reference voltage is output through the reference voltage generation circuit 31 of the interface device 10. The reference voltage can be preset or selected according to the actual situation. In the specific implementation, the multiple reference voltage generation units 311 of the reference voltage generation circuit 31 generate a different reference voltage.

[0069] Step S2: When the interface device is powered on and in the port damage detection stage, compare the power consumption voltage on the negative voltage pin or the positive voltage pin with the reference voltage, output the comparison result, and determine the damage status of the differential port based on the comparison result.

[0070] Specifically, when the interface device 10 is powered on and in the port damage detection phase, the comparator circuit 32 compares the power consumption voltage on the negative voltage pin DP (or the positive voltage pin DN) with the reference voltage, thereby outputting a comparison result. The motherboard or processor of the interface device 10 receives the comparison result to determine the damage status of the differential port 1 based on the comparison result.

[0071] Specifically, in response to a power consumption voltage higher than the reference voltage, the comparator circuit 32 outputs a first-level signal; the motherboard or processor determines, based on the first-level signal, that the negative voltage pin DP (or positive voltage pin DN) of the corresponding differential port 1 is in good condition. In response to a power consumption voltage lower than the reference voltage, the comparator circuit 32 outputs a second-level signal; the motherboard or processor determines, based on the second-level signal, that the negative voltage pin DP (or positive voltage pin DN) of the corresponding differential port 1 is damaged.

[0072] In one embodiment, see Figure 11 , Figure 11 This is a schematic diagram of the structure of a display panel provided in one embodiment of this application. A display panel is provided. The display panel can be a rigid screen or a flexible screen, used to display images during operation. The display panel includes the interface device 10 based on the mobile industry processor interface protocol involved in any of the above embodiments. The specific structure and function of the interface device 10 can be found in the specific structure and function of the interface device 10 based on the mobile industry processor interface protocol provided in the above embodiments, and can achieve the same or similar technical effects, which will not be repeated here.

[0073] Of course, the display panel also includes other structures such as a substrate, an organic light-emitting layer, and a pixel-defining layer. For details of these structures, please refer to the relevant structural descriptions of existing display panels, which can achieve the same or similar technical effects, and will not be elaborated here.

[0074] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, or indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0075] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0076] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An interface device based on a mobile industry processor interface protocol, characterized in that, include: At least one differential port; At least one electrostatic discharge (ESD) protection module, wherein each ESD protection module is connected to a corresponding differential port to provide ESD protection for the differential port; At least one port damage detection module, wherein each of the port damage detection modules is connected to a corresponding differential port to detect and determine the damage state of the corresponding differential port; A logic circuit is connected to each of the port damage detection modules, and the comparison results of each of the port damage detection modules are summarized through the logic circuit to determine whether the interface device meets the requirements. Each of the aforementioned port damage detection modules includes: A negative polarity voltage pin damage detection unit is connected to the corresponding negative polarity voltage pin of the differential port to detect and determine the damage status of the negative polarity voltage pin. A positive voltage pin damage detection unit is connected to the corresponding positive voltage pin of the differential port to detect and determine the damage status of the positive voltage pin. The negative polarity voltage pin damage detection unit or the positive polarity voltage pin damage detection unit includes: Reference voltage generation circuit, used to output reference voltage; A comparison circuit is connected to the reference voltage generation circuit and the negative or positive voltage pin of the differential port, respectively. When the interface device is powered on and in the port damage detection stage, the power consumption voltage on the negative or positive voltage pin is compared with the reference voltage, and the comparison result is output to determine the damage state of the differential port based on the comparison result. The reference voltage generation circuit includes: Multiple reference voltage generation units, wherein each reference voltage generation unit is used to generate a different reference voltage, and the comparison circuit is switchably connected to any of the reference voltage generation units to receive different reference voltages, so as to compare the power dissipation voltage on the negative voltage pin or the positive voltage pin with the different reference voltages to determine the damage level of the differential port.

2. The interface device according to claim 1, characterized in that, Each of the electrostatic discharge protection modules includes: A negative polarity electrostatic protection unit is connected to the negative polarity voltage pin of the corresponding differential port to provide electrostatic protection for the negative polarity voltage pin.

3. The interface device according to claim 1, characterized in that, Each of the electrostatic discharge protection modules includes: A positive polarity electrostatic protection unit is connected to the positive polarity voltage pin of the corresponding differential port to provide electrostatic protection for the positive polarity voltage pin.

4. The interface device according to claim 1, characterized in that, Each of the aforementioned reference voltage generating units includes: A plurality of resistors are connected in series between the working voltage and the ground voltage, wherein the connection node between any two adjacent resistors can be selected as the output node of the reference voltage generating unit to generate the corresponding reference voltage. A first control switch is connected between the output node of the reference voltage generation unit and the comparison circuit to switchably output the reference voltage generated by the reference voltage generation unit to the comparison circuit.

5. The interface device according to claim 1, characterized in that, The negative polarity voltage pin damage detection unit or the positive polarity voltage pin damage detection unit further includes: A second control switch is connected between the negative voltage pin or the positive voltage pin and the comparison circuit. When the interface device performs a port damage detection operation, the second control switch is turned on so that the comparison circuit compares the power consumption voltage on the negative voltage pin or the positive voltage pin with the reference voltage.

6. The interface device according to claim 1, characterized in that, The logic circuit includes multiple logic gates to summarize the comparison results of each of the port damage detection modules.

7. The interface device according to claim 6, characterized in that, The plurality of logic gates includes AND gates; or, The plurality of logic gates includes AND gates and OR gates; or, The plurality of logic gates includes AND gates and NOT gates; or, The plurality of logic gates include AND gates, NOT gates, and OR gates.

8. A method for detecting the damage status of an interface device, used for detecting the damage status of an interface device based on a mobile industry processor interface protocol, wherein the interface device includes a differential port, a port damage detection module, and a logic circuit; the logic circuit is connected to each of the port damage detection modules; the differential port includes a negative voltage pin and a positive voltage pin; the port damage detection module includes a positive voltage pin damage detection unit and a negative voltage pin damage detection unit, wherein the positive voltage pin damage detection unit or the negative voltage pin damage detection unit includes a reference voltage generation circuit and a comparison circuit, characterized in that, The detection method includes: Output reference voltage; wherein, the reference voltage generation circuit is used to output the reference voltage, and the reference voltage generation circuit includes a plurality of reference voltage generation units, wherein each reference voltage generation unit is used to generate a different reference voltage; When the interface device is powered on and in the port damage detection phase, the power consumption voltage on the negative voltage pin or the positive voltage pin is compared with the reference voltage, and a comparison result is output to determine the damage state of the differential port based on the comparison result. The comparison circuit is connected to the reference voltage generation circuit and the negative voltage pin or the positive voltage pin of the differential port, respectively. When the interface device is powered on and in the port damage detection phase, the power consumption voltage on the negative voltage pin or the positive voltage pin is compared with the reference voltage, and a comparison result is output to determine the damage state of the differential port based on the comparison result. The comparison circuit can be switched to any of the reference voltage generation units to receive different reference voltages, so as to determine the damage level of the differential port by comparing the power consumption voltage on the negative voltage pin or the positive voltage pin with different reference voltages. The comparison results of each of the port damage detection modules are summarized by the logic circuit operations to determine whether the interface device meets the requirements.

9. A display panel, characterized in that, Includes the interface device based on the mobile industry processor interface protocol as described in any one of claims 1-7.

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