A 10TSRAM voltage domain in-memory calculation circuit
By introducing a 10T SRAM cell array and voltage modulation circuit into the in-memory computing circuit, the bit line potential is isolated from the analog-to-digital converter, thus solving the interference problem in the in-memory computing process and improving the computing accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- NANJING INST OF INTELLIGENT TECH INST OF MICROELECTRONICS OF THE CHINESE ACAD OF
- Filing Date
- 2022-08-02
- Publication Date
- 2026-06-16
Smart Images
Figure CN115223620B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of electronic component technology, and in particular to a 10T SRAM voltage domain in-memory calculation circuit. Background Technology
[0002] As the demand for edge computing increases, the von Neumann architecture has gradually reached its bottleneck. This led to the concept of in-memory computing, which adds computational structures to existing memory arrays, enabling multiplication and accumulation calculations within the array and significantly reducing power consumption. However, existing in-memory computing processes can interfere with the nodes of memory cells, and the load on the analog-to-digital converter can cause fluctuations in the potential on the bit lines, resulting in low computational accuracy. Summary of the Invention
[0003] To address the aforementioned problems in the existing technology, this invention provides a 10T SRAM voltage domain in-memory calculation circuit.
[0004] To achieve the above objectives, the present invention provides the following solution:
[0005] A 10T SRAM voltage domain in-memory computing circuit includes: a 10T SRAM cell array, a first voltage modulation circuit, a first analog-to-digital converter, a second voltage modulation circuit, and a second analog-to-digital converter.
[0006] One end of the first voltage modulation circuit is connected to the first analog-to-digital converter; the other end of the first voltage modulation circuit is connected to the 10T SRAM cell array; one end of the second voltage modulation circuit is connected to the second analog-to-digital converter; the other end of the second voltage modulation circuit is connected to the 10T SRAM cell array.
[0007] Preferably, the 10T SRAM cell array includes: bit line GBL, bit line GBLB, and multiple 10T SRAM cells;
[0008] One end of the 10T SRAM cell is connected to the bit line GBL; the other end of the 10T SRAM cell is connected to the bit line GBLB; the other end of the first voltage modulation circuit is connected to the bit line GBL; and the other end of the second voltage modulation circuit is connected to the bit line GBLB.
[0009] Preferably, it further includes: a discharge terminal VB and a power supply VDD;
[0010] Both the discharge terminal VB and the power supply VDD are connected to the first voltage modulation circuit.
[0011] Preferably, the first voltage modulation circuit includes: transistor NM5 and transistor NM6;
[0012] The discharge terminal VB and the power supply VDD are both connected to the tube NM5; the tube NM5 is connected to the tube NM6.
[0013] Preferably, both NM5 and NM6 are NMOS transistors;
[0014] The source of transistor NM5 is connected to the power supply VDD; the gate of transistor NM5 is connected to the discharge terminal VB; the drain of transistor NM5 is connected to the drain of transistor NM6; the gate of transistor NM6 is connected to the bit line GBL; and the source of transistor NM6 is grounded.
[0015] Preferably, it further includes: a discharge terminal VB and a power supply VDD;
[0016] Both the discharge terminal VB and the power supply VDD are connected to the second voltage modulation circuit.
[0017] Preferably, the second voltage modulation circuit includes: transistor NM7 and transistor NM8;
[0018] The discharge terminal VB and the power supply VDD are both connected to the tube NM7; the tube NM7 is connected to the tube NM8.
[0019] Preferably, the transistor NM7 and the transistor NM8 are both NMOS transistors;
[0020] The source of transistor NM7 is connected to the power supply VDD; the gate of transistor NM7 is connected to the discharge terminal VB; the drain of transistor NM7 is connected to the drain of transistor NM8; the gate of transistor NM8 is connected to the bit line GBLB; and the source of transistor NM8 is grounded.
[0021] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:
[0022] The present invention provides a 10T SRAM voltage domain in-memory calculation circuit, comprising: a 10T SRAM cell array, a first voltage modulation circuit, a first analog-to-digital converter, a second voltage modulation circuit, and a second analog-to-digital converter; one end of the first voltage modulation circuit is connected to the first analog-to-digital converter; the other end of the first voltage modulation circuit is connected to the 10T SRAM cell array; one end of the second voltage modulation circuit is connected to the second analog-to-digital converter; and the other end of the second voltage modulation circuit is connected to the 10T SRAM cell array. Based on this, the present invention, by employing a voltage modulation circuit and a 10T SRAM cell array, can solve the problem of computational interference, thereby improving computational accuracy. Attached Figure Description
[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0024] Figure 1 This is a schematic diagram of the structure of the 10T SRAM voltage domain in-memory calculation circuit provided by the present invention;
[0025] Figure 2 This is a structural diagram of a 10T SRAM cell provided in an embodiment of the present invention. Detailed Implementation
[0026] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0027] The purpose of this invention is to provide a 10T SRAM voltage domain in-memory calculation circuit that can solve the problem of calculation interference and thus improve calculation accuracy.
[0028] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.
[0029] The 10T SRAM voltage domain in-memory calculation circuit provided by the present invention includes: a 10T SRAM cell array, a first voltage modulation circuit, a first analog-to-digital converter, a second voltage modulation circuit, and a second analog-to-digital converter.
[0030] One end of the first voltage modulation circuit is connected to the first analog-to-digital converter. The other end of the first voltage modulation circuit is connected to a 10T SRAM cell array. One end of the second voltage modulation circuit is connected to the second analog-to-digital converter. The other end of the second voltage modulation circuit is connected to the 10T SRAM cell array.
[0031] In practical applications, the number of 10T SRAM cell columns used in a 10T SRAM cell array can be selected according to actual needs, such as 32 columns. The following explanation uses a single 10T SRAM cell column as an example to illustrate the specific structure and working principle of the aforementioned 10T SRAM voltage domain in-memory calculation circuit.
[0032] like Figure 1As shown, in this embodiment, the 10T SRAM cell array includes: bit line GBL, bit line GBLB, and 32 10T SRAM cells (i.e., 10T cells). The 32 10T SRAM cells are used to store 1 bit weight data. This design allows for binarization operations, and the operation results are shown in Table 1 below.
[0033] One end of the 10T SRAM cell is connected to the bit line GBL. The other end of the 10T SRAM cell is connected to the bit line GBLB. The other end of the first voltage modulation circuit is connected to the bit line GBL. The other end of the second voltage modulation circuit is connected to the bit line GBLB.
[0034] Among them, such as Figure 2 As shown, the 10T SRAM cell adds two read paths compared to the traditional 6T SRAM cell: transistors NM1 and NM2 form the left read path, and transistors NM3 and NM4 form the right read path, so as to decouple the read and write paths.
[0035] Taking the left read path as an example, the specific working principle of the 10T SRAM cell used in this invention is explained: In the 10T SRAM cell, the node Q storing data controls the gate of transistor NM2, and the read signal is controlled by the word line RWL1, which controls the gate of transistor NM1. When the read pulse arrives, if the weight stored in the node Q storing data is 1, the path between transistors NM1 and NM2 is turned on, and a discharge occurs on the bit line GBL, indicating a read of 1. On the other side, the working relationship between transistors NM3 and NM4 and the node QB storing data is the same as the working principle between transistors NM1 and NM2 and the node Q storing data, and will not be repeated here. Bit lines BL and BLB are used to control the discharge of the 6T SRAM cell, and the word line WL is used to control the gate of the transistor in the 6T SRAM cell. Figure 1 and Figure 2 In this diagram, G represents the gate, S represents the source, and D represents the drain.
[0036] Table 1. Results of Binarization Operation
[0037] Input = 1 (RWL1 open) Input = 0 (RWL2 enabled) Weight = 1 (Store 1 for Q point) No discharge on either side GBLB discharge Weight = 0 (Q-point is stored as 0) GBL discharge No discharge
[0038] In order to ensure that the modulated voltage model is within a range with good linearity and to further improve the calculation accuracy, the 10T SRAM voltage domain memory calculation circuit used in this embodiment is also equipped with a discharge terminal VB and a power supply VDD.
[0039] The discharge terminal VB and the power supply VDD are connected to the first voltage modulation circuit and the second voltage modulation circuit.
[0040] The first voltage modulation circuit includes transistors NM5 and NM6. The second voltage modulation circuit includes transistors NM7 and NM8.
[0041] The discharge terminal VB and the power supply VDD are both connected to tube NM5. Tube NM5 is connected to tube NM6. The discharge terminal VB and the power supply VDD are both connected to tube NM7. Tube NM7 is connected to tube NM8.
[0042] In this embodiment, when both NM5 and NM6 are NMOS transistors, the source of NM5 is connected to the power supply VDD. The gate of NM5 is connected to the discharge terminal VB. The drain of NM5 is connected to the drain of NM6. The gate of NM6 is connected to the bit line GBL. The source of NM6 is grounded.
[0043] When both NM7 and NM8 are NMOS transistors, the source of NM7 is connected to the power supply VDD. The gate of NM7 is connected to the discharge terminal VB. The drain of NM7 is connected to the drain of NM8. The gate of NM8 is connected to the bit line GBLB. The source of NM8 is grounded.
[0044] Based on the structure of the modulation circuit provided above, taking the first voltage modulation circuit as an example, the working principles of the first and second voltage modulation circuits are explained:
[0045] The discharge result at the discharge terminal VB controls the gate of transistor NM6. The source of transistor NM6 is grounded, and the voltage at its drain reflects the calculation result. Transistor NM5, located in the linear region, acts like a current source, limiting the current in the path from NM5 to NM6 to a fixed value. Voltage modulation means representing the calculation result through voltage levels. Its function is that the voltage on the bit line GBL controls the gate of transistor NM6. When the first analog-to-digital converter (ADC) is turned on and operating, the voltage value will not jump (usually drop) due to the load on the ADC, ensuring the accuracy of the calculation. Simultaneously, the presence of the discharge terminal VB also allows the modulated voltage signal to remain within a range with good linearity.
[0046] The working principle of the voltage modulation circuit (i.e., the second voltage modulation circuit) on the other side, composed of transistors NM7 and NM8, is the same, and will not be elaborated here.
[0047] By employing 10T SRAM cells, the calculation process no longer interferes with the nodes of the storage cells, solving the problem of read interference with write operations. Furthermore, the voltage modulation circuit isolates the potentials on bit lines GBLB and GBL from the first and second analog-to-digital converters (ADCs). During the switching on of either the first or second ADC, the load on either ADC will not cause changes in the potentials on the bit lines, thus resolving the problem of interference affecting calculation accuracy in existing technologies.
[0048] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0049] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.
Claims
1. A 10T SRAM voltage domain in-memory computing circuit, characterized in that, include: 10T SRAM cell array, first voltage modulation circuit, first analog-to-digital converter, second voltage modulation circuit, second analog-to-digital converter, discharge terminal VB and power supply VDD; One end of the first voltage modulation circuit is connected to the first analog-to-digital converter; the other end of the first voltage modulation circuit is connected to the 10T SRAM cell array. One end of the second voltage modulation circuit is connected to the second analog-to-digital converter; The other end of the second voltage modulation circuit is connected to the 10T SRAM cell array; The 10T SRAM cell array includes: bit line GBL, bit line GBLB and multiple 10T SRAM cells; One end of the 10T SRAM cell is connected to the bit line GBL; the other end of the 10T SRAM cell is connected to the bit line GBLB; the other end of the first voltage modulation circuit is connected to the bit line GBL; the other end of the second voltage modulation circuit is connected to the bit line GBLB; the discharge terminal VB and the power supply VDD are both connected to the first voltage modulation circuit. The first voltage modulation circuit includes: transistor NM5 and transistor NM6; The discharge terminal VB and the power supply VDD are both connected to the tube NM5; the tube NM5 is connected to the tube NM6; The source of transistor NM5 is connected to the power supply VDD; the gate of transistor NM5 is connected to the discharge terminal VB; the drain of transistor NM5 is connected to the drain of transistor NM6; the gate of transistor NM6 is connected to the bit line GBL; and the source of transistor NM6 is grounded. Both the discharge terminal VB and the power supply VDD are connected to the second voltage modulation circuit. The second voltage modulation circuit includes: transistor NM7 and transistor NM8; The discharge terminal VB and the power supply VDD are both connected to the transistor NM7; the transistor NM7 is connected to the transistor NM8; the source of the transistor NM7 is connected to the power supply VDD; the gate of the transistor NM7 is connected to the discharge terminal VB; the drain of the transistor NM7 is connected to the drain of the transistor NM8; the gate of the transistor NM8 is connected to the bit line GBLB; and the source of the transistor NM8 is grounded.
2. The 10T SRAM voltage domain in-memory calculation circuit according to claim 1, characterized in that, Both NM5 and NM6 are NMOS transistors.
3. The 10T SRAM voltage domain in-memory calculation circuit according to claim 1, characterized in that, Both NM7 and NM8 are NMOS transistors.