Display substrate and display device

Abstract

A display substrate and a display device. The display substrate includes a first signal line and a second signal line. The display substrate includes a first area and a second area; neither the first signal line nor the second signal line passes through the second area. The first signal line extends along a first direction, and the second signal line extends along a second direction; the portions of the first signal line extending through the second area located on both sides of the second area are electrically connected via a first connecting line extending along the first direction and a second connecting line extending along the second direction; the portions of the second signal line extending through the second area located on both sides of the second area are electrically connected via a third connecting line extending along the first direction and a fourth connecting line extending along the second direction; the second connecting line overlaps the third connecting line, and the first connecting line is located on the same side of the second area as the third connecting line, away from the second area. The display substrate reduces the load mutation of the first and second signal lines while reducing the wiring space around the second area.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a display substrate and a display device. Background Art

[0002] In the field of display technology, thin film transistors (TFTs) can include amorphous silicon (a-Si) TFTs, low-temperature polysilicon (LTPS) TFTs, and oxides (such as indium gallium zinc oxide TFTs). Low-temperature polycrystalline oxide (LTPO) is a low-power display technology that integrates low-temperature polysilicon (LTPS) and oxide processes to produce both LTPS and oxide TFTs in display panels. This combines the advantages of both LTPS and oxide TFTs, maximizing the ultra-high mobility of LTPS and the low leakage current of oxides to achieve superior display performance.

[0003] As people continue to pursue the visual effects of display products, narrow bezels and full-screen displays have gradually become the major development trends of organic light-emitting diode (OLED) display products. Summary of the Invention

[0004] Embodiments of the present disclosure provide a display substrate and a display device.

[0005] In an embodiment of the present disclosure, a display substrate includes a base substrate and a plurality of first signal lines and a plurality of second signal lines located on the base substrate. The base substrate includes a first area and a second area, the first area being located around the second area; the plurality of first signal lines do not pass through the second area; the plurality of second signal lines are located in a different layer from the plurality of first signal lines and do not pass through the second area. At least part of the first signal lines extend along the first direction, and at least part of the second signal lines extend along the second direction, and the first direction intersects with the second direction; the plurality of first signal lines include part of the first signal lines whose extensions pass through the second area, and each of the part of the first signal lines includes a first sub-signal line and a second sub-signal line located on both sides of the second area, the first sub-signal line and the second sub-signal line are electrically connected by a first connecting line extending along the first direction and a second connecting line extending along the second direction, and the part of the first signal lines are electrically connected to the plurality of first connecting lines and the plurality of second connecting lines; the plurality of second signal lines include an extension line Part of the second signal lines passing through the second area, each of the part of the second signal lines includes a third sub-signal line and a fourth sub-signal line located on both sides of the second area, the third sub-signal line and the fourth sub-signal line are electrically connected through a third connecting line extending along the first direction and a fourth connecting line extending along the second direction, and the part of the second signal lines is electrically connected to multiple third connecting lines and multiple fourth connecting lines; in a direction perpendicular to the substrate, at least one second connecting line overlaps with at least one third connecting line, and on the same side of the second area, at least one first connecting line is located on a side of at least one third connecting line away from the second area.

[0006] For example, according to an embodiment of the present disclosure, the plurality of first signal lines include data lines, and the plurality of second signal lines include at least light emission control signal lines.

[0007] For example, according to an embodiment of the present disclosure, the minimum distance between a fourth connection line closest to the second area and the edge of the second area is smaller than the minimum distance between a first connection line closest to the second area and the edge of the second area.

[0008] For example, according to an embodiment of the present disclosure, on the same side of the second area, the first group of connection lines among the multiple second connection lines is located on a side of at least one fourth connection line close to the second area, and the second group of connection lines among the multiple second connection lines is located on a side of the at least one fourth connection line away from the second area.

[0009] For example, according to an embodiment of the present disclosure, along a direction perpendicular to the base substrate, the first group of connection lines overlaps with the third connection lines, and the second group of connection lines does not overlap with the third connection lines.

[0010] For example, according to an embodiment of the present disclosure, the distance between a second connection line in the first group of connection lines that is closest to the second group of connection lines and a second connection line in the second group of connection lines that is closest to the first group of connection lines is a first distance, the distance between two adjacent second connection lines in the second group of connection lines is a second distance, and the ratio of the first distance to the second distance is greater than 2.

[0011] For example, according to an embodiment of the present disclosure, the first connection line connected to the second connection line closest to the second connection line in the first group of connection lines includes two parts respectively located on both sides of the second connection line in the first direction.

[0012] For example, according to an embodiment of the present disclosure, the first connection line connected to the second connection line closest to the second connection line in the first group of connection lines extends to the position of the second connection line closest to the first connection line in the second group of connection lines.

[0013] For example, according to an embodiment of the present disclosure, each of the N first connection lines that are respectively connected to the N second connection lines closest to the second group of connection lines in the first group of connection lines includes two parts respectively located on both sides of the second connection line connected to it in the first direction, and among the N first connection lines arranged along the direction close to the second area, the length of the part of the first connection line located on the side of the second connection line connected to it close to the second group of connection lines gradually decreases, N is a positive integer greater than or equal to 1, and the number of the second connection lines in the first group of connection lines located on one side of the center of the second area is greater than or equal to N.

[0014] For example, according to an embodiment of the present disclosure, a second signal line closest to the second area among the second signal lines whose extension lines do not pass through the second area is located between a fourth connecting line closest to the second area and the fourth connecting line adjacent thereto.

[0015] For example, according to an embodiment of the present disclosure, on the same side of the second area, at least one first signal line of the plurality of first signal lines whose extension line does not pass through the second area is located on a side of the first connection line close to the second area.

[0016] For example, according to an embodiment of the present disclosure, the ratio of the distance between the closest first connection lines and the third connection lines to the distance between two adjacent third connection lines is 0.8-1.2.

[0017] For example, according to an embodiment of the present disclosure, in the first region, at least one first connection line and at least one third connection line are located in the same layer, and at least one second connection line and at least one fourth connection line are located in the same layer.

[0018] For example, according to an embodiment of the present disclosure, at least one first connection line and at least one third connection line are both located in the same layer as the plurality of first signal lines.

[0019] For example, according to an embodiment of the present disclosure, the plurality of second signal lines are located between the plurality of first signal lines and the base substrate, and the fourth connection line is located between the plurality of first signal lines and the plurality of second signal lines.

[0020] For example, according to an embodiment of the present disclosure, the first area is a display area, the first area surrounds the second area, the base substrate also includes a peripheral area surrounding the display area, the multiple second groups of connection lines include the second connection lines located in the first area and the second connection lines located in the peripheral area, the second connection lines located in the first area are arranged in a different layer from the first connection lines, and the second connection lines located in the peripheral area are arranged in the same layer as the first connection lines.

[0021] For example, according to an embodiment of the present disclosure, the second connection line located in the peripheral area is provided in the same layer as the first signal line.

[0022] For example, according to an embodiment of the present disclosure, at least one second connection line in the first group of connection lines and at least one fourth connection line are arranged in the same layer and spaced apart, and are located on the same straight line.

[0023] For example, according to an embodiment of the present disclosure, on the same side of the second region, at least one first signal line connected to the second group of connection lines overlaps with each fourth connection line in a direction perpendicular to the base substrate.

[0024] For example, according to an embodiment of the present disclosure, the orthographic projection of each first connecting line on the straight line extending along the first direction overlaps with the orthographic projection of each third connecting line on the straight line; the orthographic projection of at least one second connecting line on the straight line extending along the second direction does not overlap with the orthographic projection of at least one fourth connecting line on the straight line.

[0025] For example, according to an embodiment of the present disclosure, the display substrate further includes: a light-emitting element and a pixel circuit located on the base substrate, wherein the pixel circuit is electrically connected to the light-emitting element. The pixel circuit includes a driving transistor, a light-emitting control transistor, and a reset transistor, wherein the gate of the light-emitting control transistor is electrically connected to the light-emitting control signal line, the first electrode of the light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the light-emitting control transistor is electrically connected to the light-emitting element; the gate of the reset transistor is electrically connected to the reset control signal line, one electrode of the reset transistor is electrically connected to the second electrode of the driving transistor, or one electrode of the reset transistor is electrically connected to the second electrode of the light-emitting control transistor; and the second signal line includes the reset control signal line.

[0026] For example, according to an embodiment of the present disclosure, the display substrate also includes: a light-emitting element and a pixel circuit located on the base substrate, and the pixel circuit is electrically connected to the light-emitting element; wherein the pixel circuit includes at least one N-type thin film transistor and at least one P-type thin film transistor; the second signal line includes a signal line connected to the gate of at least one of the P-type thin film transistors.

[0027] For example, according to an embodiment of the present disclosure, the display substrate also includes: a light-emitting element and a pixel circuit located on the base substrate, and the pixel circuit is electrically connected to the light-emitting element; wherein the pixel circuit includes at least one oxide thin film transistor and at least one low-temperature polycrystalline silicon thin film transistor; the second signal line includes a signal line connected to the gate of at least one of the low-temperature polycrystalline silicon thin film transistors.

[0028] For example, according to an embodiment of the present disclosure, the first area is a display area, the first area surrounds the second area, and the base substrate also includes a peripheral area surrounding the display area; the display substrate also includes: a plurality of fifth connecting lines extending along the first direction and a plurality of sixth connecting lines extending along the second direction, the fifth connecting line that is located on the same layer and on the same straight line as the first connecting line is spaced apart from the first connecting line, the fifth connecting line that is located on the same layer and on the same straight line as the third connecting line is spaced apart from the third connecting line, the sixth connecting line that is located on the same layer and on the same straight line as the second connecting line is spaced apart from the second connecting line, the sixth connecting line that is located on the same layer and on the same straight line as the fourth connecting line is spaced apart from the fourth connecting line, and at least one of the fifth connecting line and the sixth connecting line is electrically connected to the third signal line, and the third signal line is located in the peripheral area.

[0029] For example, according to an embodiment of the present disclosure, at least one of the positions where the fifth connecting line is spaced from the first connecting line and the positions where the fifth connecting line is spaced from the third connecting line overlaps with the film layer where the fourth connecting line is located, and at least one of the positions where the sixth connecting line is spaced from the second connecting line and the positions where the sixth connecting line is spaced from the fourth connecting line overlaps with the film layer where the first connecting line is located.

[0030] For example, according to an embodiment of the present disclosure, two first signal lines adjacent to the first connecting line are arranged on both sides of at least one first connecting line, and the ratio of the minimum distance between the two first signal lines and the first connecting line is 0.9 to 1.1; two first signal lines adjacent to the third connecting line are arranged on both sides of at least one third connecting line, and the ratio of the minimum distance between the two first signal lines and the third connecting line is 0.9 to 1.1.

[0031] Another embodiment of the present disclosure provides a display device, comprising any of the above-mentioned display substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0033] Figure 1 It is a partial plan view of a display substrate provided according to an embodiment of the present disclosure.

[0034] Figure 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure.

[0035] Figures 3A to 3H Includes a schematic diagram of the different film layers in the pixel circuit.

[0036] Figure 3I for Figures 3A to 3F Schematic diagram of film layer stacking.

[0037] Figure 4 A schematic diagram of a partial plan structure is provided for another example according to an embodiment of the present disclosure.

[0038] Figure 5 for Figure 4 Schematic diagram of part of the film layer in area E1.

[0039] Figure 6 and Figure 7 for Figure 5 Schematic diagram of two conductive layers at the indicated locations.

[0040] Figure 8 for Figure 4Schematic diagram of part of the film layer in area E2.

[0041] Figures 9 and 10 for Figure 8 Schematic diagram of two conductive layers at the indicated locations.

[0042] Figure 11 for Figure 4 Schematic diagram of part of the film layer in area E3 is shown.

[0043] Figure 12 for Figure 4 Schematic diagram of part of the film layer in area E4.

[0044] Figure 13 To include Figure 4 Schematic diagram of the local film layer in area E1.

[0045] Figure 14 and Figure 15 for Figure 13 Schematic diagram of two conductive layers at the indicated locations.

[0046] Figure 16 for Figure 1 Schematic diagram of part of the film layer in area E5 is shown.

[0047] Figure 17 for Figure 16 Schematic diagram of part of the film layer in area E6 is shown.

[0048] Figure 18 for Figure 16 Schematic diagram of part of the film layer in area E7.

[0049] Figure 19 for Figure 4 Schematic diagram of a portion of the structure of area E8 is shown.

[0050] Figure 20 for Figure 19 Schematic diagram of part of the structure of area E9 is shown.

[0051] Figures 21 to 25 for Figure 20 Schematic diagram of the different membrane layers in the indicated positions. DETAILED DESCRIPTION

[0052] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0053] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0054] The features such as “parallel”, “perpendicular” and “same” used in the embodiments of the present disclosure include the features such as “parallel”, “perpendicular” and “same” in a strict sense, as well as the cases where “approximately parallel”, “approximately perpendicular” and “approximately the same” contain certain errors, taking into account the errors associated with the measurement and the measurement of specific quantities (for example, the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by ordinary technicians in this field. For example, “approximately” can mean within one or more standard deviations, or within 10% or 5% of the value. When the number of a component is not specifically indicated below in the embodiments of the present disclosure, it means that the component can be one or more, or can be understood as at least one. “At least one” means one or more, and “multiple” means at least two. The “same layer” in the embodiments of the present disclosure refers to the relationship between multiple film layers formed by the same material after the same step (for example, a one-step patterning process). The “same layer” here does not always mean that the thickness of multiple film layers is the same or the height of multiple film layers in the cross-sectional view is the same.

[0055] The embodiments of the present disclosure provide a display substrate and a display device. The display substrate includes a base substrate, and a plurality of first signal lines and a plurality of second signal lines located on the base substrate. The base substrate includes a first area and a second area, and the first area is located around the second area; the plurality of first signal lines are located on the base substrate and do not pass through the second area; the plurality of second signal lines are located in a different layer from the plurality of first signal lines and do not pass through the second area. At least part of the first signal lines extend along the first direction, and at least part of the second signal lines extend along the second direction, and the first direction intersects with the second direction; the plurality of first signal lines include part of the first signal lines whose extensions pass through the second area, and each of the part of the first signal lines includes a first sub-signal line and a second sub-signal line located on both sides of the second area, and the first sub-signal line and the second sub-signal line are electrically connected by a first connecting line extending along the first direction and a second connecting line extending along the second direction, and part of the first signal lines are electrically connected to the plurality of first connecting lines and the plurality of second connecting lines; the plurality of second signal lines include part of the first signal lines whose extensions pass through the first area. Part of the second signal lines in the second area, each of the part of the second signal lines includes a third sub-signal line and a fourth sub-signal line located on both sides of the second area, the third sub-signal line and the fourth sub-signal line are electrically connected through a third connecting line extending along the first direction and a fourth connecting line extending along the second direction, and part of the second signal lines are electrically connected to multiple third connecting lines and multiple fourth connecting lines; in a direction perpendicular to the substrate, at least one second connecting line overlaps with at least one third connecting line, and on the same side of the second area, at least one first connecting line is located on a side of the at least one third connecting line away from the second area.

[0056] The display substrate provided by the embodiment of the present disclosure uses a first connecting line, a second connecting line, a third connecting line and a fourth connecting line to connect the signal lines located on both sides of the second area. The first connecting line is located on the side of the third connecting line away from the second area, and the second connecting line overlaps with the third connecting line. While reducing the wiring space around the second area to increase the area of ​​the display area, the load mutation of the first signal line and the second signal line can be reduced.

[0057] The display substrate and the display device provided by the embodiments of the present disclosure are described below with reference to the accompanying drawings.

[0058] Figure 1 FIG. 1 is a partial plan view of a display substrate provided according to an embodiment of the present disclosure. Figure 1 As shown, the display substrate includes a base substrate 100, and a plurality of first signal lines 200 and a plurality of second signal lines 300 located on the base substrate 100. The base substrate 100 includes a first region 101 and a second region 102, and the first region 101 is located around the second region 102. For example, Figure 1It is schematically shown that the first area 101 surrounds the second area 102 , but the present invention is not limited thereto. The first area 101 may be located only at a portion of the periphery of the second area 102 , such as the first area 101 only surrounds a portion of the second area 102 .

[0059] For example, Figure 1 As shown, the first area 101 is a display area, and the second area 102 can be a hole area located in the first area 101. For example, the second area 102 can be a display area or a non-display area. For example, the second area 102 is an area where no signal line passes through. For example, the edge of the second area 102 can be the edge of the hole area. For example, at least part of the edge of the second area 102 is not parallel to the first direction and the second direction. For example, the shape of the second area 102 can be circular or elliptical. However, the shape of the second area 102 can be a polygon, such as a quadrilateral, a hexagon, or an octagon. For example, the shape of the first area 101 can be a quadrilateral, such as a rectangle, but the shape of the first area 101 can also be circular or other polygons other than a quadrilateral, such as a hexagon, an octagon, etc.

[0060] like Figure 1 As shown, the plurality of first signal lines 200 do not pass through the second region 102; the plurality of second signal lines 300 are located in a different layer from the plurality of first signal lines 200 and do not pass through the second region 102. For example, each first signal line 200 does not pass through the second region 102, and each second signal line 300 does not pass through the second region 102. For example, the plurality of first signal lines 200 that do not pass through the second region 102 include first signal lines 200 whose extensions do not pass through the second region 102 and first signal lines 200 whose extensions pass through the second region 102; the plurality of second signal lines 300 that do not pass through the second region 102 include second signal lines 300 whose extensions do not pass through the second region 102 and second signal lines 300 whose extensions pass through the second region 102.

[0061] like Figure 1 As shown, at least a portion of the first signal line 200 extends along a first direction, and at least a portion of the second signal line 300 extends along a second direction, and the first direction intersects the second direction. Figure 1It is schematically shown that the first direction is the X direction and the second direction is the Y direction, but it is not limited to this, and the first direction and the second direction can be interchangeable. For example, the first direction and the second direction can be perpendicular, but it is not limited to this, and the angle between the first direction and the second direction can be 60 to 110 degrees. For example, one of the first direction and the second direction can be the row direction, and the other can be the column direction. For example, each first signal line 200 extends along the first direction, and each second signal line 200 extends along the second direction. In the embodiment of the present disclosure, the first signal line extending along the first direction can refer to the overall extension direction of the first signal line being the first direction, and the first signal line can be a straight line extending along the first direction, or a broken line extending along the first direction; the second signal line extending along the second direction can refer to the overall extension direction of the second signal line being the second direction, and the second signal line can be a straight line extending along the second direction, or a broken line extending along the second direction.

[0062] like Figure 1 As shown, the plurality of first signal lines 200 include a portion of the first signal lines 200 extending through the second region 102. Each of the portion of the first signal lines 200 includes a first sub-signal line 210 and a second sub-signal line 220 located on either side of the second region 102. The first sub-signal line 210 and the second sub-signal line 220 are electrically connected via a first connecting line 410 extending in a first direction and a second connecting line 420 extending in a second direction. Furthermore, the portion of the first signal line 200 is electrically connected to the plurality of first connecting lines 410 and the plurality of second connecting lines 420. For example, the first connecting line 410 is electrically connected to the second connecting line 420. The first signal line 200 extending through the second region 102 is disconnected at a location in the second region 102, forming two portions, namely, the first sub-signal line 210 and the second sub-signal line 220. These two portions transmit the same signal and are electrically connected via the first connecting line 410 and the second connecting line 420.

[0063] For example, the embodiments of the present disclosure are not limited to all first connection lines being in the same layer and all second connection lines being in the same layer. For example, some second connection lines may be in the same layer as the first connection lines, and some second connection lines may be in different layers from the first connection lines.

[0064] like Figure 1As shown, the plurality of second signal lines 300 include a portion of the second signal lines 300 extending through the second region 102. Each of the portion of the second signal lines 300 includes a third sub-signal line 310 and a fourth sub-signal line 320 located on either side of the second region 102. The third sub-signal line 310 and the fourth sub-signal line 320 are electrically connected via a third connecting line 430 extending along a first direction and a fourth connecting line 440 extending along a second direction. Furthermore, the portion of the second signal lines 300 is electrically connected to the plurality of third connecting lines 430 and the plurality of fourth connecting lines 440. For example, the third connecting line 430 and the fourth connecting line 440 are electrically connected. The second signal line 300 extending through the second region 102 is disconnected at a location in the second region 102, forming two portions, namely, the third sub-signal line 310 and the fourth sub-signal line 320. These two portions transmit the same signal and are electrically connected via the fourth connecting line 440 and the third connecting line 430.

[0065] For example, the extension line of the aforementioned “portion of the first signal line 200 extending through the second region 102” may refer to the portion of the first signal line 200 extending from the end point close to the second region 102 toward the second region 102. For example, the extension line of the aforementioned “portion of the second signal line 300 extending through the second region 102” may refer to the portion of the second signal line 300 extending from the end point close to the second region 102 toward the second region 102.

[0066] For example, the embodiments of the present disclosure are not limited to all third connection lines being in the same layer and all fourth connection lines being in the same layer. For example, some fourth connection lines may be in the same layer as the third connection lines, and some fourth connection lines may be in different layers from the third connection lines.

[0067] For example, Figure 1 As shown, the first signal line 200 whose extension line does not pass through the second area 102 can be a continuous signal line, and the second signal line 300 whose extension line does not pass through the second area 102 can be a continuous signal line.

[0068] like Figure 1 As shown, in a direction perpendicular to the base substrate 100 , at least one second connection line 420 overlaps with at least one third connection line 430 , and on the same side of the second region 102 , at least one first connection line 410 is located on a side of the at least one third connection line 430 away from the second region 101 .

[0069] The display substrate provided by the embodiments of the present disclosure uses first and second connecting lines to connect the first signal lines located on both sides of the second area, while using third and fourth connecting lines to connect the second signal lines located on both sides of the second area. At least one first connecting line is located on a side of at least one third connecting line away from the second area, and the second connecting line overlaps with the third connecting line. This reduces the wiring space around the second area to increase the space of the display area, and can reduce sudden changes in the loading of the first and second signal lines, thereby preventing display unevenness, such as display mura.

[0070] Compared to a general display substrate in which at least one of the first signal line and the second signal line is wound around the boundary of the second area around the periphery of the second area, in the display substrate provided by the embodiment of the present disclosure, the first signal line and the second signal line are both passed through a connecting line extending along the first direction and the second direction, such as using a FIP (Fun-out In Pixel, fan-out line located in the pixel area) connecting line to achieve electrical connection between the two parts located on both sides of the second area, which can save the border size around the second area, such as reducing the frame around the second area, which is beneficial to increasing the area of ​​the display area and thereby improving the display effect.

[0071] For example, Figure 1 As shown, in the first area 101 of the display substrate, the length of the first signal line 200 whose extension line does not pass through the second area 102 is greater than the length of the second signal line 300 whose extension line does not pass through the second area 102 .

[0072] For example, Figure 1 As shown, the ratio of the size of the first signal line 200 whose extension line does not pass through the second area 102 in the first direction to the maximum size of the second area 102 in the first direction is r1, and the ratio of the maximum size of the second signal line 400 whose extension line does not pass through the second area 102 in the second direction to the maximum size of the second area 102 in the second direction is r2, and r1 is greater than r2.

[0073] In some examples, such as Figure 1 As shown, the minimum distance between the fourth connection line 440 closest to the second area 102 and the edge of the second area 102 is smaller than the minimum distance between the first connection line 410 closest to the second area and the edge of the second area 102 .

[0074] The proportion of the size of the second region to the length of the first signal line is smaller than the proportion of the size of the second region to the length of the second signal line. Thus, the length of the third connecting line has a greater impact on the load of the second signal line than the length of the second connecting line. In the display substrate provided in the embodiments of the present disclosure, the fourth connecting line is positioned closer to the edge of the second region than the first connecting line. This can shorten the length of the third connecting line connected to the second signal line whose extension passes through the second region, thereby reducing the difference in load on the second signal line whose extension passes through the second region and the second signal line whose extension does not pass through the second region.

[0075] For example, Figure 1 As shown, on the same side of the second area 102, the distance between a fourth connecting line 440 closest to the second area 102 and a second signal line 300 closest to the second area 102 and whose extension line does not pass through the second area 102 is D1, and the distance between a first connecting line 410 closest to the second area 102 and a first signal line 200 closest to the second area 102 and whose extension line does not pass through the second area 102 is D2, and D1 is smaller than D2.

[0076] In some examples, such as Figure 1 As shown, the first signal line 200 includes a data line, and the second signal line 300 includes at least a light emitting control signal line.

[0077] Figure 2 is an equivalent circuit diagram of a pixel circuit according to an embodiment of the present disclosure, Figures 3A to 3H Including schematic diagrams of different film layers in pixel circuits, Figure 3I for Figures 3A to 3F Schematic diagram of film layer stacking.

[0078] In some examples, such as Figure 2 As shown, the display substrate further includes a plurality of sub-pixels, and at least some of the sub-pixels include a light-emitting element 120 and a pixel circuit 110 electrically connected to the light-emitting element 120 .

[0079] For example, Figures 2 to 3I As shown, the pixel circuit includes multiple transistors and at least one capacitor. For example, the pixel circuit includes a second reset transistor T1, a threshold compensation transistor T2, a drive transistor T3, a data writing transistor T4, a second light emission control transistor T5, a first light emission control transistor T6, a first reset transistor T7, a third reset transistor T8, and a storage capacitor C.

[0080] For example, Figures 2 to 3IAs shown, the display substrate further includes reset power signal lines 561 , 551 and 554 , scan signal lines 552 , 531 and 523 , a power signal line 581 , reset control signal lines 522 , 532 and 553 , a light emitting control signal line 521 and a data line 200 .

[0081] For example, Figures 2 to 3IAs shown, the first electrode of the threshold compensation transistor T2 is electrically connected to the first electrode of the driving transistor T3, the second electrode of the threshold compensation transistor T2 is electrically connected to the gate of the driving transistor T3, and the gate of the threshold compensation transistor T2 is electrically connected to the scanning signal lines 531 and 552 to receive the compensation control signal; the first electrode of the first reset transistor T7 is electrically connected to the reset power signal line 561 to receive the reset signal Vinit2, the second electrode of the first reset transistor T7 is electrically connected to the first electrode of the light emitting element (i.e., the N4 node), and the gate of the first reset transistor T7 is electrically connected to the reset control signal line 522 to receive the reset control signal R eset(N+1); a first electrode of the third reset transistor T8 is electrically connected to the reset power supply signal line 551 to receive the reset signal Vref, a second electrode of the third reset transistor T8 is electrically connected to the second electrode of the driving transistor T3, and a gate of the third reset transistor T8 is electrically connected to the reset control signal line 522; a first electrode of the data writing transistor T4 is electrically connected to the second electrode of the driving transistor T3, a second electrode of the data writing transistor T4 is electrically connected to the data line 200 (first signal line 200) to receive the data signal Data, and a gate of the data writing transistor T4 is electrically connected to the scanning signal line 523 to receive the scanning signal. The first electrode of the storage capacitor C is electrically connected to the power signal line 581, and the second electrode of the storage capacitor C is electrically connected to the gate of the driving transistor T3; the first electrode of the second reset transistor T1 is electrically connected to the reset power signal line 554 to receive the reset signal Vinit1, the second electrode of the second reset transistor T1 is electrically connected to the gate of the driving transistor T3, and the gate of the second reset transistor T1 is electrically connected to the reset control signal lines 553 and 532 to receive the reset control signal Reset(N); the gate of the first light-emitting control transistor T6 is electrically connected to the light-emitting control signal line 521 to receive the light-emitting control signal EM. A first electrode of the first emission control transistor T6 is electrically connected to the first electrode of the driving transistor T3, and a second electrode of the first emission control transistor T6 is electrically connected to the first electrode of the light-emitting element 120. A first electrode of the second emission control transistor T5 is electrically connected to the power signal line 581 to receive the first power signal VDD, a second electrode of the second emission control transistor T5 is electrically connected to the second electrode of the driving transistor T3, and a gate of the second emission control transistor T5 is electrically connected to the emission control signal line 521 to receive the emission control signal EM. The second electrode of the light-emitting element 120 is electrically connected to the voltage terminal VSS (later referred to as the third signal line 600). The power signal line is a signal line that outputs the voltage signal VDD and can be connected to a voltage source to output a constant voltage signal, such as a positive voltage signal.

[0082] It should be noted that, in the embodiment of the present disclosure, each pixel circuit can Figure 2In addition to the 8T1C structure (i.e., eight transistors and one capacitor) shown, it can also be a structure including other numbers of transistors, such as a 7T1C structure, a 7T2C structure, a 6T1C structure, a 6T2C structure, or a 9T2C structure, which is not limited in the embodiments of the present disclosure.

[0083] Figure 3A 5. The first active layer pattern 510 is shown. Figure 3A As shown, the first active layer pattern 510 can be used to form the active layers of the aforementioned drive transistor T3, data write transistor T4, second emission control transistor T5, first emission control transistor T6, first reset transistor T7, and third reset transistor T8, thereby forming the channel regions of the aforementioned transistors. The first active layer pattern 510 includes the active region pattern (channel region) and doped region pattern (source and drain region) of the aforementioned transistors in each sub-pixel, and the active region pattern and doped region pattern of the aforementioned transistors in the same pixel circuit are integrally arranged.

[0084] For example, the first active layer pattern 510 may include an integrally formed low-temperature polysilicon layer, and the source region and the drain region may be conductively doped to achieve electrical connection between the structures. For example, the source region and the drain region may be regions doped with p-type impurities.

[0085] Figure 3B FIG. 5 shows a first conductive layer pattern 520 located on a side of the first active layer pattern 510 away from the substrate. Figure 3B As shown, the first conductive layer pattern 520 includes a reset control signal line 522, a scan signal line 523, a first electrode 524 of a capacitor, and a light-emitting control signal line 521. For example, the first conductive layer pattern 520 may include gates of a driving transistor T3, a data writing transistor T4, a second light-emitting control transistor T5, a first light-emitting control transistor T6, a first reset transistor T7, and a third reset transistor T8.

[0086] It should be noted that Figure 3A The dotted rectangular boxes in the figure show the overlapping parts of the first active layer pattern 510 and the first conductive layer pattern 520, namely the channel regions. As the channel regions of each transistor, the active semiconductor layers on both sides of each channel region are conductively connected through processes such as ion doping to serve as the first and second electrodes of each transistor. The source and drain of the transistor can be symmetrical in structure, so the source and drain can be indistinguishable in physical structure. In the embodiments of the present disclosure, in order to distinguish the transistors, except for the gate as the control electrode, one of the electrodes is directly described as the first electrode and the other electrode is the second electrode, so the first and second electrodes of all or part of the transistors in the embodiments of the present disclosure can be interchangeable as needed.

[0087] For example, Figure 3B and Figure 3I As shown, the gate of the data write transistor T4 may be the portion where the scan signal line 523 overlaps with the first active layer pattern 510; the gate of the first emission control transistor T6 may be the first portion where the emission control signal line 521 overlaps with the first active layer pattern 510; and the gate of the second emission control transistor T5 may be the second portion where the emission control signal line 521 overlaps with the first active layer pattern 510. The gate of the third reset transistor T8 may be the first portion where the reset control signal line 522 overlaps with the first active layer pattern 510; and the gate of the first reset transistor T7 may be the second portion where the reset control signal line 522 overlaps with the first active layer pattern 510.

[0088] Figure 3C FIG. 5 shows a second conductive layer pattern 530 on a side of the first conductive layer pattern 520 away from the substrate. Figure 3C As shown, the second conductive layer pattern 530 includes a scan signal line 531 , a second electrode 533 of a capacitor C, and a reset control signal line 532 .

[0089] Figure 3D FIG. 5 shows a second active layer pattern 540 on a side of the second conductive layer pattern 530 away from the substrate. Figure 3D As shown, the second active layer pattern 540 includes the channel regions of the second reset transistor T1 and the threshold compensation transistor T2. For example, when the active layers of the second reset transistor T1 and the threshold compensation transistor T2 are made of oxide semiconductor, since oxide semiconductor transistors have good hysteresis characteristics and low leakage current, oxide semiconductor transistors can be used to replace the low-temperature polysilicon material in the transistors to form a low-temperature polysilicon-oxide (LTPO) pixel circuit, achieving low leakage and improving the stability of the transistor gate voltage.

[0090] For example, Figure 3C 、 3D and Figure 3I As shown, the gate of the second reset transistor T1 may be the portion where the reset control signal line 532 overlaps with the second active layer pattern 540 , and the gate of the threshold compensation transistor T2 may be the portion where the scan signal line 531 overlaps with the second active layer pattern 540 .

[0091] Figure 3E FIG. 5 shows a third conductive layer 550 on a side of the second active layer pattern 540 away from the substrate. Figure 3E As shown, the third conductive layer 550 includes a reset power signal line 554 , a reset control signal line 553 , a scan signal line 552 and a reset power signal line 551 .

[0092] For example, Figures 3C to 3F as well as Figure 3I As shown, the reset control signal line 553 overlaps with the channel region of the second reset transistor T1, and the second reset transistor T1 includes a top gate and a bottom gate located on both sides of the active layer; the scanning signal line 552 overlaps with the channel region of the threshold compensation transistor T2, and the threshold compensation transistor T2 includes a top gate and a bottom gate located on both sides of the active layer.

[0093] For example, the second reset transistor T1 and the threshold compensation transistor T2 may be N-type transistors, and the driving transistor T3, the data writing transistor T4, the second emission control transistor T5, the first emission control transistor T6, the first reset transistor T7, and the third reset transistor T8 may be P-type transistors.

[0094] Figure 3F FIG. 5 shows a fourth conductive layer 560 located on a side of the third conductive layer 550 away from the substrate. Figure 3F As shown, the fourth conductive layer 560 includes a reset power signal line 561 , a connecting portion 568 , a connecting portion 569 , a connecting portion 563 , a connecting portion 567 , a connecting portion 562 , a connecting portion 564 , a connecting portion 565 , and a connecting portion 566 .

[0095] For example, Figures 2 to 3I As shown, the two ends of the connection portion 568 are connected to the reset power signal line 551, and the middle is connected to the first electrode of the third reset transistor T8; the connection portion 569 is connected to the first signal line 200 and the second electrode of the data writing transistor T4; the connection portion 563 is used to electrically connect the first electrode of the data writing transistor T4 and the second electrode of the third reset transistor T8 to lead the reset signal Vref to the N2 node; the connection portion 567 is used to electrically connect the first electrode of the driving transistor T3 and the first electrode of the threshold compensation transistor T2; the middle of the connection portion 562 is connected to the power signal line 581, connected The two ends of the portion 562 are connected to the second electrode 533 of the capacitor, which, on the one hand, electrically connects the adjacent second electrode 533 of the capacitor C, and on the other hand, loads the power supply voltage to the second electrode 533 of the capacitor C; one end of the connecting portion 564 is connected to the second electrode 533 of the capacitor C, and the other end of the connecting portion 564 is connected to the first electrode of the second light-emitting control transistor T5; the connecting portion 565 is used to electrically connect the first electrode of the light-emitting element and the second electrode of the first light-emitting control transistor T6; the connecting portion 566 is used to electrically connect the reset power signal line 554 and the first electrode of the second reset transistor T1.

[0096] Figure 3G FIG. 5 shows a fifth conductive layer 570 located on a side of the fourth conductive layer 560 away from the substrate. Figure 3GAs shown, the fifth conductive layer 570 includes a connecting portion 573, a connecting portion 575, a power signal line 572, a connecting portion 574, a second connecting line 420, and a sixth connecting line 460. For example, the fifth conductive layer 570 further includes a fourth connecting line.

[0097] For example, Figures 2 to 3G As shown, the connection portion 573 is electrically connected to the first signal line 200. For example, the first signal line 200 is electrically connected to the second connection line 420 through the connection portion 573 to transmit the first signal to the second connection line 420. For example, a connection block can be added between the connection portion 573 and the second connection line 420 to achieve the electrical connection between the first signal line 200 and the second connection line 420. The connection portion 575 is a reserved pad that can maintain an electrical connection with the first connection line through a via. At the location where the first and second connection lines need to be electrically connected, a connection block is added between the second connection line 420 and the connection portion 575 so that the first connection line can be electrically connected to the second connection line 420 through the reserved pad. Similarly, the third connection line can be electrically connected to the fourth connection line through the reserved pad. For example, the connection portion 574 is electrically connected to the connection portion 565 to achieve the electrical connection between the second electrode of the first light-emitting control transistor T6 and the first electrode of the light-emitting element. For example, the power signal line 572 is electrically connected to the power signal line 581.

[0098] Figure 3H The sixth conductive layer 580 is shown located on the side of the fifth conductive layer 570 away from the substrate. Figure 3H As shown, the sixth conductive layer 580 includes the first signal line 200, the power signal line 581, the fifth connection line 450, the connection portion 584, and the connection portion 585. For example, the sixth conductive layer 580 further includes a first connection line and a third connection line.

[0099] For example, the connection portion 584 and the connection portion 585 are electrically connected to first electrodes of different light-emitting elements.

[0100] For example, Figure 3G and Figure 3H As shown, the first signal line 200 includes a transfer pad 290, and the first signal line 200 is connected to the connecting portion 573 through the transfer pad 290 to be electrically connected to the second connecting line. For example, the fifth connecting line, the first connecting line, and the third connecting line all include a transfer pad 459, and each connecting line is electrically connected to the connecting portion 575 through a corresponding transfer pad 459.

[0101] For example, Figures 1 to 3H As shown, the second signal line 300 may be located in the first conductive layer pattern 520. For example, the second signal line 300 may include at least one of a light emitting control signal line 521 and a reset control signal line 522.

[0102] For example, Figures 1 to 3H As shown, the plurality of second signal lines 300 are located between the plurality of first signal lines 200 and the base substrate 100 , and the fourth connection lines 440 are located between the plurality of first signal lines 200 and the plurality of second signal lines 300 .

[0103] For example, Figure 1 As shown, on the same side of the second area 102, all first connecting lines 410 are located on the side of the third connecting lines 430 away from the second area 102. By arranging all first connecting lines to be located on the side of the third connecting lines away from the second area, it is helpful to minimize the length of the third connecting lines connected to all second signal lines extended through the second area, thereby reducing the load difference between the second signal lines extended through the second area and the second signal lines not extended through the second area.

[0104] Of course, the embodiments of the present disclosure are not limited thereto, and some first connection lines and some third connection lines may be alternately arranged, which is beneficial for reducing the load difference between the first signal line extending through the second area and the first signal line extending without passing through the second area.

[0105] For example, Figure 1 As shown, some of the second connection lines 420 and the fourth connection lines 440 are located on the same layer. Among the second connection lines 420 and the fourth connection lines 440 arranged on the same layer, at least one second connection line 420 and the fourth connection line 440 are located on the same straight line and are spaced apart. For example, in a direction perpendicular to the base substrate 100, the second connection line 420 and the fourth connection line 440 that are located on the same straight line overlap with the third connection line 430.

[0106] For example, Figure 1 As shown, on the same side of the second area 102, at least one first signal line 200 whose extension line passes through the second area 102 is located between at least one third connecting line 430 and the second area 102. For example, on the same side of the second area 102, at least one first signal line 200 whose extension line does not pass through the second area 102 is located between at least one third connecting line 430 and the second area 102. For example, at least one third connecting line 430 is located between at least one first signal line 200 whose extension line does not pass through the second area 102 and at least one first signal line 200 whose extension line passes through the second area 102.

[0107] In some examples, such as Figure 1 As shown, on the same side of the second area 102 , at least one first signal line 200 of the plurality of first signal lines 200 whose extension line does not pass through the second area 102 is located on a side of the first connecting line 410 close to the second area 102 .

[0108] For example, Figure 1As shown, at least some of the first connecting lines 410 disposed on the same side of the second region 102 are arranged at equal intervals. For example, at least some of the fourth connecting lines 440 disposed on the same side of the second region 102 are arranged at equal intervals. By arranging the first connecting lines at equal intervals, it is helpful to reduce large sudden load changes on the first signal lines connected to the first connecting lines; and by arranging the fourth connecting lines at equal intervals, it is helpful to reduce large sudden load changes on the second signal lines connected to the fourth connecting lines.

[0109] In some examples, such as Figure 1 As shown, the ratio of the distance between the closest first connection line 410 and the closest third connection line 430 to the distance between two adjacent third connection lines 430 is 0.8 to 1.2. For example, the ratio of the distance between the closest first connection line 410 and the closest third connection line 430 to the distance between two adjacent third connection lines 430 is 0.9 to 1.1. For example, the distance between the closest first connection line 410 and the closest third connection line 430 is equal to the distance between two adjacent third connection lines 430.

[0110] By setting the distance between the first connecting line closest to the second area and the third connecting line closer, the length of the second connecting line connected to the first connecting line can be shortened, thereby reducing the difference in load between the first signal line connected to the first connecting line and the load of the first signal line closest to the second area and whose extension line does not pass through the second area, which is beneficial to avoiding the occurrence of mura phenomenon on the display substrate during display.

[0111] In some examples, such as Figure 1 As shown, in the first region 101 , at least a portion of the first connection line 410 and at least a portion of the third connection line 430 are located in the same layer, and at least a portion of the second connection line 420 and at least a portion of the fourth connection line 440 are located in the same layer.

[0112] For example, the orthographic projection of each first connecting line 410 on the straight line extending along the first direction overlaps with the orthographic projection of each third connecting line 430 on the straight line extending along the first direction, and the orthographic projection of at least one second connecting line 420 on the straight line extending along the second direction does not overlap with the orthographic projection of at least one fourth connecting line 440 on the straight line.

[0113] In the embodiment of the present disclosure, the first connecting line and the third connecting line are arranged along the second direction to prevent the first connecting line from interfering with the third connecting line; since part of the second connecting line and the fourth connecting line are spaced apart in the second direction, part of the second connecting line can be inserted into the third connecting line so that this part of the second connecting line is electrically connected to the first signal line located on the side of the third connecting line close to the second area, and the length of the second connecting line can be minimized. For example, the parasitic capacitance on the second connecting line is the load difference between the first signal line (which can be called the normal signal line) and the normal signal line that are closest to the extension line and do not pass through the second area, thereby reducing the load difference between the first signal line electrically connected to the second connecting line and the normal signal line.

[0114] In some examples, such as Figure 1 As shown, among the plurality of second signal lines 300 whose extensions do not pass through the second region 102, a second signal line 300 closest to the second region 102 is located between a fourth connecting line 440 closest to the second region 102 and an adjacent fourth connecting line 440. By arranging the fourth connecting line closest to the second region closer to the second signal line closest to the second region and whose extensions do not pass through the second region, the length of the third connecting line connected to the fourth connecting line closest to the second region can be reduced, thereby reducing the difference in load between the second signal line electrically connected to the fourth connecting line and the second signal line whose extensions do not pass through the second region, thereby facilitating reduction of display mura.

[0115] In some examples, such as Figure 1 As shown, on the same side of the second region 102, a first group of connection lines 4201 among the plurality of second connection lines 420 is located on a side of the at least one fourth connection line 440 close to the second region 102, and a second group of connection lines 4202 among the plurality of second connection lines 420 is located on a side of the at least one fourth connection line 440 away from the second region 102. For example, the number of second connection lines 420 included in the first group of connection lines 4201 can be less than the number of second connection lines 420 included in the second group of connection lines 4202. For example, a plurality of fourth connection lines 440 are disposed between the first group of connection lines 4201 and the second group of connection lines 4202.

[0116] In the display device provided by the embodiment of the present disclosure, by configuring the second connecting line to include two groups of connecting lines located on both sides of the fourth connecting line, interference between the fourth connecting line and the second connecting line due to being arranged on the same layer can be prevented, while also preventing the first signal line and the second signal line from generating display mura due to sudden load changes.

[0117] In some examples, such as Figure 1As shown, along a direction perpendicular to the base substrate 100 , the first group of connection lines 4201 overlap with the third connection lines 430 , and the second group of connection lines 4202 do not overlap with the third connection lines 430 .

[0118] For example, Figure 1 As shown, at least one third connection line 430 does not overlap with the second connection line 420 in a direction perpendicular to the base substrate 100 . For example, each connection line 420 in the first group of connection lines 4201 overlaps with at least one third connection line 430 .

[0119] In some examples, such as Figure 1 As shown, on the same side of the second region 102, at least one first signal line 200 connected to the second group of connection lines 4202 overlaps with each fourth connection line 440 in a direction perpendicular to the base substrate 100. For example, on the same side of the second region 102, each first signal line 200 connected to the second group of connection lines 4202 overlaps with all fourth connection lines 440 in a direction perpendicular to the base substrate 100.

[0120] Since the first signal line connected to the second group of connection lines overlaps with the fourth connection line, in order to avoid interference between the positions of the second connection line and the fourth connection line in the second group of connection lines, in the display substrate provided by the embodiment of the present disclosure, the second group of connection lines is arranged on a side of the fourth connection line away from the second area.

[0121] For example, Figure 1 As shown, the second connection lines 420 in the first group of connection lines 4201 are arranged at equal intervals on the same side of a centerline extending along the second direction of the second area 102. For example, the second connection lines 420 in the second group of connection lines 4202 are arranged at equal intervals on the same side of a centerline extending along the second direction of the second area 102. For example, the distance between two adjacent second connection lines 420 in the first group of connection lines 4201 can be equal to the distance between two adjacent second connection lines 420 in the second group of connection lines 4202.

[0122] For example, the distance between a second connection line 420 closest to the fourth connection line 440 in the second group of connection lines 4202 and the fourth connection line 440 may be equal to the distance between two adjacent second connection lines 420 in the second group of connection lines 4202 .

[0123] In some examples, such as Figure 1As shown, the distance between a second connecting line 420 in the first group of connecting lines 4201 that is closest to the second group of connecting lines 4202 and a second connecting line 420 in the second group of connecting lines 4202 that is closest to the first group of connecting lines 4201 is a first distance S1, and the distance between two adjacent second connecting lines 420 in the second group of connecting lines 4202 is a second distance S2. The ratio of the first distance S1 to the second distance S2 is greater than 2. For example, the ratio of the first distance S1 to the second distance S2 is greater than 3. For example, the ratio of the first distance S1 to the second distance S2 is greater than 4. For example, the ratio of the first distance S1 to the second distance S2 is greater than 5. For example, the ratio of the first distance S1 to the second distance S2 is greater than 6. For example, the ratio of the first distance S1 to the second distance S2 is greater than 7. For example, the ratio of the first distance S1 to the second distance S2 is greater than 8. For example, the ratio of the first distance S1 to the second distance S2 is greater than 9. For example, the ratio of the first distance S1 to the second distance S2 is greater than 10.

[0124] Figure 4 A schematic diagram of a partial plan structure is provided for another example according to an embodiment of the present disclosure.

[0125] Figure 5 for Figure 4 Schematic diagram of part of the film layer in area E1, Figure 6 and Figure 7 for Figure 5 Schematic diagram of two conductive layers at the positions shown, Figure 8 for Figure 4 Schematic diagram of part of the film layer in area E2, Figures 9 and 10 for Figure 8 Schematic diagram of two conductive layers at the indicated locations. Figures 5 to 10 The film structure in the area shown can be Figure 1 The film layer structures in corresponding regions of the display substrate shown have the same features.

[0126] For example, Figures 4 to 10 As shown, the first signal line 200 includes first signal lines 201-1 and 201-2 whose extension lines pass through the second area 102, and first signal lines 202-1 and 202-2 whose extension lines do not pass through the second area 102. The first signal line 201-1 is the first signal line whose extension line passes through the second area 102 that is closest to the extension line that does not pass through the second area 102, and the first signal line 202-1 is the first signal line whose extension line passes through the second area 102 that is closest to the extension line that does not pass through the second area 102.

[0127] For example, Figures 4 to 10As shown, the second connection line 420 includes a second connection line 420-2 electrically connected to the first signal line 201-2 and a second connection line 420-1 electrically connected to the first signal line 201-1. For example, the second connection line 420-1 is electrically connected to the first signal line 201-1 through a connection portion 0421, and the second connection line 420-2 is electrically connected to the first signal line 201-2 through a connection portion 0422.

[0128] For example, Figures 4 to 10 As shown, the first connection line 410 includes a first connection line 410-1 connected to the second connection line 420-1 and a first connection line 410-2 electrically connected to the second connection line 420-2. For example, the second connection line 420-1 is electrically connected to the first connection line 410-1 through a connection portion 0423, and the second connection line 420-2 is electrically connected to the first connection line 410-2 through a connection portion 0425.

[0129] For example, Figures 4 to 10 As shown, the first signal line 210 (i.e., the first signal line 201-1) located on one side of the second area 102 transmits the first signal through the second connection line 420-1 and the first connection line 410-1 to the first signal line 220 located on the other side of the second area 102; the first signal line 201-2 located on one side of the second area 102 transmits the first signal through the second connection line 420-2 and the first connection line 410-2 to the first signal line 220 located on the other side of the second area 102. Figure 5 and Figure 8 The black dotted arrow in illustrative diagram schematically shows the transmission path of the first signal.

[0130] In some examples, such as Figure 9 and Figure 10 As shown, the display substrate further includes a plurality of fifth connection lines 450 extending along the first direction and a plurality of sixth connection lines 460 extending along the second direction.

[0131] In some examples, such as Figure 9 and Figure 10 As shown, the multiple fifth connection lines 450 include at least some fifth connection lines 450 that are located in the same layer as the first connection line 410, and the fifth connection lines 450 that are located in the same straight line as the first connection line 410 among the at least some fifth connection lines 450 are spaced apart from the first connection line 410, such as a space 0426 is set between the first connection line 410-1 and the fifth connection line 450.

[0132] For example, two connection lines that are located on the same straight line and are spaced apart from each other may be the same connection line divided into two different connection lines.

[0133] In some examples, such as Figure 9 and Figure 10As shown, the multiple sixth connection lines 460 include at least some of the sixth connection lines 460 that are located in the same layer as the second connection line 420, and the sixth connection lines 460 that are located in the same straight line as the second connection line 420 among the above-mentioned at least some of the sixth connection lines 460 are arranged at intervals with the second connection line 420, such as a gap 0424 is set between the second connection line 420-1 and the sixth connection line 460.

[0134] In some examples, such as Figure 1 As shown, the plurality of fifth connection lines 450 include at least some fifth connection lines 450 located in the same layer as the third connection lines 430 , and the fifth connection lines 450 located in the same straight line as the third connection lines 430 are spaced apart from the third connection lines 430 .

[0135] In some examples, such as Figure 1 As shown, the plurality of sixth connection lines 460 include at least some sixth connection lines 460 located in the same layer as the fourth connection lines 440 , and the sixth connection lines 460 located in the same straight line as the fourth connection lines 440 are spaced apart from the fourth connection lines 440 .

[0136] In some examples, such as Figure 1 As shown, the display substrate further includes a peripheral area 103, which surrounds a display area, such as the first area 101. For example, the peripheral area 103 is an area not used for display, and the display area is an area used for display, such as the first area 101.

[0137] In some examples, such as Figure 1 、 Figure 17 as well as Figure 18 As shown, the display substrate further includes a third signal line 600 located in the peripheral area 103. At least one of the fifth connecting line 450 and the sixth connecting line 460 is electrically connected to the third signal line 600. For example, the third signal line 600 can be a ring-shaped signal line surrounding the display area. For example, the third signal line 600 is configured to transmit a VSS signal. For example, the third signal line 600 is configured to be electrically connected to a second electrode, such as a cathode, of the light-emitting element.

[0138] For example, the fifth connection line 450 and the sixth connection line 460 are both electrically connected to the third signal line 600 .

[0139] The embodiment of the present disclosure provides multiple fifth connection lines and multiple sixth connection lines, which helps improve the uniformity of connection line positions and reduce display mura. In addition, by electrically connecting the fifth and sixth connection lines to the third signal line, the load on the third signal line is reduced.

[0140] In some examples, such as Figures 5 to 10As shown, at least one first connection line 410 and at least one third connection line 430 are both located on the same layer as the plurality of first signal lines 200. For example, each first connection line 410 is disposed on the same layer as the first signal line 200. For example, each third connection line 430 is disposed on the same layer as the first signal line 200.

[0141] In some examples, such as Figures 5 to 10 As shown, at least one of the positions where the fifth connection line 450 is spaced from the first connection line 410 and the positions where the fifth connection line 450 is spaced from the third connection line 430 overlaps with the film layer where the fourth connection line 440 is located, such as overlapping with the structure in the fifth conductive layer 570. For example, at least one of the positions where the sixth connection line 460 is spaced from the second connection line 420 and the positions where the sixth connection line 460 is spaced from the fourth connection line 440 overlaps with the film layer where the first connection line 410 is located, such as overlapping with the structure in the sixth conductive layer 580.

[0142] For example, Figures 5 to 10 As shown, the interval 0424 between the second connection line 420 and the sixth connection line 460 overlaps with the first signal line 200. For example, the interval 0426 between the first connection line 410 and the fifth connection line 450 overlaps with the second connection line 420.

[0143] In the display substrate provided by the embodiment of the present disclosure, by shielding the interval between two connection lines located on the same straight line by another layer of connection lines or another layer of signal lines, it is beneficial to further reduce display mura, such as screen-off mura.

[0144] In some examples, such as Figure 8 As shown, at least one first connection line 410 is provided with two first signal lines 200 adjacent to the first connection line 410 on both sides, and the ratio of the minimum distance between the two first signal lines 200 and the first connection line 410 is 0.9 to 1.1. For example, the minimum distance between the two first signal lines 200 and the first connection line 410 is the same.

[0145] For example, Figure 8 As shown, the plurality of first signal lines 200 can be divided into a plurality of first signal line pairs 200 , each first signal line pair 200 is located between two adjacent sub-pixels, such as two light-emitting elements, and a first connecting line 410 is provided between at least one first signal line pair 200 .

[0146] In some examples, such as Figure 1As shown, at least one third connection line 430 is provided with two first signal lines 200 adjacent to the third connection line 430 on both sides, and the ratio of the minimum distance between the two first signal lines 200 and the third connection line 430 is 0.9 to 1.1. For example, the minimum distance between the two first signal lines 200 and the third connection line 430 is the same.

[0147] For example, a third connection line 430 is disposed between at least one first signal line pair 200 .

[0148] For example, Figure 10 As shown, at least one fifth connection line 450 is provided with two first signal lines 200 adjacent to the fifth connection line 450 on both sides, and the ratio of the minimum distance between the two first signal lines 200 and the fifth connection line 450 is 0.9 to 1.1. For example, the minimum distance between the two first signal lines 200 and the fifth connection line 450 is the same.

[0149] In the display substrate provided by the embodiment of the present disclosure, the first connecting line and the first signal line are arranged in a 2in1 manner, the third connecting line and the first signal line are arranged in a 2in1 manner, and the fifth connecting line and the first signal line are arranged in a 2in1 manner.

[0150] Of course, the embodiments of the present disclosure are not limited thereto, and two first connection lines may be further provided between at least one first signal line pair, such as in a 1-in-1 configuration.

[0151] Figure 11 for Figure 4 Schematic diagram of part of the film layer in area E3, Figure 12 for Figure 4 Schematic diagram of part of the film layer in area E4 is shown. Figure 13 To include Figure 4 Schematic diagram of the local film layer in area E1, Figure 14 and Figure 15 for Figure 13 Schematic diagram of two conductive layers at the indicated locations.

[0152] In some examples, such as Figure 4 and Figure 11As shown, a first connection line 410 connected to a second connection line 420 in the first group of connection lines 4201 that is closest to the second group of connection lines 4202 includes two portions 411 and 412 located on either side of the second connection line 420 in the first direction. For example, portion 411 of the first connection line 410 is used to transmit the first signal to the first signal line 200 located on the other side of the second region 102, while portion 412 of the first connection line 410 is used to balance the difference between the parasitic capacitance of the first connection line 410 and the parasitic capacitance of the second connection line 420 in the second group of connection lines 4202 that is closest to the first group of connection lines 4201. For example, portion 412 can serve as a load compensation portion. For example, portion 411 of the first connection line 410 can be considered a portion extending in the forward direction, while portion 412 can be considered a portion extending in the reverse direction.

[0153] When the distance between two second connecting lines that are respectively located in the first group of connecting lines and the second group of connecting lines and are closest to each other is greater than the distance between two adjacent second connecting lines in the first group of connecting lines (or the second group of connecting lines), by extending the length of a first connecting line connected to a second connecting line in the first group of connecting lines that is closest to the second group of connecting lines, for example, the first connecting line includes a portion extending in a forward direction for transmitting a first signal line and another portion extending in a reverse direction relative to the forward extending portion, the load mutation of the second connecting lines in the two groups of connecting lines can be reduced, thereby reducing display mura and improving display quality.

[0154] In some examples, such as Figure 4 、 Figure 11 and Figure 12 As shown, the first connection line 410 connected to the second connection line 420-11 in the first group of connection lines 4201 that is closest to the second group of connection lines 4202 extends to the position of the second connection line 420-12 in the second group of connection lines 4202 that is closest to the first group of connection lines 4201. For example, the reversely extending portion 412 of the first connection line 410 connected to the second connection line 420-11 extends to the position of the second connection line 420-12.

[0155] The embodiment of the present disclosure helps to minimize the load difference between two second connection lines that are respectively located in the first group of connection lines and the second group of connection lines and are closest to each other by extending the reverse-extending portion of the first connection line connected to a second connection line that is closest to the second group of connection lines in the first group of connection lines to the position of a second connection line that is closest to the first group of connection lines, thereby preventing a large load jump caused by a large interval between the two groups of connection lines.

[0156] For example, Figure 4 、 Figure 11 and Figure 12As shown, the interval between the reverse extension portion 412 of the first connection line 410 connected to the second connection line 420 - 11 and the fifth connection line 450 overlaps with the second connection line 420 - 12 .

[0157] In some examples, such as Figure 4 、 Figures 11 to 15 As shown, each of the N first connection lines 410 that are respectively connected to the N second connection lines 420 in the first group of connection lines 4201 that are closest to the second group of connection lines 4202 includes two parts 411 and 412 that are respectively located on both sides of the second connection line 420 connected thereto in the first direction, and along the direction approaching the second area 102, the lengths of the two parts 411 and 412 that are located on both sides of the second connection line 420 connected thereto in the N first connection lines 410 gradually decrease, N is a positive integer greater than or equal to 1, and the number of the second connection lines 420 in the first group of connection lines 4101 located on one side of the center of the second area 102 is greater than or equal to N.

[0158] For example, Figure 4 、 Figures 13 to 15 As shown, the second connection line 420 closest to the second group of connection lines 4202 in the first group of connection lines 4201 includes a second connection line 420-1, a second connection line 420-2 and a second connection line 420-3, and the first connection line 410 includes a first connection line 410-1 connected to the second connection line 420-1, a first connection line 410-2 connected to the second connection line 420-2 and a first connection line 410-3 connected to the second connection line 420-3.

[0159] For example, Figure 4 、 Figures 13 to 15 As shown, along the direction of the second group of connection lines 4202 pointing to the first group of connection lines 4201, the second connection line 420-3, the second connection line 420-2 and the second connection line 420-1 are arranged in sequence, such as the second connection line 420-3 is closer to the second group of connection lines 4202 than the second connection line 420-2.

[0160] For example, Figure 4 、 Figures 13 to 15 As shown, the lengths of portion 412-3 of first connection line 410-3, portion 412-2 of first connection line 410-2, and portion 412-1 of first connection line 410-1 gradually decrease, such that the length of portion 412-3 of first connection line 410-3 is greater than the length of portion 412-2 of first connection line 410-2.

[0161] In the display substrate provided by the embodiments of the present disclosure, the length of the portion of the first connecting line extended in the opposite direction is adjusted based on the distance relationship between each second connecting line in the first group of connecting lines and the second connecting lines in the second group of connecting lines. This is beneficial for reducing the sudden load change between the second connecting lines in the second group of connecting lines and the second connecting lines in the first group of connecting lines, while minimizing the load difference between adjacent second connecting lines in the first group of connecting lines.

[0162] For example, Figure 4 、 Figures 13 to 15 As shown, the length difference between the reverse extension parts of any two adjacent first connection lines 410 in the multiple first connection lines 410 connected to at least some of the second connection lines 420 in the first group of connection lines 4201 is within a certain range. For example, the length difference can be the size of 1 to 5 sub-pixels in the first direction, and the length difference can be the size of 2 to 4 sub-pixels in the first direction.

[0163] For example, Figure 4 As shown, the first connection line 410 connected to the second connection line 420 in the first group of connection lines 4201 may include two reverse extension portions 412 and a forward extension portion 411 located between the two reverse extension portions 412. For example, the two reverse extension portions 412 included in each first connection line 410 are equal in length.

[0164] Figure 16 for Figure 1 Schematic diagram of part of the film layer in area E5, Figure 17 for Figure 16 Schematic diagram of part of the film layer in area E6, Figure 18 for Figure 16 Schematic diagram of part of the film layer in area E7.

[0165] In some examples, such as Figure 1 、 Figure 11 、 Figure 12 、 Figures 16 to 18 As shown, the plurality of second group connection lines 4202 include second connection lines 420 located in the first area 101 and second connection lines 420 located in the peripheral area 103. The second connection lines 420 located in the first area 102 are arranged in different layers from the first connection lines 410, and the second connection lines 420 located in the peripheral area 103 are arranged in the same layer as the first connection lines 410.

[0166] For example, Figure 1 、 Figures 16 to 18 As shown, a first connection line 410 is electrically connected to two second connection lines 420. Among the two second connection lines 420, one second connection line 420 located in the first area 101 is arranged in a different layer from the first connection line 410, and one second connection line 420 located in the peripheral area 103 is in the same layer as the first connection line 410 and is integrated.

[0167] In some examples, such as Figure 1 、 Figures 16 to 18 As shown, the second connection line 420 in the peripheral area 103 is provided in the same layer as the first signal line 200. For example, the second sub-signal line 220 in the second region 102 near the peripheral area 103 and the second connection line 420 connected thereto are provided in the same layer and are integrated.

[0168] For example, Figure 17 and Figure 18 The schematic diagram shows that the fifth connection line 450 is electrically connected to the third signal line 600 located in the peripheral area 103. For example, the fifth connection line 450 in the E6 area is directly electrically connected to the third signal line 600, and the fifth connection line 450 in the E7 area is electrically connected to the third signal line 600 through the adapter line 0450 provided on the same layer as the second connection line provided in the first area 101.

[0169] For example, Figure 1 As shown, the third connection line 430 and the fourth connection line 440 are both located in the first area 101 .

[0170] For example, Figure 1 As shown, each second connection line 420 included in the first group of connection lines 4201 and the first connection lines 410 connected to each second connection line 420 in the first group of connection lines 4201 are all located in the first area 101 .

[0171] For example, the display substrate further includes: a plurality of first light-emitting elements, a plurality of first pixel circuits, and a plurality of second pixel circuits located in the first region 101, and a plurality of second light-emitting elements located in the second region 102. The plurality of first pixel circuits are electrically connected to the plurality of first light-emitting elements in a one-to-one correspondence, and the plurality of second pixel circuits are electrically connected to the plurality of second light-emitting elements in a one-to-one correspondence. For example, the second region 102 may be an area for arranging a camera. The second pixel circuit that drives the second light-emitting elements in the second region 102 to emit light is located in the first region 101, which can improve the light transmittance of the second region 102. That is, the light transmittance of the second region 102 is improved by separating the light-emitting elements and the pixel circuits.

[0172] Figure 19 for Figure 4 A schematic diagram of a partial structure of area E8 is shown, Figure 20 for Figure 19 A schematic diagram of a partial structure of region E9 is shown, Figures 21 to 25 for Figure 20 Schematic diagram of the different membrane layers in the indicated locations. Region E9 is a small region within region E8.

[0173] For example, Figures 2 to 4 as well as Figures 19 to 25As shown, the second signal line 300 includes a light-emitting control signal line 521. For example, the light-emitting control signal line 521 adopts unilateral driving.

[0174] For example, Figures 2 to 4 as well as Figures 19 to 25 As shown, the light-emitting control signal line 521 is electrically connected to the fourth connection line 440-11 in the fifth conductive layer 570 through the adapter line 5611, the fourth connection line 440-11 is electrically connected to the third connection line 430-1 in the sixth conductive layer 580 through the connecting portion 575, and the third connection line 430-1 is electrically connected to the fourth connection line 440-1 through the connecting portion 575, thereby electrically connecting the third sub-signal line 310 (light-emitting control signal line 521) located on the left side of the second area 102 (the direction opposite to the Y direction arrow shown in the figure is to the left) to the fourth sub-signal line 320 (light-emitting control signal line 521) located on the right side of the second area 102.

[0175] For example, Figures 2 to 4 as well as Figures 19 to 25 As shown, among the plurality of light-emitting control signal lines 521 whose extended lines do not pass through the second area 102, the light-emitting control signal line 521 closest to the second area 102 is located between the fourth connection line 440-1 closest to the second area 102 and the fourth connection line 440-2 adjacent thereto.

[0176] For example, Figures 2 to 4 as well as Figures 19 to 25 As shown, the second signal line 300 includes a reset control signal line 522. For example, the reset control signal line 522 adopts a single-side drive.

[0177] For example, Figures 2 to 4 as well as Figures 19 to 25 As shown, the reset control signal line 522 is electrically connected to the fourth connection line 440-12 in the fifth conductive layer 570 through the adapter line in the fourth conductive layer 560, the fourth connection line 440-12 is electrically connected to the third connection line 430-2 in the sixth conductive layer 580 through the connecting portion 575, and the third connection line 430-2 is electrically connected to the fourth connection line 440-2 through the connecting portion 575, thereby electrically connecting the third sub-signal line 310 (reset control signal line 522) located on the left side of the second area 102 and the fourth sub-signal line 320 (reset control signal line 522) located on the right side of the second area 102.

[0178] In the display substrate provided by the embodiment of the present disclosure, the process of writing signals to the light-emitting control transistor is less affected by parasitic capacitance, and the signals of the reset transistors T7 and T8 are also less affected by parasitic capacitance. By setting the reset control signal line electrically connecting the reset transistors T7 and T8, and at least one of the light-emitting control signal lines to adopt a connecting line extending along the first direction and a connecting line extending along the second direction to achieve electrical connection between the two parts located on both sides of the second area, it is beneficial to reduce the wiring space around the second area to increase the area of ​​the display area while minimizing the impact on the operating performance of the pixel circuit.

[0179] For example, the scanning signal lines 523 are driven on both sides, so the scanning signal lines 523 located on both sides of the second area can be disconnected.

[0180] For example, Figures 2 to 4 as well as Figures 19 to 25 As shown, the scan signal line 531 electrically connected to the threshold compensation transistor T2 is driven on one side. For example, the scan signal line 531 located on one side of the second region 102 is electrically connected to the scan signal line 531 located on the other side of the second region 102 via the connecting line 525 in the first conductive layer 520 and / or the connecting line in the fourth conductive layer 560.

[0181] In the display substrate provided by the embodiment of the present disclosure, the scanning signal line electrically connected to the threshold compensation transistor T2 does not use a connecting line extending along the first direction and a connecting line extending along the second direction to achieve electrical connection between the two parts located on both sides of the second area. Instead, the electrical connection between the two parts located on both sides of the second area is achieved by winding around the edge of the second area. This can reduce the parasitic capacitance generated on the scanning signal line electrically connected to the threshold compensation transistor T2.

[0182] For example, Figures 2 to 4 as well as Figures 19 to 25 As shown, the reset control signal line 532 electrically connected to the second reset transistor T1 is driven on one side. For example, the reset control signal line 532 located on one side of the second region 102 is electrically connected to the reset control signal line 532 located on the other side of the second region 102 via a connecting line in the fourth conductive layer 560, or the reset control signal line 532 located on one side of the second region 102 is directly routed around the edge of the second region 102 to the other side of the second region 102.

[0183] In the display substrate provided by the embodiment of the present disclosure, the reset control signal line electrically connected to the second reset transistor T1 does not use a connecting line extending along the first direction and a connecting line extending along the second direction to achieve electrical connection between the two parts located on both sides of the second area. Instead, the electrical connection between the two parts located on both sides of the second area is achieved by a winding line around the edge of the second area. This can reduce the parasitic capacitance generated on the reset control signal line electrically connected to the second reset transistor T1.

[0184] In the pixel circuit provided by the embodiments of the present disclosure, the first light-emitting control transistor and the second light-emitting control transistor electrically connected to the light-emitting control signal line, as well as the first reset transistor and the third reset transistor electrically connected to the reset control signal line, are all P-type transistors, and the threshold compensation transistor and the second reset transistor are both N-type transistors. Since the voltage jump of the gate signal of a P-type transistor is less affected than that of an N-type transistor, it is preferred that all or part of the corresponding gate control lines of the P-type transistor adopt a connecting line extending along the first direction and a connecting line extending along the second direction (i.e., a FIP connection method) to achieve electrical connection between the two parts located on both sides of the second area, thereby reducing the non-display area around the second area to achieve a narrow frame; at the same time, the control signal line electrically connected to the gate of the threshold compensation transistor and the second reset transistor, which are N-type transistors, adopts the above-mentioned winding method.

[0185] Of course, the embodiments of the present disclosure are not limited to this. When all transistors in the pixel circuit are low-temperature polysilicon transistors (LTPS), such as when all transistors are P-type transistors, part or all of the gate control signal lines electrically connected to the gates of all P-type transistors can be electrically connected to the two parts located on both sides of the second area using the above-mentioned connecting lines extending along the first direction and the connecting lines extending along the second direction (i.e., the FIP connection method), thereby reducing the area of ​​the non-display area around the second area to achieve a narrow frame.

[0186] Optionally, according to an embodiment of the present disclosure, the display substrate further includes: a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit being electrically connected to the light-emitting element; wherein the pixel circuit includes at least one N-type thin film transistor and at least one P-type thin film transistor; and the second signal line includes a signal line connected to the gate of at least one of the P-type thin film transistors.

[0187] Optionally, according to an embodiment of the present disclosure, the display substrate further includes: a light-emitting element and a pixel circuit located on the base substrate, the pixel circuit being electrically connected to the light-emitting element; wherein the pixel circuit includes at least one oxide thin film transistor and at least one low-temperature polysilicon thin film transistor; and the second signal line includes a signal line connected to the gate of at least one of the low-temperature polysilicon thin film transistors.

[0188] Another embodiment of the present disclosure provides a display device, which includes any of the above-mentioned display substrates.

[0189] For example, the display device may be a QHD (Quad High Definition) display device, where QHD refers to four times the resolution of a full high-definition screen. For example, the display device may be an FHD (Full High Definition) display device, where FHD refers to full high definition.

[0190] For example, the display device provided in the embodiments of the present disclosure may be an organic light emitting diode display device, such as an active-matrix organic light emitting diode (AMOLED) display device.

[0191] For example, the display device may further include a cover plate located on the display side of the display substrate. For example, the display device may further include a functional component located on a side of the base substrate away from the light-emitting element, the functional component facing the second region. For example, the functional component includes at least one of a camera module (e.g., a front-facing camera module), a 3D structured light module (e.g., a 3D structured light sensor), a time-of-flight 3D imaging module (e.g., a time-of-flight sensor), an infrared sensing module (e.g., an infrared sensing sensor), and the like.

[0192] The display device provided by the embodiment of the present disclosure electrically connects the signal lines located on both sides of the second area by using the first connecting line, the second connecting line, the third connecting line and the fourth connecting line. The first connecting line is located on the side of the third connecting line away from the second area, and the second connecting line overlaps with the third connecting line. This can reduce the wiring space around the second area to increase the area of ​​the display area, and at the same time reduce the load mutation of the first signal line and the second signal line.

[0193] For example, the display device may include any product or component with a display function, such as a mobile phone, a tablet computer, a laptop computer, a navigator, etc., and the embodiments of the present disclosure are not limited to this.

[0194] There are a few points to note:

[0195] (1) The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to general designs.

[0196] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0197] The foregoing description is merely an exemplary embodiment of the present disclosure and is not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. A display substrate, comprising: A substrate, comprising a first region and a second region, wherein the first region is located around the second region; a plurality of first signal lines, located on the base substrate and not passing through the second area; a plurality of second signal lines, which are located in a different layer from the plurality of first signal lines and do not pass through the second area; Wherein, at least a portion of the first signal line extends along a first direction, at least a portion of the second signal line extends along a second direction, and the first direction intersects the second direction; The plurality of first signal lines include a portion of the first signal lines extending through the second area, each of the portion of the first signal lines includes a first sub-signal line and a second sub-signal line located on both sides of the second area, the first sub-signal line and the second sub-signal line being electrically connected via a first connecting line extending along the first direction and a second connecting line extending along the second direction, and the portion of the first signal lines is electrically connected to the plurality of first connecting lines and the plurality of second connecting lines; The plurality of second signal lines include a portion of second signal lines extending through the second area, each of the portion of second signal lines includes a third sub-signal line and a fourth sub-signal line located on both sides of the second area, the third sub-signal line and the fourth sub-signal line are electrically connected via a third connecting line extending along the first direction and a fourth connecting line extending along the second direction, and the portion of the second signal lines are electrically connected to the plurality of third connecting lines and the plurality of fourth connecting lines; In a direction perpendicular to the substrate, at least one second connection line overlaps with at least one third connection line, and on the same side of the second region, at least one first connection line is located on a side of the at least one third connection line away from the second region; The minimum distance between a fourth connection line closest to the second area and the edge of the second area is smaller than the minimum distance between a first connection line closest to the second area and the edge of the second area.

2. The display substrate according to claim 1, wherein The plurality of first signal lines include data lines, and the plurality of second signal lines include at least light emission control signal lines.

3. The display substrate according to claim 1 or 2, wherein: On the same side of the second area, a first group of connection lines among the plurality of second connection lines is located on a side of at least one fourth connection line close to the second area, and a second group of connection lines among the plurality of second connection lines is located on a side of the at least one fourth connection line away from the second area.

4. The display substrate according to claim 3, wherein: Along a direction perpendicular to the base substrate, the first group of connection lines overlaps with the third connection lines, and the second group of connection lines does not overlap with the third connection lines.

5. The display substrate according to claim 3, wherein: The distance between a second connection line in the first group of connection lines that is closest to the second group of connection lines and a second connection line in the second group of connection lines that is closest to the first group of connection lines is a first distance, the distance between two adjacent second connection lines in the second group of connection lines is a second distance, and the ratio of the first distance to the second distance is greater than 2. The display substrate according to claim 3 , wherein: The first connection line connected to a second connection line in the first group of connection lines that is closest to the second group of connection lines includes two parts respectively located on both sides of the second connection line in the first direction.

7. The display substrate according to claim 6, wherein: The first connection line connected to the one second connection line in the first group of connection lines that is closest to the second group of connection lines extends to a position of the one second connection line in the second group of connection lines that is closest to the first group of connection lines.

8. The display substrate according to claim 6, wherein: Each of the N first connection lines respectively connected to the N second connection lines closest to the second group of connection lines in the first group of connection lines includes two parts respectively located on both sides of the second connection line connected thereto in the first direction, and among the N first connection lines arranged along the direction close to the second area, the length of the part of the first connection line located on the side of the second connection line connected thereto close to the second group of connection lines gradually decreases, N is a positive integer greater than or equal to 1, and the number of the second connection lines in the first group of connection lines located on one side of the center of the second area is greater than or equal to N.

9. The display substrate according to claim 3, wherein: Among the second signal lines whose extensions do not pass through the second area, a second signal line closest to the second area is located between a fourth connecting line closest to the second area and the fourth connecting line adjacent thereto.

10. The display substrate according to claim 1 or 2, wherein: On the same side of the second area, at least one first signal line among the plurality of first signal lines whose extended line does not pass through the second area is located on a side of the first connecting line close to the second area.

11. The display substrate according to claim 1 or 2, wherein: A ratio of a distance between a first connection line and a third connection line that are closest to each other among the plurality of first connection lines and the plurality of third connection lines to a distance between two adjacent third connection lines is 0.8 to 1.

2.

12. The display substrate according to claim 1 or 2, wherein: In the first region, at least one first connecting line and at least one third connecting line are located in the same layer, and at least one second connecting line and at least one fourth connecting line are located in the same layer.

13. The display substrate according to claim 12, wherein: The at least one first connection line and the at least one third connection line are both located in the same layer as the plurality of first signal lines.

14. The display substrate according to claim 12, wherein: The plurality of second signal lines are located between the plurality of first signal lines and the base substrate, and the fourth connection line is located between the plurality of first signal lines and the plurality of second signal lines.

15. The display substrate according to claim 3, wherein The first area is a display area, the first area surrounds the second area, the base substrate also includes a peripheral area surrounding the display area, the multiple second groups of connection lines include the second connection lines located in the first area and the second connection lines located in the peripheral area, the second connection lines located in the first area are arranged in a different layer from the first connection lines, and the second connection lines located in the peripheral area are arranged in the same layer as the first connection lines.

16. The display substrate according to claim 15, wherein: The second connection line located in the peripheral area is provided in the same layer as the first signal line.

17. The display substrate according to claim 3, wherein: At least one second connection line in the first group of connection lines is in the same layer as at least one fourth connection line, is arranged at intervals, and is located on the same straight line.

18. The display substrate according to claim 3, wherein: On the same side of the second region, at least one first signal line connected to the second group of connection lines overlaps with each fourth connection line in a direction perpendicular to the base substrate.

19. The display substrate according to claim 1, wherein The orthographic projection of each first connecting line on the straight line extending along the first direction overlaps with the orthographic projection of each third connecting line on the straight line; the orthographic projection of at least one second connecting line on the straight line extending along the second direction does not overlap with the orthographic projection of at least one fourth connecting line on the straight line.

20. The display substrate according to claim 2, further comprising: A light-emitting element and a pixel circuit located on the substrate, wherein the pixel circuit is electrically connected to the light-emitting element; The pixel circuit includes a driving transistor, a light-emitting control transistor, and a reset transistor, wherein the gate of the light-emitting control transistor is electrically connected to the light-emitting control signal line, the first electrode of the light-emitting control transistor is electrically connected to the first electrode of the driving transistor, and the second electrode of the light-emitting control transistor is electrically connected to the light-emitting element; The gate of the reset transistor is electrically connected to the reset control signal line, one electrode of the reset transistor is electrically connected to the second electrode of the drive transistor, or one electrode of the reset transistor is electrically connected to the second electrode of the light emitting control transistor; The second signal line includes the reset control signal line.

21. The display substrate according to claim 1, further comprising: A light-emitting element and a pixel circuit located on the substrate, wherein the pixel circuit is electrically connected to the light-emitting element; Wherein, the pixel circuit includes at least one N-type thin film transistor and at least one P-type thin film transistor; The second signal line includes a signal line connected to a gate of at least one of the P-type thin film transistors.

22. The display substrate according to claim 1, further comprising: A light-emitting element and a pixel circuit located on the substrate, wherein the pixel circuit is electrically connected to the light-emitting element; Wherein, the pixel circuit includes at least one oxide thin film transistor and at least one low-temperature polysilicon thin film transistor; The second signal line includes a signal line connected to a gate of at least one of the low-temperature polysilicon thin film transistors.

23. The display substrate according to claim 1, wherein The first area is a display area, the first area surrounds the second area, and the base substrate further includes a peripheral area surrounding the display area; The display substrate also includes: a plurality of fifth connecting lines extending along the first direction and a plurality of sixth connecting lines extending along the second direction, the fifth connecting lines located on the same layer and on the same straight line as the first connecting lines are spaced apart from the first connecting lines, the fifth connecting lines located on the same layer and on the same straight line as the third connecting lines are spaced apart from the third connecting lines, the sixth connecting lines located on the same layer and on the same straight line as the second connecting lines are spaced apart from the second connecting lines, the sixth connecting lines located on the same layer and on the same straight line as the fourth connecting lines are spaced apart from the fourth connecting lines, and at least one of the fifth connecting lines and the sixth connecting lines is electrically connected to a third signal line, and the third signal line is located in the peripheral area.

24. The display substrate according to claim 23, wherein: At least one of the positions where the fifth connecting line is spaced from the first connecting line and the positions where the fifth connecting line is spaced from the third connecting line overlaps with the film layer where the fourth connecting line is located, and at least one of the positions where the sixth connecting line is spaced from the second connecting line and the positions where the sixth connecting line is spaced from the fourth connecting line overlaps with the film layer where the first connecting line is located.

25. The display substrate according to claim 1 or 2, wherein: Two first signal lines adjacent to the first connecting line are arranged on both sides of at least one first connecting line, and the ratio of the minimum distance between the two first signal lines and the first connecting line is 0.9 to 1.1; two first signal lines adjacent to the third connecting line are arranged on both sides of at least one third connecting line, and the ratio of the minimum distance between the two first signal lines and the third connecting line is 0.9 to 1.

1.

26. A display device comprising the display substrate according to any one of claims 1 to 25.

Images