A method for hardening missile-borne computers against single-event upsets through timed refresh
By using a timed refresh method, data is backed up to non-volatile memory and refreshed periodically in the DSP processor, which solves the problem of increased storage space and computational load in the prior art and effectively prevents single-event upsets without reducing DSP performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING INST OF COMP TECH & APPL
- Filing Date
- 2022-07-25
- Publication Date
- 2026-05-26
AI Technical Summary
Existing anti-single-event upset (SEU) software hardening methods significantly increase the internal storage space requirements and computational load of DSPs, leading to a decrease in the actual computing performance of DSPs, and there is also the problem of SEU hardening failure.
The protected data is backed up to non-volatile memory and refreshed periodically in the internal memory unit of the DSP processor using a timed refresh method. Data interaction is performed through the EMIF bus, and the refresh operation is performed when the DSP is idle using a timed interrupt mechanism. The data block length and refresh cycle are adjusted to optimize resource usage and hardening effect.
It achieves SEU protection by reducing the impact on DSP computing performance without increasing DSP storage space requirements, and flexibly adjusting the hardening process cycle and resource usage.
Smart Images
Figure CN115268779B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of missile-borne computers, specifically relating to a timed refresh method for hardening missile-borne computers against single-event upsets. Background Technology
[0002] Airborne computers typically employ high-performance digital signal processors (DSPs) for signal processing, communication, and flight control. In the space radiation environment, they are susceptible to bombardment from high-energy space plasma, protons, electrons, and heavy ions, which can cause changes in the state of the internal storage units of the DSP processor (1), resulting in data flipping, i.e., single event upset (SEU). When SEUs accumulate to a certain level or occur in the state machines of critical components such as instruction fetching, instruction decoding, and pipelined execution of the DSP, they may cause DSP malfunctions.
[0003] The current common method for hardening SEU software is to use the "triple redundancy" technique on the protected data, that is, to store the same data in different locations in the internal storage unit of the DSP processor (1), and when using it, to read out the three sets of data at the same time for comparison, and to accept the technique of two sets of the same data.
[0004] Existing technologies can mitigate the harm of SEUs to some extent, but they have the following drawbacks:
[0005] This significantly increases the internal storage space requirements of the DSP, which are three times the requirements before hardening.
[0006] Since each data read / write operation requires reading or writing three times and making a decision, it greatly increases the computational load and reduces the actual computing performance of the DSP.
[0007] When the three sets of data are different, it is impossible to determine which set of data is correct, i.e., the SEU reinforcement fails. Summary of the Invention
[0008] (a) Technical problems to be solved
[0009] The technical problem to be solved by the present invention is how to provide a time-refreshed method for hardening the anti-single-event upset (SEU) software of an airborne computer, so as to solve the problems of existing anti-single-event upset software hardening methods that significantly increase the internal storage space requirements of the DSP, greatly increase the computational load, reduce the actual computing performance of the DSP, and cause SEU hardening failure.
[0010] (II) Technical Solution
[0011] To solve the above-mentioned technical problems, this invention proposes a timed refresh method for hardening the software of an airborne computer against single-event upset (SEU). This method is applied to an airborne computer, which includes a DSP processor (1) and a non-volatile memory (2). The DSP processor (1) and the non-volatile memory (2) are connected through an EMIF bus (3). The DSP processor (1) is used to run software hardened using the SEU method. The non-volatile memory is used to back up the protected data. The EMIF bus is responsible for supporting data interaction between the DSP processor and the non-volatile memory. During system initialization, the DSP processor (1) backs up the protected data in the non-volatile memory (2). During the operation of the airborne computer, the DSP processor (1) updates the backup data stored in the non-volatile memory (2) to the internal storage unit of the DSP processor (1) at a certain period.
[0012] Furthermore, the operational steps of this reinforcement method include:
[0013] Step 1: The onboard computer is powered on, and the DSP processor (1) starts running. It divides the protected data with a total length of L into n data blocks of length k bytes. Each data block is called B1, B2, B3, ..., Bn.
[0014] Step 2: Back up the protected data after it has been divided into blocks in sequence in non-volatile memory (2);
[0015] Step 3: Configure the DSP timer and set the timer interrupt to m milliseconds;
[0016] Step 4: When the timer interrupt is triggered, refresh the data of one data block from the internal memory of the DSP processor (1) one by one from the non-volatile memory (2) to the internal memory of the DSP processor (1) in sequence; repeat this step until all the protected data is refreshed.
[0017] Furthermore, in the second step, the protected data after being divided into blocks is backed up to the non-volatile memory (2) in the order of B1, B2, B3, ..., Bn.
[0018] Furthermore, in the fourth step, data blocks are refreshed from the non-volatile memory (2) to the internal memory of the DSP processor (1) in the order of B1, B2, B3, ..., Bn.
[0019] Furthermore, in the second step, the protected data after being divided into blocks is backed up to the non-volatile memory (2) in the order of Bn, Bn-1, ..., B1.
[0020] Furthermore, in the fourth step, data blocks are refreshed from the non-volatile memory (2) to the internal storage unit of the DSP processor (1) in the order of Bn, Bn-1, ..., B1.
[0021] Furthermore, after n refresh operations, the protected data inside the DSP processor (1) is the same as the data backed up in the non-volatile memory (2).
[0022] Furthermore, the length k of each data block is adjusted according to the different impact strengths of SEU, which is the data length for each refresh.
[0023] Furthermore, the trigger interval m of the timer interrupt is adjusted according to the time slice division of the operation calculated by the DSP processor (1).
[0024] Furthermore, a refresh operation is performed when the DSP processor (1) is idle.
[0025] (III) Beneficial Effects
[0026] This invention proposes a timed-refreshing method for hardening missile-borne computers against single-event upset (SEU) software. This invention offers the following advantages:
[0027] No increase in DSP internal storage space requirements;
[0028] SEU hardening is performed at certain time intervals, and DSP computing resources are time-sharing multiplexed, which has less impact on the normal program execution process.
[0029] The length of data blocks and the cycle of SEU hardening can be flexibly adjusted, achieving a balance between computational resource consumption and SEU hardening effect. Attached Figure Description
[0030] Figure 1 This is a schematic diagram illustrating the connection between the onboard computer DSP and the non-volatile memory of this invention.
[0031] Figure 2 This is a flowchart of the timed refresh method for hardening missile-borne computer against SEU software according to the present invention;
[0032] Figure 3 This is a schematic diagram illustrating the backup of data using the non-volatile memory of the present invention. Detailed Implementation
[0033] To make the objectives, contents, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples.
[0034] The purpose of this invention is to propose a method that can significantly reduce the risk of single-event upsets without increasing the internal storage space occupied by the DSP or significantly reducing the actual computing performance of the DSP.
[0035] The timed refresh method for hardening the anti-SEU software of the missile-borne computer proposed in this invention is applied in the missile-borne computer, which includes a DSP processor (1) and a non-volatile memory (2). The DSP processor (1) and the non-volatile memory (2) are connected through an EMIF bus (3). The DSP processor (1) is used to run software using the single-event upset (SEU) hardening method, the non-volatile memory is used to back up the protected data, and the EMIF bus is responsible for supporting data interaction between the DSP processor and the non-volatile memory. The schematic diagram is shown below. Figure 1 As shown, the software using the SEU hardening method described in this invention runs in a DSP processor. The non-volatile memory is responsible for backing up the protected data, and the EMIF bus is responsible for supporting data interaction between the DSP processor and the non-volatile memory.
[0036] During system initialization, the DSP processor (1) backs up the protected data in non-volatile memory (2). During the operation of the onboard computer, the DSP processor (1) updates the backup data stored in non-volatile memory (2) to the internal storage unit of the DSP processor (1) at regular intervals, ensuring the correctness of the data in the internal storage unit of the DSP processor (1), thereby suppressing the influence of SEU. The flowchart is as follows. Figure 2 As shown.
[0037] The operating steps of this invention are as follows:
[0038] Step 1: The onboard computer is powered on, and the DSP processor (1) starts running. It divides the protected data with a total length of L into n data blocks of length k bytes. Each data block is called B1, B2, B3, ..., Bn.
[0039] Step 2: Divide the protected data into blocks according to... Figure 3 The sequential backup shown is in non-volatile memory (2);
[0040] Furthermore, the protected data after being divided into blocks is backed up to the non-volatile memory (2) in the order of B1, B2, B3, ..., Bn;
[0041] Furthermore, the protected data after being divided into blocks is backed up to the non-volatile memory (2) in the order of Bn, Bn-1, ..., B1;
[0042] Step 3: Configure the DSP timer and set the timer interrupt to m milliseconds;
[0043] Step 4: When the timer interrupt is triggered, refresh the data of one data block from the non-volatile memory (2) to the internal memory of the DSP processor (1) in the order of B1, B2, B3, ..., Bn. Repeat this step until all the protected data is refreshed.
[0044] Furthermore, data blocks are refreshed from the non-volatile memory (2) to the internal memory of the DSP processor (1) in the order of B1, B2, B3, ..., Bn.
[0045] Furthermore, data blocks are refreshed from the non-volatile memory (2) to the internal memory of the DSP processor (1) in the order of Bn, Bn-1, ..., B1.
[0046] After n refresh operations, the protected data inside the DSP processor will be identical to the data backed up in the non-volatile memory, thereby reducing the risk of single-event upsets.
[0047] Depending on the intensity of the SEU's influence, the length k of each data block can be flexibly adjusted, which is the length of the data refreshed each time, thereby flexibly adjusting the time required for each refresh operation.
[0048] Based on the time slice division of the operation calculated by the DSP processor (1), the trigger interval m of the timer interrupt can be flexibly adjusted.
[0049] Selecting the DSP processor (1) to perform a refresh operation when it is idle further reduces the impact on DSP computing performance and achieves a balance between computing resource usage and SEU hardening effect.
[0050] The timed refresh method for hardening missile-borne computers against SEU software proposed in this invention has the following beneficial effects:
[0051] No increase in DSP internal storage space requirements;
[0052] SEU hardening is performed at certain time intervals, and DSP computing resources are time-sharing multiplexed, which has less impact on the normal program execution process.
[0053] The length of data blocks and the cycle of SEU hardening can be flexibly adjusted, achieving a balance between computational resource consumption and SEU hardening effect.
[0054] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A method for timing refreshed, missile-borne computer anti-single event upset software hardening, characterized by, This method is applied to an onboard computer, which includes a DSP processor (1) and a non-volatile memory (2). The DSP processor (1) and the non-volatile memory (2) are connected via an EMIF bus (3). The DSP processor (1) is used to run software using the single-event upset (SEU) hardening method. The non-volatile memory is used to back up the protected data. The EMIF bus is responsible for supporting data interaction between the DSP processor and the non-volatile memory. During system initialization, the DSP processor (1) backs up the protected data in the non-volatile memory (2). During the operation of the onboard computer, the DSP processor (1) updates the backup data stored in the non-volatile memory (2) to the internal storage unit of the DSP processor (1) at a certain period of time. in, The operational steps of this reinforcement method include: Step 1: The onboard computer is powered on, and the DSP processor (1) starts running. It divides the protected data with a total length of L into n data blocks of length k bytes. Each data block is called B1, B2, B3, ..., Bn. Step 2: Back up the protected data after it has been divided into blocks in sequence in non-volatile memory (2); Step 3: Configure the DSP timer and set the timer interrupt to m milliseconds; Step 4: When the timer interrupt is triggered, refresh the data of one data block from the internal memory of the DSP processor (1) sequentially from the non-volatile memory (2) to the internal memory of the DSP processor (1); repeat this step until all the protected data has been refreshed. The length k of each data block is adjusted according to the different impact strengths of SEU, which is the data length for each refresh.
2. The method of claim 1, wherein the timing refreshed, missile-borne computer anti- single event upset software hardening method is characterized by, In the second step, the protected data after being divided into blocks is backed up to the non-volatile memory (2) in the order of B1, B2, B3, ..., Bn.
3. The method of claim 2, wherein the method is implemented in a timing refreshed, missile-borne computer, and wherein the method further comprises: In the fourth step, data blocks are refreshed from the non-volatile memory (2) to the internal storage unit of the DSP processor (1) in the order of B1, B2, B3, ..., Bn.
4. The method of claim 1, wherein the timing refreshed, missile-borne computer anti- single event upset software hardening method is characterized by, In the second step, the protected data after being divided into blocks is backed up to the non-volatile memory (2) in the order of Bn, Bn-1, ..., B1.
5. The timed refresh method for hardening missile-borne computer software against single-event upset as described in claim 4, characterized in that, In the fourth step, data blocks are refreshed from the non-volatile memory (2) to the internal storage unit of the DSP processor (1) in the order of Bn, Bn-1, ..., B1.
6. The timed refresh method for hardening missile-borne computer software against single-event upset as described in any one of claims 1-5, characterized in that, After n refresh operations, the protected data inside the DSP processor (1) is the same as the data backed up in the non-volatile memory (2).
7. The timed refresh method for hardening missile-borne computer software against single-event rollover as described in claim 6, characterized in that, The trigger interval m of the timer interrupt is adjusted according to the time slice division of the operation calculated by the DSP processor (1).
8. The method for hardening missile-borne computer against single-event upset software by timed refresh as described in claim 6, characterized in that, A refresh operation is performed when the DSP processor (1) is idle.