A circuit and method for long sequence data sorting

Abstract

The application discloses a circuit and method for long sequence data sorting. The circuit is used for sorting N data in K base, and the maximum element in the data contains m bits in K base. The circuit comprises a radix counting unit, a first address generating unit, a data distribution unit and two sorting buffers. The two sorting buffers are used as a source buffer and a target buffer respectively, and can read data in a given address or write a data into a specified address. The radix counting unit, the first address generating unit and the data distribution unit are connected in sequence. The two sorting buffers are connected with the data distribution unit and the radix counting unit respectively. The data sorting circuit of the application has simple structure, can be flexibly adjusted according to specific requirements, and the data sorting method has linear order time complexity and short sorting time.

Description

Technical Field

[0001] This invention relates to the field of digital signal processing, and more specifically to a hardware circuit and method for implementing fast data sorting of long sequences in an integrated circuit. Background Technology

[0002] In digital signal processing, it is often necessary to sort a series of data. For example, in the wavelet domain, noise energy needs to be estimated by solving for the median of the wavelet decomposition coefficients, or the t largest (or smallest) data points need to be found from u data points to determine their priority.

[0003] There are many solutions for data sorting on software platforms, such as bubble sort and heap sort. However, software solutions are limited by processor resources and are usually slow, making them unsuitable for applications with high real-time requirements, such as image processing and radar signal processing.

[0004] Because the circuit structure can be specifically optimized for the sorting method, data sorting implemented on hardware platforms such as FPGAs typically offers superior performance compared to software solutions. Hardware implementations can be categorized into two types: sorting networks and linear structures. Sorting networks, through parallel design, can usually achieve fast sorting speeds, but as the sequence to be sorted grows, the hardware complexity and overhead of the sorting network increase exponentially. Linear structures have lower hardware resource overhead, but require multiple iterations of the sequence to be sorted, often exhibiting quadratic time complexity and relatively slower sorting speeds. Summary of the Invention

[0005] To address the shortcomings of the existing technology, this invention provides a circuit and method for sorting long sequences, aiming to achieve high sorting speed with relatively low hardware complexity.

[0006] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0007] A circuit for sorting long sequence data is provided, used to sort N data in base K, where the largest element in the data contains m bits in base K. The circuit includes a radix counting unit, a starting address generation unit, a data allocation unit, and two sorting buffers, which serve as a source buffer and a destination buffer, respectively. Both buffers can read data from a given address or write a data to a specified address. The radix counting unit, the starting address generation unit, and the data allocation unit are connected in sequence. The two sorting buffers are each connected to the data allocation unit and the radix counting unit, respectively.

[0008] Furthermore, each of the two sorting buffers can hold at least all N data items.

[0009] Furthermore, the radix counting unit is connected to the source buffer and external circuit data respectively via a data selector.

[0010] Furthermore, the radix counting unit contains a total of K element count registers ereg0 to ereg0. K-1 The radix counting unit, when the current input element is represented as x in base K, corresponds to the element count counter ereg. x The value is increased by 1.

[0011] Furthermore, the starting address generation unit includes K starting address registers saddr0 to saddr0. K-1 Each of the K element count registers is connected to one of them; the first address register saddr0 is always 0, and the other first address registers saddr1 to saddr2 are connected to one of them. K-1 The value is obtained by accumulating the number of all elements in the radix counting unit whose radix number is less than the current starting address register.

[0012] Furthermore, the data allocation unit includes K address pointer registers paddr0 to paddr0. K-1 Each of the K address registers is connected to the corresponding K address registers; the data allocation unit reads the data in the source buffer sequentially from 0 in ascending order, and selects the x-th address pointer register paddr according to the radix x of the corresponding bit of the data to be allocated. x And write the currently unallocated data to the address pointer register paddr in the target buffer. x The address it points to.

[0013] Furthermore, when the data allocation unit begins a new data allocation, the address pointer registers paddr0 to paddr... K-1 The first address registers saddr0 to saddr1, respectively, are assigned the values ​​of the first address generation unit. K-1 When the base number of the input data to be allocated is x, the x-th address pointer register paddr corresponding to base number x is set. x The value is increased by 1.

[0014] This invention provides a sorting method for a circuit used for sorting long sequence data, the steps of which include:

[0015] Step 1: Input the data to be sorted into the source buffer;

[0016] Step 2: The radix counting unit counts the number of times the radix 0 to radix K-1 appears in each of the 0th to m-1th bits of the input data in base K during multiple data iterations, and records them one by one in the element count register;

[0017] Step 3: The starting address generation unit generates the starting address of each radix in the target buffer by accumulating the number of elements register, and stores it into the starting address register one by one; after all accumulations are completed, the address pointer register of the data allocation unit is configured as the starting address register one by one.

[0018] Step four: The data allocation unit reads the sequence to be sorted sequentially from the source buffer and reallocates each element to the corresponding position in the target buffer according to the address pointer register; when each element is reallocated, the value of the corresponding address pointer register is incremented by 1; after the reallocation is completed, the source buffer and the target buffer are swapped.

[0019] Step 5: Read the target buffer sequentially after the last data redistribution is completed, and then output the data to be sorted from smallest to largest.

[0020] Furthermore, in step one, the iterative data comes from the source buffer or external to the circuit. Steps two through four are performed m times.

[0021] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0022] 1. This invention employs a "radix sort" scheme, which has a stable linear time complexity of O(m*N) (where m is the number of iterations required for sorting), and its speed for sorting long sequences is far superior to traditional schemes with quadratic time complexity.

[0023] 2. This invention can be implemented based on a field-programmable gate array (FPGA), overcoming the slow speed of existing software implementation schemes, and can be used in fields with high requirements for data processing speed, such as real-time signal processing.

[0024] 3. The circuit structure of this invention is simple and easy to parameterize. It can quickly and flexibly adjust the radix selection strategy and the number of sorting iterations according to hardware resources, achieving optimal sorting performance under limited resources. It features high speed, low overhead, and easy expansion. Attached Figure Description

[0025] Figure 1 This is a structural diagram of an embodiment of the data sorting circuit of the present invention;

[0026] Figure 2 This is a flowchart of the data sorting method of the present invention;

[0027] Figure 3 This describes the working mode of the radix counting unit and the starting address generation unit of the present invention;

[0028] Figure 4 This is the working mode of the data allocation unit of the present invention;

[0029] Figure 5This is a comparison of the sorting time of the present invention with that of the traditional method. Detailed Implementation

[0030] To better understand the present invention, the present invention will be further described below with reference to specific embodiments.

[0031] One embodiment of the present invention is used to sort a sequence containing 1024 elements in hexadecimal, wherein the largest element in the sequence has a bit width of no more than 16 bits, that is, it contains a total of m = 4 bits in hexadecimal. Figure 1 As shown, the sorting circuit includes: a radix counting unit, a starting address generation unit, a data allocation unit, and two sorting buffers.

[0032] The system comprises two sorting buffers, a first sorting buffer and a second sorting buffer, each capable of holding at least all 1024 sorted data items. The first and second sorting buffers serve as the source and destination buffers, respectively; if one is the source buffer, the other is the destination buffer, and they can be exchanged based on the sorting iterations. Both sorting buffers can read data from a given address or write data to a specified address.

[0033] The radix counting unit contains 16 element count registers ereg0 to ereg0. 15 The radix counting unit increments the element count counter ereg when a certain digit of the current input element is represented as x in hexadecimal (where x is the radix in hexadecimal). x The value is incremented by 1. The radix counting unit can select whether the data input comes from outside the sorting circuit or from the source buffer via a 2-way data selector. The radix counting unit can count the radix of different bits in hexadecimal for the selected input element based on the current sorting iteration number. Before each count begins, the radix counting unit clears the 16 element count registers ereg0 to ereg0. 15 After each count is completed, the element count registers ereg0 to ereg0 are updated. 15 The value is used by the starting address generation unit to calculate the radix starting address.

[0034] The starting address generation unit contains 16 starting address registers saddr0 to saddr0. 15 The first address register saddr0 is always 0; the other first address registers saddr1 to saddr2 are always 0. 15 The value is obtained by accumulating the number of all elements in the radix counting unit whose radix number is less than that of the starting address register.

[0035] The data allocation unit contains 16 address pointer registers, paddr0 to paddr0. 15The data allocation unit can read data from the source buffer sequentially, starting from 0, in ascending order, and select the x-th address pointer register (paddr) based on the radix x of the corresponding bit of the data to be allocated. x And write the currently unassigned data into another sorted buffer, paddr. x The address it points to.

[0036] Before a data reallocation begins, the 16 address pointer registers paddr0 to paddr1 of the data allocation unit... 15 These are configured one-to-one as the 16 starting address registers saddr0 to saddr in the starting address generation unit. 15 The value of . When the base number of the input data to be allocated is x, the x-th address pointer register paddr corresponding to base number x is set. x The value is increased by 1.

[0037] Correspondingly, such as Figure 2 As shown, this embodiment of the invention provides a method for sorting a sequence of length 1024 in hexadecimal using the aforementioned data sorting circuit, wherein the largest element in the sequence has a bit width of no more than 16 bits, that is, a total of 4 bits in hexadecimal. The sorting method specifically includes the following steps:

[0038] Step 1, Data Input. For example... Figure 1 As shown, the data to be sorted, F10, is sequentially input into the first sorting buffer starting from address 0 until all 1024 data items are written. After the data input is complete, the first sorting buffer becomes the source buffer, and the second sorting buffer becomes the destination buffer.

[0039] Step two: Count the cardinality of elements. Before starting the count, the 16 element count registers ereg0 to ereg0 in the cardinality counting unit are... 15 All zeroed; the 16 address registers saddr0 to saddr1 of the address generation unit. 15 All values ​​are cleared to zero. When the sequence to be sorted is passed between the two buffers in step four, the radix counting unit counts the number of times the radix of the l-th position in hexadecimal (radix 0 to radix 15, i.e., K-1) appears. The value of l can be 1, 2, or 3 depending on the number of sorting iterations (0 < l ≤ m-1). For example... Figure 1 As shown, the input to the radix counting unit at this time comes from the source buffer, i.e., data stream F40 (or, depending on the iteration number, from F40'). When the radix counting unit represents the l-th bit of the current input element as x in hexadecimal (0 < x ≤ K-1), the corresponding element count counter ereg... x The value is incremented by 1. For example, when the l-th element of the current input element is represented as 3 in hexadecimal, the corresponding element count counter ereq3 is incremented by 1;

[0040] Specifically, when the sequence to be sorted is externally input into the first sorting buffer in step one, the radix counting unit counts the number of times the radix 0 to radix 15 of the sequence in hexadecimal format appears. For example... Figure 1 As shown, the input of the radix counting unit comes from the external input of the sorting circuit, namely data stream F10.

[0041] When iterating through step two in a sorting iteration, if the current execution counts the occurrences of the 1st digit (radix 0 to radix 15) of the sequence to be sorted in hexadecimal, then the next execution will count the occurrences of the (1+1)th digit (radix 0 to radix 15) of the sequence to be sorted in hexadecimal. For example, if the first execution of step two counts the occurrences of the 0th digit (radix 0 to radix 15) in hexadecimal, then the second execution of step two will count the occurrences of the 1st digit (radix 0 to radix 15) in hexadecimal.

[0042] like Figure 3 As shown, a sequence containing four elements: 0x891a, 0x3200, 0x010a, and 0x02b7. In step one, when data is input into the first sorting buffer, the radix counter unit counts the number of times radix 0 to radix 15 appear in the 0th position of the sequence to be sorted in hexadecimal. That is, radix 10 (represented as 0xa in hexadecimal) appears twice, radix 7 once, and radix 0 once. Therefore, the element count register ereg... 10 The values ​​of ereg7 and ereg0 are 2, 1, and 1 respectively, while the remaining element count registers are 0. During the first iteration of step two, the radix counting unit counts the number of times radix 0 to radix 15 appear in the first position of the sequence to be sorted in hexadecimal. That is, radix 11 (represented as 0xb in hexadecimal) appears once, radix 1 appears once, and radix 0 appears twice. Therefore, the element count register ereg7 is 0. 11 The values ​​of ereg1 and ereg0 are 1, 1, and 2 respectively, while the number of other elements in the register is 0.

[0043] Step 3: Generate the starting address of the radix of the target buffer. After the radix counting unit counts the occurrences of the radix 0 to radix 15 in the hexadecimal digit of the sequence to be sorted in step 2, the radix counting unit stores the element count registers ereg0 to ereg0. 15 The value is sent to the starting address generation unit, that is... Figure 1 The data stream is F20. The starting address generation unit uses the element count registers ereg0 to ereg0. 15 The value is used to calculate the starting address of each radix in the target buffer and store it in the starting address registers saddr0~saddr. 15 The value of the 0th address register is always 0, while the value of the xth address register (saddr) is always 0. xThe value is the register ereg0 to ereg0, which represents the number of elements from the 0th to the (x-1th)th element. x-1 The sum of the values. For example, the 12th starting address register saddr. 12 The value is the register ereg0~ereg0, which represents the number of elements from 0 to 11. 11 The sum of the values; after calculation, the starting address registers saddr0 to saddr in the starting address generation unit are added. 15 The address pointer registers paddr0 to paddr of the data reallocation unit are written one-to-one. 15 ,Right now Figure 1 Data stream F30 in the middle. For example... Figure 3 As shown, after the radix counting unit completes the counting of the radix at the 0th bit of the sequence (0x891a, 0x3200, 0x010a, 0x02b7) in hexadecimal, the starting address generator generates the starting address corresponding to each radix based on the value of the element count register. For example, the starting address corresponding to radix 6 is the sum of the first five element count registers, which is 1; the starting address corresponding to radix 11 is the sum of the first ten element count registers, which is 4.

[0044] Step four, data reallocation. The data allocation unit reads the sequence to be sorted sequentially from the source buffer, based on the address pointer registers paddr0 to paddr0. 15 The pointed-to address reallocates each element to the destination buffer. The data allocation unit reads data from the source buffer sequentially, starting from address 0. Figure 1 F40 (or possibly F40' depending on the number of iterations) in the current starting address registers saddr0~saddr 15 The storage contains the starting address of the l-th radix (0 to 15) of the sequence to be sorted in hexadecimal. Therefore, when the radix of the l-th radix of the current element to be allocated is x, the element is written to the address pointer register paddr in the target buffer. x The address it points to, i.e. Figure 1 F41 (or F41' depending on the number of iterations) in the address pointer register paddr is also used. x The value is incremented by 1. When all elements in the source buffer are reallocated to the destination buffer, the source and destination buffers are swapped. If step four reallocates data using the most significant bit (the third bit) of the data to be sorted in hexadecimal, then step five is executed after step four is completed; otherwise, step two is executed.

[0045] like Figure 4 As shown, the current starting address registers saddr0~saddr 15It stores the starting address of the first radix (0 to 15) of the sequence to be sorted in hexadecimal, and the value of the address pointer register paddr1 is 23. 11 The value is 846. The data allocation unit is sequentially reading data from source buffer address 1014 and reallocating it.

[0046] The data 0x02be stored at address 1014 in the source buffer has a base-11 hexadecimal value of 'b' in its first bit. Therefore, element 0x02be is allocated to the address pointer register paddr in the destination buffer. 11 The address it points to is 846, and paddr 11 The value is incremented by 1, thus pointing to address 847.

[0047] The data 0x801e stored at address 1015 in the source buffer has a first bit of 1 in hexadecimal. Therefore, element 0x801e is allocated to the address pointed to by address pointer register paddr1 in the destination buffer, which is 23. The value of paddr1 is then incremented by 1, thus pointing to address 24.

[0048] The data 0x01bf stored at address 1016 in the source buffer has a base of 'b' in hexadecimal, meaning its radix is ​​11. Therefore, element 0x02be is allocated to the address pointer register paddr in the destination buffer. 11 The address it points to is 847, and paddr 11 The value is incremented by 1, thus pointing to address 848.

[0049] Since this data redistribution is based on the first position of the sorted sequence in hexadecimal, after step four is completed, we will return to step two.

[0050] Step 5, Data Output. After 4 iterations, the data allocation unit, having redistributed data according to each bit of the elements to be sorted in hexadecimal in Step 4, sequentially reads the data from the current source buffer starting from address 0, thus outputting the elements in the original unsorted sequence in ascending order. This process corresponds to... Figure 1 The data stream in step five is F50 (or F50' depending on the number of iterations). In this embodiment, since the sorting process is performed four times, the source buffer in step five is the first sorting buffer, and the output data stream is F50.

[0051] like Figure 2 As shown, in a complete sorting process, the input element contains 4 digits in hexadecimal. Therefore, excluding the data input in step one and the data output in step five, steps two through four require a total of 4 iterations.

[0052] like Figure 5As shown, when sorting long sequences exceeding 512, the time complexity of this invention (O(m*N), where m is the number of iterations required for sorting) is much smaller than that of traditional logarithmic time complexity algorithms (O(N log2(N)), such as heap sort) and quadratic time complexity algorithms (O(N log2(N))). 2 (e.g., bubble sort).

[0053] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and substitutions can be made without departing from the technical principles of the present invention, and these improvements and substitutions should also be considered within the scope of protection of the present invention.

Claims

1. A circuit for sorting long sequence data, characterized in that, This circuit is used to sort N data in base K, where the largest element in the data contains m bits in base K. The circuit includes a radix counting unit, a starting address generation unit, a data allocation unit, and two sorting buffers. The two sorting buffers serve as a source buffer and a destination buffer, respectively, and can both read data from a given address or write a data to a specified address. The radix counting unit, the starting address generation unit, and the data allocation unit are connected in sequence. The two sorting buffers are each connected to the data allocation unit and the radix counting unit, respectively. The radix counting unit contains a total of K element count registers. ~ The radix counting unit is represented in base K as follows: At that time, the corresponding element count counter Increment the value by 1; The starting address generation unit contains K starting address registers. ~ Each of the K element count registers is connected to one of them; the starting address register Always 0, other starting address registers ~ The value is obtained by accumulating the number of all elements in the radix counting unit whose radix number is less than the current starting address register; The data allocation unit contains K address pointer registers. ~ Each of the K address registers is connected to one of them; the data allocation unit reads the data in the source buffer sequentially from 0 in ascending order, and allocates the data according to the radix of the corresponding bit of the data to be allocated. Select the first Address pointer registers And write the currently unallocated data to the address pointer register in the target buffer. The address it points to.

2. The circuit for sorting long sequence data according to claim 1, characterized in that, The two sorting buffers can each hold at least all N data items.

3. The circuit for sorting long sequence data according to claim 1, characterized in that, The radix counting unit is connected to the source buffer and external circuit data respectively through a data selector.

4. The circuit for sorting long sequence data according to claim 1, characterized in that, When the data allocation unit begins a new data allocation, the address pointer register... ~ The starting address registers of the starting address generation unit are respectively assigned values. ~ When the base number of the input data to be allocated is... At that time, the base number The corresponding number Address pointer registers The value is increased by 1.

5. A sorting method using the circuit for sorting long sequence data as described in claim 1, characterized in that, The sorting method includes the following steps: Step 1: Input the data to be sorted into the source buffer; Step 2: The radix counting unit counts the number of times the radix 0 to radix K-1 appears in each of the input data in the K-ary digits from 0 to m-1, and records them one by one in the element count register. Step 3: The starting address generation unit generates the starting address of each radix in the target buffer by accumulating the number of elements register, and stores it into the starting address register one by one; after all accumulations are completed, the address pointer register of the data allocation unit is configured as the starting address register one by one. Step four: The data allocation unit reads the sequence to be sorted sequentially from the source buffer and reallocates each element to the corresponding position in the target buffer according to the address pointer register; when each element is reallocated, the value of the corresponding address pointer register is incremented by 1; after the reallocation is completed, the source buffer and the target buffer are swapped. Step 5: Read the target buffer sequentially after the last data redistribution is completed, and then output the data to be sorted from smallest to largest.

6. The sorting method according to claim 5, characterized in that, In step one, the iterative data comes from the source buffer or from outside the circuit.

7. The sorting method according to claim 5, characterized in that, Perform m iterations on steps two through four.

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