Method for extracting a capacitance model of a mosfet on a fully depleted soi substrate

Abstract

The application provides a method for extracting a MOSFET capacitor model on a fully-depleted SOI substrate, comprising the following steps: short-circuiting the MOSFET source and drain, providing an AC voltage small signal, providing a DC bias on the back gate, the DC bias makes the channel region in accumulation and inversion states, and measuring the AC current small signal of the MOSFET at the gate in the above two states respectively to obtain the channel capacitor Cgc; short-circuiting the MOSFET source and drain with the back gate, providing an AC voltage small signal, and measuring the AC current small signal at the MOSFET gate to obtain the gate capacitor Cgg; and calculating the front gate oxide layer capacitor Cox and the buried oxide layer capacitor Cbox according to the measured channel capacitor Cgc and the gate capacitor Cgg. The application reconstructs the capacitor model according to the characteristics of the fully-depleted SOI substrate, and can accurately extract the MOSFET front gate oxide layer capacitor and buried oxide layer capacitor using the FDSOI substrate.

Description

Technical Field

[0001] This invention relates to the field of microelectronics technology, and in particular to a method for extracting the capacitance model of a MOSFET on a fully depleted SOI substrate. Background Technology

[0002] Accurate characterization of circuits using intensive models relies heavily on precise modeling of MOSFET current. This is because the inversion layer charge of a MOSFET is influenced by the capacitance of the front gate oxide layer, and the current magnitude must be based on accurate physical parameters. When there is a deviation between the front gate oxide layer capacitance and the buried oxide layer capacitance, it not only affects the current output characteristics but also leads to serious problems with the MOSFET's load characteristics. In the actual CV characteristic characterization of MOSFETs, the MOSFET channel capacitance Cgc and the MOSFET gate capacitance Cgg are measured as the main capacitance model parameters.

[0003] For MOSFETs using FDSOI substrates, the buried oxide layer is thicker than the front gate, resulting in a higher back-gate inversion threshold voltage. Therefore, directly testing the back-gate structure using the CV method is limited by the machine's voltage bias range, making back-gate inversion impossible. Furthermore, excessively high voltage bias may cause back-gate breakdown. Thus, back-gate inversion is not supported in the FDSOI process. Figure 1 The diagram shows a typical MOSFET structure using an FDSOI substrate. Clearly, this unique structure makes obtaining the capacitance and thickness of the front gate oxide and buried oxide layers extremely difficult. Without accurate measurement and extraction of these two capacitances, it is impossible to accurately model the MOSFET using an FDSOI substrate, thus affecting the simulation and design of the entire circuit.

[0004] Therefore, how to accurately extract the capacitance and thickness of the front gate oxide and buried oxide layer of a MOSFET using an FDSOI substrate is a problem that needs to be solved by existing technologies. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for extracting the capacitance model of a MOSFET on a fully depleted SOI substrate, which can accurately extract the capacitance of the front gate oxide layer and buried oxide layer of the MOSFET using an FDSOI substrate.

[0006] To address the aforementioned problems, this invention provides a method for extracting the capacitance model of a MOSFET on a fully depleted SOI substrate, comprising the following steps: shorting the source and drain of the MOSFET and providing a small AC voltage signal; providing a DC bias on the back gate; the DC bias causes the channel region to be in an accumulation and inversion state; and measuring the small AC current signal at the gate of the MOSFET in both states to obtain the channel capacitance Cgc; shorting the source and drain of the MOSFET to the back gate and providing a small AC voltage signal; measuring the small AC current signal at the gate of the MOSFET to obtain the gate capacitance Cgg; and calculating the front gate oxide capacitance Cox and the buried oxide capacitance Cbox based on the measured channel capacitance Cgc and gate capacitance Cgg.

[0007] This invention reconstructs the capacitance model based on the characteristics of fully depleted SOI substrates, enabling accurate extraction of the capacitance of the front gate oxide and buried oxide layers of MOSFETs using FDSOI substrates. Attached Figure Description

[0008] Appendix Figure 1 The diagram shows a typical MOSFET structure using an FDSOI substrate in the prior art.

[0009] Appendix Figure 2 This is a schematic diagram of the gate capacitance distribution of a MOSFET using an FDSOI substrate in a specific embodiment of the present invention.

[0010] Appendix Figure 3 This is a schematic diagram of the body capacitance distribution of an FDSOI MOSFET biased in accumulation and inversion states according to a specific embodiment of the present invention.

[0011] Appendix Figure 4 This is a diagram showing the MOSFET bias state and equivalent capacitance distribution in the Cgc accumulation region according to a specific embodiment of the present invention. Figure 4 The left side shows the MOSFET bias state in the Cgc accumulation region, and the right side shows the equivalent capacitance distribution of the Cgc accumulation region.

[0012] Appendix Figure 5 This is a diagram showing the bias state and equivalent capacitance distribution of the MOSFET in the Cgc inversion region according to a specific embodiment of the present invention. The left side shows the bias state of the MOSFET in the Cgc inversion region, and the right side shows the equivalent capacitance distribution of the Cgc inversion region.

[0013] Appendix Figure 6 This is a diagram showing the MOSFET bias state and equivalent capacitance distribution in the Cgg accumulation region according to a specific embodiment of the present invention, where the left side shows the MOSFET bias state in the Cgg accumulation region and the right side shows the equivalent capacitance distribution in the Cgg accumulation region. Detailed Implementation

[0014] The following detailed description, in conjunction with the accompanying drawings, illustrates the specific implementation of the capacitance model extraction method for MOSFETs on fully depleted SOI substrates provided by this invention.

[0015] Figure 2 A schematic diagram of the gate capacitance distribution of a MOSFET using an FDSOI substrate is given, in which the gate structure can be divided into five parts. Region (1) is the gate of the MOSFET, region (2) is the body region of the MOSFET, and regions (3) and (4) are the overlapping regions of the source and drain regions of the MOSFET, respectively. When the MOSFET is inverted, region (2) will be filled with minority carriers and together with regions (3) and (4) will form the lower plate of the gate capacitance. Because the source and drain injection can diffuse laterally during MOSFET formation, the source and drain regions overlap with the gate part. This part cannot provide additional current conduction capability because the doping is opposite to that of the body region. Region (5) is an interface layer of high-k dielectric and metal stacked to form the gate electric field. Because the doping types of the source and drain are different from those of the body region, the lower plate of the gate capacitance shown in the figure will be divided into three parts. By decomposing the capacitance of each part by characterizing the CV characteristics of the MOSFET, important MOSFET process parameters such as MOSFET capacitance can be obtained.

[0016] Figure 3 This diagram illustrates the body capacitance distribution of an FDSOI MOSFET under accumulation and inversion bias states. The gate oxide capacitance Cox remains constant, but the body capacitance varies significantly due to the electric field. Taking an n-MOSFET as an example, when the gate bias is negative, the vertical electric field attracts majority carriers in the body region, leading to majority carrier accumulation on the MOSFET surface and preventing source / drain conduction. As the MOSFET bias increases, the MOSFET attracts minority carriers below the gate, resulting in a depletion layer in the body region due to the loss of minority carriers. In this case, the equivalent capacitance in the vertical direction of the MOSFET body region is a series connection of the gate oxide capacitance Cox, the body capacitance Cdep, and the buried oxide capacitance Cbox.

[0017] This specific embodiment proposes a more reliable extraction method for the capacitance model of the MOSFET on the fully depleted SOI substrate described above, including the following steps: Step S11, short-circuit the source and drain of the MOSFET and provide a small AC voltage signal, and provide a DC bias on the back gate. The DC bias causes the channel region to be in an accumulation and inversion state, and the small AC current signal at the gate of the MOSFET is measured in the above two states respectively to obtain the channel capacitance Cgc; Step S12, short-circuit the source and drain of the MOSFET with the back gate and provide a small AC voltage signal, and measure the small AC current signal at the gate of the MOSFET to obtain the gate capacitance Cgg; Step S13, calculate the front gate oxide capacitance Cox and the buried oxide capacitance Cbox based on the measured channel capacitance Cgc and gate capacitance Cgg.

[0018] Referring to step S11, short-circuit the source and drain of the MOSFET and provide a small AC voltage signal. Apply a DC bias to the back gate. The DC bias puts the channel region in an accumulation and inversion state. Measure the small AC current signal at the gate of the MOSFET in both states to obtain the channel capacitance Cgc. The capacitance can be tested using a Keysight B1500A or other similar instrument.

[0019] Specifically, the Cgc measurement method is as follows: the source and drain of the MOSFET are shorted and a small AC voltage signal is provided, and a DC bias is provided on the back gate. The small AC current signal at the gate of the MOSFET is measured and can be calculated by the following formula:

[0020]

[0021] Where ii(g) is the imaginary part of the AC current signal measured at the gate of the MOSFET, v(ds) is the small-signal amplitude of the AC voltage applied to the drain and source of the MOSFET, and f is the AC signal measurement frequency. Because the MOSFET channel capacitance distribution can change with the MOSFET voltage bias, the Cgc of the MOSFET usually requires scanning the source and drain voltages. In the experiment, the DC bias voltage of the MOSFET gate was set to 0V, and the DC bias voltages of the MOSFET source and drain were scanned from Vdd to -Vdd, with the back gate bias following the source and drain biases. This inverted connection method is used because the LCR meter can only provide DC bias and AC voltage at the Hi terminal, and only provide power ground and monitor AC current at the Lo terminal. If a forward bias voltage DCIV is used, the AC current of the MOSFET will be shunted in the substrate, leading to measurement errors.

[0022] Figure 4 Diagram showing the MOSFET bias state and equivalent capacitance distribution in the Cgc accumulation region. Figure 4The left image shows the MOSFET bias state in the Cgc accumulation region, and the right image shows the equivalent capacitance distribution of the Cgc accumulation region. The MOSFET gate can overlap with the source / drain region of the MOSFET to form the upper and lower plates of the capacitor. The area of ​​the plates is determined by the overlapping area of ​​the lower plate. From the formula for a parallel-plate capacitor, we can determine the channel capacitance C in the MOSFET accumulation region. gc，acc The following relationship exists:

[0023] C gc,acc =C gso +C gdo (2)

[0024] Among them, C gso With C gdo These are the overlapping capacitances formed by the source, drain, and gate of the MOSFET, respectively. As can be seen from the above relationship, the MOSFET channel capacitance is composed of the overlapping capacitances of the MOSFET source and drain. This is because the AC signal entering from the source and drain ends can only exchange charges with the plate portion of the overlapping region. Although there are free charges with majority carriers below the body region, the isolation relationship between the drain and source and the body region prevents the plate capacitance of the body region from being connected to the potential.

[0025] Figure 5 The diagram shows the bias state and equivalent capacitance distribution of a MOSFET in the Cgc inversion region. The left side shows the MOSFET bias state in the Cgc inversion region, and the right side shows the equivalent capacitance distribution in the Cgc inversion region. The MOSFET gate and channel together form the upper and lower plates of the capacitor, with the area of ​​the plates determined by the upper plate, i.e., the width and length of the MOSFET gate. The inversion region channel capacitance C of the MOSFET is shown below. gc，inv The following relationship exists:

[0026]

[0027] Where C inv The capacitance formed by the MOSFET inversion layer is due to the attraction of a large number of free electrons on the lower surface of the MOSFET during inversion operation, causing the body region of the MOSFET to conduct with the source and drain. At this time, the area of ​​the capacitor plate changes from the overlapping portion of the accumulation region to the entire MOSFET channel. By transforming the above equation, we can obtain the thickness of the front gate oxide layer, i.e., the MOSFET dielectric layer, when the MOSFET is operating in the inversion region:

[0028]

[0029] Continuing with step S12, short-circuit the source, drain, and back gate of the MOSFET and provide a small AC voltage signal. Measure the small AC current signal at the gate of the MOSFET to obtain the gate capacitance Cgg.

[0030] The typical method for measuring the gate capacitance Cgg is as follows: the source, drain, and back gate of the MOSFET are shorted together and a small AC voltage signal is provided. A small AC current signal is then measured at the gate of the MOSFET. The capacitance can be calculated using the following formula:

[0031]

[0032] Measuring MOSFET channel capacitance provides information on the MOSFET gate thickness and overlap region, but it's insufficient for characterizing the MOSFET load because the body region still contributes a significant portion of the capacitance when the MOSFET is used as a load. To allow small AC signals to flow through the body region, in the FDSOI Cgg test, we simultaneously connect the Hi terminal to the MOSFET's back gate. Figure 6 As shown, because the back gate of the MOSFET is connected to the AC path, compared to Cgc, the capacitance composition in the accumulation region increases the contribution of the branch current through the body region. Its equivalent capacitance can be expressed by the following relationship:

[0033]

[0034] Where C box This refers to the buried oxide layer capacitance of the MOSFET.

[0035] From the Cgg measurement above, we decompose the buried oxide capacitance and buried oxide dielectric thickness of the MOSFET from the corresponding current contribution component by passing the small AC signal through the back gate structure. Since the MOSFET body region is in the accumulation region and has no capacitance, its channel capacitance path is a series connection of the front gate and the buried oxide capacitance, where the buried oxide capacitance Cbox can be expressed by the following equation:

[0036]

[0037] Figure 6 The diagram shows the MOSFET bias state and equivalent capacitance distribution in the Cgg accumulation region, with the left side showing the MOSFET bias state in the Cgg accumulation region and the right side showing the equivalent capacitance distribution in the Cgg accumulation region.

[0038] Continuing with step S13, the front gate oxide capacitance Cox and buried oxide capacitance Cbox are calculated based on the measured channel capacitance Cgc and gate capacitance Cgg.

[0039] From the above formulas (1)-(7), we can derive:

[0040] Cox = C gc,inv (8)

[0041]

[0042] To further verify the reliability of the simulation results, we calculated the front gate oxide thickness Tox and the buried oxide thickness Tbox using these results.

[0043]

[0044]

[0045] Extracting values Actual process target value Front gate oxide thickness Tox 1.36nm 1.32nm Tbox of buried oxygen layer thickness 19.8nm 20nm

[0046] Table 1 Comparison of extracted device feature parameters with actual process target values

[0047] Table 1 compares the device characteristic parameters extracted using the above formula with the actual process target values. The extracted gate oxide capacitance value of 1.36 nm is extremely close to the process target value of 1.32 nm, while the extracted buried oxide layer thickness value of 19.8 nm is almost identical to the process target value. These results demonstrate the accuracy of the above process parameter extraction process.

[0048] The above description is only a preferred embodiment of the present invention. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principle of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A method for extracting the capacitance model of a MOSFET on a fully depleted SOI substrate, characterized in that, Includes the following steps: The source and drain of the MOSFET are shorted and a small AC voltage signal is applied. A DC bias is applied to the back gate, causing the channel region to be in an accumulation and inversion state. The small AC current signal at the gate of the MOSFET is measured under both states to obtain the channel capacitance Cgc. The channel capacitance of the MOSFET in the accumulation region can be determined using the formula for a parallel-plate capacitor. The following relationship exists: in, and These are the overlapping capacitances formed by the source, drain, and gate of the MOSFET. MOSFET inversion region channel capacitance The following relationship exists: in T is the capacitance formed by the inversion layer of the MOSFET. ox This refers to the thickness of the front gate oxide layer, i.e., the MOSFET dielectric layer. By shorting the source, drain, and back gate of a MOSFET and applying a small AC voltage signal, and measuring a small AC current signal at the MOSFET gate, the gate capacitance Cgg is obtained. The capacitance of Cgg in the accumulation region increases the contribution of the branch current passing through the body region, and its equivalent capacitance can be expressed by the following relationship: in For buried oxide layer capacitance of MOSFET; The front gate oxide capacitance Cox and buried oxide capacitance Cbox are calculated based on the measured channel capacitance Cgc and gate capacitance Cgg. The calculation methods include: 。 2. The method according to claim 1, characterized in that, In the step of measuring the channel capacitance Cgc, the gate bias DC bias of the MOSFET is further set to 0V, and the source and drain DC bias of the MOSFET are scanned from Vdd to -Vdd, while the back gate bias is scanned following the source and drain bias.

3. The method according to claim 1, characterized in that, In the step of measuring the gate capacitance Cgg, the gate bias voltage of the MOSFET is further set to 0V, the MOSFET's terminal, drain, and back gate are shorted, and a DC bias voltage is applied to scan from Vdd to -Vdd. The back gate bias follows the source-drain and back gate biases for scanning.

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