Crosstalk reduction using trace coupling in integrated circuit assemblies

Abstract

Aspects of the embodiments disclosed herein include electrical systems that reduce crosstalk, such as far-end crosstalk (FEXT), between two or more signal paths of a memory system by electromagnetically coupling the two or more signal paths, each including a respective trace. Electromagnetically coupling the two or more respective traces includes positioning at least two traces in close proximity to one another such that a mutual inductance ratio (Lm / L) between the at least two signal paths matches or substantially matches a mutual capacitance ratio (Cm / C) between the at least two signal paths. Certain embodiments of the present disclosure relate to reducing FEXT between any number of signal paths without adding passive means of traces whose sole purpose is to reduce crosstalk, thereby reducing or maintaining signal density between components of an IC package design.

Description

Background Technology

[0001] In the context of data storage accessed by computer systems, large disk storage devices, initially up to six feet in size, were replaced by much smaller hard disk drives (HDDs). Generally, a hard disk drive (HDD) is a traditional storage device with a rotating platter for reading and writing data. HDDs utilize a mechanical rotating platter and a moving read / write head to access data, while integrated circuit (IC) packages typically use smaller memory chips that store information on random access memory (RAM) devices, such as dynamic random access memory (DRAM) devices, without any mechanical rotating platters. As computing demands increased, these HDDs were later replaced by IC packages that were smaller, faster, quieter, and more durable than HDDs.

[0002] Furthermore, the growth of cloud computing and, more recently, artificial intelligence (AI) has led to the wider adoption of compact IC packages in certain data centers and consumer electronics products. In some contexts, IC packages are more popular than HDDs due to their efficient and compact storage, resulting in an increased reliance on IC packages for certain storage and computing functions. With the increasing demand for memory bandwidth and capacity, memory systems face the problem of crosstalk. Crosstalk is typically caused by electromagnetic interference between closely packed communication lines in silicon, IC packages, and printed circuit boards, leading to noise and errors in data transmission. In some memory systems, this problem is exacerbated by high-frequency and parallel data transmission. Despite the existence of some mitigation techniques, crosstalk remains a significant issue in memory system design as higher memory performance continues to be an industry goal. Summary of the Invention

[0003] The various aspects of the techniques described herein generally relate to systems, methods, and computer storage media for reducing crosstalk (such as far-end crosstalk (FEXT)) between two or more signal paths in a memory system by electromagnetically coupling two or more traces. Electromagnetically coupling the two or more traces includes positioning at least two traces close to each other such that the mutual inductance ratio (Lm / L) between the at least two signal paths matches or substantially matches the mutual capacitance ratio (Cm / C) of the at least two signal paths. Taking two traces in an integrated circuit (IC) package as an example, electromagnetically coupling the first and second traces includes causing the first or second trace to generate a crosstalk cancellation pulse having an amplitude substantially similar to and opposite polarity to the crosstalk between the first and second signal paths, which are respectively portions of the two signal paths.

[0004] The aspects of the embodiments disclosed herein reduce crosstalk by coupling at least two traces, which perform functions other than crosstalk reduction. The aspects of the embodiments disclosed herein include an IC system, such as an IC package or an IC package component, the system including at least two traces, such as a first trace and a second trace. The first trace extends within the IC system between a first end and a second end, and a first signal travels along the first trace from the first end to the second end. Embodiments of the first trace have a shape defined by a first segment, a second segment, and a third segment between the first and second ends. The second trace extends within the IC system between a corresponding first end and a corresponding second end, and a second signal travels along the second trace. The second trace has a shape defined by a corresponding first segment, a corresponding second segment, and a corresponding third segment. A corresponding second segment of the second trace is electromagnetically coupled to a second segment of the first trace to reduce far-end crosstalk (FEXT) between the first and second traces by controlling a first signal to travel along the second segment in a direction opposite to the direction along which the second signal travels along the corresponding second segment of the second trace. Electromagnetic coupling is achieved by designing a corresponding second segment of the second trace such that the corresponding second segment generates a crosstalk cancellation pulse having an amplitude substantially similar to and opposite to the FEXT between the first and second signal paths.

[0005] Accordingly, embodiments of this disclosure at least partially remedy certain technical deficiencies in existing circuit systems associated with electronic devices, such as components in IC packages. Certain embodiments of this disclosure reduce the FEXT (Frequency Exceeded Length) between any number of traces without increasing the number of traces, with the sole purpose of reducing crosstalk, thereby reducing or maintaining signal density between IC package component designs. Furthermore, electromagnetically coupled traces bring two or more traces within an IC package component closer together, thereby reducing the size of the IC package component and achieving increased computing power compared to devices of similar size. Moreover, as disclosed herein, this higher computing efficiency, lower FEXT, and smaller size design can be extended to various IC packages without adding unnecessary isolation traces by electromagnetically coupling two or more traces.

[0006] This summary is provided to introduce, in a simplified form, some concepts that will be further described in the detailed embodiments described below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to help determine the scope of the claimed subject matter. Attached Figure Description

[0007] The technology described herein will be described in detail below with reference to the accompanying drawings, in which:

[0008] Figure 1AA block diagram of an example integrated circuit package applicable to the implementation of various aspects of the techniques described herein is depicted;

[0009] Figure 1B A schematic diagram depicting an example cross-sectional view of an integrated circuit package illustrating various aspects of the technology described herein;

[0010] Figure 1C A schematic diagram illustrating two traces carrying corresponding signals is depicted according to various aspects of the technology described herein;

[0011] Figure 2A A schematic diagram illustrating two traces forming a coupled trace pair with a heterogeneous coupling relationship is depicted according to various aspects of the technology described herein.

[0012] Figure 2B The diagram illustrates the formation of coupled trace pairs with heterogeneous coupling relationships according to various aspects of the technology described herein. Figure 2A A schematic diagram of the current flow between the two traces;

[0013] Figure 3A A schematic diagram illustrating two traces forming a coupled trace pair having an in-phase coupling relationship is depicted according to various aspects of the technology described herein.

[0014] Figure 3B The diagram illustrates the formation of coupled trace pairs with in-phase coupling, based on various aspects of the technology described herein. Figure 3A A schematic diagram of the current flow between the two traces;

[0015] Figure 4A A schematic diagram illustrating two traces forming a coupled trace pair and having two loops in two adjacent planes, according to various aspects of the technology described herein;

[0016] Figure 4B A schematic diagram illustrating two traces forming a coupled trace pair and having two loops in the same plane, according to various aspects of the technology described herein;

[0017] Figure 4C A schematic diagram of two traces, which form a coupled trace pair and have two loops at different vertical positions, is depicted according to various aspects of the technology described herein.

[0018] Figure 4D A schematic diagram illustrating two traces forming a coupled trace pair and having a sharp corner is depicted according to various aspects of the technology described herein.

[0019] Figure 5AA first circuit diagram is depicted according to various aspects of the technology described herein, showing two traces that are not electromagnetically coupled in a segment highlighted by a dashed rectangular box;

[0020] Figure 5B A second circuit diagram is depicted according to various aspects of the technology described herein, showing two traces electromagnetically coupled in an out-of-phase inductive relationship in a segment highlighted by a dashed rectangular box;

[0021] Figure 5C A third circuit diagram is depicted according to various aspects of the technology described herein, showing two traces inductively coupled in phase inductively in a segment highlighted by a dashed rectangular box.

[0022] Figure 5D This describes various aspects of the technology described in this article. Figure 5B The second circuit diagram or Figure 5C The heatmap of the two magnetic field contour maps associated with the third circuit diagram;

[0023] Figure 6A A schematic diagram of a system comprising multiple traces according to various aspects of the technology described herein is depicted, each trace forming multiple coupled trace pairs;

[0024] Figure 6B A schematic diagram of a system comprising multiple traces according to various aspects of the technology described herein is depicted, each trace forming at least one coupled trace pair;

[0025] Figure 7A A schematic diagram of a first system comprising two example differential trace pairs according to various aspects of the techniques described herein is depicted, the two differential trace pairs forming a coupled trace pair between two differential signal pairs;

[0026] Figure 7B A schematic diagram of a second system comprising two example differential trace pairs according to various aspects of the techniques described herein is depicted, the two differential trace pairs forming a coupled trace pair between two differential signal pairs;

[0027] Figure 8 An example method is described, based on various aspects of the techniques described herein, for modifying a proposed design layout of an integrated circuit package or printed circuit board (PCB) to generate an updated proposed design layout that undergoes fewer FEXTs compared to the original proposed design layout.

[0028] Figure 9A Example embodiments of this disclosure, including tested and simulated example IC packages, are depicted in practice according to various aspects of the techniques described herein.

[0029] Figure 9BThis describes various aspects of the technology described in this article, including those that have been put into practice, tested, and simulated. Figure 9A Insertion loss results for example embodiments;

[0030] Figure 9C This describes various aspects of the technology described in this article, including those that have been put into practice, tested, and simulated. Figure 9A The results of the far-end crosstalk (FEXT) in the example embodiment;

[0031] Figure 10A This describes various aspects of the technology described in this article, as well as those already put into practice. Figure 9A The voltage step response associated with the example embodiment;

[0032] Figure 10B This describes various aspects of the technology described in this article that have already been put into practice. Figure 9A Crosstalk response in an example embodiment;

[0033] Figure 11A Eye diagrams are depicted illustrating time-domain simulations of all channels for aspects not employing the embodiments disclosed herein;

[0034] Figure 11B The description illustrates the approach to [the application of] [technology], as well as [technology] derived from [experiences], including [technology], [testing], and [simulation]. Figure 9A The example implementation corresponds to the eye diagram of the full-channel time-domain simulation;

[0035] Figure 12 A block diagram depicts an example distributed computing environment suitable for use in implementing various aspects of the techniques described herein; and

[0036] Figure 13 This is a block diagram of an example computing device applicable to the implementation of various aspects of the techniques described herein. Detailed Implementation

[0037] The subject matter of various aspects of this disclosure is specifically described herein to satisfy legal requirements. However, this description itself is not intended to limit the scope of this patent. Rather, the subject matter claimed in this disclosure is contemplated to be implemented in other ways in combination with other existing or future technologies to include different steps or combinations of steps similar to those described in this document. Furthermore, although the terms “step” and / or “box” may be used herein to refer to different elements of the methods employed, these terms should not be construed as implying any particular order between the steps disclosed herein unless the order of the individual steps is explicitly described. Each method described herein may include a computational process that can be performed using any combination of hardware, firmware, and / or software. For example, various functions may be performed by a processor executing instructions stored in memory. The method may also be implemented as computer-usable instructions stored on a computer storage medium. The method may be provided as a standalone application, service, or managed service (independent of or in combination with another managed service), or a plug-in to another product, etc.

[0038] The various aspects of the technology described herein generally relate to systems, methods, and computer storage media for reducing crosstalk (such as far-end crosstalk (FEXT)) between two or more traces in a memory system by electromagnetically coupling two or more traces. In one example, a "trace" refers to a wire or conductive path that carries or transmits a signal along a conductive path from one electronic component to another to electrically couple the two electronic components. In one example, a "trace" refers to a portion of a "signal path" that carries a corresponding signal. In one example, a trace is soldered to a pin or pad, for example, to further guide the corresponding signal along the signal path. In one example, the term "trace" includes multiple conductive paths, such as conductive paths forming a "differential pair," as... Figure 7A and Figure 7B As illustrated in the diagram. The conductive path can be any suitable shape, such as a shape having straight sections, curved sections, or any combination thereof, along any suitable three-dimensional (3D) or two-dimensional (2D) path, such as... Figure 2A , Figure 3A , Figure 4A , Figure 4B , Figure 4C and Figure 4D The paths illustrated in the diagram. Example traces include leads that couple components outside the IC package to components on, inside, or within the IC package. In another example, the trace includes internal conductive paths that electrically couple components on, inside, or within the IC package.

[0039] In one example, “electromagnetic coupling” of two or more traces includes positioning at least two traces close to each other such that the mutual inductance ratio (Lm / L) between at least two signal paths, each of the two traces being a portion of the total signal path, is matched or substantially matched with the mutual capacitance ratio (Cm / C) between at least two signal paths, each of the two traces being a portion of the total signal path. In one example, electromagnetic coupling is both inductive and capacitive effects between at least two traces, with inductive effects being more prevalent. In one example, “closely adjacent” means that the distance between the two traces is less than or equal to 50 micrometers, such as 50 micrometers, 30 micrometers, 25 micrometers, 15 micrometers, etc., or any value in between. However, other distances are also possible, such as 100, 300, and 500 micrometers, etc., especially when more than two traces are electromagnetically coupled.

[0040] More efforts have been made to reduce size while increasing the capabilities of circuits, memory devices, computers, and other electronic products. However, this presents many challenges because expanding electronic functionality, increasing computing power, and improving responsiveness often requires adding hardware components to these devices. The addition of these hardware components increases the number of traces in electronic devices. In the context of small integrated circuit (IC) packages, these small devices and the large number of traces within the IC package can lead to crosstalk. Generally, "crosstalk" refers to unwanted coupling or interference caused by the electric or magnetic field of one telecommunications signal on one trace affecting another telecommunications signal on an adjacent trace. In some cases, crosstalk prevents certain electronic components, such as memory buses, from operating at higher speeds and higher levels of efficiency. One existing method to reduce crosstalk is to keep signals away from each other. However, this solution increases the size and cost of some IC packages, and in some cases, it is impractical given the size of certain IC packages. Another existing method to reduce crosstalk is to add more ground pins to increase isolation between traces and their corresponding signals. However, this solution is expensive and requires packaging additional components (e.g., ground pins) into the already space-constrained IC package.

[0041] In view of this, aspects of the embodiments disclosed herein reduce crosstalk by coupling at least two traces that perform functions other than crosstalk reduction. Taking two traces of an integrated circuit (IC) package as an example, electromagnetically coupling the first and second traces includes causing either the first or second trace to generate a crosstalk cancellation pulse having an amplitude substantially similar to and opposite to the crosstalk between the first and second traces. Some embodiments disclosed herein do not add a ground pin to the IC package, intending only to use the added ground pin to isolate the traces. Instead, some aspects of the embodiments disclosed herein include IC packages with traces closely adjacent to each other, transmitting signals that: (1) communicatively couple components (e.g., receivers and transceivers within the IC package), and (2) additionally generate a crosstalk cancellation pulse.

[0042] In this manner, embodiments of this disclosure preserve the signal density of the IC package between a first version of the IC package design and a second version of the IC package, thereby reducing crosstalk without adding traces or ground pins to different versions of the IC package design. As used herein, in one example, "signal density" refers to the concentration of signals within a given area or volume of the IC package. Thus, signal density can be a measure of the number of signals or components packaged within a specific space of the IC package. In one embodiment, for example, increasing the size (e.g., length) of a trace does not increase the signal density, because increasing the trace size may reduce the number of signals in a given space, and increasing the trace size does not necessarily increase the amplitude of the signal.

[0043] Embodiments of this disclosure include an IC system comprising at least two traces, such as a first trace and a second trace. In some embodiments, the first trace extends within the IC system between a first end and a second end, and a first signal travels along the first trace from the first end to the second end. Embodiments of the first trace have a shape defined by a first segment, a second segment, and a third segment between the first and second ends. In some embodiments, the second trace extends within the IC system between a corresponding first end and a corresponding second end, and a second signal travels along the second trace. Embodiments of the second trace have a shape defined by a corresponding first segment, a corresponding second segment, and a corresponding third segment. In some embodiments, a corresponding second segment of the second trace is electromagnetically coupled to a second segment of the first trace to reduce far-end crosstalk (FEXT) between the first and second traces.

[0044] In some embodiments, FEXT caused by crosstalk between signal paths (such as a first signal path and a second signal path) is reduced by a crosstalk cancellation pulse (also referred to in one example as a "second induced current") generated or induced by a trace pair (such as a trace pair formed by the first trace and the second trace). In one example, the first signal path includes a first trace, and the second signal path includes a second trace. In one example, FEXT is reduced by controlling the first signal such that the first signal travels along a second segment in a direction opposite to the direction in which the second signal travels along the corresponding second segment of the second trace. For example, FEXT is reduced by controlling the first signal such that the first signal travels along the second segment in a direction in which a second induced current is induced in the corresponding second segment of the second trace, such that the second induced current is induced in a direction opposite to the direction in which the first induced current travels along the corresponding second segment of the second trace. In one example, the first induced current appears outside the first and second traces (e.g., in other regions of the first or second signal path). For example, the first induced current arises due to electromagnetic coupling between two parts at other locations (e.g., between the first and second signal paths), such as in package areas other than the two traces, sockets, PCBs, connectors, silicon wafers, etc. In one embodiment, electromagnetic coupling is achieved by designing a corresponding second segment of the second trace to generate a crosstalk cancellation pulse that has a magnitude substantially similar to and opposite polarity to the FEXT between the first and second traces.

[0045] Embodiments of this disclosure include a method for redesigning an IC package or a portion thereof. In one embodiment, redesigning the IC package is an iterative process completed after FEXT falls below a threshold. In one embodiment, the method for redesigning an IC package or a portion thereof includes receiving a proposed design layout for a portion of the IC package. Based on the proposed design layout, embodiments of this disclosure determine traces that are adjacent to each other within a portion of the integrated circuit package. In one embodiment, the proposed design layout is digitally simulated based on the traces. Based on the trace-based digital simulation, embodiments of this disclosure determine crosstalk between first traces and second traces of a plurality of traces. In one embodiment, the location of coupled trace segment pairs for locating the first and second traces within an assembly of the integrated circuit package is determined. For example, the location of the coupled trace segment pairs is the location where the coupled trace pairs are electromagnetically coupled as described herein. In some embodiments, the proposed design layout is modified to generate an updated proposed design layout, the updated proposed design layout including the coupled trace segment pairs within that portion of the integrated circuit package.

[0046] Accordingly, embodiments of this disclosure at least partially remedy certain technical drawbacks of existing circuit systems associated with electronic devices, such as components in IC packages. Certain embodiments of this disclosure reduce FEXT between any number of traces without adding ground pins or other additional components, with the sole purpose of reducing crosstalk. In this way, certain embodiments of this disclosure provide a passive solution for reducing or maintaining signal density between designs of IC packaged components. Accordingly, in some cases, the amount of material required to implement this embodiment can be zero, thereby facilitating the implementation of extended embodiments. Furthermore, electromagnetic coupling of traces brings two or more traces within an IC packaged component closer together, thereby reducing the size of the IC packaged component and allowing for increased computing power compared to devices of similar size. Moreover, as disclosed herein, by electromagnetically coupling two or more traces, this increased computing efficiency, reduced FEXT, and smaller design size can be extended on the IC package without adding unnecessary isolation traces.

[0047] The various aspects of this technical solution can be described through examples and with reference to the accompanying drawings. Figure 1A An example system 10 is illustrated, which includes an IC package 100 suitable for use in implementing aspects of the techniques described herein. As illustrated, the example IC package 100 includes a memory controller 110 and a plurality of DRAMs 120.

[0048] In some embodiments, the memory controller 110 includes a circuitry that uses electrical signals to direct the entire IC to execute stored program instructions. In one embodiment, the memory controller 110 does not directly execute the program instructions; instead, it directs other parts of the system to do so. For example, the memory controller 110 directs the DRAM 120 to perform arithmetic and logical operations. In one embodiment, the memory controller 110 includes electronic circuitry for performing arithmetic and logical operations, such as those discussed herein. In one embodiment, the memory controller 110 performs any number of arithmetic or mathematical operations, such as addition, subtraction, multiplication, and division. Additionally, in some embodiments, the memory controller 110 also performs logical operations, such as comparisons of any data elements, such as numbers, letters, or special characters. Other logical operations that can be performed by the memory controller 110 include equal to, less than, greater than, less than or equal to, greater than or equal to, and not equal to operations, etc.

[0049] In one example, DRAM 120 refers to random access semiconductor memory, which stores each bit of data in a memory cell, typically composed of small capacitors and transistors. In some embodiments, DRAM 120 accesses data, typically in less than 10 microseconds, and is used to accelerate applications that would otherwise be hampered by the latency of certain solid-state drives (SSDs) or traditional hard disk drives (HDDs). One of the largest applications of DRAM 120 is the main memory (commonly known as random access memory or "RAM") in some computers and graphics cards, where "main memory" is also referred to as graphics memory. DRAM 120 can also be used in many portable devices and video game consoles. Although DRAM 120 is illustrated as being contained within or integrated within IC package 100, it should be understood that in some embodiments, DRAM 120 is external to IC package 100, removably coupled to IC package 100, or decoupled from IC package 100.

[0050] To enable communication between components of IC package 100, such as memory controller 110 and DRAM 120, any suitable computer bus with any number of traces can be used. For example, a computer bus that transmits data on any variation of the rising and / or falling edge of a clock signal can be used. Examples of computer buses include: Single Data Rate (SDR), which transmits one signal per clock cycle; Dual Data Rate (DDR), which transmits two signals per clock cycle; Quad Data Rate (QDR), which transmits four signals per clock cycle; and so on. The embodiments disclosed herein reduce FEXT associated with two or more signals subject to interference. In some embodiments, components outside IC package 100 can interface with components of IC package 100 via leads (in one example, a lead is a type of trace). In practice, although this example is discussed in the context of memory controller 110 and DRAM being communicatively coupled to allow signal transmission via a computer bus, it should be understood that components outside IC package 100 can also communicate with components within IC package 100.

[0051] Additionally, although Figure 1A This description is set within the context of an IC package 100 with specific components, but the various embodiments disclosed herein are also applicable to other electronic devices, such as SSDs. In one example, SSD 122 is a modular memory device that incorporates DRAM and NAND (non-AND) flash memory devices, among others. Example SSDs include those manufactured or configured by companies associated with ATP®, INTEL®, KIOXIA®, MICRON®, NVIDIA®, and SAMSUNG ELECTRONICS®.

[0052] Figure 1B A schematic diagram depicts an example cross-sectional view of an integrated circuit package 100 illustrating various aspects of the technology described herein. In one embodiment, the integrated circuit package 100 corresponds to a printed circuit board (PCB) 128. As illustrated, the IC package 100 comprises six layers, but the embodiments described herein are applicable to IC packages 100 having any number of layers. The illustrated IC package 100 includes a top layer 130, a first intermediate layer 131, a second intermediate layer 132, a third intermediate layer 133, a fourth intermediate layer 134, and a bottom layer 136. In this example, the top layer 130 includes any number of surface traces 140 made of any suitable conductive material, such as copper, gold, or aluminum. Embodiments of the top layer 130 allow electronic components external to the IC package 100 to be electrically coupled to the top layer 130 via pins or leads on the external electronic components. In one embodiment, the first intermediate layer 131 includes an internal ground plane that grounds traces in contact with that plane. In one embodiment, the second intermediate layer 132 and the third intermediate layer 133 facilitate the fabrication of the IC package 100. For example, IC package 100 is initially manufactured as three double-sided panels, each corresponding to a top layer 130, a second intermediate layer 132, and a third intermediate layer 133. In one embodiment, a fourth intermediate layer 134 corresponds to a layer carrying, for example, 3.3 volts (3V3) or 1.8 volts (1V8).

[0053] To vertically connect components on each of these layers, embodiments of the IC package 100 include any number of vias 142. In one example, a "via" refers to a conductive path forming a layer-to-layer connection in the IC package, such as the vertical conductive path illustrated. In a first example, the via 142 corresponds to a blind via 142A extending from a surface layer (such as the illustrated top layer 130 or bottom layer 136) to the next corresponding layer. The illustrated example includes a blind via 142A extending from the top layer 130 to a first intermediate layer 131 adjacent to the top layer 130. In a second example, the via 142 corresponds to a buried via 142B extending between two inner layers that are not surface layers. The illustrated example includes a buried via 142B extending from a second intermediate layer 132 to a third intermediate layer 133. In a third example, the via 142 corresponds to a through-via 142C extending through the height of the IC package 100 from the top layer 131 to the bottom layer 136. For example, through-hole 142C is formed by drilling through each layer after the layers have been fabricated and the wiring has been etched, and then using any suitable process (such as chemical plating) to form a conductive through-hole tube in the drilled hole.

[0054] Turn Figure 1CThe illustration shows two traces 150 carrying corresponding signals according to various aspects of the technology described herein. The illustrated embodiment includes a first trace 150 corresponding to a through-hole 142C carrying a first signal, and a second trace 150B corresponding to a through-hole 142C carrying a second signal. As illustrated, traces 150 include stacked vias 152. For example, the first trace 150A includes a first set of stacked vias 152A, while the second trace 150B includes a second set of stacked vias 152B. In one embodiment, the first trace 150A and the second trace 150B carry corresponding signals to or from a receiver or transceiver. For example, the first trace 150A carries and transmits the first signal to or from a pad grid array (LGA) 154. In one example, the LGA 154 is a surface mount package for IC packaging and has a pin or contact grid on the socket (as opposed to pins on the IC, referred to as a "pin grid array" [PGA]). As illustrated, the second trace 150B carries and transmits the second signal to the ball grid array (BGA) 156. In one example, the BGA 156 is a surface mount package for IC packaging and has balls forming contacts. Although trace 150 is shown as being coupled to some type of grid array, it should be understood that the embodiments disclosed herein are not limited to the LGA, PGA, or BGA disclosed herein.

[0055] In some IC packages 100 ( Figure 1A and Figure 1B In a transceiver, trace 150 carries a signal from the transceiver (transmitting the signal) to the receiver intended to receive the signal. For example, the vertical conductive path of the trace is divided into an upper and a lower portion. In this example, the lower portion is connected via a trace to the upper portion of its adjacent signal, and vice versa. In some IC packages 100, the close proximity of two or more traces 150 (in this example, two or more vias 142) causes crosstalk between the two or more traces 150, such as FEXT. Embodiments of this disclosure can reduce or substantially eliminate FEXT.

[0056] Figure 2A A schematic diagram illustrating a portion of an IC package 200 having two traces 150, which form a coupled trace pair 202 having an out-of-phase coupling relationship, is depicted according to various aspects of the technology described herein. In one example, out-of-phase coupling occurs because the first signal travels in the same direction as the second signal, but in the coupling region 202, the two signals travel in opposite directions. For example, as described herein, the first and second signals travel downwards from a first segment to a third segment. Figure 2B The illustration depicts the current flow between these two traces within a portion of the IC package 204. In one embodiment, the illustrated... Figure 2A and Figure 2B The first trace 150A and the second trace 150B correspond to Figure 1C The first trace 150A and the second trace 150B are described in parallel for ease of discussion. Figure 2A and Figure 2B .

[0057] As illustrated, a first trace 150A extends between a first end and a second end, such that a first signal travels from the first end to the second end, or from the second end to the first end. The illustrated first trace 150A has a shape defined by a first segment 211, a second segment 212, and a third segment 213. Similarly, the illustrated second trace 150B extends between a corresponding first end and a corresponding second end, such that a second signal travels from a corresponding first end to a corresponding second end, or from a corresponding second end to a corresponding first end. The illustrated second trace 150B has a shape defined by a corresponding first segment 221, a corresponding second segment 222, and a corresponding third segment 223. However, the embodiments disclosed herein are not limited to traces 150 having three segments, as these embodiments can be implemented with traces 150 having more or fewer segments.

[0058] In one embodiment, the first trace 150A and the second trace 150B are substantially parallel to each other and closely adjacent to each other. For example, the vertical conductive path of the trace is divided into an upper portion (corresponding to the first segments 211 and 221) and a lower portion (corresponding to the third segments 213 and 223). In one embodiment, the lower portion of a signal is connected to the upper portion of its adjacent signal via a trace, and the adjacent signal is connected in the same way. In one embodiment, the two connecting traces are parallel, and the spacing between the second segment 212 and the corresponding second segment 222 is very small (e.g., less than or equal to 50 micrometers, such as 50 micrometers, 30 micrometers, 25 micrometers, 15 micrometers, etc., or any value in between), or closely coupled. In the trace coupling section 202, the two signals travel in opposite directions.

[0059] In one embodiment, the first distance between the first segment 211 of the first trace 150A and the corresponding first segment 221 of the second trace 150B is greater than the second distance between the second segment 212 of the first trace 150A and the corresponding second segment 222 of the second trace 150B. In another embodiment, the third distance between the third segment 213 of the first trace 150A and the corresponding third segment 223 of the second trace 150B is greater than the second distance.

[0060] In some embodiments, as a second signal for the current 230 traveling along the second trace 150B, the first induced current ( Figure 2AThe first current (not shown) is induced within IC package 200 (e.g., in a component separate from the illustrated first trace 150A or second trace 150B). For example, the first current is induced in other parts of IC package 200, a printed circuit board, a connector, or any other location other than where the coupling trace pair 202 is formed. In one example, "current" includes alternating current (AC) or direct current (DC). In this example, the second trace 150B is the attacker inducing the first induced current, which travels along the first trace 150A at a location different from the illustrated coupling trace pair 202 via electromagnetic coupling. In this example, the first trace 150A is the victim trace. In some cases, the first induced current causes far-end crosstalk (FEXT). To reduce this FEXT, in one embodiment, a corresponding second segment 222 of the second trace 150B is electromagnetically coupled to a second segment 212 of the first trace 150A to reduce far-end crosstalk (FEXT) associated with the first induced current. In one embodiment, the FEXT associated with the first induced current is reduced by controlling a second signal (e.g., current 230) such that the second signal travels along a corresponding second segment 222 in the direction in which a second induced current 232 is induced in the second segment 212 of the first trace 150A. In this example, the second induced current 232 is induced in the opposite direction and / or with the opposite amplitude to the first induced current (e.g., induced current) traveling along the second segment 212 of the first trace 150A, thereby canceling the induced current and reducing FEXT. As described herein, the electromagnetic coupling of the second segments 212 and 222 generates a crosstalk cancellation pulse having a magnitude substantially similar to and opposite to the first induced current causing FEXT between the first trace 150A and the second trace 150B.

[0061] Figure 3A A schematic diagram illustrating a portion of an IC package 300 having two traces 150, according to various aspects of the technology described herein, is provided. These two traces form a coupled trace pair 302 having an in-phase coupling relationship 302. In one example, in-phase coupling occurs because a first signal travels in the same direction as a second signal, including within the coupling region 302. For example, as described below, the first signal travels downwards from a first segment 311 of the first trace 150A to a third segment 313, while the second signal travels downwards from a first corresponding segment 321 of the second trace 150B to a third corresponding segment 323. Figure 3B A schematic diagram of system 304, illustrating various aspects of the technology described herein, is provided, showing the formation of a pair of coupled traces 302 having in-phase coupling. Figure 3A The current flows between the two traces. Figure 3A and Figure 3B It is described in parallel.

[0062] As illustrated, a first trace 150A extends between a first end and a second end, such that a first signal travels from one end to the other. The illustrated first trace 150A has a shape defined by a first segment 311, a second segment 312, and a third segment 313. Similarly, the illustrated second trace 150B extends between a corresponding first end and a corresponding second end, such that a second signal travels from one end to the other in the same direction as the first signal. The illustrated second trace 150B has a shape defined by a corresponding first segment 321, a corresponding second segment 322, and a corresponding third segment 323. However, the embodiments disclosed herein are not limited to a trace 150 having three segments, as these embodiments can be implemented with a trace 150 having more or fewer segments. In one embodiment, the length of the second segment 312 or the corresponding second segment 322 corresponds to a distance offset 324 between the two components. For example, distance offset 324 defines the distance by which the portion of IC 100 corresponding to the BGA pad is separated from another portion of IC 100 corresponding to the port via (PTH) side.

[0063] In one embodiment, the first trace 150A and the second trace 150B are substantially parallel to each other and closely adjacent to each other. For example, the vertical conductive path of the trace is divided into an upper portion (corresponding to the first segments 311 and 321) and a lower portion (corresponding to the third segments 313 and 323). In one embodiment, the two connecting traces are parallel, and the spacing between the second segment 312 and the corresponding second segment 322 is very small (e.g., less than or equal to 50 micrometers, such as 50 micrometers, 30 micrometers, 25 micrometers, 15 micrometers, etc., or any value in between), or tightly coupled. In the trace coupling segment 302, the two signals travel in the same direction.

[0064] In some embodiments, as a second signal for the current 330 traveling along the second trace 150B, the first induced current ( Figure 2AThe first current (not shown) is induced within IC package 300 (e.g., in a component separate from the illustrated first trace 150A or second trace 150B). For example, the first current is induced in other parts of IC package 200, printed circuit boards, connectors, or any other location other than where a pair of coupled traces 302 is formed. In this example, the second trace 150B is the attacker, inducing the first induced current in the first trace 150A (which is the victim trace). In some cases, the first induced current causes far-end crosstalk (FEXT). To reduce this FEXT, in one embodiment, a corresponding second segment 322 of the second trace 150B is electromagnetically coupled to a second segment 312 of the first trace 150A to reduce far-end crosstalk (FEXT) associated with the first induced current. In one embodiment, FEXT associated with the first induced current is reduced by controlling a signal (e.g., current 330) such that a second signal travels along the corresponding second segment 222 in the direction in which a second induced current 332 is induced in the second segment 212 of the first trace 150A. In this example, the second induced current 332 is induced as a crosstalk cancellation pulse in the opposite direction and / or with the opposite amplitude to the first induced current traveling along the second segment 312 of the first trace 150A, thereby canceling the induced current and reducing FEXT. As described herein, the electromagnetic coupling to the second segments 312 and 322 includes controlling parameters of the attacker trace (in this example, the second trace 150B), for example, to generate a crosstalk cancellation pulse having a magnitude substantially similar to and opposite polarity to the first induced current causing FEXT between the first trace 150A and the second trace 150B.

[0065] In order to electromagnetically couple the first and second traces, Figure 3A and Figure 3B In the illustrated example, the first segments 311 and 321 are repositioned or rearranged to increase their respective distances; the third segments 313 and 323 are repositioned or rearranged to increase their distances; and the second segments 312 and 322 are repositioned or rearranged to make them closely adjacent to each other (as a pair of coupling traces 302), wherein the distance between them is much smaller than the distance between the first segments 311 and 321 and the third segments 313 and 323.

[0066] As shown in the diagram, Figure 2A and Figure 2B The polarity of the crosstalk cancellation pulse in the attacker's trace. Figure 3A and Figure 3B Those in it are different from the ones mentioned above. For example, for Figure 2A and Figure 2B The out-of-phase coupling relationship shown indicates that the crosstalk cancellation pulse has a positive polarity; while for Figure 3A and Figure 3BThe in-phase coupling relationship shown indicates that the crosstalk cancellation pulse has a negative polarity. This opposite polarity can be explained by Lenz's law and... Figure 2A and Figure 2B ,as well as Figure 3A and Figure 3B This can be explained by the difference in positioning between the first and third segments of the two traces 150. For example, and as... Figure 2A As illustrated, the out-of-phase coupling generated by the attacker's current induces currents in the trace coupling segment 202 that propagate in opposite directions in adjacent traces according to electromagnetic principles (such as Lenz's law) (shown by dashed lines). In the first segments 211 and 221 illustrated (which in one example correspond to vias or pin-through vias) and the third segments 213 and 223 illustrated, the induced currents are in the same direction as the attacker's current. Conversely, in Figure 3A and Figure 3B In the in-phase coupling illustrated, the induced current and the interference current are in opposite directions in the first segments 311 and 321 and the third segments 313 and 323 illustrated. In this example, the difference in the direction of the induced current explains the difference in the polarity of the crosstalk cancellation pulse. Generating a crosstalk cancellation pulse with the same amplitude as the induced current (but in the opposite direction) can bring the amplitude of the resulting FEXT close to zero.

[0067] For a more detailed explanation of the difference in polarity, please refer to Formula 1 below. Where FEXT refers to far-end crosstalk, length ( length () refers to the length of the trace. v It refers to the speed at which a signal travels along a path. This refers to the rise time of the signal. C It refers to the self-capacitance of the trace. Cm It refers to the mutual capacitance between traces. L It refers to the inductance of the trace, and Lm This refers to the mutual inductance between traces. In some cases, a large portion of FEXT is a result of the mutual capacitance and inductance between traces. Embodiments of this disclosure generate crosstalk cancellation pulses to bring the difference between the two ratios in Equation 1 close to zero. When the difference between the ratios is zero, FEXT also approaches zero. In some embodiments, the trace width, the distance between traces, the trace material, or the trace length are varied to obtain the desired crosstalk cancellation pulse and reduce FEXT. For example, the trace length is based on ( Figure 2AThe arrangement includes (1) the distance between the first segment and the corresponding first segment, and (2) the distance between the third segment and the corresponding third segment and their respective proximity. In this example, increasing the length of the second segment can reduce FEXT by generating a stronger crosstalk cancellation pulse. Accordingly, some embodiments of this disclosure reduce the difference between the first ratio and the second ratio, such that the first ratio is the ratio between the mutual capacitance of the first and second signal paths and the self-capacitance of the first or second signal path, while the second ratio is the ratio between the mutual inductance of the first and second signal paths and the self-inductance of the first or second signal path. In this example, the first trace and the second trace are portions of the first signal path and the second signal path, respectively.

[0068] While this example has a single trace that induces current in another trace (in this example, the second trace 150B induces current in the first trace 150A), it should be understood that in some embodiments, the two traces 150 simultaneously induce currents of different amplitudes and / or directions between each other. Additionally, any set of traces can induce current in any number of adjacent traces. For example, two adjacent traces can induce corresponding currents in one trace, such that one of the adjacent traces is configured to generate a crosstalk cancellation pulse.

[0069] Furthermore, the shape of trace 150 is not limited to Figure 2A , Figure 2B , Figure 3A and Figure 3B The diagram illustrates a three-segment shape. For example, some embodiments discussed herein can be implemented anywhere along or near the trace, such as a die, conductive path of a silicon chip, package, interposer, PCB, connector, cable, or any other component of an IC package. The shape of the trace can be any suitable shape located on the same layer, along a vertical direction, or on two adjacent layers, such as serpentine, sawtooth, loop, and other variations.

[0070] As a first example Figure 4A A schematic diagram illustrating two different sets of traces 150, forming corresponding coupled trace pairs and having two loops in two adjacent planes, is depicted according to various aspects of the technology described herein. Figure 4A In the first coupled trace pair 400, there is a first trace 150A and a second trace 150B arranged in an out-of-phase coupling relationship; while the second coupled trace pair 410 has a first trace 150A and a second trace 150B arranged in an in-phase coupling relationship. Figure 4A In this example, the coupled trace pairs 400 and 410 each comprise two loops in two adjacent vertical planes. The vertical planes are parallel to each other and are located at different positions along the vertical direction (defined as along one end of trace 150 to the other end of trace 150).

[0071] As a second example, Figure 4B A schematic diagram illustrating two different sets of traces 150, forming corresponding coupled trace pairs and having two loops in the same plane, is depicted according to various aspects of the technology described herein. Figure 4B In the third coupled trace pair 430, there is a first trace 150A and a second trace 150B arranged in an out-of-phase coupling relationship; while the fourth coupled trace pair 440 has a first trace 150A and a second trace 150B arranged in an in-phase coupling relationship. Figure 4A In this example, the coupled trace pairs 430 and 440 each comprise two loops in the same vertical plane. In this example, the vertical plane is orthogonal to the vertical direction (defined as along one end of trace 150 to the other end of trace 150).

[0072] As a third example Figure 4C A schematic diagram depicts two different sets of traces 150, illustrating the formation of corresponding coupled trace pairs and having two loops at different vertical positions, according to various aspects of the technology described herein. Figure 4C In the fifth coupled trace pair 450, a first trace 150A and a second trace 150B are arranged in an out-of-phase coupling relationship; while the sixth coupled trace pair 460 has a first trace 150A and a second trace 150B arranged in an in-phase coupling relationship. Figure 4C In this example, the coupled trace pairs 450 and 460 each include two loops, portions of which are located at different vertical positions and on separate planes. In this example, the vertical direction is defined as along one end of trace 150 to the other. As illustrated, the first trace 150A has a loop whose segments lie on the same horizontal plane as corresponding segments of the second trace 150B.

[0073] As a fourth example, Figure 4D A schematic diagram illustrating corresponding pairs 470 of traces 150 forming a coupled trace pair and having sharp corners, according to various aspects of the technology described herein, is depicted. For example, the illustrated first trace 150A and second trace 150B have sharp edges and form a coupled trace pair because they are closely adjacent to each other. It should be understood that in some embodiments, the coupled trace pair 150 includes any suitable shape, such as a shape having sharp edges and arranged in any suitable configuration, a shape having rounded edges, or any combination thereof.

[0074] Figure 5A A first circuit diagram 500 depicts aspects of the technology described herein, showing a first trace 150A and a second trace 150B that are not electromagnetically coupled in segments highlighted by dashed rectangular boxes. In other words, in Figure 5AIn this example, since the first trace 150A and the second trace 150B are not in-phase or out-of-phase coupled in the segment highlighted by the dashed rectangle, neither trace 150 generates a crosstalk cancellation pulse. In one example, traces 150A and 150B correspond to two DDR traces that connect the memory controller die 502 (which may correspond to a portion of the memory controller 110 in Figure 1) to the DRAM controller die 504 (which may correspond to a portion of the DRAM 120 in Figure 1). In one example, the first circuit diagram 500 corresponds to... Figure 1C The circuit diagram associated with the arrangement of traces 150 is shown in the figure. As shown in the first circuit diagram 500, the two traces 150A and 150B have one or more inductors 506 and one or more capacitors 508. In one embodiment, one or more inductors 506 or capacitors in one trace 150 induce current in the other trace 150.

[0075] Figure 5B A second circuit diagram 520 depicts aspects of the technology described herein, showing a first trace 150A and a second trace 150B electromagnetically coupled in an out-of-phase inductance relationship 522 in segments highlighted by dashed rectangular boxes. In this example, the polarity of the inductors indicates that the coupling is out-of-phase. In other words, in Figure 5B In this context, as a result of the out-of-phase coupling relationship 522, at least one of traces 150A and 150B generates a crosstalk cancellation pulse to reduce crosstalk associated with the current induced in the other trace. In one example, this crosstalk includes FEXT caused as a result of one or more inductors 506 or capacitors 508 in adjacent traces 150. In one example, traces 150A and 150B correspond to two DDR traces that connect the memory controller die 502 (which may correspond to a portion of the memory controller 110 in FIG. 1) to the DRAM controller die 504 (which may correspond to a portion of the DRAM 120 in FIG. 1). In one example, the second circuit diagram 520 corresponds to... Figure 3A The circuit diagram associated with the arrangement of trace 150 shown in Figure 3C. In one example, Figure 2A and Figure 2B The trace coupling in 202 produces an out-of-phase coupling relationship 522.

[0076] Figure 5C A third circuit diagram 530 depicts aspects of the technology described herein, showing a first trace 150A and a second trace 150B inductively coupled in phase in a segment highlighted by dashed rectangular boxes. In this example, the polarity of the inductors indicates that the coupling is in phase. In other words, in Figure 5CIn this context, as a result of in-phase coupling 532, at least one of traces 150A and 150B generates a crosstalk cancellation pulse to reduce crosstalk associated with induced current in the other trace. In one example, this crosstalk includes FEXT caused as a result of one or more inductors 506 or capacitors 508 in adjacent traces 150. In one example, traces 150A and 150B correspond to two DDR traces that connect memory controller die 502 (which may correspond to a portion of memory controller 110 in FIG. 1) to DRAM controller die 504 (which may correspond to a portion of DRAM 120 in FIG. 1). In one example, the third circuit diagram 530 corresponds to... Figure 3A and Figure 3B The circuit diagram associated with the arrangement of trace 150 shown in the figure. In one example, Figure 3A and Figure 3B The trace coupling in 302 produces an in-phase coupling relationship 532.

[0077] Turn Figure 5D What is described is the relationship between the technology described in this article and... Figure 5B The second circuit diagram or Figure 5C A heatmap 540 is associated with two magnetic field contour plots 541 and 542 of the third circuit diagram. The first magnetic field contour plot 541 illustrates how a “void” enhances the electromagnetic coupling between two traces, such as the first trace 150A and the second trace 150B discussed herein. In one example, a “void” refers to the presence of a metal gap in the metal layer of a package or printed circuit board during a metal etching process. In another example, a “void” refers to the presence of a cavitation or gap in a solder joint formed during a soldering process. In the first magnetic contour plot 542 and the second magnetic contour plot 543, traces with and without voids are shown side-by-side. The trace without voids is shown on the left, and the trace with voids is shown on the right.

[0078] The illustrated second magnetic contour plot 542 shows how coupled traces (such as coupled trace 202 and coupled trace 302 in Figure 2) enhance the electromagnetic coupling between two traces 150A and 150B. Referring to the second magnetic contour plot 542 on the left, the traces have solid reference planes above and below the trace pair. Continuing to refer to the second magnetic contour plot 542 on the right, the planes above and below the traces are empty. The illustrated first magnetic field contour plot 541 shows the magnetic field distribution when an alternating current of 1 ampere (A) and a frequency of 3.6 gigahertz (GHz) is injected into the conductor on the left. Continuing to refer to the first magnetic field contour plot 541, in the empty case on the right, the victim trace has more induced current from the inductive coupling (with the attacker trace) compared to the non-empty case. Accordingly, in some embodiments, gaps are used to increase electromagnetic coupling between traces, because in some cases, gaps increase coupling between two traces, as shown in two magnetic field contour plots 541 and 542.

[0079] Figure 6A A schematic diagram of a system 600 comprising multiple traces according to various aspects of the technology described herein is depicted, each trace forming multiple coupled trace pairs 610. The illustrated system 600 includes four traces 150: a first trace 150A, a second trace 150B, a third trace 150C, and a fourth trace 150D. Each of the illustrated traces 150 has a transmitter (marked with a solid circle) at one end and a receiver (marked with a hollow circle) at the other end. In this example, arrows indicate the direction of current. Referring to the first trace 150A, in this example, the first trace 150A forms a first coupled trace pair 610A with the second trace 150B, a second coupled trace pair 610B with the third trace 150C, and a third coupled trace pair 610C with the fourth trace 150D. In one embodiment, the first coupling trace pair 610A electromagnetically couples the first trace 150A and the second trace 150B, the second coupling trace pair 610B electromagnetically couples the first trace 150A and the third trace 150C, and the third coupling trace pair 610 electromagnetically couples the first trace 150A and the fourth trace 150D.

[0080] In one embodiment, the signal traveling through the first trace 150A includes a crosstalk cancellation pulse having a substantially similar amplitude and opposite polarity to the FEXT (induced by the current induced in the second trace 150B) between the first trace 150A and the second trace 150B, the FEXT (induced by the current induced in the third trace 150C) between the first trace 150A and the third trace 150C, and the FEXT (induced by the current induced in the fourth trace 150D) between the first trace 150A and the fourth trace 150D. In one embodiment, the second trace 150B also transmits a signal having an amplitude and polarity opposite to the FEXT (induced by the current induced in the first trace 150A) between the second trace 150B and the first trace 150A. Any number of traces can employ the embodiments disclosed herein to reduce FEXT caused by current induced by any number of adjacent traces or to reduce FEXT caused in any number of adjacent traces. For example, by employing the electromagnetic coupling disclosed herein, FEXT can be reduced by the electromagnetic coupling associated with the illustrated first coupled trace pair 610A, second coupled trace pair 610B, third coupled trace pair 610C, fourth coupled trace pair 610D, fifth coupled trace pair 610E, and sixth coupled trace pair 610F.

[0081] Figure 6B A schematic diagram of a system 650 comprising multiple traces 150 according to various aspects of the technology described herein is depicted, each trace forming two coupled trace pairs 660. The illustrated system 650 includes four traces 150: a first trace 150A, a second trace 150B, a third trace 150C, and a fourth trace 150D. In one embodiment, each of the traces 150 has a transmitter at one end and a receiver at the other end. In system 650, an "upper via" refers to a via path formed by trace 150 to an upper package of the IC package, while a "lower via" refers to a via path formed by trace 150 to, for example, a BGA or LGA at the bottom of the package.

[0082] In one embodiment, each trace implements two coupled trace pairs 660 to reduce crosstalk twice per trace, for example, at each region having coupled trace pairs 660. In this example, it is assumed that the first trace 150A and the third trace 150C guide current in a clockwise direction, and further assumed that the second trace 150B and the fourth trace 150D guide current in a counterclockwise direction. In this example, this arrangement achieves out-of-phase electromagnetic coupling between the first trace 150A and the second trace 150B (labeled as the first coupled trace pair 660A), between the first trace 150A and the fourth trace 150D (labeled as the second coupled trace pair 660B), between the second trace 150B and the third trace 150C (labeled as the third coupled trace pair 660C), and between the third trace 150C and the fourth trace 150D (labeled as the fourth coupled trace pair 660D). FEXT can be reduced by using an appropriate coupling length (or other modifications associated with the variables from Equation 1 above).

[0083] Figure 7A A schematic diagram of a first system 700 comprising two example differential trace pairs according to various aspects of the technology described herein, the two example differential trace pairs forming a coupled trace pair between two differential signal pairs. In one example, a “differential pair” comprises at least two traces or at least two conductive paths routed side-by-side, and carries signals of equal amplitude and opposite polarity on each trace. In one embodiment, the differential pair transmits binary information, or may utilize a more advanced protocol such as four-level pulse amplitude modulation (PAM4) to transmit multiple bits at once. One difference between standard digital traces and differential signaling is that differential signals are recovered and interpreted in a different manner. The illustrated first system 700 includes a first differential pair 710 and a second differential pair 720. In this example, the first differential pair 710 has a first end located on the left side, its height being greater than a second end located on the right side; the second differential pair 720 has a first end located on the right side, its height being greater than a second end located on the left side. Figure 7A In the example illustrated, when a current signal is injected into the first end of the two pairs of traces, an equivalent out-of-phase coupling is generated for the differential signal pair.

[0084] Figure 7B A schematic diagram of a second system 728 comprising two example differential trace pairs according to various aspects of the technology described herein is depicted. The illustrated second system 728 includes a third differential pair 730 and a fourth differential pair 740. In this example, the third differential pair 730 and the fourth differential pair each have a first end located on the left side, whose height is lower than that of the second end located on the right side. Figure 7B In the example illustrated in B, when a current signal is injected into the first end of the two pairs of traces, an equivalent in-phase coupling is generated for the differential signal pair.

[0085] In one example, differential pairs in system 700 or 728 induce currents in each other, causing FEXT. To reduce FEXT, the differential pairs can form a set of coupled trace pairs 750 as illustrated. In this example, the set of coupled trace pairs 750 corresponds to the portions of the trace pairs that are electromagnetically coupled to each other, thereby reducing FEXT by generating crosstalk cancellation pulses. For example, in the first system 700, the set of coupled trace pairs 750 is the portion of each differential pair in the first and second differential pairs 710 and 720 that is closely adjacent to each other, in this example, corresponding to the plane of the differential pair and located at the center. For example, suppose the first differential pair 710 induces a first induced current in the second differential pair 720, causing FEXT. In this example, the first differential pair 710 is controlled to generate a crosstalk cancellation pulse, and its coupled trace pair 750 induces another current in the second differential pair that is opposite in direction and substantially similar in amplitude to the first induced current. In this way, embodiments of the present disclosure can reduce crosstalk even for systems carrying more complex signals, such as signals associated with differential pairs.

[0086] refer to Figure 8 A flowchart illustrating a method 800 according to various aspects of the technology described herein is provided for programmatically modifying a proposed design layout of a PCB to generate an updated proposed design layout that undergoes fewer FEXTs compared to the original proposed design layout. In some embodiments, one or more components of the IC package 100 and / or other components described herein perform or benefit from Figure 8 The methods illustrated herein represent various aspects. In some embodiments, one or more computer storage media have computer-executable or computer-usable instructions implemented thereon that, when executed by one or more processors, cause one or more processors to perform method 800 or any of the embodiments disclosed herein. For example, method 800 is performed by... Figure 12 Example distributed computing environment 1200 and / or Figure 13 Example computing device 1300 is executed.

[0087] continue Figure 8 At box 810, process 800 includes receiving a proposed design layout for a portion of an integrated circuit package. For example, a portion of the integrated circuit package includes traces, silicon chips, dies, interposers, printed circuit boards (PCBs), connectors, or cables. This proposed design layout can be provided as a circuit diagram (such as...). Figure 5A , Figure 5B or Figure 5CThe circuit diagram shown in the figure may be received, or may be received as a vector representation of components within a portion of the IC package. At block 820, process 800 includes determining multiple adjacent traces within that portion of the integrated circuit package according to the proposed design layout. At block 830, process 800 includes determining crosstalk between a first trace and a second trace within the multiple traces based on digital simulation of the multiple traces. At block 840, process 800 includes identifying the positions of coupled trace segment pairs within that portion of the integrated circuit package for locating the first and second traces to reduce crosstalk between the first and second traces, as discussed herein.

[0088] At block 850, process 800 includes modifying the proposed design layout to generate an updated proposed design layout, the updated proposed design layout including a pair of coupled trace segments at the location within the portion of the integrated circuit package. The modification may include rearranging at least one of multiple existing traces without adding another trace. In one embodiment, the signal density of the updated proposed design layout matches the signal density of the proposed design layout. In one embodiment, modifying the proposed design layout includes changing at least one of the following: the length of the first or second trace, the width of the first or second trace, or the material of the first or second trace. In one embodiment, modifying the proposed design layout includes electromagnetically coupling a segment of the first trace to a segment of the second trace to reduce far-end crosstalk (FEXT), the far-end crosstalk (1) located between the first and second traces and (2) caused by a first induced current in the segment of the first trace. In this example, the signal of the first trace is controllable such that the signal travels along the segment of the first trace in the direction of a second induced current opposite to the direction of the first induced current in the segment of the second trace. Examples put into practice

[0089] This document describes illustrative example embodiments of the present disclosure that have been put into practice. These example embodiments include a heterogeneous coupling 202 (similar to the coupling in Figure 2) as described herein, which is applied... Figure 9A The IC package 902 is shown in the figure. Perform tests or simulations on this IC package 902 to generate... Figure 9B , Figure 9C , Figure 10A , Figure 10B , Figure 11A and Figure 11B The curves or graphs depicted herein. However, it should be noted that while this example focuses specifically on a particular implementation, the embodiments of the technology described herein are more generally applicable to other electronic devices, including those that transmit any suitable signals, such as SDR, DDR, or QDR.

[0090] Refer to Figures 1 to 12 respectively. Figure 7B And continue to refer to Figure 8 In process 800, the IC package 902 is constructed, tested, and verified, as described below. Figure 9A In this example, based on various aspects of the technology described herein, an example IC package 902 is tested and simulated in environment 900 as a High Frequency Structure Simulator (HFSS). In this example, two traces are repositioned such that they form a coupled trace pair 202. For example, the IC package 902 is constructed with the coupled trace pair 202 having portions of traces spaced less than 0.05 mm apart, a distance much smaller than the distance between traces in other parts of the HFSS model. As part of the test and simulation, insertion loss 910 is plotted... Figure 9B In the first curve 912; FEXT 920 is plotted in Figure 9C In the second curve 922; the step response 1000 is plotted on Figure 10A The third curve 1010 is plotted; and the crosstalk response 1020 is plotted on the fourth curve 1030.

[0091] refer to Figure 9B In the first curve 912, the IC package excluding the coupling trace pair (drawn as a solid line) and the IC package including the coupling trace pair 202 (drawn as a dashed line) are distinguished. Figure 9A The insertion loss 910 between them remains relatively constant. (Reference) Figure 9C In the second curve 922, compared to the IC package excluding the coupling trace pair, the IC package including the coupling trace pair 202 ( Figure 9A The FEXT of 920 is even lower. Specifically, the second curve 922 shows a reduction of approximately 17 dB in FEXT in the frequency domain. (Reference) Figure 10A The third curve 1010 shows an IC package including a pair of coupling traces 202. Figure 9A The step response 1000 of the extracted S-parameters for the DDR channel excluding the coupling trace pair is shown in the figure. This includes the IC package containing the coupling trace pair 202. Figure 9A The full-channel S-parameters are essentially the same between the package and the IC package excluding the coupling trace pairs. (Reference) Figure 10A The peak amplitude (measured in millivolts (mV)) of the fourth curve 1030, crosstalk response 1020, for an IC package excluding the coupling trace pair (plotted as a solid line) is higher than that of another IC package including the coupling trace pair 202. Figure 9A (This is drawn as a dashed line).

[0092] Figure 11A Eye diagram 1110 depicts a full-channel time-domain simulation 1112 illustrating aspects not employing the embodiments disclosed herein. That is, in Figure 11A The results were reproduced for the IC package excluding coupling trace pairs. On the other hand, Figure 11B The description illustrates the approach to [the application of] [technology], as well as [technology] derived from [experiences], including [technology], [testing], and [simulation]. Figure 9A The example embodiment corresponds to the eye diagram 1120 of the full-channel time-domain simulation 1122. That is, in Figure 11B The results for IC packages including coupled trace pairs (e.g., coupled trace pairs with induced inductive effects) were reproduced. In these time-domain simulations 1112 and 1122, the worst bit of the entire channel was examined. In these eye diagrams 1110 and 1120, the entire channel corresponds to the trace from the central processing unit (CPU) die to the DRAM die. Figure 11A Compared to eye diagram 1110, Figure 11B Eye diagram 1120 shows a larger eye opening and less jittering of the bit stream at the transition edges in the DDR write direction.

[0093] As a result, tests confirmed that the FEXT between the first and second traces was reduced, and computational performance was improved by employing coupled trace pairs. This improvement is achieved by controlling one trace so that the signal induces a current along the other trace in the opposite direction to the initial induced current causing the FEXT. Therefore, simulations and tests of practical embodiments confirm that aspects of this disclosure improve the signal-to-noise ratio of the memory bus. Other embodiments

[0094] In some embodiments, an integrated circuit system is provided that employs any components described in any of the embodiments above. The integrated circuit system includes a first trace and a second trace. The first trace, located within the integrated circuit system, extends between a first end and a second end and has a shape defined by a first segment, a second segment, and a third segment. A first signal travels along the first trace from the first end to the second end. The second trace extends between a corresponding first end and a corresponding second end and has a shape defined by a corresponding first segment, a corresponding second segment, and a corresponding third segment. A first induced current in the second trace is induced at a location other than the first and second traces by the first signal traveling along the first trace via electromagnetic coupling. A second segment of the first trace is electromagnetically coupled to a corresponding second segment of the second trace to reduce far-end crosstalk (FEXT) associated with the first induced current in the second trace by controlling the first signal to travel along the second segment in the direction in which the first signal induces a second induced current in the corresponding second segment of the second trace. The second induced current is induced in the opposite direction to the first induced current traveling along the corresponding second segment of the second trace.

[0095] In any combination of the above embodiments of the integrated circuit system, the electromagnetic coupling between the second segment and the corresponding second segment generates a crosstalk cancellation pulse, which has an amplitude substantially similar to and opposite polarity to the FEXT between the first and second traces.

[0096] In any combination of the above embodiments of the integrated circuit system, the electromagnetic coupling between the second segment and the corresponding second segment forms an out-of-phase coupling between the first trace and the second trace.

[0097] In any combination of the above embodiments of the integrated circuit system, the electromagnetic coupling between the second segment and the corresponding second segment forms in-phase coupling between the first trace and the second trace.

[0098] In any combination of the above embodiments of the integrated circuit system, the first distance between the first segment of the first trace and the corresponding first segment of the second trace is greater than the second distance between the second segment of the first trace and the corresponding second segment of the second trace, and wherein the third distance between the third segment of the first trace and the corresponding third segment of the second trace is greater than the second distance.

[0099] In any combination of the above embodiments of the integrated circuit system, the second distance is less than 50 micrometers, and at least one of the first distance or the third distance is greater than 300 micrometers.

[0100] In any combination of the above embodiments of the integrated circuit system, the electrical coupling between the corresponding second segment of the second trace and the second segment of the first trace reduces the difference between the first ratio and the second ratio. The first ratio is the ratio between the mutual capacitance of the first signal path and the second signal path and the self-capacitance of the first signal path or the second signal path. The second ratio is the ratio between the mutual inductance of the first signal path and the second signal path and the self-inductance of the first signal path or the second signal path. The first signal path includes the first trace, and the second signal path includes the second trace.

[0101] In any combination of the above embodiments of the integrated circuit system, the integrated circuit system includes a third trace extending between a respective first terminal and a respective second terminal. The third trace has a shape defined by a respective first segment, a respective second segment, and a respective third segment. A third current travels along the third trace. One segment of the third trace is electrically coupled to at least one of the following: a first segment of the first trace, a third segment of the first trace, a corresponding first segment of the second trace, or a corresponding third segment of the second trace, to reduce the FEXT between the third trace and at least one of the first or second traces.

[0102] In any combination of the above embodiments of the integrated circuit system, the first trace includes a plurality of conductive paths extending between the first end and the second end, and wherein the second trace includes a plurality of corresponding conductive paths.

[0103] In any combination of the above embodiments of the integrated circuit system, the first signal and the first induced current include corresponding currents, and the first trace and the second trace include corresponding conductive paths.

[0104] In any combination of the above embodiments of the integrated circuit system, the coupling between the first trace and the second trace is mutual, and the crosstalk cancellation is also mutual. For example, a third induced current induced by the second trace on the first trace is also canceled out by a fourth induced current generated by the second trace on the first trace.

[0105] In some embodiments, a computer-implemented method is provided. The computer-implemented method includes: receiving a proposed design layout for a portion of an integrated circuit package; determining, based on the proposed design layout, a plurality of adjacent traces within the portion of the integrated circuit package; determining crosstalk induction between a first signal path and a second signal path within the plurality of signal paths based on digital simulation of a plurality of signal paths including the plurality of traces; identifying the location of a pair of coupled trace segments within the portion of the integrated circuit package for locating the first and second traces; and modifying the proposed design layout to generate an updated proposed design layout, the updated proposed design layout including the pair of coupled trace segments at the location within the portion of the integrated circuit package.

[0106] In any combination of the above embodiments of the computer-implemented method, the proposed design layout modification includes changing at least one of the following: the length of the first or second trace, the distance between the first and second traces, the width of the first or second trace, or the material of the first or second trace.

[0107] In any combination of the above embodiments of the computer-implemented method, the proposed design layout modification includes: rearranging at least one of the multiple existing traces without adding another trace.

[0108] In any combination of the above embodiments of the computer-implemented method, the portion of the integrated circuit package includes at least one of the following: traces, silicon chips, dies, interposers, printed circuit boards (PCBs), connectors, or cables.

[0109] In any combination of the above embodiments of the computer-implemented method, the signal density of the updated proposed design layout matches the signal density of the proposed design layout.

[0110] In any combination of the above embodiments of the computer-implemented method, the proposed modified design layout includes: electromagnetically coupling segments of the first trace and segments of the second trace to reduce (1) far-end crosstalk (FEXT) between the first and second traces and (2) caused by a first induced current in a segment of the first trace. The signal of the first trace is controllable such that the signal travels along the segment of the first trace in the direction of a second induced current induced in a segment of the second trace in the opposite direction to the first induced current.

[0111] In some embodiments, an electrical system is provided that employs any components of the system described in any of the embodiments above. The electrical system includes a first trace and a second trace. The first trace extends between a first end and a second end and has a shape defined by a first segment and a second segment. A first signal travels along the first trace from the first end to the second end. The second trace extends between a corresponding first end and a corresponding second end and has a shape defined by a corresponding first segment and a second segment. A first induced current in the second trace is induced by the first signal traveling along the first trace at a location other than the first or second trace via electromagnetic coupling. A corresponding second segment of the second trace is electromagnetically coupled to a second segment of the first trace to reduce far-end crosstalk (FEXT) between the first and second traces by controlling the first signal to travel along the second segment in the direction in which the first signal induces a second induced current in the corresponding second segment of the second trace. The second induced current is induced in the opposite direction to the first induced current traveling along the corresponding second segment of the second trace.

[0112] In any combination of the above embodiments of the electrical system, the electrical system further includes at least one of the following: an integrated circuit package or printed circuit board including a first trace and a second trace.

[0113] In any combination of the above embodiments of the electrical system, at least one of the first or second traces includes a lead that electrically couples a first component of the integrated circuit package of the electrical system to a second component outside the integrated circuit package.

[0114] In any combination of the above embodiments of the electrical system, the electrical system includes a first electrical component and a second electrical component, wherein at least one of the first or second traces has a conductive path connecting the first and second electrical components within the electrical system. Example computing environment

[0115] Various implementations have been described; now, example computing environments suitable for implementing embodiments of this disclosure are described, including... Figure 12 and Figure 13Examples of distributed computing environments and example computing devices are described herein. Embodiments of this disclosure are described in the general context of computer code or machine-usable instructions (including computer-usable or computer-executable instructions, such as program modules), which are executed by a computer or other machine (such as a smartphone, tablet, personal computer (PC) or other mobile device, server, or client device). Generally, a program module (including routines, programs, objects, components, data structures, etc.) refers to code that performs a specific task or implements a specific abstract data type. Embodiments of this disclosure are practiced in a variety of system configurations, including mobile devices, consumer electronics, general-purpose computers, more specialized computing devices, and so on. Embodiments of this disclosure are also practiced in distributed computing environments where tasks are performed by remote processing devices linked through a communication network. In a distributed computing environment, program modules may reside on both local and remote computer storage media (including memory storage devices).

[0116] Some embodiments include end-to-end software systems that can operate within the system components described herein to operate computer hardware to provide system functionality. At a low level, the hardware processor can execute instructions selected from a machine language (also known as machine code or native) instruction set for a given processor. The processor recognizes native instructions and performs corresponding low-level functions related to, for example, logic, control, and memory operations. Low-level software written in machine code can provide more complex functionality for higher-level software. Accordingly, in some embodiments, computer-executable instructions include any software, including low-level software written in machine code, higher-level software (such as application software), and any combination thereof. At this point, system components can manage resources and provide services for system functionality. Any other variations and combinations thereof are contemplated in the embodiments of this disclosure.

[0117] Now for reference Figure 12 , Figure 12 An example distributed computing environment 1200 in which embodiments of the present disclosure may be employed is illustrated. Specifically, Figure 12 A high-level architecture of an example cloud computing platform 1210 is shown, which can host a technology solution environment or a portion thereof (e.g., a data trustee environment). It should be understood that the arrangement and other arrangements described herein are illustrated by way of example only. For example, many of the elements described herein can be implemented as discrete or distributed components, or in combination with other components, and in any suitable combination and location, as described above. Other arrangements and elements (e.g., machines, interfaces, functions, sequences, and functional groupings) may be used in addition to or in lieu of the arrangements and elements shown.

[0118] The data center can support a distributed computing environment 1200, which includes a cloud computing platform 1210, racks 1220, and nodes 1230 (e.g., computing devices, processing units, or blades) within the racks 1220. The technical solution environment can be implemented using the cloud computing platform 1210, which can run cloud services across different data centers and geographical regions. The cloud computing platform 1210 can implement a structure controller 1240 component for providing and managing resource allocation, deployment, upgrades, and management of cloud services. Typically, the cloud computing platform 1210 is used to store data or run service applications in a distributed manner. The cloud computing platform 1210 in the data center can be configured to host and support the operation of endpoints for specific service applications. The cloud computing platform 1210 can be a public cloud, a private cloud, or a dedicated cloud.

[0119] Node 1230 may be provided with host 1250 (e.g., operating system or runtime environment) on which a defined software stack runs on node 1230. Node 1230 may also be configured to perform specific functions (e.g., compute node or storage node) within cloud computing platform 1210. Node 1230 is allocated to run one or more portions of a tenant's service application. A tenant may refer to a customer utilizing the resources of cloud computing platform 1210. The service application components of cloud computing platform 1210 supporting a particular tenant may be referred to as multi-tenant infrastructure or multi-tenancy. In this document, the terms "service application," "application," or "service" are used interchangeably and broadly refer to any software or software portion running on top of storage devices, access storage devices, and compute device locations within a data center.

[0120] When node 1230 supports more than one independent service application, node 1230 can be partitioned into virtual machines (e.g., virtual machine 1252 and virtual machine 1254). Physical machines can also run independent service applications simultaneously. These virtual machines or physical machines can be configured as personalized computing environments supported by resources 1260 (e.g., hardware and software resources) in the cloud computing platform 1210. It is anticipated that resources can be configured for specific service applications. Furthermore, each service application can be divided into functional parts, allowing each functional part to run on an independent virtual machine. In the cloud computing platform 1210, multiple servers can be used to run service applications and perform data storage operations in a cluster. In particular, these servers can perform data operations independently but are presented as a single device referred to as a cluster. Each server in the cluster can be implemented as a node.

[0121] Client device 1280 can be linked to a service application in cloud computing platform 1210. Client device 1280 can be any type of computing device, corresponding to computing device 1000 described with reference to FIG. 10. For example, client device 1280 is configured to issue commands to cloud computing platform 1210. In embodiments, client device 1280 communicates with the service application via Virtual Internet Protocol (IP) and load balancers or other means that direct communication requests to a designated endpoint in cloud computing platform 1210. Components of cloud computing platform 1210 can communicate with each other via a network (not shown), which may include, but is not limited to, one or more local area networks (LANs) and / or wide area networks (WANs).

[0122] refer to Figure 13 An example computing device is provided and is generally referred to as computing device 1300. Computing device 1300 is merely an example of a suitable computing environment and is not intended to imply any limitation on the scope or functionality of the embodiments of this disclosure, nor should computing device 1300 be construed as having any dependency or requirement on any of the components illustrated or a combination thereof. Computing device 1300 includes a bus 1310 that is directly or indirectly coupled to the following devices: memory 1312, one or more processors 1314, one or more presentation components 1316, input / output ports 1318, input / output components 1320, and an illustrative power supply 1322. Bus 1310 represents a bus that may be one or more buses (such as an address bus, a data bus, or a combination thereof). For clarity of concept, Figure 13 The various boxes are illustrated with lines, and other arrangements of the described components and / or component functions are also envisioned. Presentation components (such as display devices) are examples of I / O components. Furthermore, the processor also has memory. It should be understood that this is the nature of the art, and is reiterated. Figure 13 The illustrations are merely example computing devices that can be used in conjunction with one or more embodiments of this disclosure. No distinction is made between categories such as “workstation,” “server,” “laptop,” and “handheld device,” as all these categories are envisioned in… Figure 13 Within the scope and refer to "Computing Devices".

[0123] Computing device 1300 typically includes a variety of computer-readable media. Computer-readable media can be any available medium accessible by computing device 1300, and includes volatile and non-volatile media, removable media, and non-removable media. By way of example, and not limitation, computer-readable media includes computer storage media and communication media. Computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information, such as computer-readable instructions, data structures, program modules, or other data. Computer storage media includes, but is not limited to: RAM, read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage devices, magnetic cartridges, magnetic tape, disk storage devices or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible by computing device 1300. Computer storage media itself does not include signals. Communication media typically embody computer-readable instructions, data structures, program modules, or other data in the form of modulated data signals (such as carrier waves or other transmission mechanisms), and includes any information delivery medium. The term "modulated data signal" refers to a signal whose one or more characteristics are set or altered in such a way that information is encoded in the signal. By way of example, and not limitation, communication media include wired media (such as wired networks or direct wired connections) and wireless media (such as sound waves, radio frequency (RF), infrared light, and other wireless media). Any combination of the above should also be included within the scope of computer-readable media.

[0124] Memory 1312 includes computer storage media in the form of volatile memory and / or non-volatile memory. Memory can be removable, non-removable, or a combination thereof. Example hardware devices include solid-state memory, hard disk drives, optical disk drives, etc. Computing device 1300 includes one or more processors that read data from various entities, such as memory 1312 or I / O components 1320. As used herein, the term "processor" or "a processor" can refer to more than one computer processor. In one example, the term "processor" (or "a processor") refers to at least one processor, which can be a physical processor or a virtual processor, such as a computer processor on a virtual machine. The term "processor" (or "a processor") can also refer to multiple processors, each of which can be physical or virtual, such as a multiprocessor system, distributed processing or distributed computing architecture, cloud computing system, or parallel processing performed by more than one processor. Furthermore, the various operations implemented or performed by processors as described herein can also be performed by more than one processor.

[0125] One or more presentation components 1316 present data indications to a user or other device. Example presentation components include display devices, speakers, printing components, vibration components, etc.

[0126] I / O port 1318 allows computing device 1300 to be logically coupled to other devices (including I / O component 1320, some of which may be built-in). Illustrative components include microphones, joysticks, game controllers, satellite antennas, scanners, printers, wireless devices, etc. Additional structural and functional features of embodiments of the technical solution

[0127] The various components utilized herein have been identified. It should be understood that, within the scope of this disclosure, any number of components and arrangements can be employed to achieve the desired functionality. For example, for clarity of concept, components in the embodiments depicted in the figures are shown as lines. Other arrangements and other components may also be used to implement these components. For example, although some components are depicted as single components, many of the elements described herein can be implemented as discrete or distributed components, or in combination with other components, and in any suitable combination and location. Some elements may be omitted entirely. Furthermore, the various functions performed by one or more entities as described herein can also be implemented by hardware, firmware, and / or software, as described herein. For example, various functions can be implemented by a processor executing instructions stored in memory. Thus, other arrangements and elements (e.g., machines, interfaces, functions, sequences, and functional groups) may be used in addition to or in lieu of the arrangements and elements shown.

[0128] The embodiments described herein can be combined with one or more of the specific alternatives described. In particular, the claimed embodiments may contain alternative references to more than one other embodiment. The claimed embodiments may specify further limitations on the claimed subject matter.

[0129] To meet legal requirements, the subject matter of embodiments of this disclosure has been specifically described herein. However, this description itself is not intended to limit the scope of this patent. Rather, the subject matter claimed in this disclosure is contemplated to be embodied in other ways, including different steps or combinations of steps similar to those described herein, in combination with other existing or future technologies. Furthermore, although the terms “step” and / or “box” may be used herein to imply different elements of the method employed, these terms should not be construed as implying any particular order between the steps disclosed herein unless the order of the steps is explicitly described.

[0130] For the purposes of this disclosure, "substantially" when used to describe a proximity level or similarity level generally refers to a set of elements sharing a proximity or similarity level. For example, the polarity of the crosstalk cancellation pulse is substantially similar to the amplitude of the induced current, indicating that the crosstalk cancellation pulse and the induced current have similar amplitudes or magnitudes (expressed as percentages, ratios, thresholds, etc., such as 50%, 60%, 70%, 80%, 90%, 95%, 98%, 99%, 100%, etc.). To be clearer, in one example, when the angles between the first trace 150A and the second trace 150B and each other are 170 degrees, 173 degrees, 75 degrees, 185 degrees, 188 degrees, 190 degrees, or 180 degrees, respectively, they are substantially parallel to each other.

[0131] For the purposes of this disclosure, the word "including" has the same broad meaning as the word "comprising," and the word "access" includes "receiving," "quoting," or "retrieval." Furthermore, the word "communication" has the same broad meaning as "receiving" or "transmitting" facilitated by the communication medium described herein, a software- or hardware-based bus, receiver, or transmitter. Additionally, unless otherwise stated, words such as "a" and "a" include both singular and plural forms. Thus, for example, the limitation of "a feature" is satisfied when one or more features are present. Furthermore, the term "or" includes conjunctions, disjunctive words, and both (therefore, a or b includes a or b, and a and b).

[0132] For the purposes of the detailed discussion above, the embodiments of this disclosure are described with reference to a distributed computing environment; however, the distributed computing environment depicted herein is merely an example. Components can be configured to perform novel aspects of the embodiments, wherein the term "configured for" can mean "programmed to" use code to perform a particular task or implement a particular abstract data type. Furthermore, while the embodiments of this disclosure generally refer to the technical environment and schematic diagrams described herein, it should be understood that the described techniques can be extended to other implementation environments.

[0133] As used herein, the terms "application" or "app" are used interchangeably to refer to any software-based program, package, or product executable via one or more (physical or virtual) computers or devices. An application can be any set of software products that, when executed, provide one or more computing and / or data services to an end user. In some embodiments, an application can refer to a set of applications that can be executed together to provide one or more computing and / or data services. Applications included in an application set can be executed serially, in parallel, or in any combination thereof. Execution of multiple applications, including a single application, can be interleaved. For example, an application may include a first application and a second application. Execution of an application can include serial execution of the first application and the second application, or parallel execution of the first application and the second application. In other embodiments, execution of the first application and the second application can be interleaved.

[0134] Embodiments of this disclosure have been described with respect to specific examples, which are intended in all respects to be illustrative and not restrictive. Alternative embodiments will become apparent to those skilled in the art to which this disclosure pertains without departing from the scope of this disclosure.

[0135] As can be seen from the foregoing, this disclosure is well suited to achieving all the purposes and objectives set forth above, as well as other obvious and structurally inherent advantages.

[0136] It should be understood that certain features and sub-combinations are useful and can be employed without reference to other features or sub-combinations. This is contemplated by the claims and is within the scope of the claims.

Claims

1. An integrated circuit system (100), comprising: A first trace (150A) is located within the integrated circuit system and extends between a first end and a second end. The first trace has a shape defined by a first segment (311), a second segment (312), and a third segment (313), wherein a first signal travels along the first trace from the first end to the second end. as well as A second trace (150B) extends between a corresponding first end and a corresponding second end, the second trace having a shape defined by a corresponding first segment (321), a corresponding second segment (322), and a corresponding third segment (323), wherein a first induced current in the second trace is induced by a first signal traveling along the first trace at a location other than the first trace and the second trace via electromagnetic coupling, and wherein the second segment of the first trace is electromagnetically coupled to the corresponding second segment of the second trace to reduce far-end crosstalk (FEXT) associated with the first induced current in the second trace by controlling the first signal to travel along the second segment in the direction of inducing a second induced current in the corresponding second segment of the second trace, the second induced current being induced in the opposite direction to the first induced current traveling along the corresponding second segment of the second trace.

2. The integrated circuit system of claim 1, wherein the electromagnetic coupling between the second segment and the corresponding second segment generates a crosstalk cancellation pulse, the crosstalk cancellation pulse having an amplitude substantially similar to and opposite polarity to the FEXT between the first trace and the second trace.

3. The integrated circuit system according to claim 1, wherein the electromagnetic coupling between the second segment and the corresponding second segment forms an out-of-phase coupling (202) between the first trace and the second trace.

4. The integrated circuit system according to claim 1, wherein the electromagnetic coupling between the second segment and the corresponding second segment forms in-phase coupling (302) between the first trace and the second trace.

5. The integrated circuit system of claim 1, wherein the first distance between the first segment of the first trace and the corresponding first segment of the second trace is greater than the second distance between the second segment of the first trace and the corresponding second segment of the second trace, and the third distance between the third segment of the first trace and the corresponding third segment of the second trace is greater than the second distance.

6. The integrated circuit system of claim 5, wherein the second distance is less than 50 micrometers, and wherein at least one of the first distance or the third distance is greater than 300 micrometers.

7. The integrated circuit system of claim 1, wherein the electrical coupling between the corresponding second segment of the second trace and the second segment of the first trace reduces the difference between a first ratio and a second ratio, wherein the first ratio is the ratio between the mutual capacitance of the first signal path and the second signal path and the self-capacitance of the first signal path or the second signal path, wherein the second ratio is the ratio between the mutual inductance of the first signal path and the second signal path and the self-inductance of the first signal path or the second signal path, wherein the first signal path includes the first trace, and the second signal path includes the second trace.

8. The integrated circuit system of claim 1, comprising a third trace extending between a respective first end and a respective second end, the third trace having a shape defined by a respective first segment, a respective second segment, and a respective third segment, wherein a third current travels along the third trace, and wherein one segment of the third trace is electrically coupled to at least one of the following segments: a first segment of the first trace, the third segment of the first trace, the corresponding first segment of the second trace, or the corresponding second segment of the second trace, to reduce the FEXT between the third trace and at least one of the first trace or the second trace.

9. The integrated circuit system of claim 1, wherein the first trace includes a plurality of conductive paths extending between the first end and the second end, and wherein the second trace includes a plurality of corresponding conductive paths.

10. The integrated circuit system of claim 1, wherein the first signal and the first induced current comprise corresponding currents, and wherein the first trace and the second trace comprise corresponding conductive paths.

11. A computer-implemented method (800), comprising: Receive (810) the suggested design layout for a portion of the integrated circuit package (200); Based on the proposed design layout, determine multiple adjacent traces within the portion of the integrated circuit package (820); Based on digital simulation of multiple signal paths including the multiple traces, the crosstalk induction between the first signal path and the second signal path in the multiple signal paths is determined (830). The location of the coupled trace segment pair (302) within the portion of the integrated circuit package, which is used to locate the first trace (150A) and the second trace (150B) among the plurality of traces, is marked (840); as well as Modify (850) the proposed design layout to generate an updated proposed design layout, the updated proposed design layout including the coupling trace segment pairs at the locations within the portion of the integrated circuit package.

12. The computer-implemented method of claim 11, wherein modifying the proposed design layout comprises changing at least one of the following: the length of the first or second trace, the distance between the first and second traces, the width of the first or second trace, or the material of the first or second trace.

13. The computer-implemented method of claim 11, wherein modifying the proposed design layout includes: Rearrange at least one of the multiple existing traces without adding another trace.

14. The computer-implemented method of claim 11, wherein the portion of the integrated circuit package comprises at least one of the following: traces, silicon chips, dies, interposers, printed circuit boards (PCBs), connectors, or cables.

15. The computer-implemented method of claim 11, wherein the signal density of the updated proposed design layout is matched with the signal density of the proposed design layout.

16. The computer-implemented method of claim 11, wherein modifying the proposed design layout includes: Electromagnetically couple the segments of the first trace to the segments of the second trace to reduce (1) far-end crosstalk (FEXT) between the first trace and the second trace and (2) caused by a first induced current in the segment of the first trace, wherein the signal of the first trace is controllable such that the signal travels along the segment of the first trace in the direction of a second induced current in the segment of the second trace in the opposite direction to the first induced current.

17. An electrical system comprising: A first trace (150A) extends between a first end and a second end and has a shape defined by a first segment (211) and a second segment (212), wherein a first signal travels along the first trace from the first end to the second end; as well as A second trace (150A) extends between a corresponding first end and a corresponding second end, the second trace having a shape defined by a corresponding first segment (221) and a corresponding second segment (222), wherein a first induced current in the second trace is induced by a first signal traveling along the first trace at a location other than the first trace and the second trace via electromagnetic coupling, and wherein the corresponding second segment of the second trace is electromagnetically coupled to the second segment of the first trace to reduce far-end crosstalk (FEXT) between the first trace and the second trace by controlling the first signal to travel along the second segment in the direction of inducing a second induced current in the corresponding second segment of the second trace, the second induced current being induced in the opposite direction to the first induced current traveling along the corresponding second segment of the second trace.

18. The electrical system of claim 17, comprising at least one of the following: an integrated circuit package (100) or printed circuit board including the first trace and the second trace.

19. The electrical system of claim 17, wherein at least one of the first trace or the second trace includes a lead that electrically couples a first component of the integrated circuit package of the electrical system to a second component outside the integrated circuit package.

20. The electrical system of claim 17, wherein the electrical system includes a first electrical component and a second electrical component, wherein at least one of the first trace or the second trace has a conductive path connecting the first electrical component and the second electrical component within the electrical system.

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